1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_resolve_map.h"
35 #include "intel_tex.h"
36 #include "intel_blit.h"
37 #include "intel_fbo.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
73 * This field must be set to 0 for all SINT MSRTs when all RT channels
76 * In practice this means that we have to disable MCS for all signed
77 * integer MSAA buffers. The alternative, to disable MCS only when one
78 * of the render target channels is disabled, is impractical because it
79 * would require converting between CMS and UMS MSAA layouts on the fly,
82 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
83 return INTEL_MSAA_LAYOUT_UMS
;
85 return INTEL_MSAA_LAYOUT_CMS
;
92 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
93 * scaled-down bitfield representation of the color buffer which is capable of
94 * recording when blocks of the color buffer are equal to the clear value.
95 * This function returns the block size that will be used by the MCS buffer
96 * corresponding to a certain color miptree.
98 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
99 * beneath the "Fast Color Clear" bullet (p327):
101 * The following table describes the RT alignment
115 * This alignment has the following uses:
117 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
118 * buffer contains 128 blocks horizontally and 256 blocks vertically.
120 * - For figuring out alignment restrictions for a fast clear operation. Fast
121 * clear operations must always clear aligned multiples of 16 blocks
122 * horizontally and 32 blocks vertically.
124 * - For scaling down the coordinates sent through the render pipeline during
125 * a fast clear. X coordinates must be scaled down by 8 times the block
126 * width, and Y coordinates by 16 times the block height.
128 * - For scaling down the coordinates sent through the render pipeline during
129 * a "Render Target Resolve" operation. X coordinates must be scaled down
130 * by half the block width, and Y coordinates by half the block height.
133 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*mt
,
135 unsigned *width_px
, unsigned *height
)
137 switch (mt
->tiling
) {
139 unreachable("Non-MSRT MCS requires X or Y tiling");
140 /* In release builds, fall through */
142 *width_px
= 32 / mt
->cpp
;
146 *width_px
= 64 / mt
->cpp
;
153 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
156 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
157 * beneath the "Fast Color Clear" bullet (p326):
159 * - Support is limited to tiled render targets.
160 * - Support is for non-mip-mapped and non-array surface types only.
162 * And then later, on p327:
164 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
168 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
169 struct intel_mipmap_tree
*mt
)
171 /* MCS support does not exist prior to Gen7 */
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->tiling
!= I915_TILING_X
&&
184 mt
->tiling
!= I915_TILING_Y
)
186 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
188 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
190 if (mt
->physical_depth0
!= 1)
193 /* There's no point in using an MCS buffer if the surface isn't in a
196 if (!brw
->format_supported_as_render_target
[mt
->format
])
204 * Determine depth format corresponding to a depth+stencil format,
205 * for separate stencil.
208 intel_depth_format_for_depthstencil_format(mesa_format format
) {
210 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
211 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
212 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
213 return MESA_FORMAT_Z_FLOAT32
;
221 * @param for_bo Indicates that the caller is
222 * intel_miptree_create_for_bo(). If true, then do not create
225 struct intel_mipmap_tree
*
226 intel_miptree_create_layout(struct brw_context
*brw
,
237 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
241 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
242 _mesa_lookup_enum_by_nr(target
),
243 _mesa_get_format_name(format
),
244 first_level
, last_level
, depth0
, mt
);
246 if (target
== GL_TEXTURE_1D_ARRAY
) {
247 /* For a 1D Array texture the OpenGL API will treat the height0
248 * parameter as the number of array slices. For Intel hardware, we treat
249 * the 1D array as a 2D Array with a height of 1.
251 * So, when we first come through this path to create a 1D Array
252 * texture, height0 stores the number of slices, and depth0 is 1. In
253 * this case, we want to swap height0 and depth0.
255 * Since some miptrees will be created based on the base miptree, we may
256 * come through this path and see height0 as 1 and depth0 being the
257 * number of slices. In this case we don't need to do the swap.
259 assert(height0
== 1 || depth0
== 1);
268 mt
->first_level
= first_level
;
269 mt
->last_level
= last_level
;
270 mt
->logical_width0
= width0
;
271 mt
->logical_height0
= height0
;
272 mt
->logical_depth0
= depth0
;
273 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
274 exec_list_make_empty(&mt
->hiz_map
);
276 /* The cpp is bytes per (1, blockheight)-sized block for compressed
277 * textures. This is why you'll see divides by blockheight all over
280 _mesa_get_format_block_size(format
, &bw
, &bh
);
281 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
282 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
284 mt
->num_samples
= num_samples
;
285 mt
->compressed
= _mesa_is_format_compressed(format
);
286 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
289 if (num_samples
> 1) {
290 /* Adjust width/height/depth for MSAA */
291 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
292 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
293 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
295 * "Any of the other messages (sample*, LOD, load4) used with a
296 * (4x) multisampled surface will in-effect sample a surface with
297 * double the height and width as that indicated in the surface
298 * state. Each pixel position on the original-sized surface is
299 * replaced with a 2x2 of samples with the following arrangement:
304 * Thus, when sampling from a multisampled texture, it behaves as
305 * though the layout in memory for (x,y,sample) is:
307 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
308 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
310 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
311 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
313 * However, the actual layout of multisampled data in memory is:
315 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
316 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
318 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
319 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
321 * This pattern repeats for each 2x2 pixel block.
323 * As a result, when calculating the size of our 4-sample buffer for
324 * an odd width or height, we have to align before scaling up because
325 * sample 3 is in that bottom right 2x2 block.
327 switch (num_samples
) {
329 assert(brw
->gen
>= 8);
330 width0
= ALIGN(width0
, 2) * 2;
331 height0
= ALIGN(height0
, 2);
334 width0
= ALIGN(width0
, 2) * 2;
335 height0
= ALIGN(height0
, 2) * 2;
338 width0
= ALIGN(width0
, 2) * 4;
339 height0
= ALIGN(height0
, 2) * 2;
342 /* num_samples should already have been quantized to 0, 1, 2, 4, or
345 unreachable("not reached");
348 /* Non-interleaved */
349 depth0
*= num_samples
;
353 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
354 * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
355 * TODO: can we use it elsewhere?
357 switch (mt
->msaa_layout
) {
358 case INTEL_MSAA_LAYOUT_NONE
:
359 case INTEL_MSAA_LAYOUT_IMS
:
360 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
362 case INTEL_MSAA_LAYOUT_UMS
:
363 case INTEL_MSAA_LAYOUT_CMS
:
364 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
368 if (target
== GL_TEXTURE_CUBE_MAP
) {
373 mt
->physical_width0
= width0
;
374 mt
->physical_height0
= height0
;
375 mt
->physical_depth0
= depth0
;
378 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
379 (brw
->must_use_separate_stencil
||
380 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
381 mt
->stencil_mt
= intel_miptree_create(brw
,
391 INTEL_MIPTREE_TILING_ANY
);
392 if (!mt
->stencil_mt
) {
393 intel_miptree_release(&mt
);
397 /* Fix up the Z miptree format for how we're splitting out separate
398 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
400 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
403 if (format
== mt
->format
) {
404 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
405 _mesa_get_format_name(mt
->format
));
409 brw_miptree_layout(brw
, mt
);
415 * \brief Helper function for intel_miptree_create().
418 intel_miptree_choose_tiling(struct brw_context
*brw
,
421 uint32_t num_samples
,
422 enum intel_miptree_tiling_mode requested
,
423 struct intel_mipmap_tree
*mt
)
425 if (format
== MESA_FORMAT_S_UINT8
) {
426 /* The stencil buffer is W tiled. However, we request from the kernel a
427 * non-tiled buffer because the GTT is incapable of W fencing.
429 return I915_TILING_NONE
;
432 /* Some usages may want only one type of tiling, like depth miptrees (Y
433 * tiled), or temporary BOs for uploading data once (linear).
436 case INTEL_MIPTREE_TILING_ANY
:
438 case INTEL_MIPTREE_TILING_Y
:
439 return I915_TILING_Y
;
440 case INTEL_MIPTREE_TILING_NONE
:
441 return I915_TILING_NONE
;
444 if (num_samples
> 1) {
445 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
448 * [DevSNB+]: For multi-sample render targets, this field must be
449 * 1. MSRTs can only be tiled.
451 * Our usual reason for preferring X tiling (fast blits using the
452 * blitting engine) doesn't apply to MSAA, since we'll generally be
453 * downsampling or upsampling when blitting between the MSAA buffer
454 * and another buffer, and the blitting engine doesn't support that.
455 * So use Y tiling, since it makes better use of the cache.
457 return I915_TILING_Y
;
460 GLenum base_format
= _mesa_get_format_base_format(format
);
461 if (base_format
== GL_DEPTH_COMPONENT
||
462 base_format
== GL_DEPTH_STENCIL_EXT
)
463 return I915_TILING_Y
;
465 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
467 /* If the width is much smaller than a tile, don't bother tiling. */
468 if (minimum_pitch
< 64)
469 return I915_TILING_NONE
;
471 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
472 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
473 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
474 mt
->total_width
, mt
->total_height
);
475 return I915_TILING_NONE
;
478 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
480 return I915_TILING_X
;
482 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
483 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
485 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
486 * all the way back to 965, but is explicitly permitted on Gen7.
488 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
489 return I915_TILING_X
;
491 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
492 * messages), on p64, under the heading "Surface Vertical Alignment":
494 * This field must be set to VALIGN_4 for all tiled Y Render Target
497 * So if the surface is renderable and uses a vertical alignment of 2,
498 * force it to be X tiled. This is somewhat conservative (it's possible
499 * that the client won't ever render to this surface), but it's difficult
500 * to know that ahead of time. And besides, since we use a vertical
501 * alignment of 4 as often as we can, this shouldn't happen very often.
503 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
504 brw
->format_supported_as_render_target
[format
]) {
505 return I915_TILING_X
;
508 return I915_TILING_Y
| I915_TILING_X
;
513 * Choose an appropriate uncompressed format for a requested
514 * compressed format, if unsupported.
517 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
519 /* No need to lower ETC formats on these platforms,
520 * they are supported natively.
522 if (brw
->gen
>= 8 || brw
->is_baytrail
)
526 case MESA_FORMAT_ETC1_RGB8
:
527 return MESA_FORMAT_R8G8B8X8_UNORM
;
528 case MESA_FORMAT_ETC2_RGB8
:
529 return MESA_FORMAT_R8G8B8X8_UNORM
;
530 case MESA_FORMAT_ETC2_SRGB8
:
531 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
532 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
533 return MESA_FORMAT_B8G8R8A8_SRGB
;
534 case MESA_FORMAT_ETC2_RGBA8_EAC
:
535 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
536 return MESA_FORMAT_R8G8B8A8_UNORM
;
537 case MESA_FORMAT_ETC2_R11_EAC
:
538 return MESA_FORMAT_R_UNORM16
;
539 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
540 return MESA_FORMAT_R_SNORM16
;
541 case MESA_FORMAT_ETC2_RG11_EAC
:
542 return MESA_FORMAT_R16G16_UNORM
;
543 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
544 return MESA_FORMAT_R16G16_SNORM
;
546 /* Non ETC1 / ETC2 format */
552 struct intel_mipmap_tree
*
553 intel_miptree_create(struct brw_context
*brw
,
561 bool expect_accelerated_upload
,
563 enum intel_miptree_tiling_mode requested_tiling
)
565 struct intel_mipmap_tree
*mt
;
566 mesa_format tex_format
= format
;
567 mesa_format etc_format
= MESA_FORMAT_NONE
;
568 GLuint total_width
, total_height
;
570 format
= intel_lower_compressed_format(brw
, format
);
572 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
574 mt
= intel_miptree_create_layout(brw
, target
, format
,
575 first_level
, last_level
, width0
,
579 * pitch == 0 || height == 0 indicates the null texture
581 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
582 intel_miptree_release(&mt
);
586 total_width
= mt
->total_width
;
587 total_height
= mt
->total_height
;
589 if (format
== MESA_FORMAT_S_UINT8
) {
590 /* Align to size of W tile, 64x64. */
591 total_width
= ALIGN(total_width
, 64);
592 total_height
= ALIGN(total_height
, 64);
595 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
596 num_samples
, requested_tiling
,
600 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
602 mt
->tiling
= I915_TILING_Y
;
608 mt
->etc_format
= etc_format
;
609 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
610 total_width
, total_height
, mt
->cpp
,
612 (expect_accelerated_upload
?
613 BO_ALLOC_FOR_RENDER
: 0));
616 /* If the BO is too large to fit in the aperture, we need to use the
617 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
618 * so we need to fall back to X.
620 if (y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
621 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
622 mt
->total_width
, mt
->total_height
);
624 mt
->tiling
= I915_TILING_X
;
625 drm_intel_bo_unreference(mt
->bo
);
626 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
627 total_width
, total_height
, mt
->cpp
,
629 (expect_accelerated_upload
?
630 BO_ALLOC_FOR_RENDER
: 0));
637 intel_miptree_release(&mt
);
642 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
643 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
644 intel_miptree_release(&mt
);
649 /* If this miptree is capable of supporting fast color clears, set
650 * fast_clear_state appropriately to ensure that fast clears will occur.
651 * Allocation of the MCS miptree will be deferred until the first fast
652 * clear actually occurs.
654 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
655 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
660 struct intel_mipmap_tree
*
661 intel_miptree_create_for_bo(struct brw_context
*brw
,
669 struct intel_mipmap_tree
*mt
;
670 uint32_t tiling
, swizzle
;
672 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
674 /* Nothing will be able to use this miptree with the BO if the offset isn't
677 if (tiling
!= I915_TILING_NONE
)
678 assert(offset
% 4096 == 0);
680 /* miptrees can't handle negative pitch. If you need flipping of images,
681 * that's outside of the scope of the mt.
685 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
688 true, 0 /* num_samples */);
694 drm_intel_bo_reference(bo
);
704 * For a singlesample renderbuffer, this simply wraps the given BO with a
707 * For a multisample renderbuffer, this wraps the window system's
708 * (singlesample) BO with a singlesample miptree attached to the
709 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
710 * that will contain the actual rendering (which is lazily resolved to
711 * irb->singlesample_mt).
714 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
715 struct intel_renderbuffer
*irb
,
717 uint32_t width
, uint32_t height
,
720 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
721 struct intel_mipmap_tree
*multisample_mt
= NULL
;
722 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
723 mesa_format format
= rb
->Format
;
724 int num_samples
= rb
->NumSamples
;
726 /* Only the front and back buffers, which are color buffers, are allocated
727 * through the image loader.
729 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
730 _mesa_get_format_base_format(format
) == GL_RGBA
);
732 singlesample_mt
= intel_miptree_create_for_bo(intel
,
739 if (!singlesample_mt
)
742 /* If this miptree is capable of supporting fast color clears, set
743 * mcs_state appropriately to ensure that fast clears will occur.
744 * Allocation of the MCS miptree will be deferred until the first fast
745 * clear actually occurs.
747 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
748 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
750 if (num_samples
== 0) {
751 intel_miptree_release(&irb
->mt
);
752 irb
->mt
= singlesample_mt
;
754 assert(!irb
->singlesample_mt
);
756 intel_miptree_release(&irb
->singlesample_mt
);
757 irb
->singlesample_mt
= singlesample_mt
;
760 irb
->mt
->logical_width0
!= width
||
761 irb
->mt
->logical_height0
!= height
) {
762 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
770 irb
->need_downsample
= false;
771 intel_miptree_release(&irb
->mt
);
772 irb
->mt
= multisample_mt
;
778 intel_miptree_release(&irb
->singlesample_mt
);
779 intel_miptree_release(&irb
->mt
);
783 struct intel_mipmap_tree
*
784 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
788 uint32_t num_samples
)
790 struct intel_mipmap_tree
*mt
;
793 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
795 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
796 width
, height
, depth
, true, num_samples
,
797 INTEL_MIPTREE_TILING_ANY
);
801 if (brw_is_hiz_depth_format(brw
, format
)) {
802 ok
= intel_miptree_alloc_hiz(brw
, mt
);
810 intel_miptree_release(&mt
);
815 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
816 struct intel_mipmap_tree
*src
)
821 intel_miptree_release(dst
);
825 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
833 intel_miptree_release(struct intel_mipmap_tree
**mt
)
838 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
839 if (--(*mt
)->refcount
<= 0) {
842 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
844 drm_intel_bo_unreference((*mt
)->bo
);
845 intel_miptree_release(&(*mt
)->stencil_mt
);
846 intel_miptree_release(&(*mt
)->hiz_mt
);
847 intel_miptree_release(&(*mt
)->mcs_mt
);
848 intel_resolve_map_clear(&(*mt
)->hiz_map
);
850 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
851 free((*mt
)->level
[i
].slice
);
860 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
861 int *width
, int *height
, int *depth
)
863 switch (image
->TexObject
->Target
) {
864 case GL_TEXTURE_1D_ARRAY
:
865 *width
= image
->Width
;
867 *depth
= image
->Height
;
870 *width
= image
->Width
;
871 *height
= image
->Height
;
872 *depth
= image
->Depth
;
878 * Can the image be pulled into a unified mipmap tree? This mirrors
879 * the completeness test in a lot of ways.
881 * Not sure whether I want to pass gl_texture_image here.
884 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
885 struct gl_texture_image
*image
)
887 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
888 GLuint level
= intelImage
->base
.Base
.Level
;
889 int width
, height
, depth
;
891 /* glTexImage* choose the texture object based on the target passed in, and
892 * objects can't change targets over their lifetimes, so this should be
895 assert(image
->TexObject
->Target
== mt
->target
);
897 mesa_format mt_format
= mt
->format
;
898 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
899 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
900 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
901 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
902 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
903 mt_format
= mt
->etc_format
;
905 if (image
->TexFormat
!= mt_format
)
908 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
910 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
913 int level_depth
= mt
->level
[level
].depth
;
914 if (mt
->num_samples
> 1) {
915 switch (mt
->msaa_layout
) {
916 case INTEL_MSAA_LAYOUT_NONE
:
917 case INTEL_MSAA_LAYOUT_IMS
:
919 case INTEL_MSAA_LAYOUT_UMS
:
920 case INTEL_MSAA_LAYOUT_CMS
:
921 level_depth
/= mt
->num_samples
;
926 /* Test image dimensions against the base level image adjusted for
927 * minification. This will also catch images not present in the
928 * tree, changed targets, etc.
930 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
931 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
932 depth
!= level_depth
) {
936 if (image
->NumSamples
!= mt
->num_samples
)
944 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
946 GLuint x
, GLuint y
, GLuint d
)
948 mt
->level
[level
].depth
= d
;
949 mt
->level
[level
].level_x
= x
;
950 mt
->level
[level
].level_y
= y
;
952 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
955 assert(mt
->level
[level
].slice
== NULL
);
957 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
958 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
959 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
964 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
965 GLuint level
, GLuint img
,
968 if (img
== 0 && level
== 0)
969 assert(x
== 0 && y
== 0);
971 assert(img
< mt
->level
[level
].depth
);
973 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
974 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
976 DBG("%s level %d img %d pos %d,%d\n",
977 __FUNCTION__
, level
, img
,
978 mt
->level
[level
].slice
[img
].x_offset
,
979 mt
->level
[level
].slice
[img
].y_offset
);
983 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
984 GLuint level
, GLuint slice
,
985 GLuint
*x
, GLuint
*y
)
987 assert(slice
< mt
->level
[level
].depth
);
989 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
990 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
994 * This function computes masks that may be used to select the bits of the X
995 * and Y coordinates that indicate the offset within a tile. If the BO is
996 * untiled, the masks are set to 0.
999 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1000 uint32_t *mask_x
, uint32_t *mask_y
,
1001 bool map_stencil_as_y_tiled
)
1004 uint32_t tiling
= mt
->tiling
;
1006 if (map_stencil_as_y_tiled
)
1007 tiling
= I915_TILING_Y
;
1011 unreachable("not reached");
1012 case I915_TILING_NONE
:
1013 *mask_x
= *mask_y
= 0;
1016 *mask_x
= 512 / cpp
- 1;
1020 *mask_x
= 128 / cpp
- 1;
1027 * Compute the offset (in bytes) from the start of the BO to the given x
1028 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1029 * multiples of the tile size.
1032 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1033 uint32_t x
, uint32_t y
,
1034 bool map_stencil_as_y_tiled
)
1037 uint32_t pitch
= mt
->pitch
;
1038 uint32_t tiling
= mt
->tiling
;
1040 if (map_stencil_as_y_tiled
) {
1041 tiling
= I915_TILING_Y
;
1043 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1044 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1045 * the resulting surface is twice the pitch of the original miptree,
1046 * since each row in the Y-tiled view corresponds to two rows in the
1047 * actual W-tiled surface. So we need to correct the pitch before
1048 * computing the offsets.
1055 unreachable("not reached");
1056 case I915_TILING_NONE
:
1057 return y
* pitch
+ x
* cpp
;
1059 assert((x
% (512 / cpp
)) == 0);
1060 assert((y
% 8) == 0);
1061 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1063 assert((x
% (128 / cpp
)) == 0);
1064 assert((y
% 32) == 0);
1065 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1070 * Rendering with tiled buffers requires that the base address of the buffer
1071 * be aligned to a page boundary. For renderbuffers, and sometimes with
1072 * textures, we may want the surface to point at a texture image level that
1073 * isn't at a page boundary.
1075 * This function returns an appropriately-aligned base offset
1076 * according to the tiling restrictions, plus any required x/y offset
1080 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1081 GLuint level
, GLuint slice
,
1086 uint32_t mask_x
, mask_y
;
1088 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1089 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1091 *tile_x
= x
& mask_x
;
1092 *tile_y
= y
& mask_y
;
1094 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1098 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1099 struct intel_mipmap_tree
*dst_mt
,
1100 struct intel_mipmap_tree
*src_mt
,
1107 int src_stride
, dst_stride
;
1108 int cpp
= dst_mt
->cpp
;
1110 intel_miptree_map(brw
, src_mt
,
1114 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1117 intel_miptree_map(brw
, dst_mt
,
1121 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1125 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1126 _mesa_get_format_name(src_mt
->format
),
1127 src_mt
, src
, src_stride
,
1128 _mesa_get_format_name(dst_mt
->format
),
1129 dst_mt
, dst
, dst_stride
,
1132 int row_size
= cpp
* width
;
1133 if (src_stride
== row_size
&&
1134 dst_stride
== row_size
) {
1135 memcpy(dst
, src
, row_size
* height
);
1137 for (int i
= 0; i
< height
; i
++) {
1138 memcpy(dst
, src
, row_size
);
1144 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1145 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1147 /* Don't forget to copy the stencil data over, too. We could have skipped
1148 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1149 * shuffling the two data sources in/out of temporary storage instead of
1150 * the direct mapping we get this way.
1152 if (dst_mt
->stencil_mt
) {
1153 assert(src_mt
->stencil_mt
);
1154 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1155 level
, slice
, width
, height
);
1160 intel_miptree_copy_slice(struct brw_context
*brw
,
1161 struct intel_mipmap_tree
*dst_mt
,
1162 struct intel_mipmap_tree
*src_mt
,
1168 mesa_format format
= src_mt
->format
;
1169 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1170 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1178 assert(depth
< src_mt
->level
[level
].depth
);
1179 assert(src_mt
->format
== dst_mt
->format
);
1181 if (dst_mt
->compressed
) {
1182 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1183 width
= ALIGN(width
, dst_mt
->align_w
);
1186 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1187 * below won't apply since we can't do the depth's Y tiling or the
1188 * stencil's W tiling in the blitter.
1190 if (src_mt
->stencil_mt
) {
1191 intel_miptree_copy_slice_sw(brw
,
1198 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1199 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1200 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1202 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1203 _mesa_get_format_name(src_mt
->format
),
1204 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1205 _mesa_get_format_name(dst_mt
->format
),
1206 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1209 if (!intel_miptree_blit(brw
,
1210 src_mt
, level
, slice
, 0, 0, false,
1211 dst_mt
, level
, slice
, 0, 0, false,
1212 width
, height
, GL_COPY
)) {
1213 perf_debug("miptree validate blit for %s failed\n",
1214 _mesa_get_format_name(format
));
1216 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1222 * Copies the image's current data to the given miptree, and associates that
1223 * miptree with the image.
1225 * If \c invalidate is true, then the actual image data does not need to be
1226 * copied, but the image still needs to be associated to the new miptree (this
1227 * is set to true if we're about to clear the image).
1230 intel_miptree_copy_teximage(struct brw_context
*brw
,
1231 struct intel_texture_image
*intelImage
,
1232 struct intel_mipmap_tree
*dst_mt
,
1235 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1236 struct intel_texture_object
*intel_obj
=
1237 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1238 int level
= intelImage
->base
.Base
.Level
;
1239 int face
= intelImage
->base
.Base
.Face
;
1240 GLuint depth
= intelImage
->base
.Base
.Depth
;
1243 for (int slice
= 0; slice
< depth
; slice
++) {
1244 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1248 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1249 intel_obj
->needs_validate
= true;
1253 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1254 struct intel_mipmap_tree
*mt
,
1257 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1258 assert(mt
->mcs_mt
== NULL
);
1260 /* Choose the correct format for the MCS buffer. All that really matters
1261 * is that we allocate the right buffer size, since we'll always be
1262 * accessing this miptree using MCS-specific hardware mechanisms, which
1263 * infer the correct format based on num_samples.
1266 switch (num_samples
) {
1269 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1272 format
= MESA_FORMAT_R_UNORM8
;
1275 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1276 * for each sample, plus 8 padding bits).
1278 format
= MESA_FORMAT_R_UINT32
;
1281 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1284 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1286 * "The MCS surface must be stored as Tile Y."
1288 mt
->mcs_mt
= intel_miptree_create(brw
,
1294 mt
->logical_height0
,
1297 0 /* num_samples */,
1298 INTEL_MIPTREE_TILING_Y
);
1300 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1302 * When MCS buffer is enabled and bound to MSRT, it is required that it
1303 * is cleared prior to any rendering.
1305 * Since we don't use the MCS buffer for any purpose other than rendering,
1306 * it makes sense to just clear it immediately upon allocation.
1308 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1310 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1311 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1312 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1313 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1320 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1321 struct intel_mipmap_tree
*mt
)
1323 assert(mt
->mcs_mt
== NULL
);
1325 /* The format of the MCS buffer is opaque to the driver; all that matters
1326 * is that we get its size and pitch right. We'll pretend that the format
1327 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1328 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1329 * the block width and then a further factor of 4. Since an MCS tile
1330 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1331 * we'll need to scale the height down by the block height and then a
1332 * further factor of 8.
1334 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1335 unsigned block_width_px
;
1336 unsigned block_height
;
1337 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1338 unsigned width_divisor
= block_width_px
* 4;
1339 unsigned height_divisor
= block_height
* 8;
1340 unsigned mcs_width
=
1341 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1342 unsigned mcs_height
=
1343 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1344 assert(mt
->logical_depth0
== 1);
1345 mt
->mcs_mt
= intel_miptree_create(brw
,
1354 0 /* num_samples */,
1355 INTEL_MIPTREE_TILING_Y
);
1362 * Helper for intel_miptree_alloc_hiz() that sets
1363 * \c mt->level[level].has_hiz. Return true if and only if
1364 * \c has_hiz was set.
1367 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1368 struct intel_mipmap_tree
*mt
,
1373 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1374 uint32_t width
= minify(mt
->physical_width0
, level
);
1375 uint32_t height
= minify(mt
->physical_height0
, level
);
1377 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1378 * and the height is 4 aligned. This allows our HiZ support
1379 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1380 * we can grow the width & height to allow the HiZ op to
1381 * force the proper size alignments.
1383 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1384 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1389 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1390 mt
->level
[level
].has_hiz
= true;
1397 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1398 struct intel_mipmap_tree
*mt
)
1400 assert(mt
->hiz_mt
== NULL
);
1401 mt
->hiz_mt
= intel_miptree_create(brw
,
1407 mt
->logical_height0
,
1411 INTEL_MIPTREE_TILING_ANY
);
1416 /* Mark that all slices need a HiZ resolve. */
1417 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1418 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1421 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1422 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1423 exec_node_init(&m
->link
);
1426 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1428 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1436 * Does the miptree slice have hiz enabled?
1439 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1441 intel_miptree_check_level_layer(mt
, level
, 0);
1442 return mt
->level
[level
].has_hiz
;
1446 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1450 if (!intel_miptree_level_has_hiz(mt
, level
))
1453 intel_resolve_map_set(&mt
->hiz_map
,
1454 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1459 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1463 if (!intel_miptree_level_has_hiz(mt
, level
))
1466 intel_resolve_map_set(&mt
->hiz_map
,
1467 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1471 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1475 uint32_t end_layer
= mt
->level
[level
].depth
;
1477 for (layer
= 0; layer
< end_layer
; layer
++) {
1478 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1483 intel_miptree_slice_resolve(struct brw_context
*brw
,
1484 struct intel_mipmap_tree
*mt
,
1487 enum gen6_hiz_op need
)
1489 intel_miptree_check_level_layer(mt
, level
, layer
);
1491 struct intel_resolve_map
*item
=
1492 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1494 if (!item
|| item
->need
!= need
)
1497 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1498 intel_resolve_map_remove(item
);
1503 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1504 struct intel_mipmap_tree
*mt
,
1508 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1509 GEN6_HIZ_OP_HIZ_RESOLVE
);
1513 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1514 struct intel_mipmap_tree
*mt
,
1518 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1519 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1523 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1524 struct intel_mipmap_tree
*mt
,
1525 enum gen6_hiz_op need
)
1527 bool did_resolve
= false;
1529 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1530 if (map
->need
!= need
)
1533 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1534 intel_resolve_map_remove(map
);
1542 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1543 struct intel_mipmap_tree
*mt
)
1545 return intel_miptree_all_slices_resolve(brw
, mt
,
1546 GEN6_HIZ_OP_HIZ_RESOLVE
);
1550 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1551 struct intel_mipmap_tree
*mt
)
1553 return intel_miptree_all_slices_resolve(brw
, mt
,
1554 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1559 intel_miptree_resolve_color(struct brw_context
*brw
,
1560 struct intel_mipmap_tree
*mt
)
1562 switch (mt
->fast_clear_state
) {
1563 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1564 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1565 /* No resolve needed */
1567 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1568 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1569 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1570 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1571 brw_meta_resolve_color(brw
, mt
);
1578 * Make it possible to share the BO backing the given miptree with another
1579 * process or another miptree.
1581 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1582 * then discard the MCS buffer, if present. We also set the fast_clear_state
1583 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1584 * allocated in the future.
1587 intel_miptree_make_shareable(struct brw_context
*brw
,
1588 struct intel_mipmap_tree
*mt
)
1590 /* MCS buffers are also used for multisample buffers, but we can't resolve
1591 * away a multisample MCS buffer because it's an integral part of how the
1592 * pixel data is stored. Fortunately this code path should never be
1593 * reached for multisample buffers.
1595 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1598 intel_miptree_resolve_color(brw
, mt
);
1599 intel_miptree_release(&mt
->mcs_mt
);
1600 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1606 * \brief Get pointer offset into stencil buffer.
1608 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1609 * must decode the tile's layout in software.
1612 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1614 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1616 * Even though the returned offset is always positive, the return type is
1618 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1619 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1622 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1624 uint32_t tile_size
= 4096;
1625 uint32_t tile_width
= 64;
1626 uint32_t tile_height
= 64;
1627 uint32_t row_size
= 64 * stride
;
1629 uint32_t tile_x
= x
/ tile_width
;
1630 uint32_t tile_y
= y
/ tile_height
;
1632 /* The byte's address relative to the tile's base addres. */
1633 uint32_t byte_x
= x
% tile_width
;
1634 uint32_t byte_y
= y
% tile_height
;
1636 uintptr_t u
= tile_y
* row_size
1637 + tile_x
* tile_size
1638 + 512 * (byte_x
/ 8)
1640 + 32 * ((byte_y
/ 4) % 2)
1641 + 16 * ((byte_x
/ 4) % 2)
1642 + 8 * ((byte_y
/ 2) % 2)
1643 + 4 * ((byte_x
/ 2) % 2)
1648 /* adjust for bit6 swizzling */
1649 if (((byte_x
/ 8) % 2) == 1) {
1650 if (((byte_y
/ 8) % 2) == 0) {
1662 intel_miptree_updownsample(struct brw_context
*brw
,
1663 struct intel_mipmap_tree
*src
,
1664 struct intel_mipmap_tree
*dst
)
1667 brw_blorp_blit_miptrees(brw
,
1668 src
, 0 /* level */, 0 /* layer */,
1669 dst
, 0 /* level */, 0 /* layer */,
1671 src
->logical_width0
, src
->logical_height0
,
1673 dst
->logical_width0
, dst
->logical_height0
,
1674 GL_NEAREST
, false, false /*mirror x, y*/);
1675 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1676 brw_meta_stencil_updownsample(brw
, src
, dst
);
1678 brw_meta_updownsample(brw
, src
, dst
);
1681 if (src
->stencil_mt
) {
1682 if (brw
->gen
>= 8) {
1683 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1687 brw_blorp_blit_miptrees(brw
,
1688 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1689 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1691 src
->logical_width0
, src
->logical_height0
,
1693 dst
->logical_width0
, dst
->logical_height0
,
1694 GL_NEAREST
, false, false /*mirror x, y*/);
1699 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1701 /* CPU accesses to color buffers don't understand fast color clears, so
1702 * resolve any pending fast color clears before we map.
1704 intel_miptree_resolve_color(brw
, mt
);
1706 drm_intel_bo
*bo
= mt
->bo
;
1708 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1709 intel_batchbuffer_flush(brw
);
1711 if (mt
->tiling
!= I915_TILING_NONE
)
1712 brw_bo_map_gtt(brw
, bo
, "miptree");
1714 brw_bo_map(brw
, bo
, true, "miptree");
1720 intel_miptree_unmap_raw(struct brw_context
*brw
,
1721 struct intel_mipmap_tree
*mt
)
1723 drm_intel_bo_unmap(mt
->bo
);
1727 intel_miptree_map_gtt(struct brw_context
*brw
,
1728 struct intel_mipmap_tree
*mt
,
1729 struct intel_miptree_map
*map
,
1730 unsigned int level
, unsigned int slice
)
1732 unsigned int bw
, bh
;
1734 unsigned int image_x
, image_y
;
1738 /* For compressed formats, the stride is the number of bytes per
1739 * row of blocks. intel_miptree_get_image_offset() already does
1742 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1743 assert(y
% bh
== 0);
1746 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1751 /* Note that in the case of cube maps, the caller must have passed the
1752 * slice number referencing the face.
1754 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1758 map
->stride
= mt
->pitch
;
1759 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1762 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1763 map
->x
, map
->y
, map
->w
, map
->h
,
1764 mt
, _mesa_get_format_name(mt
->format
),
1765 x
, y
, map
->ptr
, map
->stride
);
1769 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1770 struct intel_mipmap_tree
*mt
,
1771 struct intel_miptree_map
*map
,
1775 intel_miptree_unmap_raw(brw
, mt
);
1779 intel_miptree_map_blit(struct brw_context
*brw
,
1780 struct intel_mipmap_tree
*mt
,
1781 struct intel_miptree_map
*map
,
1782 unsigned int level
, unsigned int slice
)
1784 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1788 INTEL_MIPTREE_TILING_NONE
);
1790 fprintf(stderr
, "Failed to allocate blit temporary\n");
1793 map
->stride
= map
->mt
->pitch
;
1795 if (!intel_miptree_blit(brw
,
1797 map
->x
, map
->y
, false,
1800 map
->w
, map
->h
, GL_COPY
)) {
1801 fprintf(stderr
, "Failed to blit\n");
1805 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1807 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1808 map
->x
, map
->y
, map
->w
, map
->h
,
1809 mt
, _mesa_get_format_name(mt
->format
),
1810 level
, slice
, map
->ptr
, map
->stride
);
1815 intel_miptree_release(&map
->mt
);
1821 intel_miptree_unmap_blit(struct brw_context
*brw
,
1822 struct intel_mipmap_tree
*mt
,
1823 struct intel_miptree_map
*map
,
1827 struct gl_context
*ctx
= &brw
->ctx
;
1829 intel_miptree_unmap_raw(brw
, map
->mt
);
1831 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1832 bool ok
= intel_miptree_blit(brw
,
1836 map
->x
, map
->y
, false,
1837 map
->w
, map
->h
, GL_COPY
);
1838 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1841 intel_miptree_release(&map
->mt
);
1845 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1847 #if defined(USE_SSE41)
1849 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1850 struct intel_mipmap_tree
*mt
,
1851 struct intel_miptree_map
*map
,
1852 unsigned int level
, unsigned int slice
)
1854 assert(map
->mode
& GL_MAP_READ_BIT
);
1855 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1857 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1858 map
->x
, map
->y
, map
->w
, map
->h
,
1859 mt
, _mesa_get_format_name(mt
->format
),
1860 level
, slice
, map
->ptr
, map
->stride
);
1862 /* Map the original image */
1865 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1869 void *src
= intel_miptree_map_raw(brw
, mt
);
1872 src
+= image_y
* mt
->pitch
;
1873 src
+= image_x
* mt
->cpp
;
1875 /* Due to the pixel offsets for the particular image being mapped, our
1876 * src pointer may not be 16-byte aligned. However, if the pitch is
1877 * divisible by 16, then the amount by which it's misaligned will remain
1878 * consistent from row to row.
1880 assert((mt
->pitch
% 16) == 0);
1881 const int misalignment
= ((uintptr_t) src
) & 15;
1883 /* Create an untiled temporary buffer for the mapping. */
1884 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1886 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1888 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
1889 /* Offset the destination so it has the same misalignment as src. */
1890 map
->ptr
= map
->buffer
+ misalignment
;
1892 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1894 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1895 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1896 void *src_ptr
= src
+ y
* mt
->pitch
;
1898 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1901 intel_miptree_unmap_raw(brw
, mt
);
1905 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1906 struct intel_mipmap_tree
*mt
,
1907 struct intel_miptree_map
*map
,
1911 _mesa_align_free(map
->buffer
);
1918 intel_miptree_map_s8(struct brw_context
*brw
,
1919 struct intel_mipmap_tree
*mt
,
1920 struct intel_miptree_map
*map
,
1921 unsigned int level
, unsigned int slice
)
1923 map
->stride
= map
->w
;
1924 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1928 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1929 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1930 * invalidate is set, since we'll be writing the whole rectangle from our
1931 * temporary buffer back out.
1933 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1934 uint8_t *untiled_s8_map
= map
->ptr
;
1935 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1936 unsigned int image_x
, image_y
;
1938 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1940 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1941 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1942 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1943 x
+ image_x
+ map
->x
,
1944 y
+ image_y
+ map
->y
,
1945 brw
->has_swizzling
);
1946 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1950 intel_miptree_unmap_raw(brw
, mt
);
1952 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1953 map
->x
, map
->y
, map
->w
, map
->h
,
1954 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1956 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1957 map
->x
, map
->y
, map
->w
, map
->h
,
1958 mt
, map
->ptr
, map
->stride
);
1963 intel_miptree_unmap_s8(struct brw_context
*brw
,
1964 struct intel_mipmap_tree
*mt
,
1965 struct intel_miptree_map
*map
,
1969 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1970 unsigned int image_x
, image_y
;
1971 uint8_t *untiled_s8_map
= map
->ptr
;
1972 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1974 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1976 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1977 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1978 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1981 brw
->has_swizzling
);
1982 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1986 intel_miptree_unmap_raw(brw
, mt
);
1993 intel_miptree_map_etc(struct brw_context
*brw
,
1994 struct intel_mipmap_tree
*mt
,
1995 struct intel_miptree_map
*map
,
1999 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2000 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2001 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2004 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2005 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2007 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2008 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2009 map
->w
, map
->h
, 1));
2010 map
->ptr
= map
->buffer
;
2014 intel_miptree_unmap_etc(struct brw_context
*brw
,
2015 struct intel_mipmap_tree
*mt
,
2016 struct intel_miptree_map
*map
,
2022 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2027 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2028 + image_y
* mt
->pitch
2029 + image_x
* mt
->cpp
;
2031 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2032 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2033 map
->ptr
, map
->stride
,
2036 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2037 map
->ptr
, map
->stride
,
2038 map
->w
, map
->h
, mt
->etc_format
);
2040 intel_miptree_unmap_raw(brw
, mt
);
2045 * Mapping function for packed depth/stencil miptrees backed by real separate
2046 * miptrees for depth and stencil.
2048 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2049 * separate from the depth buffer. Yet at the GL API level, we have to expose
2050 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2051 * be able to map that memory for texture storage and glReadPixels-type
2052 * operations. We give Mesa core that access by mallocing a temporary and
2053 * copying the data between the actual backing store and the temporary.
2056 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2057 struct intel_mipmap_tree
*mt
,
2058 struct intel_miptree_map
*map
,
2059 unsigned int level
, unsigned int slice
)
2061 struct intel_mipmap_tree
*z_mt
= mt
;
2062 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2063 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2064 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2066 map
->stride
= map
->w
* packed_bpp
;
2067 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2071 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2072 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2073 * invalidate is set, since we'll be writing the whole rectangle from our
2074 * temporary buffer back out.
2076 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2077 uint32_t *packed_map
= map
->ptr
;
2078 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2079 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2080 unsigned int s_image_x
, s_image_y
;
2081 unsigned int z_image_x
, z_image_y
;
2083 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2084 &s_image_x
, &s_image_y
);
2085 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2086 &z_image_x
, &z_image_y
);
2088 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2089 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2090 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2091 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2094 brw
->has_swizzling
);
2095 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2097 (map_x
+ z_image_x
));
2098 uint8_t s
= s_map
[s_offset
];
2099 uint32_t z
= z_map
[z_offset
];
2101 if (map_z32f_x24s8
) {
2102 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2103 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2105 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2110 intel_miptree_unmap_raw(brw
, s_mt
);
2111 intel_miptree_unmap_raw(brw
, z_mt
);
2113 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2115 map
->x
, map
->y
, map
->w
, map
->h
,
2116 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2117 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2118 map
->ptr
, map
->stride
);
2120 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2121 map
->x
, map
->y
, map
->w
, map
->h
,
2122 mt
, map
->ptr
, map
->stride
);
2127 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2128 struct intel_mipmap_tree
*mt
,
2129 struct intel_miptree_map
*map
,
2133 struct intel_mipmap_tree
*z_mt
= mt
;
2134 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2135 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2137 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2138 uint32_t *packed_map
= map
->ptr
;
2139 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2140 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2141 unsigned int s_image_x
, s_image_y
;
2142 unsigned int z_image_x
, z_image_y
;
2144 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2145 &s_image_x
, &s_image_y
);
2146 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2147 &z_image_x
, &z_image_y
);
2149 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2150 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2151 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2152 x
+ s_image_x
+ map
->x
,
2153 y
+ s_image_y
+ map
->y
,
2154 brw
->has_swizzling
);
2155 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2157 (x
+ z_image_x
+ map
->x
));
2159 if (map_z32f_x24s8
) {
2160 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2161 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2163 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2164 s_map
[s_offset
] = packed
>> 24;
2165 z_map
[z_offset
] = packed
;
2170 intel_miptree_unmap_raw(brw
, s_mt
);
2171 intel_miptree_unmap_raw(brw
, z_mt
);
2173 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2175 map
->x
, map
->y
, map
->w
, map
->h
,
2176 z_mt
, _mesa_get_format_name(z_mt
->format
),
2177 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2178 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2179 map
->ptr
, map
->stride
);
2186 * Create and attach a map to the miptree at (level, slice). Return the
2189 static struct intel_miptree_map
*
2190 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2199 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2204 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2205 mt
->level
[level
].slice
[slice
].map
= map
;
2217 * Release the map at (level, slice).
2220 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2224 struct intel_miptree_map
**map
;
2226 map
= &mt
->level
[level
].slice
[slice
].map
;
2232 can_blit_slice(struct intel_mipmap_tree
*mt
,
2233 unsigned int level
, unsigned int slice
)
2237 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2238 if (image_x
>= 32768 || image_y
>= 32768)
2241 if (mt
->pitch
>= 32768)
2248 intel_miptree_map(struct brw_context
*brw
,
2249 struct intel_mipmap_tree
*mt
,
2260 struct intel_miptree_map
*map
;
2262 assert(mt
->num_samples
<= 1);
2264 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2271 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2272 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2273 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2276 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2277 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2278 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2279 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2280 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2281 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2282 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2284 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2285 else if (brw
->has_llc
&&
2286 !(mode
& GL_MAP_WRITE_BIT
) &&
2288 (mt
->tiling
== I915_TILING_X
||
2289 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2290 can_blit_slice(mt
, level
, slice
)) {
2291 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2292 } else if (mt
->tiling
!= I915_TILING_NONE
&&
2293 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2294 assert(can_blit_slice(mt
, level
, slice
));
2295 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2296 #if defined(USE_SSE41)
2297 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2298 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2301 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2304 *out_ptr
= map
->ptr
;
2305 *out_stride
= map
->stride
;
2307 if (map
->ptr
== NULL
)
2308 intel_miptree_release_map(mt
, level
, slice
);
2312 intel_miptree_unmap(struct brw_context
*brw
,
2313 struct intel_mipmap_tree
*mt
,
2317 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2319 assert(mt
->num_samples
<= 1);
2324 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2325 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2327 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2328 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2329 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2330 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2331 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2332 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2333 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2334 } else if (map
->mt
) {
2335 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2336 #if defined(USE_SSE41)
2337 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2338 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2341 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2344 intel_miptree_release_map(mt
, level
, slice
);