1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 target_to_target(GLenum target
)
54 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
55 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
56 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
57 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
58 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
59 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
60 return GL_TEXTURE_CUBE_MAP_ARB
;
68 * Determine which MSAA layout should be used by the MSAA surface being
69 * created, based on the chip generation and the surface type.
71 static enum intel_msaa_layout
72 compute_msaa_layout(struct brw_context
*brw
, gl_format format
, GLenum target
)
74 struct intel_context
*intel
= &brw
->intel
;
75 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
84 return INTEL_MSAA_LAYOUT_IMS
;
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (_mesa_get_format_datatype(format
) == GL_INT
) {
98 /* TODO: is this workaround needed for future chipsets? */
99 assert(intel
->gen
== 7);
100 return INTEL_MSAA_LAYOUT_UMS
;
102 /* For now, if we're going to be texturing from this surface,
103 * force UMS, so that the shader doesn't have to do different things
104 * based on whether there's a multisample control surface needing sampled first.
105 * We can't just blindly read the MCS surface in all cases because:
107 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
109 * If this field is disabled and the sampling engine <ld_mcs> message
110 * is issued on this surface, the MCS surface may be accessed. Software
111 * must ensure that the surface is defined to avoid GTT errors.
113 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
114 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
115 return INTEL_MSAA_LAYOUT_UMS
;
117 return INTEL_MSAA_LAYOUT_CMS
;
125 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
126 * scaled-down bitfield representation of the color buffer which is capable of
127 * recording when blocks of the color buffer are equal to the clear value.
128 * This function returns the block size that will be used by the MCS buffer
129 * corresponding to a certain color miptree.
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p327):
134 * The following table describes the RT alignment
148 * This alignment has the following uses:
150 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
151 * buffer contains 128 blocks horizontally and 256 blocks vertically.
153 * - For figuring out alignment restrictions for a fast clear operation. Fast
154 * clear operations must always clear aligned multiples of 16 blocks
155 * horizontally and 32 blocks vertically.
157 * - For scaling down the coordinates sent through the render pipeline during
158 * a fast clear. X coordinates must be scaled down by 8 times the block
159 * width, and Y coordinates by 16 times the block height.
161 * - For scaling down the coordinates sent through the render pipeline during
162 * a "Render Target Resolve" operation. X coordinates must be scaled down
163 * by half the block width, and Y coordinates by half the block height.
166 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
167 struct intel_mipmap_tree
*mt
,
168 unsigned *width_px
, unsigned *height
)
170 switch (mt
->region
->tiling
) {
172 assert(!"Non-MSRT MCS requires X or Y tiling");
173 /* In release builds, fall through */
175 *width_px
= 32 / mt
->cpp
;
179 *width_px
= 64 / mt
->cpp
;
186 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
189 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
190 * beneath the "Fast Color Clear" bullet (p326):
192 * - Support is limited to tiled render targets.
193 * - Support is for non-mip-mapped and non-array surface types only.
195 * And then later, on p327:
197 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
201 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
202 struct intel_mipmap_tree
*mt
)
204 struct intel_context
*intel
= &brw
->intel
;
206 /* MCS support does not exist prior to Gen7 */
210 /* MCS is only supported for color buffers */
211 switch (_mesa_get_format_base_format(mt
->format
)) {
212 case GL_DEPTH_COMPONENT
:
213 case GL_DEPTH_STENCIL
:
214 case GL_STENCIL_INDEX
:
218 if (mt
->region
->tiling
!= I915_TILING_X
&&
219 mt
->region
->tiling
!= I915_TILING_Y
)
221 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
223 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
225 if (mt
->physical_depth0
!= 1)
228 /* There's no point in using an MCS buffer if the surface isn't in a
231 if (!brw
->format_supported_as_render_target
[mt
->format
])
239 * @param for_bo Indicates that the caller is
240 * intel_miptree_create_for_bo(). If true, then do not create
243 struct intel_mipmap_tree
*
244 intel_miptree_create_layout(struct brw_context
*brw
,
255 struct intel_context
*intel
= &brw
->intel
;
256 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
260 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
261 _mesa_lookup_enum_by_nr(target
),
262 _mesa_get_format_name(format
),
263 first_level
, last_level
, mt
);
265 mt
->target
= target_to_target(target
);
267 mt
->first_level
= first_level
;
268 mt
->last_level
= last_level
;
269 mt
->logical_width0
= width0
;
270 mt
->logical_height0
= height0
;
271 mt
->logical_depth0
= depth0
;
272 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
274 /* The cpp is bytes per (1, blockheight)-sized block for compressed
275 * textures. This is why you'll see divides by blockheight all over
278 _mesa_get_format_block_size(format
, &bw
, &bh
);
279 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
280 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
282 mt
->num_samples
= num_samples
;
283 mt
->compressed
= _mesa_is_format_compressed(format
);
284 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
287 if (num_samples
> 1) {
288 /* Adjust width/height/depth for MSAA */
289 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
290 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
291 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
293 * "Any of the other messages (sample*, LOD, load4) used with a
294 * (4x) multisampled surface will in-effect sample a surface with
295 * double the height and width as that indicated in the surface
296 * state. Each pixel position on the original-sized surface is
297 * replaced with a 2x2 of samples with the following arrangement:
302 * Thus, when sampling from a multisampled texture, it behaves as
303 * though the layout in memory for (x,y,sample) is:
305 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
306 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
308 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
309 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
311 * However, the actual layout of multisampled data in memory is:
313 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
314 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
316 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
317 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
319 * This pattern repeats for each 2x2 pixel block.
321 * As a result, when calculating the size of our 4-sample buffer for
322 * an odd width or height, we have to align before scaling up because
323 * sample 3 is in that bottom right 2x2 block.
325 switch (num_samples
) {
327 width0
= ALIGN(width0
, 2) * 2;
328 height0
= ALIGN(height0
, 2) * 2;
331 width0
= ALIGN(width0
, 2) * 4;
332 height0
= ALIGN(height0
, 2) * 2;
335 /* num_samples should already have been quantized to 0, 1, 4, or
341 /* Non-interleaved */
342 depth0
*= num_samples
;
346 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
349 switch (mt
->msaa_layout
) {
350 case INTEL_MSAA_LAYOUT_NONE
:
351 case INTEL_MSAA_LAYOUT_IMS
:
352 mt
->array_spacing_lod0
= false;
354 case INTEL_MSAA_LAYOUT_UMS
:
355 case INTEL_MSAA_LAYOUT_CMS
:
356 mt
->array_spacing_lod0
= true;
360 if (target
== GL_TEXTURE_CUBE_MAP
) {
365 mt
->physical_width0
= width0
;
366 mt
->physical_height0
= height0
;
367 mt
->physical_depth0
= depth0
;
370 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
371 (intel
->must_use_separate_stencil
||
372 (intel
->has_separate_stencil
&&
373 brw_is_hiz_depth_format(brw
, format
)))) {
374 mt
->stencil_mt
= intel_miptree_create(brw
,
384 INTEL_MIPTREE_TILING_ANY
);
385 if (!mt
->stencil_mt
) {
386 intel_miptree_release(&mt
);
390 /* Fix up the Z miptree format for how we're splitting out separate
391 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
393 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
394 mt
->format
= MESA_FORMAT_X8_Z24
;
395 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
396 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
399 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
400 _mesa_get_format_name(mt
->format
));
404 brw_miptree_layout(brw
, mt
);
410 * \brief Helper function for intel_miptree_create().
413 intel_miptree_choose_tiling(struct brw_context
*brw
,
416 uint32_t num_samples
,
417 enum intel_miptree_tiling_mode requested
,
418 struct intel_mipmap_tree
*mt
)
420 struct intel_context
*intel
= &brw
->intel
;
421 if (format
== MESA_FORMAT_S8
) {
422 /* The stencil buffer is W tiled. However, we request from the kernel a
423 * non-tiled buffer because the GTT is incapable of W fencing.
425 return I915_TILING_NONE
;
428 /* Some usages may want only one type of tiling, like depth miptrees (Y
429 * tiled), or temporary BOs for uploading data once (linear).
432 case INTEL_MIPTREE_TILING_ANY
:
434 case INTEL_MIPTREE_TILING_Y
:
435 return I915_TILING_Y
;
436 case INTEL_MIPTREE_TILING_NONE
:
437 return I915_TILING_NONE
;
440 if (num_samples
> 1) {
441 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
444 * [DevSNB+]: For multi-sample render targets, this field must be
445 * 1. MSRTs can only be tiled.
447 * Our usual reason for preferring X tiling (fast blits using the
448 * blitting engine) doesn't apply to MSAA, since we'll generally be
449 * downsampling or upsampling when blitting between the MSAA buffer
450 * and another buffer, and the blitting engine doesn't support that.
451 * So use Y tiling, since it makes better use of the cache.
453 return I915_TILING_Y
;
456 GLenum base_format
= _mesa_get_format_base_format(format
);
457 if (base_format
== GL_DEPTH_COMPONENT
||
458 base_format
== GL_DEPTH_STENCIL_EXT
)
459 return I915_TILING_Y
;
461 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
463 /* If the width is much smaller than a tile, don't bother tiling. */
464 if (minimum_pitch
< 64)
465 return I915_TILING_NONE
;
467 if (ALIGN(minimum_pitch
, 512) >= 32768) {
468 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
469 mt
->total_width
, mt
->total_height
);
470 return I915_TILING_NONE
;
473 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
475 return I915_TILING_X
;
477 return I915_TILING_Y
| I915_TILING_X
;
480 struct intel_mipmap_tree
*
481 intel_miptree_create(struct brw_context
*brw
,
489 bool expect_accelerated_upload
,
491 enum intel_miptree_tiling_mode requested_tiling
)
493 struct intel_context
*intel
= &brw
->intel
;
494 struct intel_mipmap_tree
*mt
;
495 gl_format tex_format
= format
;
496 gl_format etc_format
= MESA_FORMAT_NONE
;
497 GLuint total_width
, total_height
;
499 if (!intel
->is_baytrail
) {
501 case MESA_FORMAT_ETC1_RGB8
:
502 format
= MESA_FORMAT_RGBX8888_REV
;
504 case MESA_FORMAT_ETC2_RGB8
:
505 format
= MESA_FORMAT_RGBX8888_REV
;
507 case MESA_FORMAT_ETC2_SRGB8
:
508 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
509 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
510 format
= MESA_FORMAT_SARGB8
;
512 case MESA_FORMAT_ETC2_RGBA8_EAC
:
513 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
514 format
= MESA_FORMAT_RGBA8888_REV
;
516 case MESA_FORMAT_ETC2_R11_EAC
:
517 format
= MESA_FORMAT_R16
;
519 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
520 format
= MESA_FORMAT_SIGNED_R16
;
522 case MESA_FORMAT_ETC2_RG11_EAC
:
523 format
= MESA_FORMAT_GR1616
;
525 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
526 format
= MESA_FORMAT_SIGNED_GR1616
;
529 /* Non ETC1 / ETC2 format */
534 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
536 mt
= intel_miptree_create_layout(brw
, target
, format
,
537 first_level
, last_level
, width0
,
541 * pitch == 0 || height == 0 indicates the null texture
543 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
544 intel_miptree_release(&mt
);
548 total_width
= mt
->total_width
;
549 total_height
= mt
->total_height
;
551 if (format
== MESA_FORMAT_S8
) {
552 /* Align to size of W tile, 64x64. */
553 total_width
= ALIGN(total_width
, 64);
554 total_height
= ALIGN(total_height
, 64);
557 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
558 num_samples
, requested_tiling
,
560 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
562 mt
->etc_format
= etc_format
;
563 mt
->region
= intel_region_alloc(intel
->intelScreen
,
564 y_or_x
? I915_TILING_Y
: tiling
,
568 expect_accelerated_upload
);
570 /* If the region is too large to fit in the aperture, we need to use the
571 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
572 * so we need to fall back to X.
574 if (y_or_x
&& mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
575 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
576 mt
->total_width
, mt
->total_height
);
577 intel_region_release(&mt
->region
);
579 mt
->region
= intel_region_alloc(intel
->intelScreen
,
584 expect_accelerated_upload
);
590 intel_miptree_release(&mt
);
594 /* If this miptree is capable of supporting fast color clears, set
595 * mcs_state appropriately to ensure that fast clears will occur.
596 * Allocation of the MCS miptree will be deferred until the first fast
597 * clear actually occurs.
599 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
600 mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
605 struct intel_mipmap_tree
*
606 intel_miptree_create_for_bo(struct brw_context
*brw
,
615 struct intel_mipmap_tree
*mt
;
617 struct intel_region
*region
= calloc(1, sizeof(*region
));
621 /* Nothing will be able to use this miptree with the BO if the offset isn't
624 if (tiling
!= I915_TILING_NONE
)
625 assert(offset
% 4096 == 0);
627 /* miptrees can't handle negative pitch. If you need flipping of images,
628 * that's outside of the scope of the mt.
632 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
635 true, 0 /* num_samples */);
639 region
->cpp
= mt
->cpp
;
640 region
->width
= width
;
641 region
->height
= height
;
642 region
->pitch
= pitch
;
643 region
->refcount
= 1;
644 drm_intel_bo_reference(bo
);
646 region
->tiling
= tiling
;
656 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
658 * For a multisample DRI2 buffer, this wraps the given region with
659 * a singlesample miptree, then creates a multisample miptree into which the
660 * singlesample miptree is embedded as a child.
662 struct intel_mipmap_tree
*
663 intel_miptree_create_for_dri2_buffer(struct brw_context
*brw
,
664 unsigned dri_attachment
,
666 uint32_t num_samples
,
667 struct intel_region
*region
)
669 struct intel_context
*intel
= &brw
->intel
;
670 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
671 struct intel_mipmap_tree
*multisample_mt
= NULL
;
673 /* Only the front and back buffers, which are color buffers, are shared
676 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
677 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
678 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
679 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
680 _mesa_get_format_base_format(format
) == GL_RGBA
);
682 singlesample_mt
= intel_miptree_create_for_bo(brw
,
690 if (!singlesample_mt
)
692 singlesample_mt
->region
->name
= region
->name
;
694 /* If this miptree is capable of supporting fast color clears, set
695 * mcs_state appropriately to ensure that fast clears will occur.
696 * Allocation of the MCS miptree will be deferred until the first fast
697 * clear actually occurs.
699 if (intel_is_non_msrt_mcs_buffer_supported(brw
, singlesample_mt
))
700 singlesample_mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
702 if (num_samples
== 0)
703 return singlesample_mt
;
705 multisample_mt
= intel_miptree_create_for_renderbuffer(brw
,
710 if (!multisample_mt
) {
711 intel_miptree_release(&singlesample_mt
);
715 multisample_mt
->singlesample_mt
= singlesample_mt
;
716 multisample_mt
->need_downsample
= false;
718 if (brw
->is_front_buffer_rendering
&&
719 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
720 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
721 intel_miptree_upsample(brw
, multisample_mt
);
724 return multisample_mt
;
727 struct intel_mipmap_tree
*
728 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
732 uint32_t num_samples
)
734 struct intel_mipmap_tree
*mt
;
738 mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, format
, 0, 0,
739 width
, height
, depth
, true, num_samples
,
740 INTEL_MIPTREE_TILING_ANY
);
744 if (brw_is_hiz_depth_format(brw
, format
)) {
745 ok
= intel_miptree_alloc_hiz(brw
, mt
);
750 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
751 ok
= intel_miptree_alloc_mcs(brw
, mt
, num_samples
);
759 intel_miptree_release(&mt
);
764 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
765 struct intel_mipmap_tree
*src
)
770 intel_miptree_release(dst
);
774 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
782 intel_miptree_release(struct intel_mipmap_tree
**mt
)
787 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
788 if (--(*mt
)->refcount
<= 0) {
791 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
793 intel_region_release(&((*mt
)->region
));
794 intel_miptree_release(&(*mt
)->stencil_mt
);
795 intel_miptree_release(&(*mt
)->hiz_mt
);
796 intel_miptree_release(&(*mt
)->mcs_mt
);
797 intel_miptree_release(&(*mt
)->singlesample_mt
);
798 intel_resolve_map_clear(&(*mt
)->hiz_map
);
800 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
801 free((*mt
)->level
[i
].slice
);
810 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
811 int *width
, int *height
, int *depth
)
813 switch (image
->TexObject
->Target
) {
814 case GL_TEXTURE_1D_ARRAY
:
815 *width
= image
->Width
;
817 *depth
= image
->Height
;
820 *width
= image
->Width
;
821 *height
= image
->Height
;
822 *depth
= image
->Depth
;
828 * Can the image be pulled into a unified mipmap tree? This mirrors
829 * the completeness test in a lot of ways.
831 * Not sure whether I want to pass gl_texture_image here.
834 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
835 struct gl_texture_image
*image
)
837 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
838 GLuint level
= intelImage
->base
.Base
.Level
;
839 int width
, height
, depth
;
841 /* glTexImage* choose the texture object based on the target passed in, and
842 * objects can't change targets over their lifetimes, so this should be
845 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
847 gl_format mt_format
= mt
->format
;
848 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
849 mt_format
= MESA_FORMAT_S8_Z24
;
850 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
851 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
852 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
853 mt_format
= mt
->etc_format
;
855 if (image
->TexFormat
!= mt_format
)
858 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
860 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
863 /* Test image dimensions against the base level image adjusted for
864 * minification. This will also catch images not present in the
865 * tree, changed targets, etc.
867 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
868 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
869 /* nonzero level here is always bogus */
872 if (width
!= mt
->logical_width0
||
873 height
!= mt
->logical_height0
||
874 depth
!= mt
->logical_depth0
) {
879 /* all normal textures, renderbuffers, etc */
880 if (width
!= mt
->level
[level
].width
||
881 height
!= mt
->level
[level
].height
||
882 depth
!= mt
->level
[level
].depth
) {
887 if (image
->NumSamples
!= mt
->num_samples
)
895 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
898 GLuint w
, GLuint h
, GLuint d
)
900 mt
->level
[level
].width
= w
;
901 mt
->level
[level
].height
= h
;
902 mt
->level
[level
].depth
= d
;
903 mt
->level
[level
].level_x
= x
;
904 mt
->level
[level
].level_y
= y
;
906 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
907 level
, w
, h
, d
, x
, y
);
909 assert(mt
->level
[level
].slice
== NULL
);
911 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
912 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
913 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
918 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
919 GLuint level
, GLuint img
,
922 if (img
== 0 && level
== 0)
923 assert(x
== 0 && y
== 0);
925 assert(img
< mt
->level
[level
].depth
);
927 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
928 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
930 DBG("%s level %d img %d pos %d,%d\n",
931 __FUNCTION__
, level
, img
,
932 mt
->level
[level
].slice
[img
].x_offset
,
933 mt
->level
[level
].slice
[img
].y_offset
);
937 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
938 GLuint level
, GLuint slice
,
939 GLuint
*x
, GLuint
*y
)
941 assert(slice
< mt
->level
[level
].depth
);
943 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
944 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
948 * Rendering with tiled buffers requires that the base address of the buffer
949 * be aligned to a page boundary. For renderbuffers, and sometimes with
950 * textures, we may want the surface to point at a texture image level that
951 * isn't at a page boundary.
953 * This function returns an appropriately-aligned base offset
954 * according to the tiling restrictions, plus any required x/y offset
958 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
959 GLuint level
, GLuint slice
,
963 struct intel_region
*region
= mt
->region
;
965 uint32_t mask_x
, mask_y
;
967 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
968 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
970 *tile_x
= x
& mask_x
;
971 *tile_y
= y
& mask_y
;
973 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
978 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
979 struct intel_mipmap_tree
*dst_mt
,
980 struct intel_mipmap_tree
*src_mt
,
987 int src_stride
, dst_stride
;
988 int cpp
= dst_mt
->cpp
;
990 intel_miptree_map(brw
, src_mt
,
994 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
997 intel_miptree_map(brw
, dst_mt
,
1001 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1005 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1006 _mesa_get_format_name(src_mt
->format
),
1007 src_mt
, src
, src_stride
,
1008 _mesa_get_format_name(dst_mt
->format
),
1009 dst_mt
, dst
, dst_stride
,
1012 int row_size
= cpp
* width
;
1013 if (src_stride
== row_size
&&
1014 dst_stride
== row_size
) {
1015 memcpy(dst
, src
, row_size
* height
);
1017 for (int i
= 0; i
< height
; i
++) {
1018 memcpy(dst
, src
, row_size
);
1024 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1025 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1027 /* Don't forget to copy the stencil data over, too. We could have skipped
1028 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1029 * shuffling the two data sources in/out of temporary storage instead of
1030 * the direct mapping we get this way.
1032 if (dst_mt
->stencil_mt
) {
1033 assert(src_mt
->stencil_mt
);
1034 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1035 level
, slice
, width
, height
);
1040 intel_miptree_copy_slice(struct brw_context
*brw
,
1041 struct intel_mipmap_tree
*dst_mt
,
1042 struct intel_mipmap_tree
*src_mt
,
1048 struct intel_context
*intel
= &brw
->intel
;
1049 gl_format format
= src_mt
->format
;
1050 uint32_t width
= src_mt
->level
[level
].width
;
1051 uint32_t height
= src_mt
->level
[level
].height
;
1059 assert(depth
< src_mt
->level
[level
].depth
);
1060 assert(src_mt
->format
== dst_mt
->format
);
1062 if (dst_mt
->compressed
) {
1063 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1064 width
= ALIGN(width
, dst_mt
->align_w
);
1067 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1068 * below won't apply since we can't do the depth's Y tiling or the
1069 * stencil's W tiling in the blitter.
1071 if (src_mt
->stencil_mt
) {
1072 intel_miptree_copy_slice_sw(brw
,
1079 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1080 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1081 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1083 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1084 _mesa_get_format_name(src_mt
->format
),
1085 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1086 _mesa_get_format_name(dst_mt
->format
),
1087 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1090 if (!intel_miptree_blit(brw
,
1091 src_mt
, level
, slice
, 0, 0, false,
1092 dst_mt
, level
, slice
, 0, 0, false,
1093 width
, height
, GL_COPY
)) {
1094 perf_debug("miptree validate blit for %s failed\n",
1095 _mesa_get_format_name(format
));
1097 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1103 * Copies the image's current data to the given miptree, and associates that
1104 * miptree with the image.
1106 * If \c invalidate is true, then the actual image data does not need to be
1107 * copied, but the image still needs to be associated to the new miptree (this
1108 * is set to true if we're about to clear the image).
1111 intel_miptree_copy_teximage(struct brw_context
*brw
,
1112 struct intel_texture_image
*intelImage
,
1113 struct intel_mipmap_tree
*dst_mt
,
1116 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1117 struct intel_texture_object
*intel_obj
=
1118 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1119 int level
= intelImage
->base
.Base
.Level
;
1120 int face
= intelImage
->base
.Base
.Face
;
1121 GLuint depth
= intelImage
->base
.Base
.Depth
;
1124 for (int slice
= 0; slice
< depth
; slice
++) {
1125 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1129 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1130 intel_obj
->needs_validate
= true;
1134 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1135 struct intel_mipmap_tree
*mt
,
1138 struct intel_context
*intel
= &brw
->intel
;
1139 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
1140 assert(mt
->mcs_mt
== NULL
);
1142 /* Choose the correct format for the MCS buffer. All that really matters
1143 * is that we allocate the right buffer size, since we'll always be
1144 * accessing this miptree using MCS-specific hardware mechanisms, which
1145 * infer the correct format based on num_samples.
1148 switch (num_samples
) {
1150 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1153 format
= MESA_FORMAT_R8
;
1156 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1157 * for each sample, plus 8 padding bits).
1159 format
= MESA_FORMAT_R_UINT32
;
1162 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1166 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1168 * "The MCS surface must be stored as Tile Y."
1170 mt
->mcs_state
= INTEL_MCS_STATE_MSAA
;
1171 mt
->mcs_mt
= intel_miptree_create(brw
,
1177 mt
->logical_height0
,
1180 0 /* num_samples */,
1181 INTEL_MIPTREE_TILING_Y
);
1183 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1185 * When MCS buffer is enabled and bound to MSRT, it is required that it
1186 * is cleared prior to any rendering.
1188 * Since we don't use the MCS buffer for any purpose other than rendering,
1189 * it makes sense to just clear it immediately upon allocation.
1191 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1193 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1194 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1195 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1202 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1203 struct intel_mipmap_tree
*mt
)
1205 assert(mt
->mcs_mt
== NULL
);
1207 /* The format of the MCS buffer is opaque to the driver; all that matters
1208 * is that we get its size and pitch right. We'll pretend that the format
1209 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1210 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1211 * the block width and then a further factor of 4. Since an MCS tile
1212 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1213 * we'll need to scale the height down by the block height and then a
1214 * further factor of 8.
1216 const gl_format format
= MESA_FORMAT_R_UINT32
;
1217 unsigned block_width_px
;
1218 unsigned block_height
;
1219 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1220 unsigned width_divisor
= block_width_px
* 4;
1221 unsigned height_divisor
= block_height
* 8;
1222 unsigned mcs_width
=
1223 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1224 unsigned mcs_height
=
1225 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1226 assert(mt
->logical_depth0
== 1);
1227 mt
->mcs_mt
= intel_miptree_create(brw
,
1236 0 /* num_samples */,
1237 INTEL_MIPTREE_TILING_Y
);
1244 * Helper for intel_miptree_alloc_hiz() that sets
1245 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1246 * \c has_hiz was set.
1249 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1250 struct intel_mipmap_tree
*mt
,
1254 struct intel_context
*intel
= &brw
->intel
;
1257 if (intel
->is_haswell
) {
1258 /* Disable HiZ for some slices to work around a hardware bug.
1260 * Haswell hardware fails to respect
1261 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y when during HiZ
1262 * ambiguate operations. The failure is inconsistent and affected by
1263 * other GPU contexts. Running a heavy GPU workload in a separate
1264 * process causes the failure rate to drop to nearly 0.
1266 * To workaround the bug, we enable HiZ only when we can guarantee that
1267 * the Depth Coordinate Offset fields will be set to 0. The function
1268 * brw_get_depthstencil_tile_masks() is used to calculate the fields,
1269 * and the function is sometimes called in such a way that the presence
1270 * of an attached stencil buffer changes the fuction's return value.
1272 * The largest tile size considered by brw_get_depthstencil_tile_masks()
1273 * is that of the stencil buffer. Therefore, if this hiz slice's
1274 * corresponding depth slice has an offset that is aligned to the
1275 * stencil buffer tile size, 64x64 pixels, then
1276 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y is set to 0.
1278 uint32_t depth_x_offset
= mt
->level
[level
].slice
[layer
].x_offset
;
1279 uint32_t depth_y_offset
= mt
->level
[level
].slice
[layer
].y_offset
;
1280 if ((depth_x_offset
& 63) || (depth_y_offset
& 63)) {
1285 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1292 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1293 struct intel_mipmap_tree
*mt
)
1295 assert(mt
->hiz_mt
== NULL
);
1296 mt
->hiz_mt
= intel_miptree_create(brw
,
1302 mt
->logical_height0
,
1306 INTEL_MIPTREE_TILING_ANY
);
1311 /* Mark that all slices need a HiZ resolve. */
1312 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1313 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1314 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1315 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1318 head
->next
= malloc(sizeof(*head
->next
));
1319 head
->next
->prev
= head
;
1320 head
->next
->next
= NULL
;
1323 head
->level
= level
;
1324 head
->layer
= layer
;
1325 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1333 * Does the miptree slice have hiz enabled?
1336 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1340 intel_miptree_check_level_layer(mt
, level
, layer
);
1341 return mt
->level
[level
].slice
[layer
].has_hiz
;
1345 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1349 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1352 intel_resolve_map_set(&mt
->hiz_map
,
1353 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1358 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1362 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1365 intel_resolve_map_set(&mt
->hiz_map
,
1366 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1370 intel_miptree_slice_resolve(struct brw_context
*brw
,
1371 struct intel_mipmap_tree
*mt
,
1374 enum gen6_hiz_op need
)
1376 intel_miptree_check_level_layer(mt
, level
, layer
);
1378 struct intel_resolve_map
*item
=
1379 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1381 if (!item
|| item
->need
!= need
)
1384 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1385 intel_resolve_map_remove(item
);
1390 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1391 struct intel_mipmap_tree
*mt
,
1395 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1396 GEN6_HIZ_OP_HIZ_RESOLVE
);
1400 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1401 struct intel_mipmap_tree
*mt
,
1405 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1406 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1410 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1411 struct intel_mipmap_tree
*mt
,
1412 enum gen6_hiz_op need
)
1414 bool did_resolve
= false;
1415 struct intel_resolve_map
*i
, *next
;
1417 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1419 if (i
->need
!= need
)
1422 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1423 intel_resolve_map_remove(i
);
1431 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1432 struct intel_mipmap_tree
*mt
)
1434 return intel_miptree_all_slices_resolve(brw
, mt
,
1435 GEN6_HIZ_OP_HIZ_RESOLVE
);
1439 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1440 struct intel_mipmap_tree
*mt
)
1442 return intel_miptree_all_slices_resolve(brw
, mt
,
1443 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1448 intel_miptree_resolve_color(struct brw_context
*brw
,
1449 struct intel_mipmap_tree
*mt
)
1451 switch (mt
->mcs_state
) {
1452 case INTEL_MCS_STATE_NONE
:
1453 case INTEL_MCS_STATE_MSAA
:
1454 case INTEL_MCS_STATE_RESOLVED
:
1455 /* No resolve needed */
1457 case INTEL_MCS_STATE_UNRESOLVED
:
1458 case INTEL_MCS_STATE_CLEAR
:
1459 brw_blorp_resolve_color(brw
, mt
);
1466 * Make it possible to share the region backing the given miptree with another
1467 * process or another miptree.
1469 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1470 * then discard the MCS buffer, if present. We also set the mcs_state to
1471 * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
1475 intel_miptree_make_shareable(struct brw_context
*brw
,
1476 struct intel_mipmap_tree
*mt
)
1478 /* MCS buffers are also used for multisample buffers, but we can't resolve
1479 * away a multisample MCS buffer because it's an integral part of how the
1480 * pixel data is stored. Fortunately this code path should never be
1481 * reached for multisample buffers.
1483 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1486 intel_miptree_resolve_color(brw
, mt
);
1487 intel_miptree_release(&mt
->mcs_mt
);
1488 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
1494 * \brief Get pointer offset into stencil buffer.
1496 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1497 * must decode the tile's layout in software.
1500 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1502 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1504 * Even though the returned offset is always positive, the return type is
1506 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1507 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1510 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1512 uint32_t tile_size
= 4096;
1513 uint32_t tile_width
= 64;
1514 uint32_t tile_height
= 64;
1515 uint32_t row_size
= 64 * stride
;
1517 uint32_t tile_x
= x
/ tile_width
;
1518 uint32_t tile_y
= y
/ tile_height
;
1520 /* The byte's address relative to the tile's base addres. */
1521 uint32_t byte_x
= x
% tile_width
;
1522 uint32_t byte_y
= y
% tile_height
;
1524 uintptr_t u
= tile_y
* row_size
1525 + tile_x
* tile_size
1526 + 512 * (byte_x
/ 8)
1528 + 32 * ((byte_y
/ 4) % 2)
1529 + 16 * ((byte_x
/ 4) % 2)
1530 + 8 * ((byte_y
/ 2) % 2)
1531 + 4 * ((byte_x
/ 2) % 2)
1536 /* adjust for bit6 swizzling */
1537 if (((byte_x
/ 8) % 2) == 1) {
1538 if (((byte_y
/ 8) % 2) == 0) {
1550 intel_miptree_updownsample(struct brw_context
*brw
,
1551 struct intel_mipmap_tree
*src
,
1552 struct intel_mipmap_tree
*dst
,
1561 brw_blorp_blit_miptrees(brw
,
1562 src
, 0 /* level */, 0 /* layer */,
1563 dst
, 0 /* level */, 0 /* layer */,
1568 false, false /*mirror x, y*/);
1570 if (src
->stencil_mt
) {
1571 brw_blorp_blit_miptrees(brw
,
1572 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1573 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1578 false, false /*mirror x, y*/);
1583 assert_is_flat(struct intel_mipmap_tree
*mt
)
1585 assert(mt
->target
== GL_TEXTURE_2D
);
1586 assert(mt
->first_level
== 0);
1587 assert(mt
->last_level
== 0);
1591 * \brief Downsample from mt to mt->singlesample_mt.
1593 * If the miptree needs no downsample, then skip.
1596 intel_miptree_downsample(struct brw_context
*brw
,
1597 struct intel_mipmap_tree
*mt
)
1599 /* Only flat, renderbuffer-like miptrees are supported. */
1602 if (!mt
->need_downsample
)
1604 intel_miptree_updownsample(brw
,
1605 mt
, mt
->singlesample_mt
,
1607 mt
->logical_height0
);
1608 mt
->need_downsample
= false;
1612 * \brief Upsample from mt->singlesample_mt to mt.
1614 * The upsample is done unconditionally.
1617 intel_miptree_upsample(struct brw_context
*brw
,
1618 struct intel_mipmap_tree
*mt
)
1620 /* Only flat, renderbuffer-like miptrees are supported. */
1622 assert(!mt
->need_downsample
);
1624 intel_miptree_updownsample(brw
,
1625 mt
->singlesample_mt
, mt
,
1627 mt
->logical_height0
);
1631 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1633 struct intel_context
*intel
= &brw
->intel
;
1634 struct gl_context
*ctx
= &intel
->ctx
;
1635 /* CPU accesses to color buffers don't understand fast color clears, so
1636 * resolve any pending fast color clears before we map.
1638 intel_miptree_resolve_color(brw
, mt
);
1640 drm_intel_bo
*bo
= mt
->region
->bo
;
1642 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1643 if (drm_intel_bo_busy(bo
)) {
1644 perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
1650 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1651 drm_intel_gem_bo_map_gtt(bo
);
1653 drm_intel_bo_map(bo
, true);
1659 intel_miptree_unmap_raw(struct brw_context
*brw
,
1660 struct intel_mipmap_tree
*mt
)
1662 drm_intel_bo_unmap(mt
->region
->bo
);
1666 intel_miptree_map_gtt(struct brw_context
*brw
,
1667 struct intel_mipmap_tree
*mt
,
1668 struct intel_miptree_map
*map
,
1669 unsigned int level
, unsigned int slice
)
1671 unsigned int bw
, bh
;
1673 unsigned int image_x
, image_y
;
1677 /* For compressed formats, the stride is the number of bytes per
1678 * row of blocks. intel_miptree_get_image_offset() already does
1681 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1682 assert(y
% bh
== 0);
1685 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1690 /* Note that in the case of cube maps, the caller must have passed the
1691 * slice number referencing the face.
1693 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1697 map
->stride
= mt
->region
->pitch
;
1698 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1701 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1702 map
->x
, map
->y
, map
->w
, map
->h
,
1703 mt
, _mesa_get_format_name(mt
->format
),
1704 x
, y
, map
->ptr
, map
->stride
);
1708 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1709 struct intel_mipmap_tree
*mt
,
1710 struct intel_miptree_map
*map
,
1714 intel_miptree_unmap_raw(brw
, mt
);
1718 intel_miptree_map_blit(struct brw_context
*brw
,
1719 struct intel_mipmap_tree
*mt
,
1720 struct intel_miptree_map
*map
,
1721 unsigned int level
, unsigned int slice
)
1723 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1727 INTEL_MIPTREE_TILING_NONE
);
1729 fprintf(stderr
, "Failed to allocate blit temporary\n");
1732 map
->stride
= map
->mt
->region
->pitch
;
1734 if (!intel_miptree_blit(brw
,
1736 map
->x
, map
->y
, false,
1739 map
->w
, map
->h
, GL_COPY
)) {
1740 fprintf(stderr
, "Failed to blit\n");
1744 intel_batchbuffer_flush(brw
);
1745 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1747 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1748 map
->x
, map
->y
, map
->w
, map
->h
,
1749 mt
, _mesa_get_format_name(mt
->format
),
1750 level
, slice
, map
->ptr
, map
->stride
);
1755 intel_miptree_release(&map
->mt
);
1761 intel_miptree_unmap_blit(struct brw_context
*brw
,
1762 struct intel_mipmap_tree
*mt
,
1763 struct intel_miptree_map
*map
,
1767 struct intel_context
*intel
= &brw
->intel
;
1768 struct gl_context
*ctx
= &intel
->ctx
;
1770 intel_miptree_unmap_raw(brw
, map
->mt
);
1772 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1773 bool ok
= intel_miptree_blit(brw
,
1777 map
->x
, map
->y
, false,
1778 map
->w
, map
->h
, GL_COPY
);
1779 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1782 intel_miptree_release(&map
->mt
);
1786 intel_miptree_map_s8(struct brw_context
*brw
,
1787 struct intel_mipmap_tree
*mt
,
1788 struct intel_miptree_map
*map
,
1789 unsigned int level
, unsigned int slice
)
1791 struct intel_context
*intel
= &brw
->intel
;
1792 map
->stride
= map
->w
;
1793 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1797 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1798 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1799 * invalidate is set, since we'll be writing the whole rectangle from our
1800 * temporary buffer back out.
1802 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1803 uint8_t *untiled_s8_map
= map
->ptr
;
1804 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1805 unsigned int image_x
, image_y
;
1807 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1809 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1810 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1811 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1812 x
+ image_x
+ map
->x
,
1813 y
+ image_y
+ map
->y
,
1814 intel
->has_swizzling
);
1815 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1819 intel_miptree_unmap_raw(brw
, mt
);
1821 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1822 map
->x
, map
->y
, map
->w
, map
->h
,
1823 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1825 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1826 map
->x
, map
->y
, map
->w
, map
->h
,
1827 mt
, map
->ptr
, map
->stride
);
1832 intel_miptree_unmap_s8(struct brw_context
*brw
,
1833 struct intel_mipmap_tree
*mt
,
1834 struct intel_miptree_map
*map
,
1838 struct intel_context
*intel
= &brw
->intel
;
1839 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1840 unsigned int image_x
, image_y
;
1841 uint8_t *untiled_s8_map
= map
->ptr
;
1842 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1844 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1846 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1847 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1848 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1851 intel
->has_swizzling
);
1852 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1856 intel_miptree_unmap_raw(brw
, mt
);
1863 intel_miptree_map_etc(struct brw_context
*brw
,
1864 struct intel_mipmap_tree
*mt
,
1865 struct intel_miptree_map
*map
,
1869 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1870 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1871 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1874 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1875 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1877 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1878 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1879 map
->w
, map
->h
, 1));
1880 map
->ptr
= map
->buffer
;
1884 intel_miptree_unmap_etc(struct brw_context
*brw
,
1885 struct intel_mipmap_tree
*mt
,
1886 struct intel_miptree_map
*map
,
1892 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1897 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
1898 + image_y
* mt
->region
->pitch
1899 + image_x
* mt
->region
->cpp
;
1901 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1902 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1903 map
->ptr
, map
->stride
,
1906 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1907 map
->ptr
, map
->stride
,
1908 map
->w
, map
->h
, mt
->etc_format
);
1910 intel_miptree_unmap_raw(brw
, mt
);
1915 * Mapping function for packed depth/stencil miptrees backed by real separate
1916 * miptrees for depth and stencil.
1918 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1919 * separate from the depth buffer. Yet at the GL API level, we have to expose
1920 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1921 * be able to map that memory for texture storage and glReadPixels-type
1922 * operations. We give Mesa core that access by mallocing a temporary and
1923 * copying the data between the actual backing store and the temporary.
1926 intel_miptree_map_depthstencil(struct brw_context
*brw
,
1927 struct intel_mipmap_tree
*mt
,
1928 struct intel_miptree_map
*map
,
1929 unsigned int level
, unsigned int slice
)
1931 struct intel_context
*intel
= &brw
->intel
;
1932 struct intel_mipmap_tree
*z_mt
= mt
;
1933 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1934 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1935 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1937 map
->stride
= map
->w
* packed_bpp
;
1938 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1942 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1943 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1944 * invalidate is set, since we'll be writing the whole rectangle from our
1945 * temporary buffer back out.
1947 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1948 uint32_t *packed_map
= map
->ptr
;
1949 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1950 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
1951 unsigned int s_image_x
, s_image_y
;
1952 unsigned int z_image_x
, z_image_y
;
1954 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1955 &s_image_x
, &s_image_y
);
1956 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1957 &z_image_x
, &z_image_y
);
1959 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1960 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1961 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1962 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1965 intel
->has_swizzling
);
1966 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1967 (z_mt
->region
->pitch
/ 4) +
1968 (map_x
+ z_image_x
));
1969 uint8_t s
= s_map
[s_offset
];
1970 uint32_t z
= z_map
[z_offset
];
1972 if (map_z32f_x24s8
) {
1973 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1974 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1976 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1981 intel_miptree_unmap_raw(brw
, s_mt
);
1982 intel_miptree_unmap_raw(brw
, z_mt
);
1984 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1986 map
->x
, map
->y
, map
->w
, map
->h
,
1987 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1988 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1989 map
->ptr
, map
->stride
);
1991 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1992 map
->x
, map
->y
, map
->w
, map
->h
,
1993 mt
, map
->ptr
, map
->stride
);
1998 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
1999 struct intel_mipmap_tree
*mt
,
2000 struct intel_miptree_map
*map
,
2004 struct intel_context
*intel
= &brw
->intel
;
2005 struct intel_mipmap_tree
*z_mt
= mt
;
2006 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2007 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
2009 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2010 uint32_t *packed_map
= map
->ptr
;
2011 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2012 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2013 unsigned int s_image_x
, s_image_y
;
2014 unsigned int z_image_x
, z_image_y
;
2016 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2017 &s_image_x
, &s_image_y
);
2018 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2019 &z_image_x
, &z_image_y
);
2021 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2022 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2023 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2024 x
+ s_image_x
+ map
->x
,
2025 y
+ s_image_y
+ map
->y
,
2026 intel
->has_swizzling
);
2027 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2028 (z_mt
->region
->pitch
/ 4) +
2031 if (map_z32f_x24s8
) {
2032 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2033 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2035 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2036 s_map
[s_offset
] = packed
>> 24;
2037 z_map
[z_offset
] = packed
;
2042 intel_miptree_unmap_raw(brw
, s_mt
);
2043 intel_miptree_unmap_raw(brw
, z_mt
);
2045 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2047 map
->x
, map
->y
, map
->w
, map
->h
,
2048 z_mt
, _mesa_get_format_name(z_mt
->format
),
2049 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2050 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2051 map
->ptr
, map
->stride
);
2058 * Create and attach a map to the miptree at (level, slice). Return the
2061 static struct intel_miptree_map
*
2062 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2071 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2076 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2077 mt
->level
[level
].slice
[slice
].map
= map
;
2089 * Release the map at (level, slice).
2092 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2096 struct intel_miptree_map
**map
;
2098 map
= &mt
->level
[level
].slice
[slice
].map
;
2104 intel_miptree_map_singlesample(struct brw_context
*brw
,
2105 struct intel_mipmap_tree
*mt
,
2116 struct intel_context
*intel
= &brw
->intel
;
2117 struct intel_miptree_map
*map
;
2119 assert(mt
->num_samples
<= 1);
2121 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2128 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2129 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2130 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2133 if (mt
->format
== MESA_FORMAT_S8
) {
2134 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2135 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2136 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2137 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2138 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2139 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2141 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2142 else if (intel
->has_llc
&&
2143 !(mode
& GL_MAP_WRITE_BIT
) &&
2145 (mt
->region
->tiling
== I915_TILING_X
||
2146 (intel
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2147 mt
->region
->pitch
< 32768) {
2148 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2149 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2150 mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
2151 assert(mt
->region
->pitch
< 32768);
2152 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2154 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2157 *out_ptr
= map
->ptr
;
2158 *out_stride
= map
->stride
;
2160 if (map
->ptr
== NULL
)
2161 intel_miptree_release_map(mt
, level
, slice
);
2165 intel_miptree_unmap_singlesample(struct brw_context
*brw
,
2166 struct intel_mipmap_tree
*mt
,
2170 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2172 assert(mt
->num_samples
<= 1);
2177 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2178 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2180 if (mt
->format
== MESA_FORMAT_S8
) {
2181 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2182 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2183 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2184 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2185 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2186 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2187 } else if (map
->mt
) {
2188 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2190 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2193 intel_miptree_release_map(mt
, level
, slice
);
2197 intel_miptree_map_multisample(struct brw_context
*brw
,
2198 struct intel_mipmap_tree
*mt
,
2209 struct gl_context
*ctx
= &brw
->intel
.ctx
;
2210 struct intel_miptree_map
*map
;
2212 assert(mt
->num_samples
> 1);
2214 /* Only flat, renderbuffer-like miptrees are supported. */
2215 if (mt
->target
!= GL_TEXTURE_2D
||
2216 mt
->first_level
!= 0 ||
2217 mt
->last_level
!= 0) {
2218 _mesa_problem(ctx
, "attempt to map a multisample miptree for "
2219 "which (target, first_level, last_level != "
2220 "(GL_TEXTURE_2D, 0, 0)");
2224 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2228 if (!mt
->singlesample_mt
) {
2229 mt
->singlesample_mt
=
2230 intel_miptree_create_for_renderbuffer(brw
,
2233 mt
->logical_height0
,
2235 if (!mt
->singlesample_mt
)
2238 map
->singlesample_mt_is_tmp
= true;
2239 mt
->need_downsample
= true;
2242 intel_miptree_downsample(brw
, mt
);
2243 intel_miptree_map_singlesample(brw
, mt
->singlesample_mt
,
2247 out_ptr
, out_stride
);
2251 intel_miptree_release_map(mt
, level
, slice
);
2257 intel_miptree_unmap_multisample(struct brw_context
*brw
,
2258 struct intel_mipmap_tree
*mt
,
2262 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2264 assert(mt
->num_samples
> 1);
2269 intel_miptree_unmap_singlesample(brw
, mt
->singlesample_mt
, level
, slice
);
2271 mt
->need_downsample
= false;
2272 if (map
->mode
& GL_MAP_WRITE_BIT
)
2273 intel_miptree_upsample(brw
, mt
);
2275 if (map
->singlesample_mt_is_tmp
)
2276 intel_miptree_release(&mt
->singlesample_mt
);
2278 intel_miptree_release_map(mt
, level
, slice
);
2282 intel_miptree_map(struct brw_context
*brw
,
2283 struct intel_mipmap_tree
*mt
,
2294 if (mt
->num_samples
<= 1)
2295 intel_miptree_map_singlesample(brw
, mt
,
2299 out_ptr
, out_stride
);
2301 intel_miptree_map_multisample(brw
, mt
,
2305 out_ptr
, out_stride
);
2309 intel_miptree_unmap(struct brw_context
*brw
,
2310 struct intel_mipmap_tree
*mt
,
2314 if (mt
->num_samples
<= 1)
2315 intel_miptree_unmap_singlesample(brw
, mt
, level
, slice
);
2317 intel_miptree_unmap_multisample(brw
, mt
, level
, slice
);