2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
77 switch (_mesa_get_format_base_format(mt
->format
)) {
78 case GL_DEPTH_COMPONENT
:
79 case GL_STENCIL_INDEX
:
80 case GL_DEPTH_STENCIL
:
83 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
85 * This field must be set to 0 for all SINT MSRTs when all RT channels
88 * In practice this means that we have to disable MCS for all signed
89 * integer MSAA buffers. The alternative, to disable MCS only when one
90 * of the render target channels is disabled, is impractical because it
91 * would require converting between CMS and UMS MSAA layouts on the fly,
94 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
103 intel_tiling_supports_ccs(const struct brw_context
*brw
,
104 enum isl_tiling tiling
)
106 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
115 if (devinfo
->gen
>= 9)
116 return tiling
== ISL_TILING_Y0
;
117 else if (devinfo
->gen
>= 7)
118 return tiling
!= ISL_TILING_LINEAR
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
150 /* MCS support does not exist prior to Gen7 */
151 if (devinfo
->gen
< 7)
154 /* This function applies only to non-multisampled render targets. */
155 if (mt
->surf
.samples
> 1)
158 /* MCS is only supported for color buffers */
159 switch (_mesa_get_format_base_format(mt
->format
)) {
160 case GL_DEPTH_COMPONENT
:
161 case GL_DEPTH_STENCIL
:
162 case GL_STENCIL_INDEX
:
166 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
169 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
170 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
171 mt
->surf
.logical_level0_px
.depth
> 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->surf
.samples
== 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->mesa_format_supports_render
[mt
->format
])
214 intel_tiling_supports_hiz(const struct brw_context
*brw
,
215 enum isl_tiling tiling
)
217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
219 if (devinfo
->gen
< 6)
222 return tiling
== ISL_TILING_Y0
;
226 intel_miptree_supports_hiz(const struct brw_context
*brw
,
227 const struct intel_mipmap_tree
*mt
)
232 switch (mt
->format
) {
233 case MESA_FORMAT_Z_FLOAT32
:
234 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
235 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 case MESA_FORMAT_Z_UNORM16
:
245 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
246 const struct intel_mipmap_tree
*mt
)
248 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
250 if (devinfo
->gen
< 9)
253 /* For now compression is only enabled for integer formats even though
254 * there exist supported floating point formats also. This is a heuristic
255 * decision based on current public benchmarks. In none of the cases these
256 * formats provided any improvement but a few cases were seen to regress.
257 * Hence these are left to to be enabled in the future when they are known
260 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
263 if (!intel_miptree_supports_ccs(brw
, mt
))
266 /* Many window system buffers are sRGB even if they are never rendered as
267 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
268 * surface is used as sRGB, we fall back to CCS_D.
270 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
271 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
272 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
276 * Determine depth format corresponding to a depth+stencil format,
277 * for separate stencil.
280 intel_depth_format_for_depthstencil_format(mesa_format format
) {
282 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
283 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
284 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
285 return MESA_FORMAT_Z_FLOAT32
;
292 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
293 unsigned depth0
, struct intel_mipmap_level
*table
)
295 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
297 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
299 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
300 if (!table
[level
].slice
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++)
308 free(table
[level
].slice
);
314 needs_separate_stencil(const struct brw_context
*brw
,
315 struct intel_mipmap_tree
*mt
,
318 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
321 if (brw
->must_use_separate_stencil
)
324 return brw
->has_separate_stencil
&&
325 intel_miptree_supports_hiz(brw
, mt
);
329 * Choose the aux usage for this miptree. This function must be called fairly
330 * late in the miptree create process after we have a tiling.
333 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
334 struct intel_mipmap_tree
*mt
)
336 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
338 if (intel_miptree_supports_mcs(brw
, mt
)) {
339 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
340 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
341 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
342 intel_miptree_supports_ccs(brw
, mt
)) {
343 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
344 intel_miptree_supports_ccs_e(brw
, mt
)) {
345 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
347 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
349 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
350 intel_miptree_supports_hiz(brw
, mt
)) {
351 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
354 /* We can do fast-clear on all auxiliary surface types that are
355 * allocated through the normal texture creation paths.
357 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
358 mt
->supports_fast_clear
= true;
363 * Choose an appropriate uncompressed format for a requested
364 * compressed format, if unsupported.
367 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
369 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
371 /* No need to lower ETC formats on these platforms,
372 * they are supported natively.
374 if (devinfo
->gen
>= 8 || brw
->is_baytrail
)
378 case MESA_FORMAT_ETC1_RGB8
:
379 return MESA_FORMAT_R8G8B8X8_UNORM
;
380 case MESA_FORMAT_ETC2_RGB8
:
381 return MESA_FORMAT_R8G8B8X8_UNORM
;
382 case MESA_FORMAT_ETC2_SRGB8
:
383 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
384 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
385 return MESA_FORMAT_B8G8R8A8_SRGB
;
386 case MESA_FORMAT_ETC2_RGBA8_EAC
:
387 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
388 return MESA_FORMAT_R8G8B8A8_UNORM
;
389 case MESA_FORMAT_ETC2_R11_EAC
:
390 return MESA_FORMAT_R_UNORM16
;
391 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
392 return MESA_FORMAT_R_SNORM16
;
393 case MESA_FORMAT_ETC2_RG11_EAC
:
394 return MESA_FORMAT_R16G16_UNORM
;
395 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
396 return MESA_FORMAT_R16G16_SNORM
;
398 /* Non ETC1 / ETC2 format */
404 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
406 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
407 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
409 return mt
->surf
.logical_level0_px
.array_len
;
412 UNUSED
static unsigned
413 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
415 /* In case of physical dimensions one needs to consider also the layout.
416 * See isl_calc_phys_level0_extent_sa().
418 if (surf
->dim
!= ISL_SURF_DIM_3D
)
419 return surf
->phys_level0_sa
.array_len
;
421 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
422 return minify(surf
->phys_level0_sa
.array_len
, level
);
424 return minify(surf
->phys_level0_sa
.depth
, level
);
427 /** \brief Assert that the level and layer are valid for the miptree. */
429 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
437 assert(level
>= mt
->first_level
);
438 assert(level
<= mt
->last_level
);
439 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
442 static enum isl_aux_state
**
443 create_aux_state_map(struct intel_mipmap_tree
*mt
,
444 enum isl_aux_state initial
)
446 const uint32_t levels
= mt
->last_level
+ 1;
448 uint32_t total_slices
= 0;
449 for (uint32_t level
= 0; level
< levels
; level
++)
450 total_slices
+= brw_get_num_logical_layers(mt
, level
);
452 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
454 /* We're going to allocate a single chunk of data for both the per-level
455 * reference array and the arrays of aux_state. This makes cleanup
456 * significantly easier.
458 const size_t total_size
= per_level_array_size
+
459 total_slices
* sizeof(enum isl_aux_state
);
460 void *data
= malloc(total_size
);
464 enum isl_aux_state
**per_level_arr
= data
;
465 enum isl_aux_state
*s
= data
+ per_level_array_size
;
466 for (uint32_t level
= 0; level
< levels
; level
++) {
467 per_level_arr
[level
] = s
;
468 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
469 for (uint32_t a
= 0; a
< level_layers
; a
++)
472 assert((void *)s
== data
+ total_size
);
474 return per_level_arr
;
478 free_aux_state_map(enum isl_aux_state
**state
)
484 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
485 enum isl_tiling tiling
, unsigned samples
)
490 if (tiling
== ISL_TILING_LINEAR
)
493 /* If the width is much smaller than a tile, don't bother tiling. */
497 if (ALIGN(row_pitch
, 512) >= 32768) {
498 perf_debug("row pitch %u too large to blit, falling back to untiled",
507 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
508 enum isl_tiling tiling
)
510 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
512 /* If the BO is too large to fit in the aperture, we need to use the
513 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
514 * handle Y-tiling, so we need to fall back to X.
516 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
517 tiling
== ISL_TILING_Y0
)
523 static struct intel_mipmap_tree
*
524 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
525 unsigned first_level
, unsigned last_level
,
526 unsigned width0
, unsigned height0
, unsigned depth0
,
527 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
528 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
529 unsigned row_pitch
, struct brw_bo
*bo
)
531 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
535 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
543 if (target
== GL_TEXTURE_CUBE_MAP
||
544 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
545 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
547 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
549 _mesa_enum_to_string(target
),
550 _mesa_get_format_name(format
),
551 num_samples
, width0
, height0
, depth0
,
552 first_level
, last_level
, mt
);
554 struct isl_surf_init_info init_info
= {
555 .dim
= get_isl_surf_dim(target
),
556 .format
= translate_tex_format(brw
, format
, false),
559 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
560 .levels
= last_level
- first_level
+ 1,
561 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
562 .samples
= num_samples
,
563 .row_pitch
= row_pitch
,
564 .usage
= isl_usage_flags
,
565 .tiling_flags
= tiling_flags
,
568 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
571 /* In case caller doesn't specifically request Y-tiling (needed
572 * unconditionally for depth), check for corner cases needing special
575 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
576 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
577 mt
->surf
.tiling
, mt
->surf
.samples
)) {
578 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
579 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
581 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
582 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
583 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
588 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
589 * the size may not be multiple of row_pitch.
590 * See isl_apply_surface_padding().
592 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
593 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
596 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
598 isl_tiling_to_i915_tiling(
600 mt
->surf
.row_pitch
, alloc_flags
);
607 mt
->first_level
= first_level
;
608 mt
->last_level
= last_level
;
611 mt
->aux_state
= NULL
;
612 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
613 mt
->compressed
= _mesa_is_format_compressed(format
);
614 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
619 intel_miptree_release(&mt
);
624 make_separate_stencil_surface(struct brw_context
*brw
,
625 struct intel_mipmap_tree
*mt
)
627 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
628 0, mt
->surf
.levels
- 1,
629 mt
->surf
.logical_level0_px
.width
,
630 mt
->surf
.logical_level0_px
.height
,
631 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
632 mt
->surf
.logical_level0_px
.depth
:
633 mt
->surf
.logical_level0_px
.array_len
,
634 mt
->surf
.samples
, ISL_TILING_W_BIT
,
635 ISL_SURF_USAGE_STENCIL_BIT
|
636 ISL_SURF_USAGE_TEXTURE_BIT
,
637 BO_ALLOC_BUSY
, 0, NULL
);
642 mt
->stencil_mt
->r8stencil_needs_update
= true;
647 static struct intel_mipmap_tree
*
648 miptree_create(struct brw_context
*brw
,
657 enum intel_miptree_create_flags flags
)
659 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
661 if (format
== MESA_FORMAT_S_UINT8
)
662 return make_surface(brw
, target
, format
, first_level
, last_level
,
663 width0
, height0
, depth0
, num_samples
,
665 ISL_SURF_USAGE_STENCIL_BIT
|
666 ISL_SURF_USAGE_TEXTURE_BIT
,
671 const GLenum base_format
= _mesa_get_format_base_format(format
);
672 if ((base_format
== GL_DEPTH_COMPONENT
||
673 base_format
== GL_DEPTH_STENCIL
) &&
674 !(flags
& MIPTREE_CREATE_LINEAR
)) {
675 /* Fix up the Z miptree format for how we're splitting out separate
676 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
678 const mesa_format depth_only_format
=
679 intel_depth_format_for_depthstencil_format(format
);
680 struct intel_mipmap_tree
*mt
= make_surface(
681 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
682 first_level
, last_level
,
683 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
684 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
685 BO_ALLOC_BUSY
, 0, NULL
);
687 if (needs_separate_stencil(brw
, mt
, format
) &&
688 !make_separate_stencil_surface(brw
, mt
)) {
689 intel_miptree_release(&mt
);
693 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
694 intel_miptree_choose_aux_usage(brw
, mt
);
699 mesa_format tex_format
= format
;
700 mesa_format etc_format
= MESA_FORMAT_NONE
;
701 uint32_t alloc_flags
= 0;
703 format
= intel_lower_compressed_format(brw
, format
);
705 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
707 if (flags
& MIPTREE_CREATE_BUSY
)
708 alloc_flags
|= BO_ALLOC_BUSY
;
710 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
711 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
713 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
714 if (devinfo
->gen
< 6)
715 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
717 struct intel_mipmap_tree
*mt
= make_surface(
719 first_level
, last_level
,
720 width0
, height0
, depth0
,
721 num_samples
, tiling_flags
,
722 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
723 ISL_SURF_USAGE_TEXTURE_BIT
,
724 alloc_flags
, 0, NULL
);
728 mt
->etc_format
= etc_format
;
730 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
731 intel_miptree_choose_aux_usage(brw
, mt
);
736 struct intel_mipmap_tree
*
737 intel_miptree_create(struct brw_context
*brw
,
746 enum intel_miptree_create_flags flags
)
748 assert(num_samples
> 0);
750 struct intel_mipmap_tree
*mt
= miptree_create(
752 first_level
, last_level
,
753 width0
, height0
, depth0
, num_samples
,
760 if (!intel_miptree_alloc_aux(brw
, mt
)) {
761 intel_miptree_release(&mt
);
768 struct intel_mipmap_tree
*
769 intel_miptree_create_for_bo(struct brw_context
*brw
,
777 enum intel_miptree_create_flags flags
)
779 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
780 struct intel_mipmap_tree
*mt
;
781 uint32_t tiling
, swizzle
;
782 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
783 const GLenum base_format
= _mesa_get_format_base_format(format
);
785 if ((base_format
== GL_DEPTH_COMPONENT
||
786 base_format
== GL_DEPTH_STENCIL
)) {
787 const mesa_format depth_only_format
=
788 intel_depth_format_for_depthstencil_format(format
);
789 mt
= make_surface(brw
, target
,
790 devinfo
->gen
>= 6 ? depth_only_format
: format
,
791 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
792 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
793 BO_ALLOC_BUSY
, pitch
, bo
);
797 brw_bo_reference(bo
);
799 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
800 intel_miptree_choose_aux_usage(brw
, mt
);
803 } else if (format
== MESA_FORMAT_S_UINT8
) {
804 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
805 0, 0, width
, height
, depth
, 1,
807 ISL_SURF_USAGE_STENCIL_BIT
|
808 ISL_SURF_USAGE_TEXTURE_BIT
,
809 BO_ALLOC_BUSY
, pitch
, bo
);
813 assert(bo
->size
>= mt
->surf
.size
);
815 brw_bo_reference(bo
);
819 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
821 /* Nothing will be able to use this miptree with the BO if the offset isn't
824 if (tiling
!= I915_TILING_NONE
)
825 assert(offset
% 4096 == 0);
827 /* miptrees can't handle negative pitch. If you need flipping of images,
828 * that's outside of the scope of the mt.
832 /* The BO already has a tiling format and we shouldn't confuse the lower
833 * layers by making it try to find a tiling format again.
835 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
837 mt
= make_surface(brw
, target
, format
,
838 0, 0, width
, height
, depth
, 1,
839 1lu << isl_tiling_from_i915_tiling(tiling
),
840 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
841 ISL_SURF_USAGE_TEXTURE_BIT
,
846 brw_bo_reference(bo
);
850 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
851 intel_miptree_choose_aux_usage(brw
, mt
);
853 if (!intel_miptree_alloc_aux(brw
, mt
)) {
854 intel_miptree_release(&mt
);
862 static struct intel_mipmap_tree
*
863 miptree_create_for_planar_image(struct brw_context
*brw
,
864 __DRIimage
*image
, GLenum target
)
866 const struct intel_image_format
*f
= image
->planar_format
;
867 struct intel_mipmap_tree
*planar_mt
= NULL
;
869 for (int i
= 0; i
< f
->nplanes
; i
++) {
870 const int index
= f
->planes
[i
].buffer_index
;
871 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
872 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
873 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
874 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
876 /* Disable creation of the texture's aux buffers because the driver
877 * exposes no EGL API to manage them. That is, there is no API for
878 * resolving the aux buffer's content to the main buffer nor for
879 * invalidating the aux buffer's content.
881 struct intel_mipmap_tree
*mt
=
882 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
883 image
->offsets
[index
],
885 image
->strides
[index
],
886 MIPTREE_CREATE_NO_AUX
);
895 planar_mt
->plane
[i
- 1] = mt
;
898 planar_mt
->drm_modifier
= image
->modifier
;
904 create_ccs_buf_for_image(struct brw_context
*brw
,
906 struct intel_mipmap_tree
*mt
,
907 enum isl_aux_state initial_state
)
909 struct isl_surf temp_ccs_surf
;
911 /* CCS is only supported for very simple miptrees */
912 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
913 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
914 assert(mt
->surf
.samples
== 1);
915 assert(mt
->surf
.levels
== 1);
916 assert(mt
->surf
.logical_level0_px
.depth
== 1);
917 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
918 assert(mt
->first_level
== 0);
919 assert(mt
->last_level
== 0);
921 /* We shouldn't already have a CCS */
922 assert(!mt
->mcs_buf
);
924 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
928 assert(image
->aux_offset
< image
->bo
->size
);
929 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
931 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
932 if (mt
->mcs_buf
== NULL
)
935 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
936 if (!mt
->aux_state
) {
942 mt
->mcs_buf
->bo
= image
->bo
;
943 brw_bo_reference(image
->bo
);
945 mt
->mcs_buf
->offset
= image
->aux_offset
;
946 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
947 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
948 mt
->mcs_buf
->qpitch
= 0;
949 mt
->mcs_buf
->surf
= temp_ccs_surf
;
954 struct intel_mipmap_tree
*
955 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
956 __DRIimage
*image
, GLenum target
,
957 enum isl_colorspace colorspace
,
958 bool is_winsys_image
)
960 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
961 assert(colorspace
== ISL_COLORSPACE_NONE
||
962 colorspace
== ISL_COLORSPACE_YUV
);
963 return miptree_create_for_planar_image(brw
, image
, target
);
966 if (image
->planar_format
)
967 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
969 mesa_format format
= image
->format
;
970 switch (colorspace
) {
971 case ISL_COLORSPACE_NONE
:
972 /* Keep the image format unmodified */
975 case ISL_COLORSPACE_LINEAR
:
976 format
=_mesa_get_srgb_format_linear(format
);
979 case ISL_COLORSPACE_SRGB
:
980 format
=_mesa_get_linear_format_srgb(format
);
984 unreachable("Inalid colorspace for non-planar image");
987 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
988 /* The texture storage paths in core Mesa detect if the driver does not
989 * support the user-requested format, and then searches for a
990 * fallback format. The DRIimage code bypasses core Mesa, though. So we
991 * do the fallbacks here for important formats.
993 * We must support DRM_FOURCC_XBGR8888 textures because the Android
994 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
995 * the Chrome OS compositor consumes as dma_buf EGLImages.
997 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1000 if (!brw
->ctx
.TextureFormatSupported
[format
])
1003 const struct isl_drm_modifier_info
*mod_info
=
1004 isl_drm_modifier_get_info(image
->modifier
);
1006 enum intel_miptree_create_flags mt_create_flags
= 0;
1008 /* If this image comes in from a window system, we have different
1009 * requirements than if it comes in via an EGL import operation. Window
1010 * system images can use any form of auxiliary compression we wish because
1011 * they get "flushed" before being handed off to the window system and we
1012 * have the opportunity to do resolves. Non window-system images, on the
1013 * other hand, have no resolve point so we can't have aux without a
1016 if (!is_winsys_image
)
1017 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1019 /* If we have a modifier which specifies aux, don't create one yet */
1020 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1021 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1023 /* Disable creation of the texture's aux buffers because the driver exposes
1024 * no EGL API to manage them. That is, there is no API for resolving the aux
1025 * buffer's content to the main buffer nor for invalidating the aux buffer's
1028 struct intel_mipmap_tree
*mt
=
1029 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1030 image
->offset
, image
->width
, image
->height
, 1,
1031 image
->pitch
, mt_create_flags
);
1035 mt
->target
= target
;
1036 mt
->level
[0].level_x
= image
->tile_x
;
1037 mt
->level
[0].level_y
= image
->tile_y
;
1038 mt
->drm_modifier
= image
->modifier
;
1040 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1041 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1042 * trouble resolving back to destination image due to alignment issues.
1044 if (!brw
->has_surface_tile_offset
) {
1045 uint32_t draw_x
, draw_y
;
1046 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1048 if (draw_x
!= 0 || draw_y
!= 0) {
1049 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1050 intel_miptree_release(&mt
);
1055 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1056 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1058 mt
->aux_usage
= mod_info
->aux_usage
;
1059 /* If we are a window system buffer, then we can support fast-clears
1060 * even if the modifier doesn't support them by doing a partial resolve
1061 * as part of the flush operation.
1063 mt
->supports_fast_clear
=
1064 is_winsys_image
|| mod_info
->supports_clear_color
;
1066 /* We don't know the actual state of the surface when we get it but we
1067 * can make a pretty good guess based on the modifier. What we do know
1068 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1069 * a worst case of compression.
1071 enum isl_aux_state initial_state
=
1072 mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1073 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1075 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1076 intel_miptree_release(&mt
);
1081 /* Don't assume coherency for imported EGLimages. We don't know what
1082 * external clients are going to do with it. They may scan it out.
1084 image
->bo
->cache_coherent
= false;
1090 * For a singlesample renderbuffer, this simply wraps the given BO with a
1093 * For a multisample renderbuffer, this wraps the window system's
1094 * (singlesample) BO with a singlesample miptree attached to the
1095 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1096 * that will contain the actual rendering (which is lazily resolved to
1097 * irb->singlesample_mt).
1100 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1101 struct intel_renderbuffer
*irb
,
1102 struct intel_mipmap_tree
*singlesample_mt
,
1103 uint32_t width
, uint32_t height
,
1106 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1107 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1108 mesa_format format
= rb
->Format
;
1109 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1111 /* Only the front and back buffers, which are color buffers, are allocated
1112 * through the image loader.
1114 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1115 _mesa_get_format_base_format(format
) == GL_RGBA
);
1117 assert(singlesample_mt
);
1119 if (num_samples
== 1) {
1120 intel_miptree_release(&irb
->mt
);
1121 irb
->mt
= singlesample_mt
;
1123 assert(!irb
->singlesample_mt
);
1125 intel_miptree_release(&irb
->singlesample_mt
);
1126 irb
->singlesample_mt
= singlesample_mt
;
1129 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1130 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1131 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1136 if (!multisample_mt
)
1139 irb
->need_downsample
= false;
1140 intel_miptree_release(&irb
->mt
);
1141 irb
->mt
= multisample_mt
;
1147 intel_miptree_release(&irb
->mt
);
1151 struct intel_mipmap_tree
*
1152 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1156 uint32_t num_samples
)
1158 struct intel_mipmap_tree
*mt
;
1160 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1162 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1163 width
, height
, depth
, num_samples
,
1164 MIPTREE_CREATE_BUSY
);
1171 intel_miptree_release(&mt
);
1176 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1177 struct intel_mipmap_tree
*src
)
1182 intel_miptree_release(dst
);
1186 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1193 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1195 if (aux_buf
== NULL
)
1198 brw_bo_unreference(aux_buf
->bo
);
1204 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1209 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1210 if (--(*mt
)->refcount
<= 0) {
1213 DBG("%s deleting %p\n", __func__
, *mt
);
1215 brw_bo_unreference((*mt
)->bo
);
1216 intel_miptree_release(&(*mt
)->stencil_mt
);
1217 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1218 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1219 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1220 free_aux_state_map((*mt
)->aux_state
);
1222 intel_miptree_release(&(*mt
)->plane
[0]);
1223 intel_miptree_release(&(*mt
)->plane
[1]);
1225 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1226 free((*mt
)->level
[i
].slice
);
1236 intel_get_image_dims(struct gl_texture_image
*image
,
1237 int *width
, int *height
, int *depth
)
1239 switch (image
->TexObject
->Target
) {
1240 case GL_TEXTURE_1D_ARRAY
:
1241 /* For a 1D Array texture the OpenGL API will treat the image height as
1242 * the number of array slices. For Intel hardware, we treat the 1D array
1243 * as a 2D Array with a height of 1. So, here we want to swap image
1246 assert(image
->Depth
== 1);
1247 *width
= image
->Width
;
1249 *depth
= image
->Height
;
1251 case GL_TEXTURE_CUBE_MAP
:
1252 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1253 * though we really have 6 slices.
1255 assert(image
->Depth
== 1);
1256 *width
= image
->Width
;
1257 *height
= image
->Height
;
1261 *width
= image
->Width
;
1262 *height
= image
->Height
;
1263 *depth
= image
->Depth
;
1269 * Can the image be pulled into a unified mipmap tree? This mirrors
1270 * the completeness test in a lot of ways.
1272 * Not sure whether I want to pass gl_texture_image here.
1275 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1276 struct gl_texture_image
*image
)
1278 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1279 GLuint level
= intelImage
->base
.Base
.Level
;
1280 int width
, height
, depth
;
1282 /* glTexImage* choose the texture object based on the target passed in, and
1283 * objects can't change targets over their lifetimes, so this should be
1286 assert(image
->TexObject
->Target
== mt
->target
);
1288 mesa_format mt_format
= mt
->format
;
1289 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1290 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1291 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1292 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1293 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1294 mt_format
= mt
->etc_format
;
1296 if (image
->TexFormat
!= mt_format
)
1299 intel_get_image_dims(image
, &width
, &height
, &depth
);
1301 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1304 if (level
>= mt
->surf
.levels
)
1307 const unsigned level_depth
=
1308 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1309 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1310 mt
->surf
.logical_level0_px
.array_len
;
1312 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1313 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1314 depth
== level_depth
&&
1315 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1319 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1320 GLuint level
, GLuint slice
,
1321 GLuint
*x
, GLuint
*y
)
1323 if (level
== 0 && slice
== 0) {
1324 *x
= mt
->level
[0].level_x
;
1325 *y
= mt
->level
[0].level_y
;
1329 uint32_t x_offset_sa
, y_offset_sa
;
1331 /* Miptree itself can have an offset only if it represents a single
1332 * slice in an imported buffer object.
1333 * See intel_miptree_create_for_dri_image().
1335 assert(mt
->level
[0].level_x
== 0);
1336 assert(mt
->level
[0].level_y
== 0);
1338 /* Given level is relative to level zero while the miptree may be
1339 * represent just a subset of all levels starting from 'first_level'.
1341 assert(level
>= mt
->first_level
);
1342 level
-= mt
->first_level
;
1344 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1345 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1346 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1347 &x_offset_sa
, &y_offset_sa
);
1355 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1356 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1357 * and tile_h is set to 1.
1360 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1361 uint32_t *tile_w
, uint32_t *tile_h
)
1372 case ISL_TILING_LINEAR
:
1377 unreachable("not reached");
1383 * This function computes masks that may be used to select the bits of the X
1384 * and Y coordinates that indicate the offset within a tile. If the BO is
1385 * untiled, the masks are set to 0.
1388 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1389 uint32_t *mask_x
, uint32_t *mask_y
)
1391 uint32_t tile_w_bytes
, tile_h
;
1393 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1395 *mask_x
= tile_w_bytes
/ cpp
- 1;
1396 *mask_y
= tile_h
- 1;
1400 * Compute the offset (in bytes) from the start of the BO to the given x
1401 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1402 * multiples of the tile size.
1405 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1406 uint32_t x
, uint32_t y
)
1409 uint32_t pitch
= mt
->surf
.row_pitch
;
1411 switch (mt
->surf
.tiling
) {
1413 unreachable("not reached");
1414 case ISL_TILING_LINEAR
:
1415 return y
* pitch
+ x
* cpp
;
1417 assert((x
% (512 / cpp
)) == 0);
1418 assert((y
% 8) == 0);
1419 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1421 assert((x
% (128 / cpp
)) == 0);
1422 assert((y
% 32) == 0);
1423 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1428 * Rendering with tiled buffers requires that the base address of the buffer
1429 * be aligned to a page boundary. For renderbuffers, and sometimes with
1430 * textures, we may want the surface to point at a texture image level that
1431 * isn't at a page boundary.
1433 * This function returns an appropriately-aligned base offset
1434 * according to the tiling restrictions, plus any required x/y offset
1438 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1439 GLuint level
, GLuint slice
,
1444 uint32_t mask_x
, mask_y
;
1446 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1447 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1449 *tile_x
= x
& mask_x
;
1450 *tile_y
= y
& mask_y
;
1452 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1456 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1457 struct intel_mipmap_tree
*src_mt
,
1458 unsigned src_level
, unsigned src_layer
,
1459 struct intel_mipmap_tree
*dst_mt
,
1460 unsigned dst_level
, unsigned dst_layer
,
1461 unsigned width
, unsigned height
)
1464 ptrdiff_t src_stride
, dst_stride
;
1465 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1467 intel_miptree_map(brw
, src_mt
,
1468 src_level
, src_layer
,
1471 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1474 intel_miptree_map(brw
, dst_mt
,
1475 dst_level
, dst_layer
,
1478 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1482 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1483 _mesa_get_format_name(src_mt
->format
),
1484 src_mt
, src
, src_stride
,
1485 _mesa_get_format_name(dst_mt
->format
),
1486 dst_mt
, dst
, dst_stride
,
1489 int row_size
= cpp
* width
;
1490 if (src_stride
== row_size
&&
1491 dst_stride
== row_size
) {
1492 memcpy(dst
, src
, row_size
* height
);
1494 for (int i
= 0; i
< height
; i
++) {
1495 memcpy(dst
, src
, row_size
);
1501 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1502 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1504 /* Don't forget to copy the stencil data over, too. We could have skipped
1505 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1506 * shuffling the two data sources in/out of temporary storage instead of
1507 * the direct mapping we get this way.
1509 if (dst_mt
->stencil_mt
) {
1510 assert(src_mt
->stencil_mt
);
1511 intel_miptree_copy_slice_sw(brw
,
1512 src_mt
->stencil_mt
, src_level
, src_layer
,
1513 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1519 intel_miptree_copy_slice(struct brw_context
*brw
,
1520 struct intel_mipmap_tree
*src_mt
,
1521 unsigned src_level
, unsigned src_layer
,
1522 struct intel_mipmap_tree
*dst_mt
,
1523 unsigned dst_level
, unsigned dst_layer
)
1526 mesa_format format
= src_mt
->format
;
1527 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1528 src_level
- src_mt
->first_level
);
1529 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1530 src_level
- src_mt
->first_level
);
1532 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1533 src_level
- src_mt
->first_level
));
1535 assert(src_mt
->format
== dst_mt
->format
);
1537 if (dst_mt
->compressed
) {
1539 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1540 height
= ALIGN_NPOT(height
, j
) / j
;
1541 width
= ALIGN_NPOT(width
, i
) / i
;
1544 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1545 * below won't apply since we can't do the depth's Y tiling or the
1546 * stencil's W tiling in the blitter.
1548 if (src_mt
->stencil_mt
) {
1549 intel_miptree_copy_slice_sw(brw
,
1550 src_mt
, src_level
, src_layer
,
1551 dst_mt
, dst_level
, dst_layer
,
1556 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1557 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1559 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1562 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1563 _mesa_get_format_name(src_mt
->format
),
1564 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1565 _mesa_get_format_name(dst_mt
->format
),
1566 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1569 if (!intel_miptree_blit(brw
,
1570 src_mt
, src_level
, src_layer
, 0, 0, false,
1571 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1572 width
, height
, GL_COPY
)) {
1573 perf_debug("miptree validate blit for %s failed\n",
1574 _mesa_get_format_name(format
));
1576 intel_miptree_copy_slice_sw(brw
,
1577 src_mt
, src_level
, src_layer
,
1578 dst_mt
, dst_level
, dst_layer
,
1584 * Copies the image's current data to the given miptree, and associates that
1585 * miptree with the image.
1587 * If \c invalidate is true, then the actual image data does not need to be
1588 * copied, but the image still needs to be associated to the new miptree (this
1589 * is set to true if we're about to clear the image).
1592 intel_miptree_copy_teximage(struct brw_context
*brw
,
1593 struct intel_texture_image
*intelImage
,
1594 struct intel_mipmap_tree
*dst_mt
,
1597 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1598 struct intel_texture_object
*intel_obj
=
1599 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1600 int level
= intelImage
->base
.Base
.Level
;
1601 const unsigned face
= intelImage
->base
.Base
.Face
;
1602 unsigned start_layer
, end_layer
;
1604 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1606 assert(intelImage
->base
.Base
.Height
);
1608 end_layer
= intelImage
->base
.Base
.Height
- 1;
1609 } else if (face
> 0) {
1613 assert(intelImage
->base
.Base
.Depth
);
1615 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1619 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1620 intel_miptree_copy_slice(brw
,
1626 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1627 intel_obj
->needs_validate
= true;
1631 intel_miptree_init_mcs(struct brw_context
*brw
,
1632 struct intel_mipmap_tree
*mt
,
1635 assert(mt
->mcs_buf
!= NULL
);
1637 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1639 * When MCS buffer is enabled and bound to MSRT, it is required that it
1640 * is cleared prior to any rendering.
1642 * Since we don't use the MCS buffer for any purpose other than rendering,
1643 * it makes sense to just clear it immediately upon allocation.
1645 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1647 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1648 if (unlikely(map
== NULL
)) {
1649 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1650 brw_bo_unreference(mt
->mcs_buf
->bo
);
1655 memset(data
, init_value
, mt
->mcs_buf
->size
);
1656 brw_bo_unmap(mt
->mcs_buf
->bo
);
1659 static struct intel_miptree_aux_buffer
*
1660 intel_alloc_aux_buffer(struct brw_context
*brw
,
1662 const struct isl_surf
*aux_surf
,
1663 uint32_t alloc_flags
,
1664 struct intel_mipmap_tree
*mt
)
1666 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1670 buf
->size
= aux_surf
->size
;
1671 buf
->pitch
= aux_surf
->row_pitch
;
1672 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1674 /* ISL has stricter set of alignment rules then the drm allocator.
1675 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1676 * trying to recalculate based on different format block sizes.
1678 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1679 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1685 buf
->surf
= *aux_surf
;
1691 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1692 struct intel_mipmap_tree
*mt
,
1695 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1697 assert(devinfo
->gen
>= 7); /* MCS only used on Gen7+ */
1698 assert(mt
->mcs_buf
== NULL
);
1699 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1701 /* Multisampled miptrees are only supported for single level. */
1702 assert(mt
->first_level
== 0);
1703 enum isl_aux_state
**aux_state
=
1704 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1708 struct isl_surf temp_mcs_surf
;
1710 MAYBE_UNUSED
bool ok
=
1711 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1714 /* Buffer needs to be initialised requiring the buffer to be immediately
1715 * mapped to cpu space for writing. Therefore do not use the gpu access
1716 * flag which can cause an unnecessary delay if the backing pages happened
1717 * to be just used by the GPU.
1719 const uint32_t alloc_flags
= 0;
1720 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1721 &temp_mcs_surf
, alloc_flags
, mt
);
1727 mt
->aux_state
= aux_state
;
1729 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1735 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1736 struct intel_mipmap_tree
*mt
)
1738 assert(mt
->mcs_buf
== NULL
);
1739 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1740 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1742 struct isl_surf temp_ccs_surf
;
1744 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1747 assert(temp_ccs_surf
.size
&&
1748 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1750 enum isl_aux_state
**aux_state
=
1751 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1755 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1756 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1758 * "If Software wants to enable Color Compression without Fast clear,
1759 * Software needs to initialize MCS with zeros."
1761 * A CCS value of 0 indicates that the corresponding block is in the
1762 * pass-through state which is what we want.
1764 * For CCS_D, on the other hand, we don't care as we're about to perform a
1765 * fast-clear operation. In that case, being hot in caches more useful.
1767 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1768 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1769 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1770 &temp_ccs_surf
, alloc_flags
, mt
);
1776 mt
->aux_state
= aux_state
;
1782 * Helper for intel_miptree_alloc_hiz() that sets
1783 * \c mt->level[level].has_hiz. Return true if and only if
1784 * \c has_hiz was set.
1787 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1788 struct intel_mipmap_tree
*mt
,
1791 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1793 assert(mt
->hiz_buf
);
1794 assert(mt
->surf
.size
> 0);
1796 if (devinfo
->gen
>= 8 || brw
->is_haswell
) {
1797 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1798 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1800 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1801 * and the height is 4 aligned. This allows our HiZ support
1802 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1803 * we can grow the width & height to allow the HiZ op to
1804 * force the proper size alignments.
1806 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1807 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1812 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1813 mt
->level
[level
].has_hiz
= true;
1818 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1819 struct intel_mipmap_tree
*mt
)
1821 assert(mt
->hiz_buf
== NULL
);
1822 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1824 enum isl_aux_state
**aux_state
=
1825 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1829 struct isl_surf temp_hiz_surf
;
1831 MAYBE_UNUSED
bool ok
=
1832 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1835 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1836 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1837 &temp_hiz_surf
, alloc_flags
, mt
);
1844 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1845 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1847 mt
->aux_state
= aux_state
;
1854 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1856 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1857 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1858 * compress clear color so we wait until an actual fast-clear to allocate it.
1861 intel_miptree_alloc_aux(struct brw_context
*brw
,
1862 struct intel_mipmap_tree
*mt
)
1864 switch (mt
->aux_usage
) {
1865 case ISL_AUX_USAGE_NONE
:
1868 case ISL_AUX_USAGE_HIZ
:
1869 assert(!_mesa_is_format_color_format(mt
->format
));
1870 if (!intel_miptree_alloc_hiz(brw
, mt
))
1874 case ISL_AUX_USAGE_MCS
:
1875 assert(_mesa_is_format_color_format(mt
->format
));
1876 assert(mt
->surf
.samples
> 1);
1877 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1881 case ISL_AUX_USAGE_CCS_D
:
1882 /* Since CCS_D can only compress clear color so we wait until an actual
1883 * fast-clear to allocate it.
1887 case ISL_AUX_USAGE_CCS_E
:
1888 assert(_mesa_is_format_color_format(mt
->format
));
1889 assert(mt
->surf
.samples
== 1);
1890 if (!intel_miptree_alloc_ccs(brw
, mt
))
1895 unreachable("Invalid aux usage");
1900 * Can the miptree sample using the hiz buffer?
1903 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1904 struct intel_mipmap_tree
*mt
)
1906 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1908 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1909 * so keep things conservative for now and never enable it unless we're SKL+.
1911 if (devinfo
->gen
< 9) {
1919 /* It seems the hardware won't fallback to the depth buffer if some of the
1920 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1921 * of the texture to be HiZ enabled.
1923 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1924 if (!intel_miptree_level_has_hiz(mt
, level
))
1928 /* If compressed multisampling is enabled, then we use it for the auxiliary
1931 * From the BDW PRM (Volume 2d: Command Reference: Structures
1932 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1934 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1935 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1937 * There is no such blurb for 1D textures, but there is sufficient evidence
1938 * that this is broken on SKL+.
1940 return (mt
->surf
.samples
== 1 &&
1941 mt
->target
!= GL_TEXTURE_3D
&&
1942 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1946 * Does the miptree slice have hiz enabled?
1949 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1951 intel_miptree_check_level_layer(mt
, level
, 0);
1952 return mt
->level
[level
].has_hiz
;
1955 static inline uint32_t
1956 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1957 uint32_t start_level
, uint32_t num_levels
)
1959 assert(start_level
>= mt
->first_level
);
1960 assert(start_level
<= mt
->last_level
);
1962 if (num_levels
== INTEL_REMAINING_LAYERS
)
1963 num_levels
= mt
->last_level
- start_level
+ 1;
1964 /* Check for overflow */
1965 assert(start_level
+ num_levels
>= start_level
);
1966 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1971 static inline uint32_t
1972 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1973 uint32_t start_layer
, uint32_t num_layers
)
1975 assert(level
<= mt
->last_level
);
1977 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1978 assert(start_layer
< total_num_layers
);
1979 if (num_layers
== INTEL_REMAINING_LAYERS
)
1980 num_layers
= total_num_layers
- start_layer
;
1981 /* Check for overflow */
1982 assert(start_layer
+ num_layers
>= start_layer
);
1983 assert(start_layer
+ num_layers
<= total_num_layers
);
1989 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1990 unsigned start_level
, unsigned num_levels
,
1991 unsigned start_layer
, unsigned num_layers
)
1993 assert(_mesa_is_format_color_format(mt
->format
));
1998 /* Clamp the level range to fit the miptree */
1999 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2001 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2002 const uint32_t level
= start_level
+ l
;
2003 const uint32_t level_layers
=
2004 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2005 for (unsigned a
= 0; a
< level_layers
; a
++) {
2006 enum isl_aux_state aux_state
=
2007 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2008 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2009 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2018 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2019 const struct intel_mipmap_tree
*mt
,
2020 unsigned level
, unsigned layer
)
2022 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2027 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2028 assert(devinfo
->gen
>= 8 ||
2029 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2031 /* Compression of arrayed msaa surfaces is supported. */
2032 if (mt
->surf
.samples
> 1)
2035 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2036 assert(devinfo
->gen
>= 8 ||
2038 mt
->surf
.logical_level0_px
.depth
== 1 &&
2039 mt
->surf
.logical_level0_px
.array_len
== 1));
2045 static enum blorp_fast_clear_op
2046 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2047 enum isl_aux_usage aux_usage
,
2048 bool fast_clear_supported
)
2050 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2052 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2054 assert(ccs_supported
== fast_clear_supported
);
2056 switch (aux_state
) {
2057 case ISL_AUX_STATE_CLEAR
:
2058 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2060 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2062 return BLORP_FAST_CLEAR_OP_NONE
;
2064 case ISL_AUX_STATE_PASS_THROUGH
:
2065 return BLORP_FAST_CLEAR_OP_NONE
;
2067 case ISL_AUX_STATE_RESOLVED
:
2068 case ISL_AUX_STATE_AUX_INVALID
:
2069 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2070 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2074 unreachable("Invalid aux state for CCS_D");
2077 static enum blorp_fast_clear_op
2078 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2079 enum isl_aux_usage aux_usage
,
2080 bool fast_clear_supported
)
2082 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2083 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2084 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2085 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2087 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2088 assert(fast_clear_supported
);
2090 switch (aux_state
) {
2091 case ISL_AUX_STATE_CLEAR
:
2092 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2093 if (fast_clear_supported
)
2094 return BLORP_FAST_CLEAR_OP_NONE
;
2095 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2096 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2098 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2100 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2101 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2102 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2103 else if (!fast_clear_supported
)
2104 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2106 return BLORP_FAST_CLEAR_OP_NONE
;
2108 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2109 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2110 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2112 return BLORP_FAST_CLEAR_OP_NONE
;
2114 case ISL_AUX_STATE_PASS_THROUGH
:
2115 return BLORP_FAST_CLEAR_OP_NONE
;
2117 case ISL_AUX_STATE_RESOLVED
:
2118 case ISL_AUX_STATE_AUX_INVALID
:
2122 unreachable("Invalid aux state for CCS_E");
2126 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2127 struct intel_mipmap_tree
*mt
,
2128 uint32_t level
, uint32_t layer
,
2129 enum isl_aux_usage aux_usage
,
2130 bool fast_clear_supported
)
2132 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2134 enum blorp_fast_clear_op resolve_op
;
2135 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2136 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2137 fast_clear_supported
);
2139 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2140 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2141 fast_clear_supported
);
2144 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2145 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2146 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2148 switch (resolve_op
) {
2149 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2150 /* The CCS full resolve operation destroys the CCS and sets it to the
2151 * pass-through state. (You can also think of this as being both a
2152 * resolve and an ambiguate in one operation.)
2154 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2155 ISL_AUX_STATE_PASS_THROUGH
);
2158 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2159 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2160 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2164 unreachable("Invalid resolve op");
2170 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2171 struct intel_mipmap_tree
*mt
,
2172 uint32_t level
, uint32_t layer
,
2173 enum isl_aux_usage aux_usage
)
2175 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2176 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2177 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2179 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2181 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2182 switch (aux_state
) {
2183 case ISL_AUX_STATE_CLEAR
:
2184 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2185 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2186 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2188 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2189 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2190 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2191 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2192 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2193 ISL_AUX_STATE_PARTIAL_CLEAR
);
2197 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2198 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2199 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2200 break; /* Nothing to do */
2202 case ISL_AUX_STATE_PASS_THROUGH
:
2203 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2204 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2205 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2211 case ISL_AUX_STATE_RESOLVED
:
2212 case ISL_AUX_STATE_AUX_INVALID
:
2213 unreachable("Invalid aux state for CCS_E");
2216 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2217 /* CCS_D is a bit simpler */
2218 switch (aux_state
) {
2219 case ISL_AUX_STATE_CLEAR
:
2220 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2221 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2222 ISL_AUX_STATE_PARTIAL_CLEAR
);
2225 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2226 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2227 break; /* Nothing to do */
2229 case ISL_AUX_STATE_PASS_THROUGH
:
2233 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2234 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2235 case ISL_AUX_STATE_RESOLVED
:
2236 case ISL_AUX_STATE_AUX_INVALID
:
2237 unreachable("Invalid aux state for CCS_D");
2243 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2244 struct intel_mipmap_tree
*mt
,
2246 enum isl_aux_usage aux_usage
,
2247 bool fast_clear_supported
)
2249 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2251 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2252 case ISL_AUX_STATE_CLEAR
:
2253 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2254 if (!fast_clear_supported
) {
2255 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2256 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2257 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2261 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2262 break; /* Nothing to do */
2264 case ISL_AUX_STATE_RESOLVED
:
2265 case ISL_AUX_STATE_PASS_THROUGH
:
2266 case ISL_AUX_STATE_AUX_INVALID
:
2267 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2268 unreachable("Invalid aux state for MCS");
2273 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2274 struct intel_mipmap_tree
*mt
,
2276 enum isl_aux_usage aux_usage
)
2278 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2280 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2281 case ISL_AUX_STATE_CLEAR
:
2282 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2283 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2286 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2287 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2288 break; /* Nothing to do */
2290 case ISL_AUX_STATE_RESOLVED
:
2291 case ISL_AUX_STATE_PASS_THROUGH
:
2292 case ISL_AUX_STATE_AUX_INVALID
:
2293 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2294 unreachable("Invalid aux state for MCS");
2299 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2300 struct intel_mipmap_tree
*mt
,
2301 uint32_t level
, uint32_t layer
,
2302 enum isl_aux_usage aux_usage
,
2303 bool fast_clear_supported
)
2305 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2307 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2308 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2309 case ISL_AUX_STATE_CLEAR
:
2310 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2311 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2312 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2315 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2316 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2317 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2320 case ISL_AUX_STATE_PASS_THROUGH
:
2321 case ISL_AUX_STATE_RESOLVED
:
2324 case ISL_AUX_STATE_AUX_INVALID
:
2325 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2326 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2329 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2330 unreachable("Invalid HiZ state");
2333 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2334 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2337 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2338 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2339 ISL_AUX_STATE_RESOLVED
);
2342 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2343 /* The HiZ resolve operation is actually an ambiguate */
2344 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2345 ISL_AUX_STATE_PASS_THROUGH
);
2349 unreachable("Invalid HiZ op");
2355 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 uint32_t level
, uint32_t layer
,
2358 enum isl_aux_usage aux_usage
)
2360 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2362 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2363 case ISL_AUX_STATE_CLEAR
:
2364 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2365 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2366 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2369 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2370 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2371 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2372 break; /* Nothing to do */
2374 case ISL_AUX_STATE_RESOLVED
:
2375 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2376 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2377 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2379 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2380 ISL_AUX_STATE_AUX_INVALID
);
2384 case ISL_AUX_STATE_PASS_THROUGH
:
2385 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2386 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2387 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2391 case ISL_AUX_STATE_AUX_INVALID
:
2392 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2395 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2396 unreachable("Invalid HiZ state");
2401 intel_miptree_prepare_access(struct brw_context
*brw
,
2402 struct intel_mipmap_tree
*mt
,
2403 uint32_t start_level
, uint32_t num_levels
,
2404 uint32_t start_layer
, uint32_t num_layers
,
2405 enum isl_aux_usage aux_usage
,
2406 bool fast_clear_supported
)
2408 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2410 switch (mt
->aux_usage
) {
2411 case ISL_AUX_USAGE_NONE
:
2415 case ISL_AUX_USAGE_MCS
:
2416 assert(mt
->mcs_buf
);
2417 assert(start_level
== 0 && num_levels
== 1);
2418 const uint32_t level_layers
=
2419 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2420 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2421 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2422 aux_usage
, fast_clear_supported
);
2426 case ISL_AUX_USAGE_CCS_D
:
2427 case ISL_AUX_USAGE_CCS_E
:
2431 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2432 const uint32_t level
= start_level
+ l
;
2433 const uint32_t level_layers
=
2434 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2435 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2436 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2438 aux_usage
, fast_clear_supported
);
2443 case ISL_AUX_USAGE_HIZ
:
2444 assert(mt
->hiz_buf
);
2445 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2446 const uint32_t level
= start_level
+ l
;
2447 if (!intel_miptree_level_has_hiz(mt
, level
))
2450 const uint32_t level_layers
=
2451 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2452 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2453 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2454 aux_usage
, fast_clear_supported
);
2460 unreachable("Invalid aux usage");
2465 intel_miptree_finish_write(struct brw_context
*brw
,
2466 struct intel_mipmap_tree
*mt
, uint32_t level
,
2467 uint32_t start_layer
, uint32_t num_layers
,
2468 enum isl_aux_usage aux_usage
)
2470 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2472 switch (mt
->aux_usage
) {
2473 case ISL_AUX_USAGE_NONE
:
2477 case ISL_AUX_USAGE_MCS
:
2478 assert(mt
->mcs_buf
);
2479 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2480 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2485 case ISL_AUX_USAGE_CCS_D
:
2486 case ISL_AUX_USAGE_CCS_E
:
2490 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2491 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2496 case ISL_AUX_USAGE_HIZ
:
2497 if (!intel_miptree_level_has_hiz(mt
, level
))
2500 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2501 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2507 unreachable("Invavlid aux usage");
2512 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2513 uint32_t level
, uint32_t layer
)
2515 intel_miptree_check_level_layer(mt
, level
, layer
);
2517 if (_mesa_is_format_color_format(mt
->format
)) {
2518 assert(mt
->mcs_buf
!= NULL
);
2519 assert(mt
->surf
.samples
== 1 ||
2520 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2521 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2522 unreachable("Cannot get aux state for stencil");
2524 assert(intel_miptree_level_has_hiz(mt
, level
));
2527 return mt
->aux_state
[level
][layer
];
2531 intel_miptree_set_aux_state(struct brw_context
*brw
,
2532 struct intel_mipmap_tree
*mt
, uint32_t level
,
2533 uint32_t start_layer
, uint32_t num_layers
,
2534 enum isl_aux_state aux_state
)
2536 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2538 if (_mesa_is_format_color_format(mt
->format
)) {
2539 assert(mt
->mcs_buf
!= NULL
);
2540 assert(mt
->surf
.samples
== 1 ||
2541 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2542 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2543 unreachable("Cannot get aux state for stencil");
2545 assert(intel_miptree_level_has_hiz(mt
, level
));
2548 for (unsigned a
= 0; a
< num_layers
; a
++)
2549 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2552 /* On Gen9 color buffers may be compressed by the hardware (lossless
2553 * compression). There are, however, format restrictions and care needs to be
2554 * taken that the sampler engine is capable for re-interpreting a buffer with
2555 * format different the buffer was originally written with.
2557 * For example, SRGB formats are not compressible and the sampler engine isn't
2558 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2559 * color buffer needs to be resolved so that the sampling surface can be
2560 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2564 can_texture_with_ccs(struct brw_context
*brw
,
2565 struct intel_mipmap_tree
*mt
,
2566 enum isl_format view_format
)
2568 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2571 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2572 mt
->surf
.format
, view_format
)) {
2573 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2574 isl_format_get_layout(view_format
)->name
,
2575 _mesa_get_format_name(mt
->format
));
2583 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2584 struct intel_mipmap_tree
*mt
,
2585 enum isl_format view_format
)
2587 switch (mt
->aux_usage
) {
2588 case ISL_AUX_USAGE_HIZ
:
2589 if (intel_miptree_sample_with_hiz(brw
, mt
))
2590 return ISL_AUX_USAGE_HIZ
;
2593 case ISL_AUX_USAGE_MCS
:
2594 return ISL_AUX_USAGE_MCS
;
2596 case ISL_AUX_USAGE_CCS_D
:
2597 case ISL_AUX_USAGE_CCS_E
:
2599 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2600 return ISL_AUX_USAGE_NONE
;
2603 /* If we don't have any unresolved color, report an aux usage of
2604 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2605 * aux surface and we can save some bandwidth.
2607 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2608 0, INTEL_REMAINING_LAYERS
))
2609 return ISL_AUX_USAGE_NONE
;
2611 if (can_texture_with_ccs(brw
, mt
, view_format
))
2612 return ISL_AUX_USAGE_CCS_E
;
2619 return ISL_AUX_USAGE_NONE
;
2623 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2625 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2626 * values so sRGB curve application was a no-op for all fast-clearable
2629 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2630 * values, the hardware interprets the floats, not as what would be
2631 * returned from the sampler (or written by the shader), but as being
2632 * between format conversion and sRGB curve application. This means that
2633 * we can switch between sRGB and UNORM without having to whack the clear
2636 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2640 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2641 struct intel_mipmap_tree
*mt
,
2642 enum isl_format view_format
,
2643 uint32_t start_level
, uint32_t num_levels
,
2644 uint32_t start_layer
, uint32_t num_layers
,
2645 bool *aux_supported_out
)
2647 enum isl_aux_usage aux_usage
=
2648 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2649 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2651 /* Clear color is specified as ints or floats and the conversion is done by
2652 * the sampler. If we have a texture view, we would have to perform the
2653 * clear color conversion manually. Just disable clear color.
2655 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2656 clear_supported
= false;
2658 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2659 start_layer
, num_layers
,
2660 aux_usage
, clear_supported
);
2661 if (aux_supported_out
)
2662 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2666 intel_miptree_prepare_texture(struct brw_context
*brw
,
2667 struct intel_mipmap_tree
*mt
,
2668 enum isl_format view_format
,
2669 bool *aux_supported_out
)
2671 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2672 0, INTEL_REMAINING_LEVELS
,
2673 0, INTEL_REMAINING_LAYERS
,
2678 intel_miptree_prepare_image(struct brw_context
*brw
,
2679 struct intel_mipmap_tree
*mt
)
2681 /* The data port doesn't understand any compression */
2682 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2683 0, INTEL_REMAINING_LAYERS
,
2684 ISL_AUX_USAGE_NONE
, false);
2688 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2689 struct intel_mipmap_tree
*mt
, uint32_t level
,
2690 uint32_t start_layer
, uint32_t num_layers
)
2692 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2693 start_layer
, num_layers
, NULL
);
2697 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2698 struct intel_mipmap_tree
*mt
,
2699 bool srgb_enabled
, bool blend_enabled
)
2701 switch (mt
->aux_usage
) {
2702 case ISL_AUX_USAGE_MCS
:
2703 assert(mt
->mcs_buf
);
2704 return ISL_AUX_USAGE_MCS
;
2706 case ISL_AUX_USAGE_CCS_D
:
2707 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2709 case ISL_AUX_USAGE_CCS_E
: {
2710 mesa_format mesa_format
=
2711 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2712 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2714 /* If the format supports CCS_E, then we can just use it */
2715 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2716 return ISL_AUX_USAGE_CCS_E
;
2718 /* Otherwise, we have to fall back to CCS_D */
2720 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2721 * formats. However, there are issues with blending where it doesn't
2722 * properly apply the sRGB curve to the clear color when blending.
2724 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2725 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2726 return ISL_AUX_USAGE_NONE
;
2728 return ISL_AUX_USAGE_CCS_D
;
2732 return ISL_AUX_USAGE_NONE
;
2737 intel_miptree_prepare_render(struct brw_context
*brw
,
2738 struct intel_mipmap_tree
*mt
, uint32_t level
,
2739 uint32_t start_layer
, uint32_t layer_count
,
2740 bool srgb_enabled
, bool blend_enabled
)
2742 enum isl_aux_usage aux_usage
=
2743 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2744 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2745 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2749 intel_miptree_finish_render(struct brw_context
*brw
,
2750 struct intel_mipmap_tree
*mt
, uint32_t level
,
2751 uint32_t start_layer
, uint32_t layer_count
,
2752 bool srgb_enabled
, bool blend_enabled
)
2754 assert(_mesa_is_format_color_format(mt
->format
));
2756 enum isl_aux_usage aux_usage
=
2757 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2758 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2763 intel_miptree_prepare_depth(struct brw_context
*brw
,
2764 struct intel_mipmap_tree
*mt
, uint32_t level
,
2765 uint32_t start_layer
, uint32_t layer_count
)
2767 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2768 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2772 intel_miptree_finish_depth(struct brw_context
*brw
,
2773 struct intel_mipmap_tree
*mt
, uint32_t level
,
2774 uint32_t start_layer
, uint32_t layer_count
,
2777 if (depth_written
) {
2778 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2779 mt
->hiz_buf
!= NULL
);
2784 intel_miptree_prepare_external(struct brw_context
*brw
,
2785 struct intel_mipmap_tree
*mt
)
2787 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2788 bool supports_fast_clear
= false;
2790 const struct isl_drm_modifier_info
*mod_info
=
2791 isl_drm_modifier_get_info(mt
->drm_modifier
);
2793 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2794 /* CCS_E is the only supported aux for external images and it's only
2795 * supported on very simple images.
2797 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2798 assert(_mesa_is_format_color_format(mt
->format
));
2799 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2800 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2801 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2802 assert(mt
->surf
.samples
== 1);
2803 assert(mt
->mcs_buf
!= NULL
);
2805 aux_usage
= mod_info
->aux_usage
;
2806 supports_fast_clear
= mod_info
->supports_clear_color
;
2809 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2810 0, INTEL_REMAINING_LAYERS
,
2811 aux_usage
, supports_fast_clear
);
2815 * Make it possible to share the BO backing the given miptree with another
2816 * process or another miptree.
2818 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2819 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2820 * ensure that no MCS buffer gets allocated in the future.
2822 * HiZ is similarly unsafe with shared buffers.
2825 intel_miptree_make_shareable(struct brw_context
*brw
,
2826 struct intel_mipmap_tree
*mt
)
2828 /* MCS buffers are also used for multisample buffers, but we can't resolve
2829 * away a multisample MCS buffer because it's an integral part of how the
2830 * pixel data is stored. Fortunately this code path should never be
2831 * reached for multisample buffers.
2833 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2834 mt
->surf
.samples
== 1);
2836 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2837 0, INTEL_REMAINING_LAYERS
,
2838 ISL_AUX_USAGE_NONE
, false);
2841 brw_bo_unreference(mt
->mcs_buf
->bo
);
2845 /* Any pending MCS/CCS operations are no longer needed. Trying to
2846 * execute any will likely crash due to the missing aux buffer. So let's
2847 * delete all pending ops.
2849 free(mt
->aux_state
);
2850 mt
->aux_state
= NULL
;
2854 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2857 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2858 mt
->level
[l
].has_hiz
= false;
2861 /* Any pending HiZ operations are no longer needed. Trying to execute
2862 * any will likely crash due to the missing aux buffer. So let's delete
2865 free(mt
->aux_state
);
2866 mt
->aux_state
= NULL
;
2869 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2870 mt
->supports_fast_clear
= false;
2875 * \brief Get pointer offset into stencil buffer.
2877 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2878 * must decode the tile's layout in software.
2881 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2883 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2885 * Even though the returned offset is always positive, the return type is
2887 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2888 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2891 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2893 uint32_t tile_size
= 4096;
2894 uint32_t tile_width
= 64;
2895 uint32_t tile_height
= 64;
2896 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2898 uint32_t tile_x
= x
/ tile_width
;
2899 uint32_t tile_y
= y
/ tile_height
;
2901 /* The byte's address relative to the tile's base addres. */
2902 uint32_t byte_x
= x
% tile_width
;
2903 uint32_t byte_y
= y
% tile_height
;
2905 uintptr_t u
= tile_y
* row_size
2906 + tile_x
* tile_size
2907 + 512 * (byte_x
/ 8)
2909 + 32 * ((byte_y
/ 4) % 2)
2910 + 16 * ((byte_x
/ 4) % 2)
2911 + 8 * ((byte_y
/ 2) % 2)
2912 + 4 * ((byte_x
/ 2) % 2)
2917 /* adjust for bit6 swizzling */
2918 if (((byte_x
/ 8) % 2) == 1) {
2919 if (((byte_y
/ 8) % 2) == 0) {
2931 intel_miptree_updownsample(struct brw_context
*brw
,
2932 struct intel_mipmap_tree
*src
,
2933 struct intel_mipmap_tree
*dst
)
2935 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2936 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2937 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2938 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2940 brw_blorp_blit_miptrees(brw
,
2941 src
, 0 /* level */, 0 /* layer */,
2942 src
->format
, SWIZZLE_XYZW
,
2943 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2946 GL_NEAREST
, false, false /*mirror x, y*/,
2949 if (src
->stencil_mt
) {
2950 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2951 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2952 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2953 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2955 brw_blorp_blit_miptrees(brw
,
2956 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2957 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2958 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2959 dst
->stencil_mt
->format
,
2962 GL_NEAREST
, false, false /*mirror x, y*/,
2963 false, false /* decode/encode srgb */);
2968 intel_update_r8stencil(struct brw_context
*brw
,
2969 struct intel_mipmap_tree
*mt
)
2971 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2973 assert(devinfo
->gen
>= 7);
2974 struct intel_mipmap_tree
*src
=
2975 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2976 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2979 assert(src
->surf
.size
> 0);
2981 if (!mt
->r8stencil_mt
) {
2982 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2983 mt
->r8stencil_mt
= make_surface(
2986 MESA_FORMAT_R_UINT8
,
2987 src
->first_level
, src
->last_level
,
2988 src
->surf
.logical_level0_px
.width
,
2989 src
->surf
.logical_level0_px
.height
,
2990 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2991 src
->surf
.logical_level0_px
.depth
:
2992 src
->surf
.logical_level0_px
.array_len
,
2995 ISL_SURF_USAGE_TEXTURE_BIT
,
2996 BO_ALLOC_BUSY
, 0, NULL
);
2997 assert(mt
->r8stencil_mt
);
3000 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3002 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3003 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3004 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3005 src
->surf
.phys_level0_sa
.array_len
;
3007 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3008 brw_blorp_copy_miptrees(brw
,
3012 minify(src
->surf
.logical_level0_px
.width
,
3014 minify(src
->surf
.logical_level0_px
.height
,
3019 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3020 src
->r8stencil_needs_update
= false;
3024 intel_miptree_map_raw(struct brw_context
*brw
,
3025 struct intel_mipmap_tree
*mt
,
3028 struct brw_bo
*bo
= mt
->bo
;
3030 if (brw_batch_references(&brw
->batch
, bo
))
3031 intel_batchbuffer_flush(brw
);
3033 return brw_bo_map(brw
, bo
, mode
);
3037 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3039 brw_bo_unmap(mt
->bo
);
3043 intel_miptree_map_gtt(struct brw_context
*brw
,
3044 struct intel_mipmap_tree
*mt
,
3045 struct intel_miptree_map
*map
,
3046 unsigned int level
, unsigned int slice
)
3048 unsigned int bw
, bh
;
3050 unsigned int image_x
, image_y
;
3051 intptr_t x
= map
->x
;
3052 intptr_t y
= map
->y
;
3054 /* For compressed formats, the stride is the number of bytes per
3055 * row of blocks. intel_miptree_get_image_offset() already does
3058 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3059 assert(y
% bh
== 0);
3060 assert(x
% bw
== 0);
3064 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3071 /* Note that in the case of cube maps, the caller must have passed the
3072 * slice number referencing the face.
3074 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3078 map
->stride
= mt
->surf
.row_pitch
;
3079 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3082 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3083 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3084 map
->x
, map
->y
, map
->w
, map
->h
,
3085 mt
, _mesa_get_format_name(mt
->format
),
3086 x
, y
, map
->ptr
, map
->stride
);
3090 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3092 intel_miptree_unmap_raw(mt
);
3096 intel_miptree_map_blit(struct brw_context
*brw
,
3097 struct intel_mipmap_tree
*mt
,
3098 struct intel_miptree_map
*map
,
3099 unsigned int level
, unsigned int slice
)
3101 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3102 /* first_level */ 0,
3106 MIPTREE_CREATE_LINEAR
);
3108 if (!map
->linear_mt
) {
3109 fprintf(stderr
, "Failed to allocate blit temporary\n");
3112 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3114 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3115 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3116 * invalidate is set, since we'll be writing the whole rectangle from our
3117 * temporary buffer back out.
3119 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3120 if (!intel_miptree_copy(brw
,
3121 mt
, level
, slice
, map
->x
, map
->y
,
3122 map
->linear_mt
, 0, 0, 0, 0,
3124 fprintf(stderr
, "Failed to blit\n");
3129 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3131 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3132 map
->x
, map
->y
, map
->w
, map
->h
,
3133 mt
, _mesa_get_format_name(mt
->format
),
3134 level
, slice
, map
->ptr
, map
->stride
);
3139 intel_miptree_release(&map
->linear_mt
);
3145 intel_miptree_unmap_blit(struct brw_context
*brw
,
3146 struct intel_mipmap_tree
*mt
,
3147 struct intel_miptree_map
*map
,
3151 struct gl_context
*ctx
= &brw
->ctx
;
3153 intel_miptree_unmap_raw(map
->linear_mt
);
3155 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3156 bool ok
= intel_miptree_copy(brw
,
3157 map
->linear_mt
, 0, 0, 0, 0,
3158 mt
, level
, slice
, map
->x
, map
->y
,
3160 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3163 intel_miptree_release(&map
->linear_mt
);
3167 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3169 #if defined(USE_SSE41)
3171 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3172 struct intel_mipmap_tree
*mt
,
3173 struct intel_miptree_map
*map
,
3174 unsigned int level
, unsigned int slice
)
3176 assert(map
->mode
& GL_MAP_READ_BIT
);
3177 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3179 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3180 map
->x
, map
->y
, map
->w
, map
->h
,
3181 mt
, _mesa_get_format_name(mt
->format
),
3182 level
, slice
, map
->ptr
, map
->stride
);
3184 /* Map the original image */
3187 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3191 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3197 src
+= image_y
* mt
->surf
.row_pitch
;
3198 src
+= image_x
* mt
->cpp
;
3200 /* Due to the pixel offsets for the particular image being mapped, our
3201 * src pointer may not be 16-byte aligned. However, if the pitch is
3202 * divisible by 16, then the amount by which it's misaligned will remain
3203 * consistent from row to row.
3205 assert((mt
->surf
.row_pitch
% 16) == 0);
3206 const int misalignment
= ((uintptr_t) src
) & 15;
3208 /* Create an untiled temporary buffer for the mapping. */
3209 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3211 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3213 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3214 /* Offset the destination so it has the same misalignment as src. */
3215 map
->ptr
= map
->buffer
+ misalignment
;
3217 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3219 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3220 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3221 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3223 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3226 intel_miptree_unmap_raw(mt
);
3230 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3231 struct intel_mipmap_tree
*mt
,
3232 struct intel_miptree_map
*map
,
3236 _mesa_align_free(map
->buffer
);
3243 intel_miptree_map_s8(struct brw_context
*brw
,
3244 struct intel_mipmap_tree
*mt
,
3245 struct intel_miptree_map
*map
,
3246 unsigned int level
, unsigned int slice
)
3248 map
->stride
= map
->w
;
3249 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3253 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3254 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3255 * invalidate is set, since we'll be writing the whole rectangle from our
3256 * temporary buffer back out.
3258 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3259 uint8_t *untiled_s8_map
= map
->ptr
;
3260 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3261 unsigned int image_x
, image_y
;
3263 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3265 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3266 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3267 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3268 x
+ image_x
+ map
->x
,
3269 y
+ image_y
+ map
->y
,
3270 brw
->has_swizzling
);
3271 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3275 intel_miptree_unmap_raw(mt
);
3277 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3278 map
->x
, map
->y
, map
->w
, map
->h
,
3279 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3281 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3282 map
->x
, map
->y
, map
->w
, map
->h
,
3283 mt
, map
->ptr
, map
->stride
);
3288 intel_miptree_unmap_s8(struct brw_context
*brw
,
3289 struct intel_mipmap_tree
*mt
,
3290 struct intel_miptree_map
*map
,
3294 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3295 unsigned int image_x
, image_y
;
3296 uint8_t *untiled_s8_map
= map
->ptr
;
3297 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3299 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3301 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3302 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3303 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3304 image_x
+ x
+ map
->x
,
3305 image_y
+ y
+ map
->y
,
3306 brw
->has_swizzling
);
3307 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3311 intel_miptree_unmap_raw(mt
);
3318 intel_miptree_map_etc(struct brw_context
*brw
,
3319 struct intel_mipmap_tree
*mt
,
3320 struct intel_miptree_map
*map
,
3324 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3325 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3326 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3329 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3330 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3332 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3333 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3334 map
->w
, map
->h
, 1));
3335 map
->ptr
= map
->buffer
;
3339 intel_miptree_unmap_etc(struct brw_context
*brw
,
3340 struct intel_mipmap_tree
*mt
,
3341 struct intel_miptree_map
*map
,
3347 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3352 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3353 + image_y
* mt
->surf
.row_pitch
3354 + image_x
* mt
->cpp
;
3356 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3357 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3358 map
->ptr
, map
->stride
,
3361 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3362 map
->ptr
, map
->stride
,
3363 map
->w
, map
->h
, mt
->etc_format
);
3365 intel_miptree_unmap_raw(mt
);
3370 * Mapping function for packed depth/stencil miptrees backed by real separate
3371 * miptrees for depth and stencil.
3373 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3374 * separate from the depth buffer. Yet at the GL API level, we have to expose
3375 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3376 * be able to map that memory for texture storage and glReadPixels-type
3377 * operations. We give Mesa core that access by mallocing a temporary and
3378 * copying the data between the actual backing store and the temporary.
3381 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3382 struct intel_mipmap_tree
*mt
,
3383 struct intel_miptree_map
*map
,
3384 unsigned int level
, unsigned int slice
)
3386 struct intel_mipmap_tree
*z_mt
= mt
;
3387 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3388 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3389 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3391 map
->stride
= map
->w
* packed_bpp
;
3392 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3396 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3397 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3398 * invalidate is set, since we'll be writing the whole rectangle from our
3399 * temporary buffer back out.
3401 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3402 uint32_t *packed_map
= map
->ptr
;
3403 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3404 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3405 unsigned int s_image_x
, s_image_y
;
3406 unsigned int z_image_x
, z_image_y
;
3408 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3409 &s_image_x
, &s_image_y
);
3410 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3411 &z_image_x
, &z_image_y
);
3413 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3414 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3415 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3416 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3419 brw
->has_swizzling
);
3420 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3421 (z_mt
->surf
.row_pitch
/ 4) +
3422 (map_x
+ z_image_x
));
3423 uint8_t s
= s_map
[s_offset
];
3424 uint32_t z
= z_map
[z_offset
];
3426 if (map_z32f_x24s8
) {
3427 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3428 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3430 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3435 intel_miptree_unmap_raw(s_mt
);
3436 intel_miptree_unmap_raw(z_mt
);
3438 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3440 map
->x
, map
->y
, map
->w
, map
->h
,
3441 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3442 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3443 map
->ptr
, map
->stride
);
3445 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3446 map
->x
, map
->y
, map
->w
, map
->h
,
3447 mt
, map
->ptr
, map
->stride
);
3452 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3453 struct intel_mipmap_tree
*mt
,
3454 struct intel_miptree_map
*map
,
3458 struct intel_mipmap_tree
*z_mt
= mt
;
3459 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3460 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3462 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3463 uint32_t *packed_map
= map
->ptr
;
3464 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3465 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3466 unsigned int s_image_x
, s_image_y
;
3467 unsigned int z_image_x
, z_image_y
;
3469 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3470 &s_image_x
, &s_image_y
);
3471 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3472 &z_image_x
, &z_image_y
);
3474 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3475 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3476 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3477 x
+ s_image_x
+ map
->x
,
3478 y
+ s_image_y
+ map
->y
,
3479 brw
->has_swizzling
);
3480 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3481 (z_mt
->surf
.row_pitch
/ 4) +
3482 (x
+ z_image_x
+ map
->x
));
3484 if (map_z32f_x24s8
) {
3485 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3486 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3488 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3489 s_map
[s_offset
] = packed
>> 24;
3490 z_map
[z_offset
] = packed
;
3495 intel_miptree_unmap_raw(s_mt
);
3496 intel_miptree_unmap_raw(z_mt
);
3498 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3500 map
->x
, map
->y
, map
->w
, map
->h
,
3501 z_mt
, _mesa_get_format_name(z_mt
->format
),
3502 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3503 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3504 map
->ptr
, map
->stride
);
3511 * Create and attach a map to the miptree at (level, slice). Return the
3514 static struct intel_miptree_map
*
3515 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3524 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3529 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3530 mt
->level
[level
].slice
[slice
].map
= map
;
3542 * Release the map at (level, slice).
3545 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3549 struct intel_miptree_map
**map
;
3551 map
= &mt
->level
[level
].slice
[slice
].map
;
3557 can_blit_slice(struct intel_mipmap_tree
*mt
,
3558 unsigned int level
, unsigned int slice
)
3560 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3561 if (mt
->surf
.row_pitch
>= 32768)
3568 use_intel_mipree_map_blit(struct brw_context
*brw
,
3569 struct intel_mipmap_tree
*mt
,
3574 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3577 /* It's probably not worth swapping to the blit ring because of
3578 * all the overhead involved.
3580 !(mode
& GL_MAP_WRITE_BIT
) &&
3582 (mt
->surf
.tiling
== ISL_TILING_X
||
3583 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3584 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3585 /* Fast copy blit on skl+ supports all tiling formats. */
3586 devinfo
->gen
>= 9) &&
3587 can_blit_slice(mt
, level
, slice
))
3590 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3591 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3592 assert(can_blit_slice(mt
, level
, slice
));
3600 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3601 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3602 * arithmetic overflow.
3604 * If you call this function and use \a out_stride, then you're doing pointer
3605 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3606 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3607 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3608 * which usually have type uint32_t or GLuint.
3611 intel_miptree_map(struct brw_context
*brw
,
3612 struct intel_mipmap_tree
*mt
,
3621 ptrdiff_t *out_stride
)
3623 struct intel_miptree_map
*map
;
3625 assert(mt
->surf
.samples
== 1);
3627 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3634 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3635 map
->mode
& GL_MAP_WRITE_BIT
);
3637 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3638 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3639 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3640 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3641 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3642 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3643 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3644 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3645 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3646 #if defined(USE_SSE41)
3647 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3648 !mt
->compressed
&& cpu_has_sse4_1
&&
3649 (mt
->surf
.row_pitch
% 16 == 0)) {
3650 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3653 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3656 *out_ptr
= map
->ptr
;
3657 *out_stride
= map
->stride
;
3659 if (map
->ptr
== NULL
)
3660 intel_miptree_release_map(mt
, level
, slice
);
3664 intel_miptree_unmap(struct brw_context
*brw
,
3665 struct intel_mipmap_tree
*mt
,
3669 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3671 assert(mt
->surf
.samples
== 1);
3676 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3677 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3679 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3680 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3681 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3682 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3683 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3684 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3685 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3686 } else if (map
->linear_mt
) {
3687 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3688 #if defined(USE_SSE41)
3689 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3690 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3693 intel_miptree_unmap_gtt(mt
);
3696 intel_miptree_release_map(mt
, level
, slice
);
3700 get_isl_surf_dim(GLenum target
)
3704 case GL_TEXTURE_1D_ARRAY
:
3705 return ISL_SURF_DIM_1D
;
3708 case GL_TEXTURE_2D_ARRAY
:
3709 case GL_TEXTURE_RECTANGLE
:
3710 case GL_TEXTURE_CUBE_MAP
:
3711 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3712 case GL_TEXTURE_2D_MULTISAMPLE
:
3713 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3714 case GL_TEXTURE_EXTERNAL_OES
:
3715 return ISL_SURF_DIM_2D
;
3718 return ISL_SURF_DIM_3D
;
3721 unreachable("Invalid texture target");
3725 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3726 enum isl_tiling tiling
, GLenum target
)
3730 case GL_TEXTURE_1D_ARRAY
:
3731 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3732 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3735 case GL_TEXTURE_2D_ARRAY
:
3736 case GL_TEXTURE_RECTANGLE
:
3737 case GL_TEXTURE_2D_MULTISAMPLE
:
3738 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3739 case GL_TEXTURE_EXTERNAL_OES
:
3740 return ISL_DIM_LAYOUT_GEN4_2D
;
3742 case GL_TEXTURE_CUBE_MAP
:
3743 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3744 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3745 ISL_DIM_LAYOUT_GEN4_2D
);
3748 return (devinfo
->gen
>= 9 ?
3749 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3752 unreachable("Invalid texture target");
3756 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3757 const struct intel_mipmap_tree
*mt
)
3760 return ISL_AUX_USAGE_HIZ
;
3763 return ISL_AUX_USAGE_NONE
;
3765 return mt
->aux_usage
;