1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 intel_miptree_alloc_mcs(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
58 * Determine which MSAA layout should be used by the MSAA surface being
59 * created, based on the chip generation and the surface type.
61 static enum intel_msaa_layout
62 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
,
63 bool disable_aux_buffers
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
67 return INTEL_MSAA_LAYOUT_IMS
;
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
74 return INTEL_MSAA_LAYOUT_IMS
;
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
88 return INTEL_MSAA_LAYOUT_UMS
;
89 } else if (disable_aux_buffers
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->tiling
) {
149 unreachable("Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
163 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
170 * - Support is for non-mip-mapped and non-array surface types only.
172 * And then later, on p327:
174 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
178 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
179 struct intel_mipmap_tree
*mt
)
181 /* MCS support does not exist prior to Gen7 */
185 if (mt
->disable_aux_buffers
)
188 /* MCS is only supported for color buffers */
189 switch (_mesa_get_format_base_format(mt
->format
)) {
190 case GL_DEPTH_COMPONENT
:
191 case GL_DEPTH_STENCIL
:
192 case GL_STENCIL_INDEX
:
196 if (mt
->tiling
!= I915_TILING_X
&&
197 mt
->tiling
!= I915_TILING_Y
)
199 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
201 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
203 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
204 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
209 if (mt
->physical_depth0
!= 1) {
211 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
212 mt
->logical_width0
, mt
->logical_height0
,
213 mt
->physical_depth0
);
219 /* There's no point in using an MCS buffer if the surface isn't in a
222 if (!brw
->format_supported_as_render_target
[mt
->format
])
230 * Determine depth format corresponding to a depth+stencil format,
231 * for separate stencil.
234 intel_depth_format_for_depthstencil_format(mesa_format format
) {
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
238 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
239 return MESA_FORMAT_Z_FLOAT32
;
247 * @param for_bo Indicates that the caller is
248 * intel_miptree_create_for_bo(). If true, then do not create
251 static struct intel_mipmap_tree
*
252 intel_miptree_create_layout(struct brw_context
*brw
,
262 enum intel_miptree_tiling_mode requested
,
263 bool force_all_slices_at_each_lod
,
264 bool disable_aux_buffers
)
266 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
270 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
271 _mesa_lookup_enum_by_nr(target
),
272 _mesa_get_format_name(format
),
273 first_level
, last_level
, depth0
, mt
);
275 if (target
== GL_TEXTURE_1D_ARRAY
) {
276 /* For a 1D Array texture the OpenGL API will treat the height0
277 * parameter as the number of array slices. For Intel hardware, we treat
278 * the 1D array as a 2D Array with a height of 1.
280 * So, when we first come through this path to create a 1D Array
281 * texture, height0 stores the number of slices, and depth0 is 1. In
282 * this case, we want to swap height0 and depth0.
284 * Since some miptrees will be created based on the base miptree, we may
285 * come through this path and see height0 as 1 and depth0 being the
286 * number of slices. In this case we don't need to do the swap.
288 assert(height0
== 1 || depth0
== 1);
297 mt
->first_level
= first_level
;
298 mt
->last_level
= last_level
;
299 mt
->logical_width0
= width0
;
300 mt
->logical_height0
= height0
;
301 mt
->logical_depth0
= depth0
;
302 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
303 mt
->disable_aux_buffers
= disable_aux_buffers
;
304 exec_list_make_empty(&mt
->hiz_map
);
306 /* The cpp is bytes per (1, blockheight)-sized block for compressed
307 * textures. This is why you'll see divides by blockheight all over
310 _mesa_get_format_block_size(format
, &bw
, &bh
);
311 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
312 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
314 mt
->num_samples
= num_samples
;
315 mt
->compressed
= _mesa_is_format_compressed(format
);
316 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
319 if (num_samples
> 1) {
320 /* Adjust width/height/depth for MSAA */
321 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
322 mt
->target
, mt
->disable_aux_buffers
);
323 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
324 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
325 * "If the surface is multisampled and it is a depth or stencil
326 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
327 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
330 * +----------------------------------------------------------------+
331 * | Num Multisamples | W_l = | H_l = |
332 * +----------------------------------------------------------------+
333 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
334 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
335 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
336 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
337 * +----------------------------------------------------------------+
340 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
341 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
342 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
344 * Another more complicated explanation for these adjustments comes
345 * from the Sandybridge PRM, volume 4, part 1, page 31:
347 * "Any of the other messages (sample*, LOD, load4) used with a
348 * (4x) multisampled surface will in-effect sample a surface with
349 * double the height and width as that indicated in the surface
350 * state. Each pixel position on the original-sized surface is
351 * replaced with a 2x2 of samples with the following arrangement:
356 * Thus, when sampling from a multisampled texture, it behaves as
357 * though the layout in memory for (x,y,sample) is:
359 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
360 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
362 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
363 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
365 * However, the actual layout of multisampled data in memory is:
367 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
368 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
370 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
371 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
373 * This pattern repeats for each 2x2 pixel block.
375 * As a result, when calculating the size of our 4-sample buffer for
376 * an odd width or height, we have to align before scaling up because
377 * sample 3 is in that bottom right 2x2 block.
379 switch (num_samples
) {
381 assert(brw
->gen
>= 8);
382 width0
= ALIGN(width0
, 2) * 2;
383 height0
= ALIGN(height0
, 2);
386 width0
= ALIGN(width0
, 2) * 2;
387 height0
= ALIGN(height0
, 2) * 2;
390 width0
= ALIGN(width0
, 2) * 4;
391 height0
= ALIGN(height0
, 2) * 2;
394 /* num_samples should already have been quantized to 0, 1, 2, 4, or
397 unreachable("not reached");
400 /* Non-interleaved */
401 depth0
*= num_samples
;
405 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
406 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
407 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
408 * used on Gen8 to make it pick a qpitch value which doesn't include space
409 * for the mipmaps. On Gen9 this is not necessary because it will
410 * automatically pick a packed qpitch value whenever mt->first_level ==
412 * TODO: can we use it elsewhere?
413 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
416 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
418 switch (mt
->msaa_layout
) {
419 case INTEL_MSAA_LAYOUT_NONE
:
420 case INTEL_MSAA_LAYOUT_IMS
:
421 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
423 case INTEL_MSAA_LAYOUT_UMS
:
424 case INTEL_MSAA_LAYOUT_CMS
:
425 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
430 if (target
== GL_TEXTURE_CUBE_MAP
) {
435 mt
->physical_width0
= width0
;
436 mt
->physical_height0
= height0
;
437 mt
->physical_depth0
= depth0
;
440 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
441 (brw
->must_use_separate_stencil
||
442 (brw
->has_separate_stencil
&&
443 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
444 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
445 mt
->stencil_mt
= intel_miptree_create(brw
,
455 INTEL_MIPTREE_TILING_ANY
,
456 force_all_slices_at_each_lod
);
457 if (!mt
->stencil_mt
) {
458 intel_miptree_release(&mt
);
462 /* Fix up the Z miptree format for how we're splitting out separate
463 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
465 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
468 if (format
== mt
->format
) {
469 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
470 _mesa_get_format_name(mt
->format
));
474 if (force_all_slices_at_each_lod
)
475 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
477 brw_miptree_layout(brw
, for_bo
, requested
, mt
);
479 if (mt
->disable_aux_buffers
)
480 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
487 * Choose an appropriate uncompressed format for a requested
488 * compressed format, if unsupported.
491 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
493 /* No need to lower ETC formats on these platforms,
494 * they are supported natively.
496 if (brw
->gen
>= 8 || brw
->is_baytrail
)
500 case MESA_FORMAT_ETC1_RGB8
:
501 return MESA_FORMAT_R8G8B8X8_UNORM
;
502 case MESA_FORMAT_ETC2_RGB8
:
503 return MESA_FORMAT_R8G8B8X8_UNORM
;
504 case MESA_FORMAT_ETC2_SRGB8
:
505 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
506 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
507 return MESA_FORMAT_B8G8R8A8_SRGB
;
508 case MESA_FORMAT_ETC2_RGBA8_EAC
:
509 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
510 return MESA_FORMAT_R8G8B8A8_UNORM
;
511 case MESA_FORMAT_ETC2_R11_EAC
:
512 return MESA_FORMAT_R_UNORM16
;
513 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
514 return MESA_FORMAT_R_SNORM16
;
515 case MESA_FORMAT_ETC2_RG11_EAC
:
516 return MESA_FORMAT_R16G16_UNORM
;
517 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
518 return MESA_FORMAT_R16G16_SNORM
;
520 /* Non ETC1 / ETC2 format */
526 struct intel_mipmap_tree
*
527 intel_miptree_create(struct brw_context
*brw
,
535 bool expect_accelerated_upload
,
537 enum intel_miptree_tiling_mode requested_tiling
,
538 bool force_all_slices_at_each_lod
)
540 struct intel_mipmap_tree
*mt
;
541 mesa_format tex_format
= format
;
542 mesa_format etc_format
= MESA_FORMAT_NONE
;
543 GLuint total_width
, total_height
;
545 format
= intel_lower_compressed_format(brw
, format
);
547 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
549 mt
= intel_miptree_create_layout(brw
, target
, format
,
550 first_level
, last_level
, width0
,
554 force_all_slices_at_each_lod
,
555 false /*disable_aux_buffers*/);
560 total_width
= mt
->total_width
;
561 total_height
= mt
->total_height
;
563 if (format
== MESA_FORMAT_S_UINT8
) {
564 /* Align to size of W tile, 64x64. */
565 total_width
= ALIGN(total_width
, 64);
566 total_height
= ALIGN(total_height
, 64);
571 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
573 mt
->tiling
= I915_TILING_Y
;
577 mt
->etc_format
= etc_format
;
578 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
579 total_width
, total_height
, mt
->cpp
,
581 (expect_accelerated_upload
?
582 BO_ALLOC_FOR_RENDER
: 0));
585 /* If the BO is too large to fit in the aperture, we need to use the
586 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
587 * handle Y-tiling, so we need to fall back to X.
589 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
590 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
591 mt
->total_width
, mt
->total_height
);
593 mt
->tiling
= I915_TILING_X
;
594 drm_intel_bo_unreference(mt
->bo
);
595 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
596 total_width
, total_height
, mt
->cpp
,
598 (expect_accelerated_upload
?
599 BO_ALLOC_FOR_RENDER
: 0));
606 intel_miptree_release(&mt
);
611 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
612 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
613 intel_miptree_release(&mt
);
618 /* If this miptree is capable of supporting fast color clears, set
619 * fast_clear_state appropriately to ensure that fast clears will occur.
620 * Allocation of the MCS miptree will be deferred until the first fast
621 * clear actually occurs.
623 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
624 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
629 struct intel_mipmap_tree
*
630 intel_miptree_create_for_bo(struct brw_context
*brw
,
638 bool disable_aux_buffers
)
640 struct intel_mipmap_tree
*mt
;
641 uint32_t tiling
, swizzle
;
644 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
646 /* Nothing will be able to use this miptree with the BO if the offset isn't
649 if (tiling
!= I915_TILING_NONE
)
650 assert(offset
% 4096 == 0);
652 /* miptrees can't handle negative pitch. If you need flipping of images,
653 * that's outside of the scope of the mt.
657 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
659 /* 'requested' parameter of intel_miptree_create_layout() is relevant
660 * only for non bo miptree. Tiling for bo is already computed above.
661 * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is
662 * just a place holder and will not make any change to the miptree
665 mt
= intel_miptree_create_layout(brw
, target
, format
,
667 width
, height
, depth
,
669 INTEL_MIPTREE_TILING_ANY
,
671 disable_aux_buffers
);
675 drm_intel_bo_reference(bo
);
685 * For a singlesample renderbuffer, this simply wraps the given BO with a
688 * For a multisample renderbuffer, this wraps the window system's
689 * (singlesample) BO with a singlesample miptree attached to the
690 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
691 * that will contain the actual rendering (which is lazily resolved to
692 * irb->singlesample_mt).
695 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
696 struct intel_renderbuffer
*irb
,
698 uint32_t width
, uint32_t height
,
701 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
702 struct intel_mipmap_tree
*multisample_mt
= NULL
;
703 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
704 mesa_format format
= rb
->Format
;
705 int num_samples
= rb
->NumSamples
;
707 /* Only the front and back buffers, which are color buffers, are allocated
708 * through the image loader.
710 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
711 _mesa_get_format_base_format(format
) == GL_RGBA
);
713 singlesample_mt
= intel_miptree_create_for_bo(intel
,
722 if (!singlesample_mt
)
725 /* If this miptree is capable of supporting fast color clears, set
726 * mcs_state appropriately to ensure that fast clears will occur.
727 * Allocation of the MCS miptree will be deferred until the first fast
728 * clear actually occurs.
730 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
731 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
733 if (num_samples
== 0) {
734 intel_miptree_release(&irb
->mt
);
735 irb
->mt
= singlesample_mt
;
737 assert(!irb
->singlesample_mt
);
739 intel_miptree_release(&irb
->singlesample_mt
);
740 irb
->singlesample_mt
= singlesample_mt
;
743 irb
->mt
->logical_width0
!= width
||
744 irb
->mt
->logical_height0
!= height
) {
745 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
753 irb
->need_downsample
= false;
754 intel_miptree_release(&irb
->mt
);
755 irb
->mt
= multisample_mt
;
761 intel_miptree_release(&irb
->singlesample_mt
);
762 intel_miptree_release(&irb
->mt
);
766 struct intel_mipmap_tree
*
767 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
771 uint32_t num_samples
)
773 struct intel_mipmap_tree
*mt
;
776 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
778 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
779 width
, height
, depth
, true, num_samples
,
780 INTEL_MIPTREE_TILING_ANY
, false);
784 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
785 ok
= intel_miptree_alloc_hiz(brw
, mt
);
793 intel_miptree_release(&mt
);
798 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
799 struct intel_mipmap_tree
*src
)
804 intel_miptree_release(dst
);
808 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
816 intel_miptree_release(struct intel_mipmap_tree
**mt
)
821 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
822 if (--(*mt
)->refcount
<= 0) {
825 DBG("%s deleting %p\n", __func__
, *mt
);
827 drm_intel_bo_unreference((*mt
)->bo
);
828 intel_miptree_release(&(*mt
)->stencil_mt
);
829 if ((*mt
)->hiz_buf
) {
830 if ((*mt
)->hiz_buf
->mt
)
831 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
833 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
834 free((*mt
)->hiz_buf
);
836 intel_miptree_release(&(*mt
)->mcs_mt
);
837 intel_resolve_map_clear(&(*mt
)->hiz_map
);
839 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
840 free((*mt
)->level
[i
].slice
);
849 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
850 int *width
, int *height
, int *depth
)
852 switch (image
->TexObject
->Target
) {
853 case GL_TEXTURE_1D_ARRAY
:
854 *width
= image
->Width
;
856 *depth
= image
->Height
;
859 *width
= image
->Width
;
860 *height
= image
->Height
;
861 *depth
= image
->Depth
;
867 * Can the image be pulled into a unified mipmap tree? This mirrors
868 * the completeness test in a lot of ways.
870 * Not sure whether I want to pass gl_texture_image here.
873 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
874 struct gl_texture_image
*image
)
876 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
877 GLuint level
= intelImage
->base
.Base
.Level
;
878 int width
, height
, depth
;
880 /* glTexImage* choose the texture object based on the target passed in, and
881 * objects can't change targets over their lifetimes, so this should be
884 assert(image
->TexObject
->Target
== mt
->target
);
886 mesa_format mt_format
= mt
->format
;
887 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
888 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
889 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
890 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
891 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
892 mt_format
= mt
->etc_format
;
894 if (image
->TexFormat
!= mt_format
)
897 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
899 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
902 int level_depth
= mt
->level
[level
].depth
;
903 if (mt
->num_samples
> 1) {
904 switch (mt
->msaa_layout
) {
905 case INTEL_MSAA_LAYOUT_NONE
:
906 case INTEL_MSAA_LAYOUT_IMS
:
908 case INTEL_MSAA_LAYOUT_UMS
:
909 case INTEL_MSAA_LAYOUT_CMS
:
910 level_depth
/= mt
->num_samples
;
915 /* Test image dimensions against the base level image adjusted for
916 * minification. This will also catch images not present in the
917 * tree, changed targets, etc.
919 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
920 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
921 depth
!= level_depth
) {
925 if (image
->NumSamples
!= mt
->num_samples
)
933 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
935 GLuint x
, GLuint y
, GLuint d
)
937 mt
->level
[level
].depth
= d
;
938 mt
->level
[level
].level_x
= x
;
939 mt
->level
[level
].level_y
= y
;
941 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
944 assert(mt
->level
[level
].slice
== NULL
);
946 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
947 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
948 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
953 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
954 GLuint level
, GLuint img
,
957 if (img
== 0 && level
== 0)
958 assert(x
== 0 && y
== 0);
960 assert(img
< mt
->level
[level
].depth
);
962 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
963 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
965 DBG("%s level %d img %d pos %d,%d\n",
966 __func__
, level
, img
,
967 mt
->level
[level
].slice
[img
].x_offset
,
968 mt
->level
[level
].slice
[img
].y_offset
);
972 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
973 GLuint level
, GLuint slice
,
974 GLuint
*x
, GLuint
*y
)
976 assert(slice
< mt
->level
[level
].depth
);
978 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
979 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
983 * This function computes masks that may be used to select the bits of the X
984 * and Y coordinates that indicate the offset within a tile. If the BO is
985 * untiled, the masks are set to 0.
988 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
989 uint32_t *mask_x
, uint32_t *mask_y
,
990 bool map_stencil_as_y_tiled
)
993 uint32_t tiling
= mt
->tiling
;
995 if (map_stencil_as_y_tiled
)
996 tiling
= I915_TILING_Y
;
1000 unreachable("not reached");
1001 case I915_TILING_NONE
:
1002 *mask_x
= *mask_y
= 0;
1005 *mask_x
= 512 / cpp
- 1;
1009 *mask_x
= 128 / cpp
- 1;
1016 * Compute the offset (in bytes) from the start of the BO to the given x
1017 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1018 * multiples of the tile size.
1021 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1022 uint32_t x
, uint32_t y
,
1023 bool map_stencil_as_y_tiled
)
1026 uint32_t pitch
= mt
->pitch
;
1027 uint32_t tiling
= mt
->tiling
;
1029 if (map_stencil_as_y_tiled
) {
1030 tiling
= I915_TILING_Y
;
1032 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1033 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1034 * the resulting surface is twice the pitch of the original miptree,
1035 * since each row in the Y-tiled view corresponds to two rows in the
1036 * actual W-tiled surface. So we need to correct the pitch before
1037 * computing the offsets.
1044 unreachable("not reached");
1045 case I915_TILING_NONE
:
1046 return y
* pitch
+ x
* cpp
;
1048 assert((x
% (512 / cpp
)) == 0);
1049 assert((y
% 8) == 0);
1050 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1052 assert((x
% (128 / cpp
)) == 0);
1053 assert((y
% 32) == 0);
1054 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1059 * Rendering with tiled buffers requires that the base address of the buffer
1060 * be aligned to a page boundary. For renderbuffers, and sometimes with
1061 * textures, we may want the surface to point at a texture image level that
1062 * isn't at a page boundary.
1064 * This function returns an appropriately-aligned base offset
1065 * according to the tiling restrictions, plus any required x/y offset
1069 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1070 GLuint level
, GLuint slice
,
1075 uint32_t mask_x
, mask_y
;
1077 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1078 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1080 *tile_x
= x
& mask_x
;
1081 *tile_y
= y
& mask_y
;
1083 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1087 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1088 struct intel_mipmap_tree
*dst_mt
,
1089 struct intel_mipmap_tree
*src_mt
,
1096 ptrdiff_t src_stride
, dst_stride
;
1097 int cpp
= dst_mt
->cpp
;
1099 intel_miptree_map(brw
, src_mt
,
1103 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1106 intel_miptree_map(brw
, dst_mt
,
1110 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1114 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1115 _mesa_get_format_name(src_mt
->format
),
1116 src_mt
, src
, src_stride
,
1117 _mesa_get_format_name(dst_mt
->format
),
1118 dst_mt
, dst
, dst_stride
,
1121 int row_size
= cpp
* width
;
1122 if (src_stride
== row_size
&&
1123 dst_stride
== row_size
) {
1124 memcpy(dst
, src
, row_size
* height
);
1126 for (int i
= 0; i
< height
; i
++) {
1127 memcpy(dst
, src
, row_size
);
1133 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1134 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1136 /* Don't forget to copy the stencil data over, too. We could have skipped
1137 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1138 * shuffling the two data sources in/out of temporary storage instead of
1139 * the direct mapping we get this way.
1141 if (dst_mt
->stencil_mt
) {
1142 assert(src_mt
->stencil_mt
);
1143 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1144 level
, slice
, width
, height
);
1149 intel_miptree_copy_slice(struct brw_context
*brw
,
1150 struct intel_mipmap_tree
*dst_mt
,
1151 struct intel_mipmap_tree
*src_mt
,
1157 mesa_format format
= src_mt
->format
;
1158 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1159 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1167 assert(depth
< src_mt
->level
[level
].depth
);
1168 assert(src_mt
->format
== dst_mt
->format
);
1170 if (dst_mt
->compressed
) {
1171 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1172 width
= ALIGN(width
, dst_mt
->align_w
);
1175 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1176 * below won't apply since we can't do the depth's Y tiling or the
1177 * stencil's W tiling in the blitter.
1179 if (src_mt
->stencil_mt
) {
1180 intel_miptree_copy_slice_sw(brw
,
1187 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1188 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1189 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1191 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1192 _mesa_get_format_name(src_mt
->format
),
1193 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1194 _mesa_get_format_name(dst_mt
->format
),
1195 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1198 if (!intel_miptree_blit(brw
,
1199 src_mt
, level
, slice
, 0, 0, false,
1200 dst_mt
, level
, slice
, 0, 0, false,
1201 width
, height
, GL_COPY
)) {
1202 perf_debug("miptree validate blit for %s failed\n",
1203 _mesa_get_format_name(format
));
1205 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1211 * Copies the image's current data to the given miptree, and associates that
1212 * miptree with the image.
1214 * If \c invalidate is true, then the actual image data does not need to be
1215 * copied, but the image still needs to be associated to the new miptree (this
1216 * is set to true if we're about to clear the image).
1219 intel_miptree_copy_teximage(struct brw_context
*brw
,
1220 struct intel_texture_image
*intelImage
,
1221 struct intel_mipmap_tree
*dst_mt
,
1224 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1225 struct intel_texture_object
*intel_obj
=
1226 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1227 int level
= intelImage
->base
.Base
.Level
;
1228 int face
= intelImage
->base
.Base
.Face
;
1231 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1232 depth
= intelImage
->base
.Base
.Height
;
1234 depth
= intelImage
->base
.Base
.Depth
;
1237 for (int slice
= 0; slice
< depth
; slice
++) {
1238 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1242 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1243 intel_obj
->needs_validate
= true;
1247 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1248 struct intel_mipmap_tree
*mt
,
1251 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1252 assert(mt
->mcs_mt
== NULL
);
1253 assert(!mt
->disable_aux_buffers
);
1255 /* Choose the correct format for the MCS buffer. All that really matters
1256 * is that we allocate the right buffer size, since we'll always be
1257 * accessing this miptree using MCS-specific hardware mechanisms, which
1258 * infer the correct format based on num_samples.
1261 switch (num_samples
) {
1264 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1267 format
= MESA_FORMAT_R_UNORM8
;
1270 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1271 * for each sample, plus 8 padding bits).
1273 format
= MESA_FORMAT_R_UINT32
;
1276 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1279 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1281 * "The MCS surface must be stored as Tile Y."
1283 mt
->mcs_mt
= intel_miptree_create(brw
,
1289 mt
->logical_height0
,
1292 0 /* num_samples */,
1293 INTEL_MIPTREE_TILING_Y
,
1296 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1298 * When MCS buffer is enabled and bound to MSRT, it is required that it
1299 * is cleared prior to any rendering.
1301 * Since we don't use the MCS buffer for any purpose other than rendering,
1302 * it makes sense to just clear it immediately upon allocation.
1304 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1306 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1307 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1308 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1309 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1316 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1317 struct intel_mipmap_tree
*mt
)
1319 assert(mt
->mcs_mt
== NULL
);
1320 assert(!mt
->disable_aux_buffers
);
1322 /* The format of the MCS buffer is opaque to the driver; all that matters
1323 * is that we get its size and pitch right. We'll pretend that the format
1324 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1325 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1326 * the block width and then a further factor of 4. Since an MCS tile
1327 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1328 * we'll need to scale the height down by the block height and then a
1329 * further factor of 8.
1331 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1332 unsigned block_width_px
;
1333 unsigned block_height
;
1334 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1335 unsigned width_divisor
= block_width_px
* 4;
1336 unsigned height_divisor
= block_height
* 8;
1337 unsigned mcs_width
=
1338 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1339 unsigned mcs_height
=
1340 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1341 assert(mt
->logical_depth0
== 1);
1342 mt
->mcs_mt
= intel_miptree_create(brw
,
1351 0 /* num_samples */,
1352 INTEL_MIPTREE_TILING_Y
,
1360 * Helper for intel_miptree_alloc_hiz() that sets
1361 * \c mt->level[level].has_hiz. Return true if and only if
1362 * \c has_hiz was set.
1365 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1366 struct intel_mipmap_tree
*mt
,
1369 assert(mt
->hiz_buf
);
1371 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1372 uint32_t width
= minify(mt
->physical_width0
, level
);
1373 uint32_t height
= minify(mt
->physical_height0
, level
);
1375 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1376 * and the height is 4 aligned. This allows our HiZ support
1377 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1378 * we can grow the width & height to allow the HiZ op to
1379 * force the proper size alignments.
1381 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1382 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1387 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1388 mt
->level
[level
].has_hiz
= true;
1394 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1395 * buffer dimensions and allocates a bo for the hiz buffer.
1397 static struct intel_miptree_aux_buffer
*
1398 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1399 struct intel_mipmap_tree
*mt
)
1401 unsigned z_width
= mt
->logical_width0
;
1402 unsigned z_height
= mt
->logical_height0
;
1403 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1404 unsigned hz_width
, hz_height
;
1405 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1410 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1411 * adjustments required for Z_Height and Z_Width based on multisampling.
1413 switch (mt
->num_samples
) {
1427 unreachable("unsupported sample count");
1430 const unsigned vertical_align
= 8; /* 'j' in the docs */
1431 const unsigned H0
= z_height
;
1432 const unsigned h0
= ALIGN(H0
, vertical_align
);
1433 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1434 const unsigned Z0
= z_depth
;
1436 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1437 hz_width
= ALIGN(z_width
, 16);
1439 if (mt
->target
== GL_TEXTURE_3D
) {
1443 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1444 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1445 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1446 hz_height
+= h_i
* Z_i
;
1447 H_i
= minify(H_i
, 1);
1448 Z_i
= minify(Z_i
, 1);
1451 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1453 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1455 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1456 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1457 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1458 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1459 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1461 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1462 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1466 unsigned long pitch
;
1467 uint32_t tiling
= I915_TILING_Y
;
1468 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1469 hz_width
, hz_height
, 1,
1471 BO_ALLOC_FOR_RENDER
);
1475 } else if (tiling
!= I915_TILING_Y
) {
1476 drm_intel_bo_unreference(buf
->bo
);
1488 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1489 * buffer dimensions and allocates a bo for the hiz buffer.
1491 static struct intel_miptree_aux_buffer
*
1492 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1493 struct intel_mipmap_tree
*mt
)
1495 unsigned z_width
= mt
->logical_width0
;
1496 unsigned z_height
= mt
->logical_height0
;
1497 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1498 unsigned hz_width
, hz_height
;
1499 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1504 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1505 * adjustments required for Z_Height and Z_Width based on multisampling.
1507 switch (mt
->num_samples
) {
1521 unreachable("unsupported sample count");
1524 const unsigned vertical_align
= 8; /* 'j' in the docs */
1525 const unsigned H0
= z_height
;
1526 const unsigned h0
= ALIGN(H0
, vertical_align
);
1527 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1528 const unsigned Z0
= z_depth
;
1530 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1531 hz_width
= ALIGN(z_width
, 16);
1535 unsigned sum_h_i
= 0;
1536 unsigned hz_height_3d_sum
= 0;
1537 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1538 unsigned i
= level
- mt
->first_level
;
1539 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1540 /* sum(i=2 to m; h_i) */
1544 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1545 hz_height_3d_sum
+= h_i
* Z_i
;
1546 H_i
= minify(H_i
, 1);
1547 Z_i
= minify(Z_i
, 1);
1549 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1550 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1552 if (mt
->target
== GL_TEXTURE_3D
) {
1553 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1554 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1556 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1557 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1558 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1559 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1560 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1562 * We can can just take our hz_height calculation from above, and
1563 * multiply by 6 for the cube map and cube map array types.
1569 unsigned long pitch
;
1570 uint32_t tiling
= I915_TILING_Y
;
1571 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1572 hz_width
, hz_height
, 1,
1574 BO_ALLOC_FOR_RENDER
);
1578 } else if (tiling
!= I915_TILING_Y
) {
1579 drm_intel_bo_unreference(buf
->bo
);
1590 static struct intel_miptree_aux_buffer
*
1591 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1592 struct intel_mipmap_tree
*mt
)
1594 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1595 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1600 buf
->mt
= intel_miptree_create(brw
,
1606 mt
->logical_height0
,
1610 INTEL_MIPTREE_TILING_ANY
,
1611 force_all_slices_at_each_lod
);
1617 buf
->bo
= buf
->mt
->bo
;
1618 buf
->pitch
= buf
->mt
->pitch
;
1619 buf
->qpitch
= buf
->mt
->qpitch
;
1625 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1626 struct intel_mipmap_tree
*mt
)
1631 if (mt
->hiz_buf
!= NULL
)
1634 if (mt
->disable_aux_buffers
)
1637 switch (mt
->format
) {
1638 case MESA_FORMAT_Z_FLOAT32
:
1639 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1640 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1641 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1642 case MESA_FORMAT_Z_UNORM16
:
1650 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1651 struct intel_mipmap_tree
*mt
)
1653 assert(mt
->hiz_buf
== NULL
);
1654 assert(!mt
->disable_aux_buffers
);
1656 if (brw
->gen
== 7) {
1657 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1658 } else if (brw
->gen
>= 8) {
1659 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1661 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1667 /* Mark that all slices need a HiZ resolve. */
1668 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1669 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1672 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1673 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1674 exec_node_init(&m
->link
);
1677 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1679 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1687 * Does the miptree slice have hiz enabled?
1690 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1692 intel_miptree_check_level_layer(mt
, level
, 0);
1693 return mt
->level
[level
].has_hiz
;
1697 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1701 if (!intel_miptree_level_has_hiz(mt
, level
))
1704 intel_resolve_map_set(&mt
->hiz_map
,
1705 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1710 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1714 if (!intel_miptree_level_has_hiz(mt
, level
))
1717 intel_resolve_map_set(&mt
->hiz_map
,
1718 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1722 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1726 uint32_t end_layer
= mt
->level
[level
].depth
;
1728 for (layer
= 0; layer
< end_layer
; layer
++) {
1729 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1734 intel_miptree_slice_resolve(struct brw_context
*brw
,
1735 struct intel_mipmap_tree
*mt
,
1738 enum gen6_hiz_op need
)
1740 intel_miptree_check_level_layer(mt
, level
, layer
);
1742 struct intel_resolve_map
*item
=
1743 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1745 if (!item
|| item
->need
!= need
)
1748 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1749 intel_resolve_map_remove(item
);
1754 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1755 struct intel_mipmap_tree
*mt
,
1759 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1760 GEN6_HIZ_OP_HIZ_RESOLVE
);
1764 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1765 struct intel_mipmap_tree
*mt
,
1769 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1770 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1774 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1775 struct intel_mipmap_tree
*mt
,
1776 enum gen6_hiz_op need
)
1778 bool did_resolve
= false;
1780 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1781 if (map
->need
!= need
)
1784 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1785 intel_resolve_map_remove(map
);
1793 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1794 struct intel_mipmap_tree
*mt
)
1796 return intel_miptree_all_slices_resolve(brw
, mt
,
1797 GEN6_HIZ_OP_HIZ_RESOLVE
);
1801 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1802 struct intel_mipmap_tree
*mt
)
1804 return intel_miptree_all_slices_resolve(brw
, mt
,
1805 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1810 intel_miptree_resolve_color(struct brw_context
*brw
,
1811 struct intel_mipmap_tree
*mt
)
1813 switch (mt
->fast_clear_state
) {
1814 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1815 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1816 /* No resolve needed */
1818 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1819 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1820 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1821 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1822 brw_meta_resolve_color(brw
, mt
);
1829 * Make it possible to share the BO backing the given miptree with another
1830 * process or another miptree.
1832 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1833 * then discard the MCS buffer, if present. We also set the fast_clear_state
1834 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1835 * allocated in the future.
1838 intel_miptree_make_shareable(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*mt
)
1841 /* MCS buffers are also used for multisample buffers, but we can't resolve
1842 * away a multisample MCS buffer because it's an integral part of how the
1843 * pixel data is stored. Fortunately this code path should never be
1844 * reached for multisample buffers.
1846 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1849 intel_miptree_resolve_color(brw
, mt
);
1850 intel_miptree_release(&mt
->mcs_mt
);
1851 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1857 * \brief Get pointer offset into stencil buffer.
1859 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1860 * must decode the tile's layout in software.
1863 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1865 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1867 * Even though the returned offset is always positive, the return type is
1869 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1870 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1873 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1875 uint32_t tile_size
= 4096;
1876 uint32_t tile_width
= 64;
1877 uint32_t tile_height
= 64;
1878 uint32_t row_size
= 64 * stride
;
1880 uint32_t tile_x
= x
/ tile_width
;
1881 uint32_t tile_y
= y
/ tile_height
;
1883 /* The byte's address relative to the tile's base addres. */
1884 uint32_t byte_x
= x
% tile_width
;
1885 uint32_t byte_y
= y
% tile_height
;
1887 uintptr_t u
= tile_y
* row_size
1888 + tile_x
* tile_size
1889 + 512 * (byte_x
/ 8)
1891 + 32 * ((byte_y
/ 4) % 2)
1892 + 16 * ((byte_x
/ 4) % 2)
1893 + 8 * ((byte_y
/ 2) % 2)
1894 + 4 * ((byte_x
/ 2) % 2)
1899 /* adjust for bit6 swizzling */
1900 if (((byte_x
/ 8) % 2) == 1) {
1901 if (((byte_y
/ 8) % 2) == 0) {
1913 intel_miptree_updownsample(struct brw_context
*brw
,
1914 struct intel_mipmap_tree
*src
,
1915 struct intel_mipmap_tree
*dst
)
1918 brw_blorp_blit_miptrees(brw
,
1919 src
, 0 /* level */, 0 /* layer */, src
->format
,
1920 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
1922 src
->logical_width0
, src
->logical_height0
,
1924 dst
->logical_width0
, dst
->logical_height0
,
1925 GL_NEAREST
, false, false /*mirror x, y*/);
1926 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1927 brw_meta_stencil_updownsample(brw
, src
, dst
);
1929 brw_meta_updownsample(brw
, src
, dst
);
1932 if (src
->stencil_mt
) {
1933 if (brw
->gen
>= 8) {
1934 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1938 brw_blorp_blit_miptrees(brw
,
1939 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1940 src
->stencil_mt
->format
,
1941 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1942 dst
->stencil_mt
->format
,
1944 src
->logical_width0
, src
->logical_height0
,
1946 dst
->logical_width0
, dst
->logical_height0
,
1947 GL_NEAREST
, false, false /*mirror x, y*/);
1952 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1954 /* CPU accesses to color buffers don't understand fast color clears, so
1955 * resolve any pending fast color clears before we map.
1957 intel_miptree_resolve_color(brw
, mt
);
1959 drm_intel_bo
*bo
= mt
->bo
;
1961 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1962 intel_batchbuffer_flush(brw
);
1964 if (mt
->tiling
!= I915_TILING_NONE
)
1965 brw_bo_map_gtt(brw
, bo
, "miptree");
1967 brw_bo_map(brw
, bo
, true, "miptree");
1973 intel_miptree_unmap_raw(struct brw_context
*brw
,
1974 struct intel_mipmap_tree
*mt
)
1976 drm_intel_bo_unmap(mt
->bo
);
1980 intel_miptree_map_gtt(struct brw_context
*brw
,
1981 struct intel_mipmap_tree
*mt
,
1982 struct intel_miptree_map
*map
,
1983 unsigned int level
, unsigned int slice
)
1985 unsigned int bw
, bh
;
1987 unsigned int image_x
, image_y
;
1988 intptr_t x
= map
->x
;
1989 intptr_t y
= map
->y
;
1991 /* For compressed formats, the stride is the number of bytes per
1992 * row of blocks. intel_miptree_get_image_offset() already does
1995 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1996 assert(y
% bh
== 0);
1999 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2004 /* Note that in the case of cube maps, the caller must have passed the
2005 * slice number referencing the face.
2007 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2011 map
->stride
= mt
->pitch
;
2012 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2015 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2016 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2017 map
->x
, map
->y
, map
->w
, map
->h
,
2018 mt
, _mesa_get_format_name(mt
->format
),
2019 x
, y
, map
->ptr
, map
->stride
);
2023 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2024 struct intel_mipmap_tree
*mt
,
2025 struct intel_miptree_map
*map
,
2029 intel_miptree_unmap_raw(brw
, mt
);
2033 intel_miptree_map_blit(struct brw_context
*brw
,
2034 struct intel_mipmap_tree
*mt
,
2035 struct intel_miptree_map
*map
,
2036 unsigned int level
, unsigned int slice
)
2038 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2042 INTEL_MIPTREE_TILING_NONE
,
2045 fprintf(stderr
, "Failed to allocate blit temporary\n");
2048 map
->stride
= map
->mt
->pitch
;
2050 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2051 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2052 * invalidate is set, since we'll be writing the whole rectangle from our
2053 * temporary buffer back out.
2055 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2056 if (!intel_miptree_blit(brw
,
2058 map
->x
, map
->y
, false,
2061 map
->w
, map
->h
, GL_COPY
)) {
2062 fprintf(stderr
, "Failed to blit\n");
2067 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2069 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2070 map
->x
, map
->y
, map
->w
, map
->h
,
2071 mt
, _mesa_get_format_name(mt
->format
),
2072 level
, slice
, map
->ptr
, map
->stride
);
2077 intel_miptree_release(&map
->mt
);
2083 intel_miptree_unmap_blit(struct brw_context
*brw
,
2084 struct intel_mipmap_tree
*mt
,
2085 struct intel_miptree_map
*map
,
2089 struct gl_context
*ctx
= &brw
->ctx
;
2091 intel_miptree_unmap_raw(brw
, map
->mt
);
2093 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2094 bool ok
= intel_miptree_blit(brw
,
2098 map
->x
, map
->y
, false,
2099 map
->w
, map
->h
, GL_COPY
);
2100 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2103 intel_miptree_release(&map
->mt
);
2107 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2109 #if defined(USE_SSE41)
2111 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2112 struct intel_mipmap_tree
*mt
,
2113 struct intel_miptree_map
*map
,
2114 unsigned int level
, unsigned int slice
)
2116 assert(map
->mode
& GL_MAP_READ_BIT
);
2117 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2119 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2120 map
->x
, map
->y
, map
->w
, map
->h
,
2121 mt
, _mesa_get_format_name(mt
->format
),
2122 level
, slice
, map
->ptr
, map
->stride
);
2124 /* Map the original image */
2127 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2131 void *src
= intel_miptree_map_raw(brw
, mt
);
2134 src
+= image_y
* mt
->pitch
;
2135 src
+= image_x
* mt
->cpp
;
2137 /* Due to the pixel offsets for the particular image being mapped, our
2138 * src pointer may not be 16-byte aligned. However, if the pitch is
2139 * divisible by 16, then the amount by which it's misaligned will remain
2140 * consistent from row to row.
2142 assert((mt
->pitch
% 16) == 0);
2143 const int misalignment
= ((uintptr_t) src
) & 15;
2145 /* Create an untiled temporary buffer for the mapping. */
2146 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2148 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2150 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2151 /* Offset the destination so it has the same misalignment as src. */
2152 map
->ptr
= map
->buffer
+ misalignment
;
2154 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2156 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2157 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2158 void *src_ptr
= src
+ y
* mt
->pitch
;
2160 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2163 intel_miptree_unmap_raw(brw
, mt
);
2167 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2168 struct intel_mipmap_tree
*mt
,
2169 struct intel_miptree_map
*map
,
2173 _mesa_align_free(map
->buffer
);
2180 intel_miptree_map_s8(struct brw_context
*brw
,
2181 struct intel_mipmap_tree
*mt
,
2182 struct intel_miptree_map
*map
,
2183 unsigned int level
, unsigned int slice
)
2185 map
->stride
= map
->w
;
2186 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2190 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2191 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2192 * invalidate is set, since we'll be writing the whole rectangle from our
2193 * temporary buffer back out.
2195 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2196 uint8_t *untiled_s8_map
= map
->ptr
;
2197 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2198 unsigned int image_x
, image_y
;
2200 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2202 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2203 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2204 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2205 x
+ image_x
+ map
->x
,
2206 y
+ image_y
+ map
->y
,
2207 brw
->has_swizzling
);
2208 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2212 intel_miptree_unmap_raw(brw
, mt
);
2214 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2215 map
->x
, map
->y
, map
->w
, map
->h
,
2216 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2218 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2219 map
->x
, map
->y
, map
->w
, map
->h
,
2220 mt
, map
->ptr
, map
->stride
);
2225 intel_miptree_unmap_s8(struct brw_context
*brw
,
2226 struct intel_mipmap_tree
*mt
,
2227 struct intel_miptree_map
*map
,
2231 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2232 unsigned int image_x
, image_y
;
2233 uint8_t *untiled_s8_map
= map
->ptr
;
2234 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2236 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2238 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2239 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2240 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2243 brw
->has_swizzling
);
2244 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2248 intel_miptree_unmap_raw(brw
, mt
);
2255 intel_miptree_map_etc(struct brw_context
*brw
,
2256 struct intel_mipmap_tree
*mt
,
2257 struct intel_miptree_map
*map
,
2261 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2262 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2263 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2266 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2267 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2269 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2270 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2271 map
->w
, map
->h
, 1));
2272 map
->ptr
= map
->buffer
;
2276 intel_miptree_unmap_etc(struct brw_context
*brw
,
2277 struct intel_mipmap_tree
*mt
,
2278 struct intel_miptree_map
*map
,
2284 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2289 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2290 + image_y
* mt
->pitch
2291 + image_x
* mt
->cpp
;
2293 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2294 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2295 map
->ptr
, map
->stride
,
2298 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2299 map
->ptr
, map
->stride
,
2300 map
->w
, map
->h
, mt
->etc_format
);
2302 intel_miptree_unmap_raw(brw
, mt
);
2307 * Mapping function for packed depth/stencil miptrees backed by real separate
2308 * miptrees for depth and stencil.
2310 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2311 * separate from the depth buffer. Yet at the GL API level, we have to expose
2312 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2313 * be able to map that memory for texture storage and glReadPixels-type
2314 * operations. We give Mesa core that access by mallocing a temporary and
2315 * copying the data between the actual backing store and the temporary.
2318 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2319 struct intel_mipmap_tree
*mt
,
2320 struct intel_miptree_map
*map
,
2321 unsigned int level
, unsigned int slice
)
2323 struct intel_mipmap_tree
*z_mt
= mt
;
2324 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2325 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2326 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2328 map
->stride
= map
->w
* packed_bpp
;
2329 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2333 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2334 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2335 * invalidate is set, since we'll be writing the whole rectangle from our
2336 * temporary buffer back out.
2338 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2339 uint32_t *packed_map
= map
->ptr
;
2340 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2341 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2342 unsigned int s_image_x
, s_image_y
;
2343 unsigned int z_image_x
, z_image_y
;
2345 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2346 &s_image_x
, &s_image_y
);
2347 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2348 &z_image_x
, &z_image_y
);
2350 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2351 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2352 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2353 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2356 brw
->has_swizzling
);
2357 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2359 (map_x
+ z_image_x
));
2360 uint8_t s
= s_map
[s_offset
];
2361 uint32_t z
= z_map
[z_offset
];
2363 if (map_z32f_x24s8
) {
2364 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2365 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2367 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2372 intel_miptree_unmap_raw(brw
, s_mt
);
2373 intel_miptree_unmap_raw(brw
, z_mt
);
2375 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2377 map
->x
, map
->y
, map
->w
, map
->h
,
2378 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2379 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2380 map
->ptr
, map
->stride
);
2382 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2383 map
->x
, map
->y
, map
->w
, map
->h
,
2384 mt
, map
->ptr
, map
->stride
);
2389 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2390 struct intel_mipmap_tree
*mt
,
2391 struct intel_miptree_map
*map
,
2395 struct intel_mipmap_tree
*z_mt
= mt
;
2396 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2397 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2399 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2400 uint32_t *packed_map
= map
->ptr
;
2401 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2402 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2403 unsigned int s_image_x
, s_image_y
;
2404 unsigned int z_image_x
, z_image_y
;
2406 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2407 &s_image_x
, &s_image_y
);
2408 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2409 &z_image_x
, &z_image_y
);
2411 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2412 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2413 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2414 x
+ s_image_x
+ map
->x
,
2415 y
+ s_image_y
+ map
->y
,
2416 brw
->has_swizzling
);
2417 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2419 (x
+ z_image_x
+ map
->x
));
2421 if (map_z32f_x24s8
) {
2422 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2423 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2425 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2426 s_map
[s_offset
] = packed
>> 24;
2427 z_map
[z_offset
] = packed
;
2432 intel_miptree_unmap_raw(brw
, s_mt
);
2433 intel_miptree_unmap_raw(brw
, z_mt
);
2435 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2437 map
->x
, map
->y
, map
->w
, map
->h
,
2438 z_mt
, _mesa_get_format_name(z_mt
->format
),
2439 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2440 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2441 map
->ptr
, map
->stride
);
2448 * Create and attach a map to the miptree at (level, slice). Return the
2451 static struct intel_miptree_map
*
2452 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2461 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2466 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2467 mt
->level
[level
].slice
[slice
].map
= map
;
2479 * Release the map at (level, slice).
2482 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2486 struct intel_miptree_map
**map
;
2488 map
= &mt
->level
[level
].slice
[slice
].map
;
2494 can_blit_slice(struct intel_mipmap_tree
*mt
,
2495 unsigned int level
, unsigned int slice
)
2499 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2500 if (image_x
>= 32768 || image_y
>= 32768)
2503 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2504 if (mt
->pitch
>= 32768)
2511 use_intel_mipree_map_blit(struct brw_context
*brw
,
2512 struct intel_mipmap_tree
*mt
,
2518 /* It's probably not worth swapping to the blit ring because of
2519 * all the overhead involved.
2521 !(mode
& GL_MAP_WRITE_BIT
) &&
2523 (mt
->tiling
== I915_TILING_X
||
2524 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2525 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2526 can_blit_slice(mt
, level
, slice
))
2529 if (mt
->tiling
!= I915_TILING_NONE
&&
2530 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2531 assert(can_blit_slice(mt
, level
, slice
));
2539 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2540 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2541 * arithmetic overflow.
2543 * If you call this function and use \a out_stride, then you're doing pointer
2544 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2545 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2546 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2547 * which usually have type uint32_t or GLuint.
2550 intel_miptree_map(struct brw_context
*brw
,
2551 struct intel_mipmap_tree
*mt
,
2560 ptrdiff_t *out_stride
)
2562 struct intel_miptree_map
*map
;
2564 assert(mt
->num_samples
<= 1);
2566 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2573 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2574 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2575 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2578 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2579 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2580 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2581 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2582 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2583 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2584 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2585 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2586 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2587 #if defined(USE_SSE41)
2588 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2589 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2592 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2595 *out_ptr
= map
->ptr
;
2596 *out_stride
= map
->stride
;
2598 if (map
->ptr
== NULL
)
2599 intel_miptree_release_map(mt
, level
, slice
);
2603 intel_miptree_unmap(struct brw_context
*brw
,
2604 struct intel_mipmap_tree
*mt
,
2608 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2610 assert(mt
->num_samples
<= 1);
2615 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2616 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2618 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2619 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2620 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2621 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2622 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2623 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2624 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2625 } else if (map
->mt
) {
2626 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2627 #if defined(USE_SSE41)
2628 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2629 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2632 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2635 intel_miptree_release_map(mt
, level
, slice
);