2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return isl_format_supports_lossless_compression(brw
->intelScreen
->devinfo
,
271 /* On Gen9 support for color buffer compression was extended to single
272 * sampled surfaces. This is a helper considering both auxiliary buffer
273 * type and number of samples telling if the given miptree represents
274 * the new single sampled case - also called lossless compression.
277 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
278 const struct intel_mipmap_tree
*mt
)
280 /* Only available from Gen9 onwards. */
284 /* Compression always requires auxiliary buffer. */
288 /* Single sample compression is represented re-using msaa compression
289 * layout type: "Compressed Multisampled Surfaces".
291 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
294 /* And finally distinguish between msaa and single sample case. */
295 return mt
->num_samples
<= 1;
299 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
300 const struct intel_mipmap_tree
*mt
)
302 /* For now compression is only enabled for integer formats even though
303 * there exist supported floating point formats also. This is a heuristic
304 * decision based on current public benchmarks. In none of the cases these
305 * formats provided any improvement but a few cases were seen to regress.
306 * Hence these are left to to be enabled in the future when they are known
309 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
312 /* Fast clear mechanism and lossless compression go hand in hand. */
313 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
316 /* Fast clear can be also used to clear srgb surfaces by using equivalent
317 * linear format. This trick, however, can't be extended to be used with
318 * lossless compression and therefore a check is needed to see if the format
321 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
325 * Determine depth format corresponding to a depth+stencil format,
326 * for separate stencil.
329 intel_depth_format_for_depthstencil_format(mesa_format format
) {
331 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
332 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
333 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
334 return MESA_FORMAT_Z_FLOAT32
;
342 * @param for_bo Indicates that the caller is
343 * intel_miptree_create_for_bo(). If true, then do not create
346 static struct intel_mipmap_tree
*
347 intel_miptree_create_layout(struct brw_context
*brw
,
356 uint32_t layout_flags
)
358 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
362 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
363 _mesa_enum_to_string(target
),
364 _mesa_get_format_name(format
),
365 first_level
, last_level
, depth0
, mt
);
367 if (target
== GL_TEXTURE_1D_ARRAY
)
368 assert(height0
== 1);
372 mt
->first_level
= first_level
;
373 mt
->last_level
= last_level
;
374 mt
->logical_width0
= width0
;
375 mt
->logical_height0
= height0
;
376 mt
->logical_depth0
= depth0
;
377 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
378 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
379 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
380 exec_list_make_empty(&mt
->hiz_map
);
381 mt
->cpp
= _mesa_get_format_bytes(format
);
382 mt
->num_samples
= num_samples
;
383 mt
->compressed
= _mesa_is_format_compressed(format
);
384 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
387 if (num_samples
> 1) {
388 /* Adjust width/height/depth for MSAA */
389 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
390 mt
->disable_aux_buffers
);
391 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
392 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
393 * "If the surface is multisampled and it is a depth or stencil
394 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
395 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
398 * +----------------------------------------------------------------+
399 * | Num Multisamples | W_l = | H_l = |
400 * +----------------------------------------------------------------+
401 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
402 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
403 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
404 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
405 * +----------------------------------------------------------------+
408 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
409 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
410 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
412 * Another more complicated explanation for these adjustments comes
413 * from the Sandybridge PRM, volume 4, part 1, page 31:
415 * "Any of the other messages (sample*, LOD, load4) used with a
416 * (4x) multisampled surface will in-effect sample a surface with
417 * double the height and width as that indicated in the surface
418 * state. Each pixel position on the original-sized surface is
419 * replaced with a 2x2 of samples with the following arrangement:
424 * Thus, when sampling from a multisampled texture, it behaves as
425 * though the layout in memory for (x,y,sample) is:
427 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
428 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
430 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
431 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
433 * However, the actual layout of multisampled data in memory is:
435 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
436 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
438 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
439 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
441 * This pattern repeats for each 2x2 pixel block.
443 * As a result, when calculating the size of our 4-sample buffer for
444 * an odd width or height, we have to align before scaling up because
445 * sample 3 is in that bottom right 2x2 block.
447 switch (num_samples
) {
449 assert(brw
->gen
>= 8);
450 width0
= ALIGN(width0
, 2) * 2;
451 height0
= ALIGN(height0
, 2);
454 width0
= ALIGN(width0
, 2) * 2;
455 height0
= ALIGN(height0
, 2) * 2;
458 width0
= ALIGN(width0
, 2) * 4;
459 height0
= ALIGN(height0
, 2) * 2;
462 width0
= ALIGN(width0
, 2) * 4;
463 height0
= ALIGN(height0
, 2) * 4;
466 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
469 unreachable("not reached");
472 /* Non-interleaved */
473 depth0
*= num_samples
;
477 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
478 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
479 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
480 * used on Gen8 to make it pick a qpitch value which doesn't include space
481 * for the mipmaps. On Gen9 this is not necessary because it will
482 * automatically pick a packed qpitch value whenever mt->first_level ==
484 * TODO: can we use it elsewhere?
485 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
488 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
490 switch (mt
->msaa_layout
) {
491 case INTEL_MSAA_LAYOUT_NONE
:
492 case INTEL_MSAA_LAYOUT_IMS
:
493 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
495 case INTEL_MSAA_LAYOUT_UMS
:
496 case INTEL_MSAA_LAYOUT_CMS
:
497 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
502 if (target
== GL_TEXTURE_CUBE_MAP
)
505 mt
->physical_width0
= width0
;
506 mt
->physical_height0
= height0
;
507 mt
->physical_depth0
= depth0
;
509 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
510 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
511 (brw
->must_use_separate_stencil
||
512 (brw
->has_separate_stencil
&&
513 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
514 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
516 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
517 MIPTREE_LAYOUT_TILING_ANY
;
520 mt
->stencil_mt
= intel_miptree_create(brw
,
531 if (!mt
->stencil_mt
) {
532 intel_miptree_release(&mt
);
536 /* Fix up the Z miptree format for how we're splitting out separate
537 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
539 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
542 if (format
== mt
->format
) {
543 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
544 _mesa_get_format_name(mt
->format
));
548 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
549 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
552 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
553 * multisampled or have an AUX buffer attached to it.
555 * GEN | MSRT | AUX_CCS_* or AUX_MCS
556 * -------------------------------------------
557 * 9 | HALIGN_16 | HALIGN_16
558 * 8 | HALIGN_ANY | HALIGN_16
562 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
563 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
564 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
565 } else if (brw
->gen
>= 9 && num_samples
> 1) {
566 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
568 const UNUSED
bool is_lossless_compressed_aux
=
569 brw
->gen
>= 9 && num_samples
== 1 &&
570 mt
->format
== MESA_FORMAT_R_UINT32
;
572 /* For now, nothing else has this requirement */
573 assert(is_lossless_compressed_aux
||
574 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
577 brw_miptree_layout(brw
, mt
, layout_flags
);
579 if (mt
->disable_aux_buffers
)
580 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
587 * Choose an appropriate uncompressed format for a requested
588 * compressed format, if unsupported.
591 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
593 /* No need to lower ETC formats on these platforms,
594 * they are supported natively.
596 if (brw
->gen
>= 8 || brw
->is_baytrail
)
600 case MESA_FORMAT_ETC1_RGB8
:
601 return MESA_FORMAT_R8G8B8X8_UNORM
;
602 case MESA_FORMAT_ETC2_RGB8
:
603 return MESA_FORMAT_R8G8B8X8_UNORM
;
604 case MESA_FORMAT_ETC2_SRGB8
:
605 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
606 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
607 return MESA_FORMAT_B8G8R8A8_SRGB
;
608 case MESA_FORMAT_ETC2_RGBA8_EAC
:
609 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
610 return MESA_FORMAT_R8G8B8A8_UNORM
;
611 case MESA_FORMAT_ETC2_R11_EAC
:
612 return MESA_FORMAT_R_UNORM16
;
613 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
614 return MESA_FORMAT_R_SNORM16
;
615 case MESA_FORMAT_ETC2_RG11_EAC
:
616 return MESA_FORMAT_R16G16_UNORM
;
617 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
618 return MESA_FORMAT_R16G16_SNORM
;
620 /* Non ETC1 / ETC2 format */
625 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
627 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
628 unsigned long *pitch
)
630 uint32_t tile_width
, tile_height
;
631 unsigned long stride
, size
, aligned_y
;
633 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
634 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
635 &tile_width
, &tile_height
);
637 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
638 stride
= mt
->total_width
* mt
->cpp
;
639 stride
= ALIGN(stride
, tile_width
);
640 size
= stride
* aligned_y
;
642 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
643 assert(size
% 4096 == 0);
646 assert(size
% (64 * 1024) == 0);
647 *alignment
= 64 * 1024;
653 static struct intel_mipmap_tree
*
654 miptree_create(struct brw_context
*brw
,
663 uint32_t layout_flags
)
665 struct intel_mipmap_tree
*mt
;
666 mesa_format tex_format
= format
;
667 mesa_format etc_format
= MESA_FORMAT_NONE
;
668 uint32_t alloc_flags
= 0;
670 format
= intel_lower_compressed_format(brw
, format
);
672 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
674 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
675 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
676 mt
= intel_miptree_create_layout(brw
, target
, format
,
677 first_level
, last_level
, width0
,
678 height0
, depth0
, num_samples
,
681 * pitch == 0 || height == 0 indicates the null texture
683 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
684 intel_miptree_release(&mt
);
688 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
689 mt
->tiling
= I915_TILING_Y
;
691 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
692 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
695 mt
->etc_format
= etc_format
;
697 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
698 unsigned alignment
= 0;
700 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
702 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
705 if (format
== MESA_FORMAT_S_UINT8
) {
706 /* Align to size of W tile, 64x64. */
707 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
708 ALIGN(mt
->total_width
, 64),
709 ALIGN(mt
->total_height
, 64),
710 mt
->cpp
, &mt
->tiling
, &pitch
,
713 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
714 mt
->total_width
, mt
->total_height
,
715 mt
->cpp
, &mt
->tiling
, &pitch
,
725 struct intel_mipmap_tree
*
726 intel_miptree_create(struct brw_context
*brw
,
735 uint32_t layout_flags
)
737 struct intel_mipmap_tree
*mt
= miptree_create(
739 first_level
, last_level
,
740 width0
, height0
, depth0
, num_samples
,
743 /* If the BO is too large to fit in the aperture, we need to use the
744 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
745 * handle Y-tiling, so we need to fall back to X.
747 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
748 mt
->tiling
== I915_TILING_Y
) {
749 unsigned long pitch
= mt
->pitch
;
750 const uint32_t alloc_flags
=
751 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
752 BO_ALLOC_FOR_RENDER
: 0;
753 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
754 mt
->total_width
, mt
->total_height
);
756 mt
->tiling
= I915_TILING_X
;
757 drm_intel_bo_unreference(mt
->bo
);
758 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
759 mt
->total_width
, mt
->total_height
, mt
->cpp
,
760 &mt
->tiling
, &pitch
, alloc_flags
);
767 intel_miptree_release(&mt
);
772 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
773 assert(mt
->num_samples
> 1);
774 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
775 intel_miptree_release(&mt
);
780 /* If this miptree is capable of supporting fast color clears, set
781 * fast_clear_state appropriately to ensure that fast clears will occur.
782 * Allocation of the MCS miptree will be deferred until the first fast
783 * clear actually occurs or when compressed single sampled buffer is
784 * written by the GPU for the first time.
786 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
787 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
788 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
789 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
795 struct intel_mipmap_tree
*
796 intel_miptree_create_for_bo(struct brw_context
*brw
,
804 uint32_t layout_flags
)
806 struct intel_mipmap_tree
*mt
;
807 uint32_t tiling
, swizzle
;
810 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
812 /* Nothing will be able to use this miptree with the BO if the offset isn't
815 if (tiling
!= I915_TILING_NONE
)
816 assert(offset
% 4096 == 0);
818 /* miptrees can't handle negative pitch. If you need flipping of images,
819 * that's outside of the scope of the mt.
823 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
825 /* The BO already has a tiling format and we shouldn't confuse the lower
826 * layers by making it try to find a tiling format again.
828 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
829 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
831 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
832 mt
= intel_miptree_create_layout(brw
, target
, format
,
834 width
, height
, depth
, 0,
839 drm_intel_bo_reference(bo
);
849 * For a singlesample renderbuffer, this simply wraps the given BO with a
852 * For a multisample renderbuffer, this wraps the window system's
853 * (singlesample) BO with a singlesample miptree attached to the
854 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
855 * that will contain the actual rendering (which is lazily resolved to
856 * irb->singlesample_mt).
859 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
860 struct intel_renderbuffer
*irb
,
862 uint32_t width
, uint32_t height
,
865 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
866 struct intel_mipmap_tree
*multisample_mt
= NULL
;
867 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
868 mesa_format format
= rb
->Format
;
869 int num_samples
= rb
->NumSamples
;
871 /* Only the front and back buffers, which are color buffers, are allocated
872 * through the image loader.
874 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
875 _mesa_get_format_base_format(format
) == GL_RGBA
);
877 singlesample_mt
= intel_miptree_create_for_bo(intel
,
885 MIPTREE_LAYOUT_FOR_SCANOUT
);
886 if (!singlesample_mt
)
889 /* If this miptree is capable of supporting fast color clears, set
890 * mcs_state appropriately to ensure that fast clears will occur.
891 * Allocation of the MCS miptree will be deferred until the first fast
892 * clear actually occurs.
894 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
895 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
896 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
899 if (num_samples
== 0) {
900 intel_miptree_release(&irb
->mt
);
901 irb
->mt
= singlesample_mt
;
903 assert(!irb
->singlesample_mt
);
905 intel_miptree_release(&irb
->singlesample_mt
);
906 irb
->singlesample_mt
= singlesample_mt
;
909 irb
->mt
->logical_width0
!= width
||
910 irb
->mt
->logical_height0
!= height
) {
911 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
919 irb
->need_downsample
= false;
920 intel_miptree_release(&irb
->mt
);
921 irb
->mt
= multisample_mt
;
927 intel_miptree_release(&irb
->singlesample_mt
);
928 intel_miptree_release(&irb
->mt
);
932 struct intel_mipmap_tree
*
933 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
937 uint32_t num_samples
)
939 struct intel_mipmap_tree
*mt
;
942 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
943 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
944 MIPTREE_LAYOUT_TILING_ANY
|
945 MIPTREE_LAYOUT_FOR_SCANOUT
;
947 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
948 width
, height
, depth
, num_samples
,
953 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
954 ok
= intel_miptree_alloc_hiz(brw
, mt
);
962 intel_miptree_release(&mt
);
967 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
968 struct intel_mipmap_tree
*src
)
973 intel_miptree_release(dst
);
977 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
985 intel_miptree_release(struct intel_mipmap_tree
**mt
)
990 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
991 if (--(*mt
)->refcount
<= 0) {
994 DBG("%s deleting %p\n", __func__
, *mt
);
996 drm_intel_bo_unreference((*mt
)->bo
);
997 intel_miptree_release(&(*mt
)->stencil_mt
);
998 if ((*mt
)->hiz_buf
) {
999 if ((*mt
)->hiz_buf
->mt
)
1000 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1002 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1003 free((*mt
)->hiz_buf
);
1005 intel_miptree_release(&(*mt
)->mcs_mt
);
1006 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1008 intel_miptree_release(&(*mt
)->plane
[0]);
1009 intel_miptree_release(&(*mt
)->plane
[1]);
1011 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1012 free((*mt
)->level
[i
].slice
);
1022 intel_get_image_dims(struct gl_texture_image
*image
,
1023 int *width
, int *height
, int *depth
)
1025 switch (image
->TexObject
->Target
) {
1026 case GL_TEXTURE_1D_ARRAY
:
1027 /* For a 1D Array texture the OpenGL API will treat the image height as
1028 * the number of array slices. For Intel hardware, we treat the 1D array
1029 * as a 2D Array with a height of 1. So, here we want to swap image
1032 assert(image
->Depth
== 1);
1033 *width
= image
->Width
;
1035 *depth
= image
->Height
;
1037 case GL_TEXTURE_CUBE_MAP
:
1038 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1039 * though we really have 6 slices.
1041 assert(image
->Depth
== 1);
1042 *width
= image
->Width
;
1043 *height
= image
->Height
;
1047 *width
= image
->Width
;
1048 *height
= image
->Height
;
1049 *depth
= image
->Depth
;
1055 * Can the image be pulled into a unified mipmap tree? This mirrors
1056 * the completeness test in a lot of ways.
1058 * Not sure whether I want to pass gl_texture_image here.
1061 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1062 struct gl_texture_image
*image
)
1064 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1065 GLuint level
= intelImage
->base
.Base
.Level
;
1066 int width
, height
, depth
;
1068 /* glTexImage* choose the texture object based on the target passed in, and
1069 * objects can't change targets over their lifetimes, so this should be
1072 assert(image
->TexObject
->Target
== mt
->target
);
1074 mesa_format mt_format
= mt
->format
;
1075 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1076 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1077 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1078 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1079 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1080 mt_format
= mt
->etc_format
;
1082 if (image
->TexFormat
!= mt_format
)
1085 intel_get_image_dims(image
, &width
, &height
, &depth
);
1087 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1090 int level_depth
= mt
->level
[level
].depth
;
1091 if (mt
->num_samples
> 1) {
1092 switch (mt
->msaa_layout
) {
1093 case INTEL_MSAA_LAYOUT_NONE
:
1094 case INTEL_MSAA_LAYOUT_IMS
:
1096 case INTEL_MSAA_LAYOUT_UMS
:
1097 case INTEL_MSAA_LAYOUT_CMS
:
1098 level_depth
/= mt
->num_samples
;
1103 /* Test image dimensions against the base level image adjusted for
1104 * minification. This will also catch images not present in the
1105 * tree, changed targets, etc.
1107 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1108 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1109 depth
!= level_depth
) {
1113 if (image
->NumSamples
!= mt
->num_samples
)
1121 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1123 GLuint x
, GLuint y
, GLuint d
)
1125 mt
->level
[level
].depth
= d
;
1126 mt
->level
[level
].level_x
= x
;
1127 mt
->level
[level
].level_y
= y
;
1129 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1132 assert(mt
->level
[level
].slice
== NULL
);
1134 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1135 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1136 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1141 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1142 GLuint level
, GLuint img
,
1145 if (img
== 0 && level
== 0)
1146 assert(x
== 0 && y
== 0);
1148 assert(img
< mt
->level
[level
].depth
);
1150 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1151 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1153 DBG("%s level %d img %d pos %d,%d\n",
1154 __func__
, level
, img
,
1155 mt
->level
[level
].slice
[img
].x_offset
,
1156 mt
->level
[level
].slice
[img
].y_offset
);
1160 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1161 GLuint level
, GLuint slice
,
1162 GLuint
*x
, GLuint
*y
)
1164 assert(slice
< mt
->level
[level
].depth
);
1166 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1167 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1172 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1173 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1174 * and tile_h is set to 1.
1177 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1178 uint32_t *tile_w
, uint32_t *tile_h
)
1180 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1190 case I915_TILING_NONE
:
1195 unreachable("not reached");
1198 uint32_t aspect_ratio
= 1;
1199 assert(_mesa_is_pow_two(cpp
));
1214 unreachable("not reached");
1217 if (cpp
== 2 || cpp
== 8)
1220 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1223 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1229 * This function computes masks that may be used to select the bits of the X
1230 * and Y coordinates that indicate the offset within a tile. If the BO is
1231 * untiled, the masks are set to 0.
1234 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1235 uint32_t *mask_x
, uint32_t *mask_y
)
1237 uint32_t tile_w_bytes
, tile_h
;
1239 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1241 *mask_x
= tile_w_bytes
/ cpp
- 1;
1242 *mask_y
= tile_h
- 1;
1246 * Compute the offset (in bytes) from the start of the BO to the given x
1247 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1248 * multiples of the tile size.
1251 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1252 uint32_t x
, uint32_t y
,
1253 bool map_stencil_as_y_tiled
)
1256 uint32_t pitch
= mt
->pitch
;
1257 uint32_t tiling
= mt
->tiling
;
1259 if (map_stencil_as_y_tiled
) {
1260 tiling
= I915_TILING_Y
;
1262 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1263 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1264 * the resulting surface is twice the pitch of the original miptree,
1265 * since each row in the Y-tiled view corresponds to two rows in the
1266 * actual W-tiled surface. So we need to correct the pitch before
1267 * computing the offsets.
1274 unreachable("not reached");
1275 case I915_TILING_NONE
:
1276 return y
* pitch
+ x
* cpp
;
1278 assert((x
% (512 / cpp
)) == 0);
1279 assert((y
% 8) == 0);
1280 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1282 assert((x
% (128 / cpp
)) == 0);
1283 assert((y
% 32) == 0);
1284 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1289 * Rendering with tiled buffers requires that the base address of the buffer
1290 * be aligned to a page boundary. For renderbuffers, and sometimes with
1291 * textures, we may want the surface to point at a texture image level that
1292 * isn't at a page boundary.
1294 * This function returns an appropriately-aligned base offset
1295 * according to the tiling restrictions, plus any required x/y offset
1299 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1300 GLuint level
, GLuint slice
,
1305 uint32_t mask_x
, mask_y
;
1307 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, &mask_x
, &mask_y
);
1308 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1310 *tile_x
= x
& mask_x
;
1311 *tile_y
= y
& mask_y
;
1313 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1317 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1318 struct intel_mipmap_tree
*dst_mt
,
1319 struct intel_mipmap_tree
*src_mt
,
1326 ptrdiff_t src_stride
, dst_stride
;
1327 int cpp
= dst_mt
->cpp
;
1329 intel_miptree_map(brw
, src_mt
,
1333 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1336 intel_miptree_map(brw
, dst_mt
,
1340 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1344 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1345 _mesa_get_format_name(src_mt
->format
),
1346 src_mt
, src
, src_stride
,
1347 _mesa_get_format_name(dst_mt
->format
),
1348 dst_mt
, dst
, dst_stride
,
1351 int row_size
= cpp
* width
;
1352 if (src_stride
== row_size
&&
1353 dst_stride
== row_size
) {
1354 memcpy(dst
, src
, row_size
* height
);
1356 for (int i
= 0; i
< height
; i
++) {
1357 memcpy(dst
, src
, row_size
);
1363 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1364 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1366 /* Don't forget to copy the stencil data over, too. We could have skipped
1367 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1368 * shuffling the two data sources in/out of temporary storage instead of
1369 * the direct mapping we get this way.
1371 if (dst_mt
->stencil_mt
) {
1372 assert(src_mt
->stencil_mt
);
1373 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1374 level
, slice
, width
, height
);
1379 intel_miptree_copy_slice(struct brw_context
*brw
,
1380 struct intel_mipmap_tree
*dst_mt
,
1381 struct intel_mipmap_tree
*src_mt
,
1387 mesa_format format
= src_mt
->format
;
1388 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1389 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1397 assert(depth
< src_mt
->level
[level
].depth
);
1398 assert(src_mt
->format
== dst_mt
->format
);
1400 if (dst_mt
->compressed
) {
1402 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1403 height
= ALIGN_NPOT(height
, j
) / j
;
1404 width
= ALIGN_NPOT(width
, i
) / i
;
1407 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1408 * below won't apply since we can't do the depth's Y tiling or the
1409 * stencil's W tiling in the blitter.
1411 if (src_mt
->stencil_mt
) {
1412 intel_miptree_copy_slice_sw(brw
,
1419 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1420 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1421 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1423 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1424 _mesa_get_format_name(src_mt
->format
),
1425 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1426 _mesa_get_format_name(dst_mt
->format
),
1427 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1430 if (!intel_miptree_blit(brw
,
1431 src_mt
, level
, slice
, 0, 0, false,
1432 dst_mt
, level
, slice
, 0, 0, false,
1433 width
, height
, GL_COPY
)) {
1434 perf_debug("miptree validate blit for %s failed\n",
1435 _mesa_get_format_name(format
));
1437 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1443 * Copies the image's current data to the given miptree, and associates that
1444 * miptree with the image.
1446 * If \c invalidate is true, then the actual image data does not need to be
1447 * copied, but the image still needs to be associated to the new miptree (this
1448 * is set to true if we're about to clear the image).
1451 intel_miptree_copy_teximage(struct brw_context
*brw
,
1452 struct intel_texture_image
*intelImage
,
1453 struct intel_mipmap_tree
*dst_mt
,
1456 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1457 struct intel_texture_object
*intel_obj
=
1458 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1459 int level
= intelImage
->base
.Base
.Level
;
1460 int face
= intelImage
->base
.Base
.Face
;
1463 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1464 depth
= intelImage
->base
.Base
.Height
;
1466 depth
= intelImage
->base
.Base
.Depth
;
1469 for (int slice
= 0; slice
< depth
; slice
++) {
1470 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1474 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1475 intel_obj
->needs_validate
= true;
1479 intel_miptree_init_mcs(struct brw_context
*brw
,
1480 struct intel_mipmap_tree
*mt
,
1483 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1485 * When MCS buffer is enabled and bound to MSRT, it is required that it
1486 * is cleared prior to any rendering.
1488 * Since we don't use the MCS buffer for any purpose other than rendering,
1489 * it makes sense to just clear it immediately upon allocation.
1491 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1493 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1494 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1495 intel_miptree_unmap_raw(mt
->mcs_mt
);
1496 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1500 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1501 struct intel_mipmap_tree
*mt
,
1504 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1505 assert(mt
->mcs_mt
== NULL
);
1506 assert(!mt
->disable_aux_buffers
);
1508 /* Choose the correct format for the MCS buffer. All that really matters
1509 * is that we allocate the right buffer size, since we'll always be
1510 * accessing this miptree using MCS-specific hardware mechanisms, which
1511 * infer the correct format based on num_samples.
1514 switch (num_samples
) {
1517 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1520 format
= MESA_FORMAT_R_UNORM8
;
1523 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1524 * for each sample, plus 8 padding bits).
1526 format
= MESA_FORMAT_R_UINT32
;
1529 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1532 format
= MESA_FORMAT_RG_UINT32
;
1535 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1538 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1540 * "The MCS surface must be stored as Tile Y."
1542 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1543 MIPTREE_LAYOUT_TILING_Y
;
1544 mt
->mcs_mt
= miptree_create(brw
,
1550 mt
->logical_height0
,
1552 0 /* num_samples */,
1555 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1562 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1563 struct intel_mipmap_tree
*mt
)
1565 assert(mt
->mcs_mt
== NULL
);
1566 assert(!mt
->disable_aux_buffers
);
1568 /* The format of the MCS buffer is opaque to the driver; all that matters
1569 * is that we get its size and pitch right. We'll pretend that the format
1570 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1571 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1572 * the block width and then a further factor of 4. Since an MCS tile
1573 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1574 * we'll need to scale the height down by the block height and then a
1575 * further factor of 8.
1577 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1578 unsigned block_width_px
;
1579 unsigned block_height
;
1580 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1581 unsigned width_divisor
= block_width_px
* 4;
1582 unsigned height_divisor
= block_height
* 8;
1584 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1586 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1587 * in the main surface. In Skylake, it's two bits. The extra bit
1588 * doubles the MCS height, not width, because in Skylake the MCS is always
1592 height_divisor
/= 2;
1594 unsigned mcs_width
=
1595 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1596 unsigned mcs_height
=
1597 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1598 assert(mt
->logical_depth0
== 1);
1599 uint32_t layout_flags
= MIPTREE_LAYOUT_TILING_Y
;
1601 if (brw
->gen
>= 8) {
1602 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1605 /* On Gen9+ clients are not currently capable of consuming compressed
1606 * single-sampled buffers. Disabling compression allows us to skip
1609 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
1610 const bool is_lossless_compressed
=
1611 unlikely(!lossless_compression_disabled
) &&
1612 brw
->gen
>= 9 && !mt
->is_scanout
&&
1613 intel_miptree_supports_lossless_compressed(brw
, mt
);
1615 /* In case of compression mcs buffer needs to be initialised requiring the
1616 * buffer to be immediately mapped to cpu space for writing. Therefore do
1617 * not use the gpu access flag which can cause an unnecessary delay if the
1618 * backing pages happened to be just used by the GPU.
1620 if (!is_lossless_compressed
)
1621 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1623 mt
->mcs_mt
= miptree_create(brw
,
1631 0 /* num_samples */,
1634 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1635 * used for lossless compression which requires similar initialisation
1636 * as multi-sample compression.
1638 if (is_lossless_compressed
) {
1639 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1640 * resolve. Initialize it accordingly in case the first renderer is
1641 * cpu (or other none compression aware party).
1643 * This is also explicitly stated in the spec (MCS Buffer for Render
1645 * "If Software wants to enable Color Compression without Fast clear,
1646 * Software needs to initialize MCS with zeros."
1648 intel_miptree_init_mcs(brw
, mt
, 0);
1649 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1650 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1657 intel_miptree_prepare_mcs(struct brw_context
*brw
,
1658 struct intel_mipmap_tree
*mt
)
1666 /* Single sample compression is represented re-using msaa compression
1667 * layout type: "Compressed Multisampled Surfaces".
1669 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
|| mt
->num_samples
> 1)
1672 /* Clients are not currently capable of consuming compressed
1673 * single-sampled buffers.
1678 assert(intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) ||
1679 intel_miptree_supports_lossless_compressed(brw
, mt
));
1681 /* Consider if lossless compression is supported but the needed
1682 * auxiliary buffer doesn't exist yet.
1684 * Failing to allocate the auxiliary buffer means running out of
1685 * memory. The pointer to the aux miptree is left NULL which should
1686 * signal non-compressed behavior.
1688 if (!intel_miptree_alloc_non_msrt_mcs(brw
, mt
)) {
1690 "Failed to allocated aux buffer for lossless"
1691 " compressed %p %u:%u %s\n",
1692 mt
, mt
->logical_width0
, mt
->logical_height0
,
1693 _mesa_get_format_name(mt
->format
));
1698 * Helper for intel_miptree_alloc_hiz() that sets
1699 * \c mt->level[level].has_hiz. Return true if and only if
1700 * \c has_hiz was set.
1703 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1704 struct intel_mipmap_tree
*mt
,
1707 assert(mt
->hiz_buf
);
1709 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1710 uint32_t width
= minify(mt
->physical_width0
, level
);
1711 uint32_t height
= minify(mt
->physical_height0
, level
);
1713 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1714 * and the height is 4 aligned. This allows our HiZ support
1715 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1716 * we can grow the width & height to allow the HiZ op to
1717 * force the proper size alignments.
1719 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1720 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1725 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1726 mt
->level
[level
].has_hiz
= true;
1732 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1733 * buffer dimensions and allocates a bo for the hiz buffer.
1735 static struct intel_miptree_aux_buffer
*
1736 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1737 struct intel_mipmap_tree
*mt
)
1739 unsigned z_width
= mt
->logical_width0
;
1740 unsigned z_height
= mt
->logical_height0
;
1741 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1742 unsigned hz_width
, hz_height
;
1743 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1748 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1749 * adjustments required for Z_Height and Z_Width based on multisampling.
1751 switch (mt
->num_samples
) {
1765 unreachable("unsupported sample count");
1768 const unsigned vertical_align
= 8; /* 'j' in the docs */
1769 const unsigned H0
= z_height
;
1770 const unsigned h0
= ALIGN(H0
, vertical_align
);
1771 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1772 const unsigned Z0
= z_depth
;
1774 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1775 hz_width
= ALIGN(z_width
, 16);
1777 if (mt
->target
== GL_TEXTURE_3D
) {
1781 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1782 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1783 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1784 hz_height
+= h_i
* Z_i
;
1785 H_i
= minify(H_i
, 1);
1786 Z_i
= minify(Z_i
, 1);
1789 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1791 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1793 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1794 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1795 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1798 unsigned long pitch
;
1799 uint32_t tiling
= I915_TILING_Y
;
1800 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1801 hz_width
, hz_height
, 1,
1803 BO_ALLOC_FOR_RENDER
);
1807 } else if (tiling
!= I915_TILING_Y
) {
1808 drm_intel_bo_unreference(buf
->bo
);
1820 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1821 * buffer dimensions and allocates a bo for the hiz buffer.
1823 static struct intel_miptree_aux_buffer
*
1824 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1825 struct intel_mipmap_tree
*mt
)
1827 unsigned z_width
= mt
->logical_width0
;
1828 unsigned z_height
= mt
->logical_height0
;
1829 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1830 unsigned hz_width
, hz_height
;
1831 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1836 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1837 * adjustments required for Z_Height and Z_Width based on multisampling.
1840 switch (mt
->num_samples
) {
1854 unreachable("unsupported sample count");
1858 const unsigned vertical_align
= 8; /* 'j' in the docs */
1859 const unsigned H0
= z_height
;
1860 const unsigned h0
= ALIGN(H0
, vertical_align
);
1861 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1862 const unsigned Z0
= z_depth
;
1864 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1865 hz_width
= ALIGN(z_width
, 16);
1869 unsigned sum_h_i
= 0;
1870 unsigned hz_height_3d_sum
= 0;
1871 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1872 unsigned i
= level
- mt
->first_level
;
1873 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1874 /* sum(i=2 to m; h_i) */
1878 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1879 hz_height_3d_sum
+= h_i
* Z_i
;
1880 H_i
= minify(H_i
, 1);
1881 Z_i
= minify(Z_i
, 1);
1883 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1884 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1886 if (mt
->target
== GL_TEXTURE_3D
) {
1887 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1888 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1890 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1891 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1894 unsigned long pitch
;
1895 uint32_t tiling
= I915_TILING_Y
;
1896 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1897 hz_width
, hz_height
, 1,
1899 BO_ALLOC_FOR_RENDER
);
1903 } else if (tiling
!= I915_TILING_Y
) {
1904 drm_intel_bo_unreference(buf
->bo
);
1915 static struct intel_miptree_aux_buffer
*
1916 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1917 struct intel_mipmap_tree
*mt
)
1919 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1920 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1923 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1928 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1929 buf
->mt
= intel_miptree_create(brw
,
1935 mt
->logical_height0
,
1944 buf
->bo
= buf
->mt
->bo
;
1945 buf
->pitch
= buf
->mt
->pitch
;
1946 buf
->qpitch
= buf
->mt
->qpitch
;
1952 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1953 struct intel_mipmap_tree
*mt
)
1958 if (mt
->hiz_buf
!= NULL
)
1961 if (mt
->disable_aux_buffers
)
1964 switch (mt
->format
) {
1965 case MESA_FORMAT_Z_FLOAT32
:
1966 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1967 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1968 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1969 case MESA_FORMAT_Z_UNORM16
:
1977 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1978 struct intel_mipmap_tree
*mt
)
1980 assert(mt
->hiz_buf
== NULL
);
1981 assert(!mt
->disable_aux_buffers
);
1983 if (brw
->gen
== 7) {
1984 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1985 } else if (brw
->gen
>= 8) {
1986 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1988 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1994 /* Mark that all slices need a HiZ resolve. */
1995 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1996 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1999 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
2000 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
2001 exec_node_init(&m
->link
);
2004 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
2006 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
2014 * Does the miptree slice have hiz enabled?
2017 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2019 intel_miptree_check_level_layer(mt
, level
, 0);
2020 return mt
->level
[level
].has_hiz
;
2024 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2028 if (!intel_miptree_level_has_hiz(mt
, level
))
2031 intel_resolve_map_set(&mt
->hiz_map
,
2032 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
2037 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2041 if (!intel_miptree_level_has_hiz(mt
, level
))
2044 intel_resolve_map_set(&mt
->hiz_map
,
2045 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
2049 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2053 uint32_t end_layer
= mt
->level
[level
].depth
;
2055 for (layer
= 0; layer
< end_layer
; layer
++) {
2056 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2061 intel_miptree_slice_resolve(struct brw_context
*brw
,
2062 struct intel_mipmap_tree
*mt
,
2065 enum gen6_hiz_op need
)
2067 intel_miptree_check_level_layer(mt
, level
, layer
);
2069 struct intel_resolve_map
*item
=
2070 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2072 if (!item
|| item
->need
!= need
)
2075 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2076 intel_resolve_map_remove(item
);
2081 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2082 struct intel_mipmap_tree
*mt
,
2086 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2087 GEN6_HIZ_OP_HIZ_RESOLVE
);
2091 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2092 struct intel_mipmap_tree
*mt
,
2096 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2097 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2101 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2102 struct intel_mipmap_tree
*mt
,
2103 enum gen6_hiz_op need
)
2105 bool did_resolve
= false;
2107 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2108 if (map
->need
!= need
)
2111 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2112 intel_resolve_map_remove(map
);
2120 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2121 struct intel_mipmap_tree
*mt
)
2123 return intel_miptree_all_slices_resolve(brw
, mt
,
2124 GEN6_HIZ_OP_HIZ_RESOLVE
);
2128 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2129 struct intel_mipmap_tree
*mt
)
2131 return intel_miptree_all_slices_resolve(brw
, mt
,
2132 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2137 intel_miptree_resolve_color(struct brw_context
*brw
,
2138 struct intel_mipmap_tree
*mt
,
2141 /* From gen9 onwards there is new compression scheme for single sampled
2142 * surfaces called "lossless compressed". These don't need to be always
2145 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2146 intel_miptree_is_lossless_compressed(brw
, mt
))
2149 switch (mt
->fast_clear_state
) {
2150 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2151 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2152 /* No resolve needed */
2154 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2155 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2156 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2157 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2158 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2159 brw_blorp_resolve_color(brw
, mt
);
2167 * Make it possible to share the BO backing the given miptree with another
2168 * process or another miptree.
2170 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2171 * then discard the MCS buffer, if present. We also set the fast_clear_state
2172 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2173 * allocated in the future.
2176 intel_miptree_make_shareable(struct brw_context
*brw
,
2177 struct intel_mipmap_tree
*mt
)
2179 /* MCS buffers are also used for multisample buffers, but we can't resolve
2180 * away a multisample MCS buffer because it's an integral part of how the
2181 * pixel data is stored. Fortunately this code path should never be
2182 * reached for multisample buffers.
2184 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2187 intel_miptree_resolve_color(brw
, mt
, 0);
2188 intel_miptree_release(&mt
->mcs_mt
);
2189 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2195 * \brief Get pointer offset into stencil buffer.
2197 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2198 * must decode the tile's layout in software.
2201 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2203 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2205 * Even though the returned offset is always positive, the return type is
2207 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2208 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2211 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2213 uint32_t tile_size
= 4096;
2214 uint32_t tile_width
= 64;
2215 uint32_t tile_height
= 64;
2216 uint32_t row_size
= 64 * stride
;
2218 uint32_t tile_x
= x
/ tile_width
;
2219 uint32_t tile_y
= y
/ tile_height
;
2221 /* The byte's address relative to the tile's base addres. */
2222 uint32_t byte_x
= x
% tile_width
;
2223 uint32_t byte_y
= y
% tile_height
;
2225 uintptr_t u
= tile_y
* row_size
2226 + tile_x
* tile_size
2227 + 512 * (byte_x
/ 8)
2229 + 32 * ((byte_y
/ 4) % 2)
2230 + 16 * ((byte_x
/ 4) % 2)
2231 + 8 * ((byte_y
/ 2) % 2)
2232 + 4 * ((byte_x
/ 2) % 2)
2237 /* adjust for bit6 swizzling */
2238 if (((byte_x
/ 8) % 2) == 1) {
2239 if (((byte_y
/ 8) % 2) == 0) {
2251 intel_miptree_updownsample(struct brw_context
*brw
,
2252 struct intel_mipmap_tree
*src
,
2253 struct intel_mipmap_tree
*dst
)
2255 brw_blorp_blit_miptrees(brw
,
2256 src
, 0 /* level */, 0 /* layer */,
2257 src
->format
, SWIZZLE_XYZW
,
2258 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2260 src
->logical_width0
, src
->logical_height0
,
2262 dst
->logical_width0
, dst
->logical_height0
,
2263 GL_NEAREST
, false, false /*mirror x, y*/,
2266 if (src
->stencil_mt
) {
2267 brw_blorp_blit_miptrees(brw
,
2268 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2269 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2270 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2271 dst
->stencil_mt
->format
,
2273 src
->logical_width0
, src
->logical_height0
,
2275 dst
->logical_width0
, dst
->logical_height0
,
2276 GL_NEAREST
, false, false /*mirror x, y*/,
2277 false, false /* decode/encode srgb */);
2282 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2284 /* CPU accesses to color buffers don't understand fast color clears, so
2285 * resolve any pending fast color clears before we map.
2287 intel_miptree_resolve_color(brw
, mt
, 0);
2289 drm_intel_bo
*bo
= mt
->bo
;
2291 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2292 intel_batchbuffer_flush(brw
);
2294 if (mt
->tiling
!= I915_TILING_NONE
)
2295 brw_bo_map_gtt(brw
, bo
, "miptree");
2297 brw_bo_map(brw
, bo
, true, "miptree");
2303 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2305 drm_intel_bo_unmap(mt
->bo
);
2309 intel_miptree_map_gtt(struct brw_context
*brw
,
2310 struct intel_mipmap_tree
*mt
,
2311 struct intel_miptree_map
*map
,
2312 unsigned int level
, unsigned int slice
)
2314 unsigned int bw
, bh
;
2316 unsigned int image_x
, image_y
;
2317 intptr_t x
= map
->x
;
2318 intptr_t y
= map
->y
;
2320 /* For compressed formats, the stride is the number of bytes per
2321 * row of blocks. intel_miptree_get_image_offset() already does
2324 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2325 assert(y
% bh
== 0);
2326 assert(x
% bw
== 0);
2330 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2335 /* Note that in the case of cube maps, the caller must have passed the
2336 * slice number referencing the face.
2338 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2342 map
->stride
= mt
->pitch
;
2343 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2346 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2347 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2348 map
->x
, map
->y
, map
->w
, map
->h
,
2349 mt
, _mesa_get_format_name(mt
->format
),
2350 x
, y
, map
->ptr
, map
->stride
);
2354 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2356 intel_miptree_unmap_raw(mt
);
2360 intel_miptree_map_blit(struct brw_context
*brw
,
2361 struct intel_mipmap_tree
*mt
,
2362 struct intel_miptree_map
*map
,
2363 unsigned int level
, unsigned int slice
)
2365 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2366 /* first_level */ 0,
2370 MIPTREE_LAYOUT_TILING_NONE
);
2372 if (!map
->linear_mt
) {
2373 fprintf(stderr
, "Failed to allocate blit temporary\n");
2376 map
->stride
= map
->linear_mt
->pitch
;
2378 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2379 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2380 * invalidate is set, since we'll be writing the whole rectangle from our
2381 * temporary buffer back out.
2383 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2384 if (!intel_miptree_blit(brw
,
2386 map
->x
, map
->y
, false,
2387 map
->linear_mt
, 0, 0,
2389 map
->w
, map
->h
, GL_COPY
)) {
2390 fprintf(stderr
, "Failed to blit\n");
2395 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2397 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2398 map
->x
, map
->y
, map
->w
, map
->h
,
2399 mt
, _mesa_get_format_name(mt
->format
),
2400 level
, slice
, map
->ptr
, map
->stride
);
2405 intel_miptree_release(&map
->linear_mt
);
2411 intel_miptree_unmap_blit(struct brw_context
*brw
,
2412 struct intel_mipmap_tree
*mt
,
2413 struct intel_miptree_map
*map
,
2417 struct gl_context
*ctx
= &brw
->ctx
;
2419 intel_miptree_unmap_raw(map
->linear_mt
);
2421 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2422 bool ok
= intel_miptree_blit(brw
,
2423 map
->linear_mt
, 0, 0,
2426 map
->x
, map
->y
, false,
2427 map
->w
, map
->h
, GL_COPY
);
2428 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2431 intel_miptree_release(&map
->linear_mt
);
2435 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2437 #if defined(USE_SSE41)
2439 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2440 struct intel_mipmap_tree
*mt
,
2441 struct intel_miptree_map
*map
,
2442 unsigned int level
, unsigned int slice
)
2444 assert(map
->mode
& GL_MAP_READ_BIT
);
2445 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2447 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2448 map
->x
, map
->y
, map
->w
, map
->h
,
2449 mt
, _mesa_get_format_name(mt
->format
),
2450 level
, slice
, map
->ptr
, map
->stride
);
2452 /* Map the original image */
2455 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2459 void *src
= intel_miptree_map_raw(brw
, mt
);
2465 src
+= image_y
* mt
->pitch
;
2466 src
+= image_x
* mt
->cpp
;
2468 /* Due to the pixel offsets for the particular image being mapped, our
2469 * src pointer may not be 16-byte aligned. However, if the pitch is
2470 * divisible by 16, then the amount by which it's misaligned will remain
2471 * consistent from row to row.
2473 assert((mt
->pitch
% 16) == 0);
2474 const int misalignment
= ((uintptr_t) src
) & 15;
2476 /* Create an untiled temporary buffer for the mapping. */
2477 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2479 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2481 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2482 /* Offset the destination so it has the same misalignment as src. */
2483 map
->ptr
= map
->buffer
+ misalignment
;
2485 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2487 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2488 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2489 void *src_ptr
= src
+ y
* mt
->pitch
;
2491 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2494 intel_miptree_unmap_raw(mt
);
2498 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2499 struct intel_mipmap_tree
*mt
,
2500 struct intel_miptree_map
*map
,
2504 _mesa_align_free(map
->buffer
);
2511 intel_miptree_map_s8(struct brw_context
*brw
,
2512 struct intel_mipmap_tree
*mt
,
2513 struct intel_miptree_map
*map
,
2514 unsigned int level
, unsigned int slice
)
2516 map
->stride
= map
->w
;
2517 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2521 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2522 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2523 * invalidate is set, since we'll be writing the whole rectangle from our
2524 * temporary buffer back out.
2526 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2527 uint8_t *untiled_s8_map
= map
->ptr
;
2528 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2529 unsigned int image_x
, image_y
;
2531 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2533 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2534 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2535 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2536 x
+ image_x
+ map
->x
,
2537 y
+ image_y
+ map
->y
,
2538 brw
->has_swizzling
);
2539 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2543 intel_miptree_unmap_raw(mt
);
2545 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2546 map
->x
, map
->y
, map
->w
, map
->h
,
2547 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2549 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2550 map
->x
, map
->y
, map
->w
, map
->h
,
2551 mt
, map
->ptr
, map
->stride
);
2556 intel_miptree_unmap_s8(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
,
2558 struct intel_miptree_map
*map
,
2562 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2563 unsigned int image_x
, image_y
;
2564 uint8_t *untiled_s8_map
= map
->ptr
;
2565 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2567 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2569 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2570 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2571 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2572 image_x
+ x
+ map
->x
,
2573 image_y
+ y
+ map
->y
,
2574 brw
->has_swizzling
);
2575 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2579 intel_miptree_unmap_raw(mt
);
2586 intel_miptree_map_etc(struct brw_context
*brw
,
2587 struct intel_mipmap_tree
*mt
,
2588 struct intel_miptree_map
*map
,
2592 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2593 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2594 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2597 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2598 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2600 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2601 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2602 map
->w
, map
->h
, 1));
2603 map
->ptr
= map
->buffer
;
2607 intel_miptree_unmap_etc(struct brw_context
*brw
,
2608 struct intel_mipmap_tree
*mt
,
2609 struct intel_miptree_map
*map
,
2615 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2620 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2621 + image_y
* mt
->pitch
2622 + image_x
* mt
->cpp
;
2624 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2625 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2626 map
->ptr
, map
->stride
,
2629 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2630 map
->ptr
, map
->stride
,
2631 map
->w
, map
->h
, mt
->etc_format
);
2633 intel_miptree_unmap_raw(mt
);
2638 * Mapping function for packed depth/stencil miptrees backed by real separate
2639 * miptrees for depth and stencil.
2641 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2642 * separate from the depth buffer. Yet at the GL API level, we have to expose
2643 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2644 * be able to map that memory for texture storage and glReadPixels-type
2645 * operations. We give Mesa core that access by mallocing a temporary and
2646 * copying the data between the actual backing store and the temporary.
2649 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2650 struct intel_mipmap_tree
*mt
,
2651 struct intel_miptree_map
*map
,
2652 unsigned int level
, unsigned int slice
)
2654 struct intel_mipmap_tree
*z_mt
= mt
;
2655 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2656 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2657 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2659 map
->stride
= map
->w
* packed_bpp
;
2660 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2664 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2665 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2666 * invalidate is set, since we'll be writing the whole rectangle from our
2667 * temporary buffer back out.
2669 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2670 uint32_t *packed_map
= map
->ptr
;
2671 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2672 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2673 unsigned int s_image_x
, s_image_y
;
2674 unsigned int z_image_x
, z_image_y
;
2676 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2677 &s_image_x
, &s_image_y
);
2678 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2679 &z_image_x
, &z_image_y
);
2681 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2682 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2683 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2684 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2687 brw
->has_swizzling
);
2688 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2690 (map_x
+ z_image_x
));
2691 uint8_t s
= s_map
[s_offset
];
2692 uint32_t z
= z_map
[z_offset
];
2694 if (map_z32f_x24s8
) {
2695 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2696 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2698 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2703 intel_miptree_unmap_raw(s_mt
);
2704 intel_miptree_unmap_raw(z_mt
);
2706 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2708 map
->x
, map
->y
, map
->w
, map
->h
,
2709 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2710 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2711 map
->ptr
, map
->stride
);
2713 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2714 map
->x
, map
->y
, map
->w
, map
->h
,
2715 mt
, map
->ptr
, map
->stride
);
2720 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2721 struct intel_mipmap_tree
*mt
,
2722 struct intel_miptree_map
*map
,
2726 struct intel_mipmap_tree
*z_mt
= mt
;
2727 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2728 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2730 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2731 uint32_t *packed_map
= map
->ptr
;
2732 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2733 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2734 unsigned int s_image_x
, s_image_y
;
2735 unsigned int z_image_x
, z_image_y
;
2737 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2738 &s_image_x
, &s_image_y
);
2739 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2740 &z_image_x
, &z_image_y
);
2742 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2743 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2744 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2745 x
+ s_image_x
+ map
->x
,
2746 y
+ s_image_y
+ map
->y
,
2747 brw
->has_swizzling
);
2748 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2750 (x
+ z_image_x
+ map
->x
));
2752 if (map_z32f_x24s8
) {
2753 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2754 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2756 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2757 s_map
[s_offset
] = packed
>> 24;
2758 z_map
[z_offset
] = packed
;
2763 intel_miptree_unmap_raw(s_mt
);
2764 intel_miptree_unmap_raw(z_mt
);
2766 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2768 map
->x
, map
->y
, map
->w
, map
->h
,
2769 z_mt
, _mesa_get_format_name(z_mt
->format
),
2770 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2771 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2772 map
->ptr
, map
->stride
);
2779 * Create and attach a map to the miptree at (level, slice). Return the
2782 static struct intel_miptree_map
*
2783 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2792 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2797 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2798 mt
->level
[level
].slice
[slice
].map
= map
;
2810 * Release the map at (level, slice).
2813 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2817 struct intel_miptree_map
**map
;
2819 map
= &mt
->level
[level
].slice
[slice
].map
;
2825 can_blit_slice(struct intel_mipmap_tree
*mt
,
2826 unsigned int level
, unsigned int slice
)
2830 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2831 if (image_x
>= 32768 || image_y
>= 32768)
2834 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2835 if (mt
->pitch
>= 32768)
2842 use_intel_mipree_map_blit(struct brw_context
*brw
,
2843 struct intel_mipmap_tree
*mt
,
2849 /* It's probably not worth swapping to the blit ring because of
2850 * all the overhead involved. But, we must use blitter for the
2851 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2853 (!(mode
& GL_MAP_WRITE_BIT
) ||
2854 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2856 (mt
->tiling
== I915_TILING_X
||
2857 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2858 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2859 /* Fast copy blit on skl+ supports all tiling formats. */
2861 can_blit_slice(mt
, level
, slice
))
2864 if (mt
->tiling
!= I915_TILING_NONE
&&
2865 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2866 assert(can_blit_slice(mt
, level
, slice
));
2874 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2875 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2876 * arithmetic overflow.
2878 * If you call this function and use \a out_stride, then you're doing pointer
2879 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2880 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2881 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2882 * which usually have type uint32_t or GLuint.
2885 intel_miptree_map(struct brw_context
*brw
,
2886 struct intel_mipmap_tree
*mt
,
2895 ptrdiff_t *out_stride
)
2897 struct intel_miptree_map
*map
;
2899 assert(mt
->num_samples
<= 1);
2901 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2908 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2909 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2910 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2913 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2914 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2915 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2916 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2917 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2918 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2919 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2920 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2921 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2922 #if defined(USE_SSE41)
2923 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2924 !mt
->compressed
&& cpu_has_sse4_1
&&
2925 (mt
->pitch
% 16 == 0)) {
2926 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2929 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2930 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2931 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2934 *out_ptr
= map
->ptr
;
2935 *out_stride
= map
->stride
;
2937 if (map
->ptr
== NULL
)
2938 intel_miptree_release_map(mt
, level
, slice
);
2942 intel_miptree_unmap(struct brw_context
*brw
,
2943 struct intel_mipmap_tree
*mt
,
2947 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2949 assert(mt
->num_samples
<= 1);
2954 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2955 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2957 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2958 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2959 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2960 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2961 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2962 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2963 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2964 } else if (map
->linear_mt
) {
2965 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2966 #if defined(USE_SSE41)
2967 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2968 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2971 intel_miptree_unmap_gtt(mt
);
2974 intel_miptree_release_map(mt
, level
, slice
);
2978 intel_miptree_get_isl_surf(struct brw_context
*brw
,
2979 const struct intel_mipmap_tree
*mt
,
2980 struct isl_surf
*surf
)
2982 switch (mt
->target
) {
2984 case GL_TEXTURE_1D_ARRAY
: {
2985 surf
->dim
= ISL_SURF_DIM_1D
;
2986 if (brw
->gen
>= 9 && mt
->tiling
== I915_TILING_NONE
)
2987 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN9_1D
;
2989 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
2993 case GL_TEXTURE_2D_ARRAY
:
2994 case GL_TEXTURE_RECTANGLE
:
2995 case GL_TEXTURE_CUBE_MAP
:
2996 case GL_TEXTURE_CUBE_MAP_ARRAY
:
2997 case GL_TEXTURE_2D_MULTISAMPLE
:
2998 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
2999 case GL_TEXTURE_EXTERNAL_OES
:
3000 surf
->dim
= ISL_SURF_DIM_2D
;
3001 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3004 surf
->dim
= ISL_SURF_DIM_3D
;
3006 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3008 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_3D
;
3011 unreachable("Invalid texture target");
3014 if (mt
->num_samples
> 1) {
3015 switch (mt
->msaa_layout
) {
3016 case INTEL_MSAA_LAYOUT_IMS
:
3017 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3019 case INTEL_MSAA_LAYOUT_UMS
:
3020 case INTEL_MSAA_LAYOUT_CMS
:
3021 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3024 unreachable("Invalid MSAA layout");
3027 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3030 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3031 surf
->tiling
= ISL_TILING_W
;
3032 /* The ISL definition of row_pitch matches the surface state pitch field
3033 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3034 * the factor of 2 for W-tiling in row_pitch.
3036 surf
->row_pitch
= 2 * mt
->pitch
;
3038 switch (mt
->tiling
) {
3039 case I915_TILING_NONE
:
3040 surf
->tiling
= ISL_TILING_LINEAR
;
3043 surf
->tiling
= ISL_TILING_X
;
3046 switch (mt
->tr_mode
) {
3047 case INTEL_MIPTREE_TRMODE_NONE
:
3048 surf
->tiling
= ISL_TILING_Y0
;
3050 case INTEL_MIPTREE_TRMODE_YF
:
3051 surf
->tiling
= ISL_TILING_Yf
;
3053 case INTEL_MIPTREE_TRMODE_YS
:
3054 surf
->tiling
= ISL_TILING_Ys
;
3059 unreachable("Invalid tiling mode");
3062 surf
->row_pitch
= mt
->pitch
;
3065 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3067 if (brw
->gen
>= 9) {
3068 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3069 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3070 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3072 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3073 * alignment in terms of surface elements like we want.
3075 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3078 /* On earlier gens it's stored in pixels. */
3080 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3081 surf
->image_alignment_el
=
3082 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3085 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3086 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3087 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3088 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3089 surf
->logical_level0_px
.array_len
= 1;
3091 surf
->logical_level0_px
.depth
= 1;
3092 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3095 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3096 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3097 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3098 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3099 surf
->phys_level0_sa
.array_len
= 1;
3101 surf
->phys_level0_sa
.depth
= 1;
3102 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3105 surf
->levels
= mt
->last_level
+ 1;
3106 surf
->samples
= MAX2(mt
->num_samples
, 1);
3108 surf
->size
= 0; /* TODO */
3109 surf
->alignment
= 0; /* TODO */
3111 switch (surf
->dim_layout
) {
3112 case ISL_DIM_LAYOUT_GEN4_2D
:
3113 case ISL_DIM_LAYOUT_GEN4_3D
:
3114 if (brw
->gen
>= 9) {
3115 surf
->array_pitch_el_rows
= mt
->qpitch
;
3118 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3119 assert(mt
->qpitch
% bh
== 0);
3120 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3123 case ISL_DIM_LAYOUT_GEN9_1D
:
3124 surf
->array_pitch_el_rows
= 1;
3128 switch (mt
->array_layout
) {
3129 case ALL_LOD_IN_EACH_SLICE
:
3130 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3132 case ALL_SLICES_AT_EACH_LOD
:
3133 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3136 unreachable("Invalid array layout");
3139 surf
->usage
= 0; /* TODO */
3142 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3143 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3144 * PASS IT INTO isl_surf_fill_state.
3147 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3148 const struct intel_mipmap_tree
*mt
,
3149 struct isl_surf
*surf
,
3150 enum isl_aux_usage
*usage
)
3152 /* Much is the same as the regular surface */
3153 intel_miptree_get_isl_surf(brw
, mt
->mcs_mt
, surf
);
3155 /* Figure out the layout */
3156 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3157 *usage
= ISL_AUX_USAGE_HIZ
;
3158 } else if (mt
->num_samples
> 1) {
3159 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3160 *usage
= ISL_AUX_USAGE_MCS
;
3161 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3162 assert(brw
->gen
>= 9);
3163 *usage
= ISL_AUX_USAGE_CCS_E
;
3164 } else if (mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_NO_MCS
) {
3165 *usage
= ISL_AUX_USAGE_CCS_D
;
3167 unreachable("Invalid MCS miptree");
3170 /* Figure out the format and tiling of the auxiliary surface */
3172 case ISL_AUX_USAGE_NONE
:
3173 unreachable("Invalid MCS miptree");
3175 case ISL_AUX_USAGE_HIZ
:
3176 surf
->format
= ISL_FORMAT_HIZ
;
3177 surf
->tiling
= ISL_TILING_HIZ
;
3178 surf
->usage
= ISL_SURF_USAGE_HIZ_BIT
;
3181 case ISL_AUX_USAGE_MCS
:
3184 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3185 * HALIGN 16 must be used."
3188 assert(mt
->halign
== 16);
3190 surf
->usage
= ISL_SURF_USAGE_MCS_BIT
;
3192 switch (mt
->num_samples
) {
3193 case 2: surf
->format
= ISL_FORMAT_MCS_2X
; break;
3194 case 4: surf
->format
= ISL_FORMAT_MCS_4X
; break;
3195 case 8: surf
->format
= ISL_FORMAT_MCS_8X
; break;
3196 case 16: surf
->format
= ISL_FORMAT_MCS_16X
; break;
3198 unreachable("Invalid number of samples");
3202 case ISL_AUX_USAGE_CCS_D
:
3203 case ISL_AUX_USAGE_CCS_E
:
3205 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3207 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3209 * From the hardware spec for GEN9:
3211 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3212 * HALIGN 16 must be used."
3214 assert(mt
->num_samples
<= 1);
3216 assert(mt
->halign
== 16);
3218 surf
->tiling
= ISL_TILING_CCS
;
3219 surf
->usage
= ISL_SURF_USAGE_CCS_BIT
;
3221 if (brw
->gen
>= 9) {
3222 assert(mt
->tiling
== I915_TILING_Y
);
3223 switch (_mesa_get_format_bytes(mt
->format
)) {
3224 case 4: surf
->format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
3225 case 8: surf
->format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
3226 case 16: surf
->format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
3228 unreachable("Invalid format size for color compression");
3230 } else if (mt
->tiling
== I915_TILING_Y
) {
3231 switch (_mesa_get_format_bytes(mt
->format
)) {
3232 case 4: surf
->format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
3233 case 8: surf
->format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
3234 case 16: surf
->format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
3236 unreachable("Invalid format size for color compression");
3239 assert(mt
->tiling
== I915_TILING_X
);
3240 switch (_mesa_get_format_bytes(mt
->format
)) {
3241 case 4: surf
->format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
3242 case 8: surf
->format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
3243 case 16: surf
->format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
3245 unreachable("Invalid format size for color compression");
3251 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3252 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3253 * in elements of the primary color surface so we have to divide by the
3254 * compression block height.
3256 surf
->array_pitch_el_rows
= mt
->qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3259 union isl_color_value
3260 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3261 const struct intel_mipmap_tree
*mt
)
3263 union isl_color_value clear_color
;
3265 if (brw
->gen
>= 9) {
3266 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3267 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3268 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3269 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3270 } else if (_mesa_is_format_integer(mt
->format
)) {
3271 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3272 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3273 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3274 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3276 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3277 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3278 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3279 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;