1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
38 #include "intel_fbo.h"
40 #include "brw_blorp.h"
41 #include "brw_context.h"
43 #include "main/enums.h"
44 #include "main/fbobject.h"
45 #include "main/formats.h"
46 #include "main/glformats.h"
47 #include "main/texcompress_etc.h"
48 #include "main/teximage.h"
49 #include "main/streaming-load-memcpy.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* Disable MCS on Broadwell for now. We can enable it once things
72 * are working without it.
75 perf_debug("Missing CMS support on Broadwell.\n");
76 return INTEL_MSAA_LAYOUT_UMS
;
79 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
81 * This field must be set to 0 for all SINT MSRTs when all RT channels
84 * In practice this means that we have to disable MCS for all signed
85 * integer MSAA buffers. The alternative, to disable MCS only when one
86 * of the render target channels is disabled, is impractical because it
87 * would require converting between CMS and UMS MSAA layouts on the fly,
90 if (_mesa_get_format_datatype(format
) == GL_INT
) {
91 /* TODO: is this workaround needed for future chipsets? */
92 assert(brw
->gen
== 7);
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->region
->tiling
) {
149 assert(!"Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
163 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
170 * - Support is for non-mip-mapped and non-array surface types only.
172 * And then later, on p327:
174 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
178 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
179 struct intel_mipmap_tree
*mt
)
181 /* MCS support does not exist prior to Gen7 */
182 if (brw
->gen
< 7 || brw
->gen
>= 8)
185 /* MCS is only supported for color buffers */
186 switch (_mesa_get_format_base_format(mt
->format
)) {
187 case GL_DEPTH_COMPONENT
:
188 case GL_DEPTH_STENCIL
:
189 case GL_STENCIL_INDEX
:
193 if (mt
->region
->tiling
!= I915_TILING_X
&&
194 mt
->region
->tiling
!= I915_TILING_Y
)
196 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
198 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
200 if (mt
->physical_depth0
!= 1)
203 /* There's no point in using an MCS buffer if the surface isn't in a
206 if (!brw
->format_supported_as_render_target
[mt
->format
])
214 * Determine depth format corresponding to a depth+stencil format,
215 * for separate stencil.
218 intel_depth_format_for_depthstencil_format(mesa_format format
) {
220 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
221 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
222 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
223 return MESA_FORMAT_Z_FLOAT32
;
231 * @param for_bo Indicates that the caller is
232 * intel_miptree_create_for_bo(). If true, then do not create
235 struct intel_mipmap_tree
*
236 intel_miptree_create_layout(struct brw_context
*brw
,
247 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
251 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
252 _mesa_lookup_enum_by_nr(target
),
253 _mesa_get_format_name(format
),
254 first_level
, last_level
, depth0
, mt
);
258 mt
->first_level
= first_level
;
259 mt
->last_level
= last_level
;
260 mt
->logical_width0
= width0
;
261 mt
->logical_height0
= height0
;
262 mt
->logical_depth0
= depth0
;
263 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
265 /* The cpp is bytes per (1, blockheight)-sized block for compressed
266 * textures. This is why you'll see divides by blockheight all over
269 _mesa_get_format_block_size(format
, &bw
, &bh
);
270 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
271 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
273 mt
->num_samples
= num_samples
;
274 mt
->compressed
= _mesa_is_format_compressed(format
);
275 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
278 if (num_samples
> 1) {
279 /* Adjust width/height/depth for MSAA */
280 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
281 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
282 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
284 * "Any of the other messages (sample*, LOD, load4) used with a
285 * (4x) multisampled surface will in-effect sample a surface with
286 * double the height and width as that indicated in the surface
287 * state. Each pixel position on the original-sized surface is
288 * replaced with a 2x2 of samples with the following arrangement:
293 * Thus, when sampling from a multisampled texture, it behaves as
294 * though the layout in memory for (x,y,sample) is:
296 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
297 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
299 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
300 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
302 * However, the actual layout of multisampled data in memory is:
304 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
305 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
307 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
308 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
310 * This pattern repeats for each 2x2 pixel block.
312 * As a result, when calculating the size of our 4-sample buffer for
313 * an odd width or height, we have to align before scaling up because
314 * sample 3 is in that bottom right 2x2 block.
316 switch (num_samples
) {
318 assert(brw
->gen
>= 8);
319 width0
= ALIGN(width0
, 2) * 2;
320 height0
= ALIGN(height0
, 2);
323 width0
= ALIGN(width0
, 2) * 2;
324 height0
= ALIGN(height0
, 2) * 2;
327 width0
= ALIGN(width0
, 2) * 4;
328 height0
= ALIGN(height0
, 2) * 2;
331 /* num_samples should already have been quantized to 0, 1, 2, 4, or
337 /* Non-interleaved */
338 depth0
*= num_samples
;
342 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
345 switch (mt
->msaa_layout
) {
346 case INTEL_MSAA_LAYOUT_NONE
:
347 case INTEL_MSAA_LAYOUT_IMS
:
348 mt
->array_spacing_lod0
= false;
350 case INTEL_MSAA_LAYOUT_UMS
:
351 case INTEL_MSAA_LAYOUT_CMS
:
352 mt
->array_spacing_lod0
= true;
356 if (target
== GL_TEXTURE_CUBE_MAP
) {
361 mt
->physical_width0
= width0
;
362 mt
->physical_height0
= height0
;
363 mt
->physical_depth0
= depth0
;
366 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
367 (brw
->must_use_separate_stencil
||
368 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
369 mt
->stencil_mt
= intel_miptree_create(brw
,
379 INTEL_MIPTREE_TILING_ANY
);
380 if (!mt
->stencil_mt
) {
381 intel_miptree_release(&mt
);
385 /* Fix up the Z miptree format for how we're splitting out separate
386 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
388 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
391 if (format
== mt
->format
) {
392 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
393 _mesa_get_format_name(mt
->format
));
397 brw_miptree_layout(brw
, mt
);
403 * \brief Helper function for intel_miptree_create().
406 intel_miptree_choose_tiling(struct brw_context
*brw
,
409 uint32_t num_samples
,
410 enum intel_miptree_tiling_mode requested
,
411 struct intel_mipmap_tree
*mt
)
413 if (format
== MESA_FORMAT_S_UINT8
) {
414 /* The stencil buffer is W tiled. However, we request from the kernel a
415 * non-tiled buffer because the GTT is incapable of W fencing.
417 return I915_TILING_NONE
;
420 /* Some usages may want only one type of tiling, like depth miptrees (Y
421 * tiled), or temporary BOs for uploading data once (linear).
424 case INTEL_MIPTREE_TILING_ANY
:
426 case INTEL_MIPTREE_TILING_Y
:
427 return I915_TILING_Y
;
428 case INTEL_MIPTREE_TILING_NONE
:
429 return I915_TILING_NONE
;
432 if (num_samples
> 1) {
433 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
436 * [DevSNB+]: For multi-sample render targets, this field must be
437 * 1. MSRTs can only be tiled.
439 * Our usual reason for preferring X tiling (fast blits using the
440 * blitting engine) doesn't apply to MSAA, since we'll generally be
441 * downsampling or upsampling when blitting between the MSAA buffer
442 * and another buffer, and the blitting engine doesn't support that.
443 * So use Y tiling, since it makes better use of the cache.
445 return I915_TILING_Y
;
448 GLenum base_format
= _mesa_get_format_base_format(format
);
449 if (base_format
== GL_DEPTH_COMPONENT
||
450 base_format
== GL_DEPTH_STENCIL_EXT
)
451 return I915_TILING_Y
;
453 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
455 /* If the width is much smaller than a tile, don't bother tiling. */
456 if (minimum_pitch
< 64)
457 return I915_TILING_NONE
;
459 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
460 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
461 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
462 mt
->total_width
, mt
->total_height
);
463 return I915_TILING_NONE
;
466 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
468 return I915_TILING_X
;
470 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
471 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
473 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
474 * all the way back to 965, but is explicitly permitted on Gen7.
476 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
477 return I915_TILING_X
;
479 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
480 * messages), on p64, under the heading "Surface Vertical Alignment":
482 * This field must be set to VALIGN_4 for all tiled Y Render Target
485 * So if the surface is renderable and uses a vertical alignment of 2,
486 * force it to be X tiled. This is somewhat conservative (it's possible
487 * that the client won't ever render to this surface), but it's difficult
488 * to know that ahead of time. And besides, since we use a vertical
489 * alignment of 4 as often as we can, this shouldn't happen very often.
491 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
492 brw
->format_supported_as_render_target
[format
]) {
493 return I915_TILING_X
;
496 return I915_TILING_Y
| I915_TILING_X
;
501 * Choose an appropriate uncompressed format for a requested
502 * compressed format, if unsupported.
505 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
507 /* No need to lower ETC formats on these platforms,
508 * they are supported natively.
510 if (brw
->gen
>= 8 || brw
->is_baytrail
)
514 case MESA_FORMAT_ETC1_RGB8
:
515 return MESA_FORMAT_R8G8B8X8_UNORM
;
516 case MESA_FORMAT_ETC2_RGB8
:
517 return MESA_FORMAT_R8G8B8X8_UNORM
;
518 case MESA_FORMAT_ETC2_SRGB8
:
519 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
520 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
521 return MESA_FORMAT_B8G8R8A8_SRGB
;
522 case MESA_FORMAT_ETC2_RGBA8_EAC
:
523 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
524 return MESA_FORMAT_R8G8B8A8_UNORM
;
525 case MESA_FORMAT_ETC2_R11_EAC
:
526 return MESA_FORMAT_R_UNORM16
;
527 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
528 return MESA_FORMAT_R_SNORM16
;
529 case MESA_FORMAT_ETC2_RG11_EAC
:
530 return MESA_FORMAT_R16G16_UNORM
;
531 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
532 return MESA_FORMAT_R16G16_SNORM
;
534 /* Non ETC1 / ETC2 format */
540 struct intel_mipmap_tree
*
541 intel_miptree_create(struct brw_context
*brw
,
549 bool expect_accelerated_upload
,
551 enum intel_miptree_tiling_mode requested_tiling
)
553 struct intel_mipmap_tree
*mt
;
554 mesa_format tex_format
= format
;
555 mesa_format etc_format
= MESA_FORMAT_NONE
;
556 GLuint total_width
, total_height
;
558 format
= intel_lower_compressed_format(brw
, format
);
560 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
562 mt
= intel_miptree_create_layout(brw
, target
, format
,
563 first_level
, last_level
, width0
,
567 * pitch == 0 || height == 0 indicates the null texture
569 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
570 intel_miptree_release(&mt
);
574 total_width
= mt
->total_width
;
575 total_height
= mt
->total_height
;
577 if (format
== MESA_FORMAT_S_UINT8
) {
578 /* Align to size of W tile, 64x64. */
579 total_width
= ALIGN(total_width
, 64);
580 total_height
= ALIGN(total_height
, 64);
583 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
584 num_samples
, requested_tiling
,
586 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
588 mt
->etc_format
= etc_format
;
589 mt
->region
= intel_region_alloc(brw
->intelScreen
,
590 y_or_x
? I915_TILING_Y
: tiling
,
594 expect_accelerated_upload
);
596 /* If the region is too large to fit in the aperture, we need to use the
597 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
598 * so we need to fall back to X.
600 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
601 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
602 mt
->total_width
, mt
->total_height
);
603 intel_region_release(&mt
->region
);
605 mt
->region
= intel_region_alloc(brw
->intelScreen
,
610 expect_accelerated_upload
);
616 intel_miptree_release(&mt
);
621 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
622 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
623 intel_miptree_release(&mt
);
628 /* If this miptree is capable of supporting fast color clears, set
629 * fast_clear_state appropriately to ensure that fast clears will occur.
630 * Allocation of the MCS miptree will be deferred until the first fast
631 * clear actually occurs.
633 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
634 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
639 struct intel_mipmap_tree
*
640 intel_miptree_create_for_bo(struct brw_context
*brw
,
648 struct intel_mipmap_tree
*mt
;
649 uint32_t tiling
, swizzle
;
651 struct intel_region
*region
= calloc(1, sizeof(*region
));
655 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
657 /* Nothing will be able to use this miptree with the BO if the offset isn't
660 if (tiling
!= I915_TILING_NONE
)
661 assert(offset
% 4096 == 0);
663 /* miptrees can't handle negative pitch. If you need flipping of images,
664 * that's outside of the scope of the mt.
668 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
671 true, 0 /* num_samples */);
677 region
->cpp
= mt
->cpp
;
678 region
->width
= width
;
679 region
->height
= height
;
680 region
->pitch
= pitch
;
681 region
->refcount
= 1;
682 drm_intel_bo_reference(bo
);
684 region
->tiling
= tiling
;
693 * For a singlesample image buffer, this simply wraps the given region with a miptree.
695 * For a multisample image buffer, this wraps the given region with
696 * a singlesample miptree, then creates a multisample miptree into which the
697 * singlesample miptree is embedded as a child.
700 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
701 struct intel_renderbuffer
*irb
,
702 struct intel_region
*region
)
704 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
705 struct intel_mipmap_tree
*multisample_mt
= NULL
;
706 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
707 mesa_format format
= rb
->Format
;
708 int num_samples
= rb
->NumSamples
;
710 /* Only the front and back buffers, which are color buffers, are allocated
711 * through the image loader.
713 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
714 _mesa_get_format_base_format(format
) == GL_RGBA
);
716 singlesample_mt
= intel_miptree_create_for_bo(intel
,
723 if (!singlesample_mt
)
726 /* If this miptree is capable of supporting fast color clears, set
727 * mcs_state appropriately to ensure that fast clears will occur.
728 * Allocation of the MCS miptree will be deferred until the first fast
729 * clear actually occurs.
731 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
732 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
734 if (num_samples
== 0) {
735 intel_miptree_release(&irb
->mt
);
736 irb
->mt
= singlesample_mt
;
738 assert(!irb
->singlesample_mt
);
740 intel_miptree_release(&irb
->singlesample_mt
);
741 irb
->singlesample_mt
= singlesample_mt
;
744 irb
->mt
->logical_width0
!= region
->width
||
745 irb
->mt
->logical_height0
!= region
->height
) {
746 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
754 irb
->need_downsample
= false;
755 intel_miptree_release(&irb
->mt
);
756 irb
->mt
= multisample_mt
;
762 intel_miptree_release(&irb
->singlesample_mt
);
763 intel_miptree_release(&irb
->mt
);
767 struct intel_mipmap_tree
*
768 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
772 uint32_t num_samples
)
774 struct intel_mipmap_tree
*mt
;
777 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
779 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
780 width
, height
, depth
, true, num_samples
,
781 INTEL_MIPTREE_TILING_ANY
);
785 if (brw_is_hiz_depth_format(brw
, format
)) {
786 ok
= intel_miptree_alloc_hiz(brw
, mt
);
794 intel_miptree_release(&mt
);
799 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
800 struct intel_mipmap_tree
*src
)
805 intel_miptree_release(dst
);
809 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
817 intel_miptree_release(struct intel_mipmap_tree
**mt
)
822 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
823 if (--(*mt
)->refcount
<= 0) {
826 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
828 intel_region_release(&((*mt
)->region
));
829 intel_miptree_release(&(*mt
)->stencil_mt
);
830 intel_miptree_release(&(*mt
)->hiz_mt
);
831 intel_miptree_release(&(*mt
)->mcs_mt
);
832 intel_resolve_map_clear(&(*mt
)->hiz_map
);
834 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
835 free((*mt
)->level
[i
].slice
);
844 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
845 int *width
, int *height
, int *depth
)
847 switch (image
->TexObject
->Target
) {
848 case GL_TEXTURE_1D_ARRAY
:
849 *width
= image
->Width
;
851 *depth
= image
->Height
;
854 *width
= image
->Width
;
855 *height
= image
->Height
;
856 *depth
= image
->Depth
;
862 * Can the image be pulled into a unified mipmap tree? This mirrors
863 * the completeness test in a lot of ways.
865 * Not sure whether I want to pass gl_texture_image here.
868 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
869 struct gl_texture_image
*image
)
871 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
872 GLuint level
= intelImage
->base
.Base
.Level
;
873 int width
, height
, depth
;
875 /* glTexImage* choose the texture object based on the target passed in, and
876 * objects can't change targets over their lifetimes, so this should be
879 assert(image
->TexObject
->Target
== mt
->target
);
881 mesa_format mt_format
= mt
->format
;
882 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
883 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
884 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
885 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
886 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
887 mt_format
= mt
->etc_format
;
889 if (image
->TexFormat
!= mt_format
)
892 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
894 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
897 int level_depth
= mt
->level
[level
].depth
;
898 if (mt
->num_samples
> 1) {
899 switch (mt
->msaa_layout
) {
900 case INTEL_MSAA_LAYOUT_NONE
:
901 case INTEL_MSAA_LAYOUT_IMS
:
903 case INTEL_MSAA_LAYOUT_UMS
:
904 case INTEL_MSAA_LAYOUT_CMS
:
905 level_depth
/= mt
->num_samples
;
910 /* Test image dimensions against the base level image adjusted for
911 * minification. This will also catch images not present in the
912 * tree, changed targets, etc.
914 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
915 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
916 depth
!= level_depth
) {
920 if (image
->NumSamples
!= mt
->num_samples
)
928 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
930 GLuint x
, GLuint y
, GLuint d
)
932 mt
->level
[level
].depth
= d
;
933 mt
->level
[level
].level_x
= x
;
934 mt
->level
[level
].level_y
= y
;
936 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
939 assert(mt
->level
[level
].slice
== NULL
);
941 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
942 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
943 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
948 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
949 GLuint level
, GLuint img
,
952 if (img
== 0 && level
== 0)
953 assert(x
== 0 && y
== 0);
955 assert(img
< mt
->level
[level
].depth
);
957 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
958 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
960 DBG("%s level %d img %d pos %d,%d\n",
961 __FUNCTION__
, level
, img
,
962 mt
->level
[level
].slice
[img
].x_offset
,
963 mt
->level
[level
].slice
[img
].y_offset
);
967 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
968 GLuint level
, GLuint slice
,
969 GLuint
*x
, GLuint
*y
)
971 assert(slice
< mt
->level
[level
].depth
);
973 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
974 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
978 * This function computes masks that may be used to select the bits of the X
979 * and Y coordinates that indicate the offset within a tile. If the BO is
980 * untiled, the masks are set to 0.
983 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
984 uint32_t *mask_x
, uint32_t *mask_y
,
985 bool map_stencil_as_y_tiled
)
987 int cpp
= mt
->region
->cpp
;
988 uint32_t tiling
= mt
->region
->tiling
;
990 if (map_stencil_as_y_tiled
)
991 tiling
= I915_TILING_Y
;
996 case I915_TILING_NONE
:
997 *mask_x
= *mask_y
= 0;
1000 *mask_x
= 512 / cpp
- 1;
1004 *mask_x
= 128 / cpp
- 1;
1011 * Compute the offset (in bytes) from the start of the BO to the given x
1012 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1013 * multiples of the tile size.
1016 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1017 uint32_t x
, uint32_t y
,
1018 bool map_stencil_as_y_tiled
)
1020 int cpp
= mt
->region
->cpp
;
1021 uint32_t pitch
= mt
->region
->pitch
;
1022 uint32_t tiling
= mt
->region
->tiling
;
1024 if (map_stencil_as_y_tiled
) {
1025 tiling
= I915_TILING_Y
;
1027 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1028 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1029 * the resulting surface is twice the pitch of the original miptree,
1030 * since each row in the Y-tiled view corresponds to two rows in the
1031 * actual W-tiled surface. So we need to correct the pitch before
1032 * computing the offsets.
1040 case I915_TILING_NONE
:
1041 return y
* pitch
+ x
* cpp
;
1043 assert((x
% (512 / cpp
)) == 0);
1044 assert((y
% 8) == 0);
1045 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1047 assert((x
% (128 / cpp
)) == 0);
1048 assert((y
% 32) == 0);
1049 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1054 * Rendering with tiled buffers requires that the base address of the buffer
1055 * be aligned to a page boundary. For renderbuffers, and sometimes with
1056 * textures, we may want the surface to point at a texture image level that
1057 * isn't at a page boundary.
1059 * This function returns an appropriately-aligned base offset
1060 * according to the tiling restrictions, plus any required x/y offset
1064 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1065 GLuint level
, GLuint slice
,
1070 uint32_t mask_x
, mask_y
;
1072 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1073 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1075 *tile_x
= x
& mask_x
;
1076 *tile_y
= y
& mask_y
;
1078 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1082 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1083 struct intel_mipmap_tree
*dst_mt
,
1084 struct intel_mipmap_tree
*src_mt
,
1091 int src_stride
, dst_stride
;
1092 int cpp
= dst_mt
->cpp
;
1094 intel_miptree_map(brw
, src_mt
,
1098 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1101 intel_miptree_map(brw
, dst_mt
,
1105 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1109 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1110 _mesa_get_format_name(src_mt
->format
),
1111 src_mt
, src
, src_stride
,
1112 _mesa_get_format_name(dst_mt
->format
),
1113 dst_mt
, dst
, dst_stride
,
1116 int row_size
= cpp
* width
;
1117 if (src_stride
== row_size
&&
1118 dst_stride
== row_size
) {
1119 memcpy(dst
, src
, row_size
* height
);
1121 for (int i
= 0; i
< height
; i
++) {
1122 memcpy(dst
, src
, row_size
);
1128 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1129 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1131 /* Don't forget to copy the stencil data over, too. We could have skipped
1132 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1133 * shuffling the two data sources in/out of temporary storage instead of
1134 * the direct mapping we get this way.
1136 if (dst_mt
->stencil_mt
) {
1137 assert(src_mt
->stencil_mt
);
1138 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1139 level
, slice
, width
, height
);
1144 intel_miptree_copy_slice(struct brw_context
*brw
,
1145 struct intel_mipmap_tree
*dst_mt
,
1146 struct intel_mipmap_tree
*src_mt
,
1152 mesa_format format
= src_mt
->format
;
1153 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1154 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1162 assert(depth
< src_mt
->level
[level
].depth
);
1163 assert(src_mt
->format
== dst_mt
->format
);
1165 if (dst_mt
->compressed
) {
1166 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1167 width
= ALIGN(width
, dst_mt
->align_w
);
1170 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1171 * below won't apply since we can't do the depth's Y tiling or the
1172 * stencil's W tiling in the blitter.
1174 if (src_mt
->stencil_mt
) {
1175 intel_miptree_copy_slice_sw(brw
,
1182 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1183 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1184 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1186 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1187 _mesa_get_format_name(src_mt
->format
),
1188 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1189 _mesa_get_format_name(dst_mt
->format
),
1190 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1193 if (!intel_miptree_blit(brw
,
1194 src_mt
, level
, slice
, 0, 0, false,
1195 dst_mt
, level
, slice
, 0, 0, false,
1196 width
, height
, GL_COPY
)) {
1197 perf_debug("miptree validate blit for %s failed\n",
1198 _mesa_get_format_name(format
));
1200 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1206 * Copies the image's current data to the given miptree, and associates that
1207 * miptree with the image.
1209 * If \c invalidate is true, then the actual image data does not need to be
1210 * copied, but the image still needs to be associated to the new miptree (this
1211 * is set to true if we're about to clear the image).
1214 intel_miptree_copy_teximage(struct brw_context
*brw
,
1215 struct intel_texture_image
*intelImage
,
1216 struct intel_mipmap_tree
*dst_mt
,
1219 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1220 struct intel_texture_object
*intel_obj
=
1221 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1222 int level
= intelImage
->base
.Base
.Level
;
1223 int face
= intelImage
->base
.Base
.Face
;
1224 GLuint depth
= intelImage
->base
.Base
.Depth
;
1227 for (int slice
= 0; slice
< depth
; slice
++) {
1228 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1232 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1233 intel_obj
->needs_validate
= true;
1237 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1238 struct intel_mipmap_tree
*mt
,
1241 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1242 assert(mt
->mcs_mt
== NULL
);
1244 /* Choose the correct format for the MCS buffer. All that really matters
1245 * is that we allocate the right buffer size, since we'll always be
1246 * accessing this miptree using MCS-specific hardware mechanisms, which
1247 * infer the correct format based on num_samples.
1250 switch (num_samples
) {
1252 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1255 format
= MESA_FORMAT_R_UNORM8
;
1258 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1259 * for each sample, plus 8 padding bits).
1261 format
= MESA_FORMAT_R_UINT32
;
1264 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1268 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1270 * "The MCS surface must be stored as Tile Y."
1272 mt
->mcs_mt
= intel_miptree_create(brw
,
1278 mt
->logical_height0
,
1281 0 /* num_samples */,
1282 INTEL_MIPTREE_TILING_Y
);
1284 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1286 * When MCS buffer is enabled and bound to MSRT, it is required that it
1287 * is cleared prior to any rendering.
1289 * Since we don't use the MCS buffer for any purpose other than rendering,
1290 * it makes sense to just clear it immediately upon allocation.
1292 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1294 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1295 memset(data
, 0xff, mt
->mcs_mt
->region
->height
* mt
->mcs_mt
->region
->pitch
);
1296 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1297 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1304 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1305 struct intel_mipmap_tree
*mt
)
1307 assert(mt
->mcs_mt
== NULL
);
1309 /* The format of the MCS buffer is opaque to the driver; all that matters
1310 * is that we get its size and pitch right. We'll pretend that the format
1311 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1312 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1313 * the block width and then a further factor of 4. Since an MCS tile
1314 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1315 * we'll need to scale the height down by the block height and then a
1316 * further factor of 8.
1318 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1319 unsigned block_width_px
;
1320 unsigned block_height
;
1321 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1322 unsigned width_divisor
= block_width_px
* 4;
1323 unsigned height_divisor
= block_height
* 8;
1324 unsigned mcs_width
=
1325 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1326 unsigned mcs_height
=
1327 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1328 assert(mt
->logical_depth0
== 1);
1329 mt
->mcs_mt
= intel_miptree_create(brw
,
1338 0 /* num_samples */,
1339 INTEL_MIPTREE_TILING_Y
);
1346 * Helper for intel_miptree_alloc_hiz() that sets
1347 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1348 * \c has_hiz was set.
1351 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1352 struct intel_mipmap_tree
*mt
,
1358 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1359 uint32_t width
= minify(mt
->physical_width0
, level
);
1360 uint32_t height
= minify(mt
->physical_height0
, level
);
1362 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1363 * and the height is 4 aligned. This allows our HiZ support
1364 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1365 * we can grow the width & height to allow the HiZ op to
1366 * force the proper size alignments.
1368 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1373 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1380 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1381 struct intel_mipmap_tree
*mt
)
1383 assert(mt
->hiz_mt
== NULL
);
1384 mt
->hiz_mt
= intel_miptree_create(brw
,
1390 mt
->logical_height0
,
1394 INTEL_MIPTREE_TILING_ANY
);
1399 /* Mark that all slices need a HiZ resolve. */
1400 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1401 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1402 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1403 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1406 head
->next
= malloc(sizeof(*head
->next
));
1407 head
->next
->prev
= head
;
1408 head
->next
->next
= NULL
;
1411 head
->level
= level
;
1412 head
->layer
= layer
;
1413 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1421 * Does the miptree slice have hiz enabled?
1424 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1428 intel_miptree_check_level_layer(mt
, level
, layer
);
1429 return mt
->level
[level
].slice
[layer
].has_hiz
;
1433 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1437 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1440 intel_resolve_map_set(&mt
->hiz_map
,
1441 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1446 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1450 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1453 intel_resolve_map_set(&mt
->hiz_map
,
1454 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1458 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1462 uint32_t end_layer
= mt
->level
[level
].depth
;
1464 for (layer
= 0; layer
< end_layer
; layer
++) {
1465 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1470 intel_miptree_slice_resolve(struct brw_context
*brw
,
1471 struct intel_mipmap_tree
*mt
,
1474 enum gen6_hiz_op need
)
1476 intel_miptree_check_level_layer(mt
, level
, layer
);
1478 struct intel_resolve_map
*item
=
1479 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1481 if (!item
|| item
->need
!= need
)
1484 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1485 intel_resolve_map_remove(item
);
1490 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1491 struct intel_mipmap_tree
*mt
,
1495 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1496 GEN6_HIZ_OP_HIZ_RESOLVE
);
1500 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1501 struct intel_mipmap_tree
*mt
,
1505 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1506 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1510 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1511 struct intel_mipmap_tree
*mt
,
1512 enum gen6_hiz_op need
)
1514 bool did_resolve
= false;
1515 struct intel_resolve_map
*i
, *next
;
1517 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1519 if (i
->need
!= need
)
1522 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1523 intel_resolve_map_remove(i
);
1531 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1532 struct intel_mipmap_tree
*mt
)
1534 return intel_miptree_all_slices_resolve(brw
, mt
,
1535 GEN6_HIZ_OP_HIZ_RESOLVE
);
1539 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1540 struct intel_mipmap_tree
*mt
)
1542 return intel_miptree_all_slices_resolve(brw
, mt
,
1543 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1548 intel_miptree_resolve_color(struct brw_context
*brw
,
1549 struct intel_mipmap_tree
*mt
)
1551 switch (mt
->fast_clear_state
) {
1552 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1553 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1554 /* No resolve needed */
1556 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1557 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1558 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1559 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1560 brw_blorp_resolve_color(brw
, mt
);
1567 * Make it possible to share the region backing the given miptree with another
1568 * process or another miptree.
1570 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1571 * then discard the MCS buffer, if present. We also set the fast_clear_state
1572 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1573 * allocated in the future.
1576 intel_miptree_make_shareable(struct brw_context
*brw
,
1577 struct intel_mipmap_tree
*mt
)
1579 /* MCS buffers are also used for multisample buffers, but we can't resolve
1580 * away a multisample MCS buffer because it's an integral part of how the
1581 * pixel data is stored. Fortunately this code path should never be
1582 * reached for multisample buffers.
1584 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1587 intel_miptree_resolve_color(brw
, mt
);
1588 intel_miptree_release(&mt
->mcs_mt
);
1589 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1595 * \brief Get pointer offset into stencil buffer.
1597 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1598 * must decode the tile's layout in software.
1601 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1603 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1605 * Even though the returned offset is always positive, the return type is
1607 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1608 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1611 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1613 uint32_t tile_size
= 4096;
1614 uint32_t tile_width
= 64;
1615 uint32_t tile_height
= 64;
1616 uint32_t row_size
= 64 * stride
;
1618 uint32_t tile_x
= x
/ tile_width
;
1619 uint32_t tile_y
= y
/ tile_height
;
1621 /* The byte's address relative to the tile's base addres. */
1622 uint32_t byte_x
= x
% tile_width
;
1623 uint32_t byte_y
= y
% tile_height
;
1625 uintptr_t u
= tile_y
* row_size
1626 + tile_x
* tile_size
1627 + 512 * (byte_x
/ 8)
1629 + 32 * ((byte_y
/ 4) % 2)
1630 + 16 * ((byte_x
/ 4) % 2)
1631 + 8 * ((byte_y
/ 2) % 2)
1632 + 4 * ((byte_x
/ 2) % 2)
1637 /* adjust for bit6 swizzling */
1638 if (((byte_x
/ 8) % 2) == 1) {
1639 if (((byte_y
/ 8) % 2) == 0) {
1651 intel_miptree_updownsample(struct brw_context
*brw
,
1652 struct intel_mipmap_tree
*src
,
1653 struct intel_mipmap_tree
*dst
)
1655 if (brw
->gen
< 8 || src
->format
== MESA_FORMAT_S_UINT8
) {
1656 brw_blorp_blit_miptrees(brw
,
1657 src
, 0 /* level */, 0 /* layer */,
1658 dst
, 0 /* level */, 0 /* layer */,
1660 src
->logical_width0
, src
->logical_height0
,
1662 dst
->logical_width0
, dst
->logical_height0
,
1663 GL_NEAREST
, false, false /*mirror x, y*/);
1665 brw_meta_updownsample(brw
, src
, dst
);
1668 if (src
->stencil_mt
) {
1669 brw_blorp_blit_miptrees(brw
,
1670 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1671 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1673 src
->logical_width0
, src
->logical_height0
,
1675 dst
->logical_width0
, dst
->logical_height0
,
1676 GL_NEAREST
, false, false /*mirror x, y*/);
1681 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1683 /* CPU accesses to color buffers don't understand fast color clears, so
1684 * resolve any pending fast color clears before we map.
1686 intel_miptree_resolve_color(brw
, mt
);
1688 drm_intel_bo
*bo
= mt
->region
->bo
;
1690 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1691 intel_batchbuffer_flush(brw
);
1693 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1694 brw_bo_map_gtt(brw
, bo
, "miptree");
1696 brw_bo_map(brw
, bo
, true, "miptree");
1702 intel_miptree_unmap_raw(struct brw_context
*brw
,
1703 struct intel_mipmap_tree
*mt
)
1705 drm_intel_bo_unmap(mt
->region
->bo
);
1709 intel_miptree_map_gtt(struct brw_context
*brw
,
1710 struct intel_mipmap_tree
*mt
,
1711 struct intel_miptree_map
*map
,
1712 unsigned int level
, unsigned int slice
)
1714 unsigned int bw
, bh
;
1716 unsigned int image_x
, image_y
;
1720 /* For compressed formats, the stride is the number of bytes per
1721 * row of blocks. intel_miptree_get_image_offset() already does
1724 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1725 assert(y
% bh
== 0);
1728 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1733 /* Note that in the case of cube maps, the caller must have passed the
1734 * slice number referencing the face.
1736 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1740 map
->stride
= mt
->region
->pitch
;
1741 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1744 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1745 map
->x
, map
->y
, map
->w
, map
->h
,
1746 mt
, _mesa_get_format_name(mt
->format
),
1747 x
, y
, map
->ptr
, map
->stride
);
1751 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1752 struct intel_mipmap_tree
*mt
,
1753 struct intel_miptree_map
*map
,
1757 intel_miptree_unmap_raw(brw
, mt
);
1761 intel_miptree_map_blit(struct brw_context
*brw
,
1762 struct intel_mipmap_tree
*mt
,
1763 struct intel_miptree_map
*map
,
1764 unsigned int level
, unsigned int slice
)
1766 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1770 INTEL_MIPTREE_TILING_NONE
);
1772 fprintf(stderr
, "Failed to allocate blit temporary\n");
1775 map
->stride
= map
->mt
->region
->pitch
;
1777 if (!intel_miptree_blit(brw
,
1779 map
->x
, map
->y
, false,
1782 map
->w
, map
->h
, GL_COPY
)) {
1783 fprintf(stderr
, "Failed to blit\n");
1787 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1789 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1790 map
->x
, map
->y
, map
->w
, map
->h
,
1791 mt
, _mesa_get_format_name(mt
->format
),
1792 level
, slice
, map
->ptr
, map
->stride
);
1797 intel_miptree_release(&map
->mt
);
1803 intel_miptree_unmap_blit(struct brw_context
*brw
,
1804 struct intel_mipmap_tree
*mt
,
1805 struct intel_miptree_map
*map
,
1809 struct gl_context
*ctx
= &brw
->ctx
;
1811 intel_miptree_unmap_raw(brw
, map
->mt
);
1813 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1814 bool ok
= intel_miptree_blit(brw
,
1818 map
->x
, map
->y
, false,
1819 map
->w
, map
->h
, GL_COPY
);
1820 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1823 intel_miptree_release(&map
->mt
);
1828 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1831 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1832 struct intel_mipmap_tree
*mt
,
1833 struct intel_miptree_map
*map
,
1834 unsigned int level
, unsigned int slice
)
1836 assert(map
->mode
& GL_MAP_READ_BIT
);
1837 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1839 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1840 map
->x
, map
->y
, map
->w
, map
->h
,
1841 mt
, _mesa_get_format_name(mt
->format
),
1842 level
, slice
, map
->ptr
, map
->stride
);
1844 /* Map the original image */
1847 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1851 void *src
= intel_miptree_map_raw(brw
, mt
);
1854 src
+= image_y
* mt
->region
->pitch
;
1855 src
+= image_x
* mt
->region
->cpp
;
1857 /* Due to the pixel offsets for the particular image being mapped, our
1858 * src pointer may not be 16-byte aligned. However, if the pitch is
1859 * divisible by 16, then the amount by which it's misaligned will remain
1860 * consistent from row to row.
1862 assert((mt
->region
->pitch
% 16) == 0);
1863 const int misalignment
= ((uintptr_t) src
) & 15;
1865 /* Create an untiled temporary buffer for the mapping. */
1866 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1868 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1870 map
->buffer
= malloc(map
->stride
* map
->h
);
1871 /* Offset the destination so it has the same misalignment as src. */
1872 map
->ptr
= map
->buffer
+ misalignment
;
1874 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1876 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1877 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1878 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1880 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1883 intel_miptree_unmap_raw(brw
, mt
);
1887 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1888 struct intel_mipmap_tree
*mt
,
1889 struct intel_miptree_map
*map
,
1900 intel_miptree_map_s8(struct brw_context
*brw
,
1901 struct intel_mipmap_tree
*mt
,
1902 struct intel_miptree_map
*map
,
1903 unsigned int level
, unsigned int slice
)
1905 map
->stride
= map
->w
;
1906 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1910 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1911 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1912 * invalidate is set, since we'll be writing the whole rectangle from our
1913 * temporary buffer back out.
1915 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1916 uint8_t *untiled_s8_map
= map
->ptr
;
1917 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1918 unsigned int image_x
, image_y
;
1920 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1922 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1923 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1924 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1925 x
+ image_x
+ map
->x
,
1926 y
+ image_y
+ map
->y
,
1927 brw
->has_swizzling
);
1928 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1932 intel_miptree_unmap_raw(brw
, mt
);
1934 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1935 map
->x
, map
->y
, map
->w
, map
->h
,
1936 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1938 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1939 map
->x
, map
->y
, map
->w
, map
->h
,
1940 mt
, map
->ptr
, map
->stride
);
1945 intel_miptree_unmap_s8(struct brw_context
*brw
,
1946 struct intel_mipmap_tree
*mt
,
1947 struct intel_miptree_map
*map
,
1951 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1952 unsigned int image_x
, image_y
;
1953 uint8_t *untiled_s8_map
= map
->ptr
;
1954 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1956 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1958 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1959 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1960 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1963 brw
->has_swizzling
);
1964 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1968 intel_miptree_unmap_raw(brw
, mt
);
1975 intel_miptree_map_etc(struct brw_context
*brw
,
1976 struct intel_mipmap_tree
*mt
,
1977 struct intel_miptree_map
*map
,
1981 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1982 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1983 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1986 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1987 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1989 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1990 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1991 map
->w
, map
->h
, 1));
1992 map
->ptr
= map
->buffer
;
1996 intel_miptree_unmap_etc(struct brw_context
*brw
,
1997 struct intel_mipmap_tree
*mt
,
1998 struct intel_miptree_map
*map
,
2004 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2009 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2010 + image_y
* mt
->region
->pitch
2011 + image_x
* mt
->region
->cpp
;
2013 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2014 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
2015 map
->ptr
, map
->stride
,
2018 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
2019 map
->ptr
, map
->stride
,
2020 map
->w
, map
->h
, mt
->etc_format
);
2022 intel_miptree_unmap_raw(brw
, mt
);
2027 * Mapping function for packed depth/stencil miptrees backed by real separate
2028 * miptrees for depth and stencil.
2030 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2031 * separate from the depth buffer. Yet at the GL API level, we have to expose
2032 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2033 * be able to map that memory for texture storage and glReadPixels-type
2034 * operations. We give Mesa core that access by mallocing a temporary and
2035 * copying the data between the actual backing store and the temporary.
2038 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2039 struct intel_mipmap_tree
*mt
,
2040 struct intel_miptree_map
*map
,
2041 unsigned int level
, unsigned int slice
)
2043 struct intel_mipmap_tree
*z_mt
= mt
;
2044 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2045 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2046 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2048 map
->stride
= map
->w
* packed_bpp
;
2049 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2053 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2054 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2055 * invalidate is set, since we'll be writing the whole rectangle from our
2056 * temporary buffer back out.
2058 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2059 uint32_t *packed_map
= map
->ptr
;
2060 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2061 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2062 unsigned int s_image_x
, s_image_y
;
2063 unsigned int z_image_x
, z_image_y
;
2065 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2066 &s_image_x
, &s_image_y
);
2067 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2068 &z_image_x
, &z_image_y
);
2070 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2071 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2072 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2073 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2076 brw
->has_swizzling
);
2077 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2078 (z_mt
->region
->pitch
/ 4) +
2079 (map_x
+ z_image_x
));
2080 uint8_t s
= s_map
[s_offset
];
2081 uint32_t z
= z_map
[z_offset
];
2083 if (map_z32f_x24s8
) {
2084 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2085 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2087 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2092 intel_miptree_unmap_raw(brw
, s_mt
);
2093 intel_miptree_unmap_raw(brw
, z_mt
);
2095 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2097 map
->x
, map
->y
, map
->w
, map
->h
,
2098 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2099 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2100 map
->ptr
, map
->stride
);
2102 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2103 map
->x
, map
->y
, map
->w
, map
->h
,
2104 mt
, map
->ptr
, map
->stride
);
2109 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2110 struct intel_mipmap_tree
*mt
,
2111 struct intel_miptree_map
*map
,
2115 struct intel_mipmap_tree
*z_mt
= mt
;
2116 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2117 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2119 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2120 uint32_t *packed_map
= map
->ptr
;
2121 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2122 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2123 unsigned int s_image_x
, s_image_y
;
2124 unsigned int z_image_x
, z_image_y
;
2126 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2127 &s_image_x
, &s_image_y
);
2128 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2129 &z_image_x
, &z_image_y
);
2131 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2132 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2133 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2134 x
+ s_image_x
+ map
->x
,
2135 y
+ s_image_y
+ map
->y
,
2136 brw
->has_swizzling
);
2137 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2138 (z_mt
->region
->pitch
/ 4) +
2141 if (map_z32f_x24s8
) {
2142 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2143 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2145 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2146 s_map
[s_offset
] = packed
>> 24;
2147 z_map
[z_offset
] = packed
;
2152 intel_miptree_unmap_raw(brw
, s_mt
);
2153 intel_miptree_unmap_raw(brw
, z_mt
);
2155 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2157 map
->x
, map
->y
, map
->w
, map
->h
,
2158 z_mt
, _mesa_get_format_name(z_mt
->format
),
2159 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2160 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2161 map
->ptr
, map
->stride
);
2168 * Create and attach a map to the miptree at (level, slice). Return the
2171 static struct intel_miptree_map
*
2172 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2181 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2186 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2187 mt
->level
[level
].slice
[slice
].map
= map
;
2199 * Release the map at (level, slice).
2202 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2206 struct intel_miptree_map
**map
;
2208 map
= &mt
->level
[level
].slice
[slice
].map
;
2214 can_blit_slice(struct intel_mipmap_tree
*mt
,
2215 unsigned int level
, unsigned int slice
)
2219 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2220 if (image_x
>= 32768 || image_y
>= 32768)
2223 if (mt
->region
->pitch
>= 32768)
2230 intel_miptree_map(struct brw_context
*brw
,
2231 struct intel_mipmap_tree
*mt
,
2242 struct intel_miptree_map
*map
;
2244 assert(mt
->num_samples
<= 1);
2246 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2253 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2254 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2255 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2258 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2259 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2260 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2261 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2262 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2263 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2264 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2266 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2267 else if (brw
->has_llc
&&
2268 !(mode
& GL_MAP_WRITE_BIT
) &&
2270 (mt
->region
->tiling
== I915_TILING_X
||
2271 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2272 can_blit_slice(mt
, level
, slice
)) {
2273 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2274 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2275 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2276 assert(can_blit_slice(mt
, level
, slice
));
2277 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2279 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2280 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2283 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2286 *out_ptr
= map
->ptr
;
2287 *out_stride
= map
->stride
;
2289 if (map
->ptr
== NULL
)
2290 intel_miptree_release_map(mt
, level
, slice
);
2294 intel_miptree_unmap(struct brw_context
*brw
,
2295 struct intel_mipmap_tree
*mt
,
2299 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2301 assert(mt
->num_samples
<= 1);
2306 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2307 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2309 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2310 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2311 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2312 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2313 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2314 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2315 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2316 } else if (map
->mt
) {
2317 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2319 } else if (map
->buffer
) {
2320 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2323 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2326 intel_miptree_release_map(mt
, level
, slice
);