2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 uint32_t layout_flags
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
107 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
108 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
110 * - Support is limited to tiled render targets.
112 * Gen9 changes the restriction to Y-tile only.
115 return tiling
== I915_TILING_Y
;
116 else if (brw
->gen
>= 7)
117 return tiling
!= I915_TILING_NONE
;
123 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
124 * can be used. This doesn't (and should not) inspect any of the properties of
127 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
128 * beneath the "Fast Color Clear" bullet (p326):
130 * - Support is for non-mip-mapped and non-array surface types only.
132 * And then later, on p327:
134 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
137 * From the Skylake documentation, it is made clear that X-tiling is no longer
140 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
144 intel_miptree_supports_ccs(struct brw_context
*brw
,
145 const struct intel_mipmap_tree
*mt
)
147 /* MCS support does not exist prior to Gen7 */
151 /* This function applies only to non-multisampled render targets. */
152 if (mt
->num_samples
> 1)
155 /* MCS is only supported for color buffers */
156 switch (_mesa_get_format_base_format(mt
->format
)) {
157 case GL_DEPTH_COMPONENT
:
158 case GL_DEPTH_STENCIL
:
159 case GL_STENCIL_INDEX
:
163 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
166 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
167 const bool arrayed
= mt
->physical_depth0
!= 1;
170 /* Multisample surfaces with the CMS layout are not layered surfaces,
171 * yet still have physical_depth0 > 1. Assert that we don't
172 * accidentally reject a multisampled surface here. We should have
173 * rejected it earlier by explicitly checking the sample count.
175 assert(mt
->num_samples
<= 1);
178 /* Handle the hardware restrictions...
180 * All GENs have the following restriction: "MCS buffer for non-MSRT is
181 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
183 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
184 * Non-MultiSampler Render Target Restrictions) Support is for
185 * non-mip-mapped and non-array surface types only.
187 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
188 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
189 * surfaces are supported with MCS buffer layout with these alignments in
190 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
192 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
193 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
194 * surfaces are supported with MCS buffer layout with these alignments in
195 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
197 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
200 /* There's no point in using an MCS buffer if the surface isn't in a
203 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
208 const enum isl_format isl_format
=
209 brw_isl_format_for_mesa_format(linear_format
);
210 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
216 intel_tiling_supports_hiz(const struct brw_context
*brw
, unsigned tiling
)
221 return tiling
== I915_TILING_Y
;
225 intel_miptree_supports_hiz(struct brw_context
*brw
,
226 struct intel_mipmap_tree
*mt
)
231 switch (mt
->format
) {
232 case MESA_FORMAT_Z_FLOAT32
:
233 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
234 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
235 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
236 case MESA_FORMAT_Z_UNORM16
:
244 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
245 const struct intel_mipmap_tree
*mt
)
247 /* For now compression is only enabled for integer formats even though
248 * there exist supported floating point formats also. This is a heuristic
249 * decision based on current public benchmarks. In none of the cases these
250 * formats provided any improvement but a few cases were seen to regress.
251 * Hence these are left to to be enabled in the future when they are known
254 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
257 if (!intel_miptree_supports_ccs(brw
, mt
))
260 /* Fast clear can be also used to clear srgb surfaces by using equivalent
261 * linear format. This trick, however, can't be extended to be used with
262 * lossless compression and therefore a check is needed to see if the format
265 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
269 * Determine depth format corresponding to a depth+stencil format,
270 * for separate stencil.
273 intel_depth_format_for_depthstencil_format(mesa_format format
) {
275 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
276 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
277 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
278 return MESA_FORMAT_Z_FLOAT32
;
285 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
286 unsigned depth0
, struct intel_mipmap_level
*table
)
288 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
290 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
292 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
293 if (!table
[level
].slice
)
300 for (unsigned level
= first_level
; level
<= last_level
; level
++)
301 free(table
[level
].slice
);
307 * @param for_bo Indicates that the caller is
308 * intel_miptree_create_for_bo(). If true, then do not create
311 static struct intel_mipmap_tree
*
312 intel_miptree_create_layout(struct brw_context
*brw
,
321 uint32_t layout_flags
)
323 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
327 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
328 _mesa_enum_to_string(target
),
329 _mesa_get_format_name(format
),
330 first_level
, last_level
, depth0
, mt
);
332 if (target
== GL_TEXTURE_1D_ARRAY
)
333 assert(height0
== 1);
337 mt
->first_level
= first_level
;
338 mt
->last_level
= last_level
;
339 mt
->logical_width0
= width0
;
340 mt
->logical_height0
= height0
;
341 mt
->logical_depth0
= depth0
;
342 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
343 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
344 mt
->supports_fast_clear
= false;
345 mt
->aux_state
= NULL
;
346 mt
->cpp
= _mesa_get_format_bytes(format
);
347 mt
->num_samples
= num_samples
;
348 mt
->compressed
= _mesa_is_format_compressed(format
);
349 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
352 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
353 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
355 int depth_multiply
= 1;
356 if (num_samples
> 1) {
357 /* Adjust width/height/depth for MSAA */
358 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
359 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
360 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
361 * "If the surface is multisampled and it is a depth or stencil
362 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
363 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
366 * +----------------------------------------------------------------+
367 * | Num Multisamples | W_l = | H_l = |
368 * +----------------------------------------------------------------+
369 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
370 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
371 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
372 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
373 * +----------------------------------------------------------------+
376 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
377 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
378 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
380 * Another more complicated explanation for these adjustments comes
381 * from the Sandybridge PRM, volume 4, part 1, page 31:
383 * "Any of the other messages (sample*, LOD, load4) used with a
384 * (4x) multisampled surface will in-effect sample a surface with
385 * double the height and width as that indicated in the surface
386 * state. Each pixel position on the original-sized surface is
387 * replaced with a 2x2 of samples with the following arrangement:
392 * Thus, when sampling from a multisampled texture, it behaves as
393 * though the layout in memory for (x,y,sample) is:
395 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
396 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
398 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
399 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
401 * However, the actual layout of multisampled data in memory is:
403 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
404 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
406 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
407 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
409 * This pattern repeats for each 2x2 pixel block.
411 * As a result, when calculating the size of our 4-sample buffer for
412 * an odd width or height, we have to align before scaling up because
413 * sample 3 is in that bottom right 2x2 block.
415 switch (num_samples
) {
417 assert(brw
->gen
>= 8);
418 width0
= ALIGN(width0
, 2) * 2;
419 height0
= ALIGN(height0
, 2);
422 width0
= ALIGN(width0
, 2) * 2;
423 height0
= ALIGN(height0
, 2) * 2;
426 width0
= ALIGN(width0
, 2) * 4;
427 height0
= ALIGN(height0
, 2) * 2;
430 width0
= ALIGN(width0
, 2) * 4;
431 height0
= ALIGN(height0
, 2) * 4;
434 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
437 unreachable("not reached");
440 /* Non-interleaved */
441 depth_multiply
= num_samples
;
442 depth0
*= depth_multiply
;
446 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
452 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
453 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
454 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
455 * used on Gen8 to make it pick a qpitch value which doesn't include space
456 * for the mipmaps. On Gen9 this is not necessary because it will
457 * automatically pick a packed qpitch value whenever mt->first_level ==
459 * TODO: can we use it elsewhere?
460 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
463 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
465 switch (mt
->msaa_layout
) {
466 case INTEL_MSAA_LAYOUT_NONE
:
467 case INTEL_MSAA_LAYOUT_IMS
:
468 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
470 case INTEL_MSAA_LAYOUT_UMS
:
471 case INTEL_MSAA_LAYOUT_CMS
:
472 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
477 if (target
== GL_TEXTURE_CUBE_MAP
)
478 assert(depth0
== 6 * depth_multiply
);
480 mt
->physical_width0
= width0
;
481 mt
->physical_height0
= height0
;
482 mt
->physical_depth0
= depth0
;
484 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
485 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
486 (brw
->must_use_separate_stencil
||
487 (brw
->has_separate_stencil
&& intel_miptree_supports_hiz(brw
, mt
)))) {
488 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
490 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
493 mt
->stencil_mt
= intel_miptree_create(brw
,
504 if (!mt
->stencil_mt
) {
505 intel_miptree_release(&mt
);
508 mt
->stencil_mt
->r8stencil_needs_update
= true;
510 /* Fix up the Z miptree format for how we're splitting out separate
511 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
513 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
516 if (format
== mt
->format
) {
517 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
518 _mesa_get_format_name(mt
->format
));
522 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
523 mt
->array_layout
= GEN6_HIZ_STENCIL
;
526 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
527 * multisampled or have an AUX buffer attached to it.
529 * GEN | MSRT | AUX_CCS_* or AUX_MCS
530 * -------------------------------------------
531 * 9 | HALIGN_16 | HALIGN_16
532 * 8 | HALIGN_ANY | HALIGN_16
536 if (intel_miptree_supports_ccs(brw
, mt
)) {
537 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
538 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
539 } else if (brw
->gen
>= 9 && num_samples
> 1) {
540 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
542 const UNUSED
bool is_lossless_compressed_aux
=
543 brw
->gen
>= 9 && num_samples
== 1 &&
544 mt
->format
== MESA_FORMAT_R_UINT32
;
546 /* For now, nothing else has this requirement */
547 assert(is_lossless_compressed_aux
||
548 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
551 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
552 intel_miptree_release(&mt
);
561 * Choose the aux usage for this miptree. This function must be called fairly
562 * late in the miptree create process after we have a tiling.
565 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
566 struct intel_mipmap_tree
*mt
)
568 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
570 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
571 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
572 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
573 intel_miptree_supports_ccs(brw
, mt
)) {
574 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
575 brw
->gen
>= 9 && !mt
->is_scanout
&&
576 intel_miptree_supports_ccs_e(brw
, mt
)) {
577 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
579 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
581 } else if (intel_tiling_supports_hiz(brw
, mt
->tiling
) &&
582 intel_miptree_supports_hiz(brw
, mt
)) {
583 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
586 /* We can do fast-clear on all auxiliary surface types that are
587 * allocated through the normal texture creation paths.
589 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
590 mt
->supports_fast_clear
= true;
595 * Choose an appropriate uncompressed format for a requested
596 * compressed format, if unsupported.
599 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
601 /* No need to lower ETC formats on these platforms,
602 * they are supported natively.
604 if (brw
->gen
>= 8 || brw
->is_baytrail
)
608 case MESA_FORMAT_ETC1_RGB8
:
609 return MESA_FORMAT_R8G8B8X8_UNORM
;
610 case MESA_FORMAT_ETC2_RGB8
:
611 return MESA_FORMAT_R8G8B8X8_UNORM
;
612 case MESA_FORMAT_ETC2_SRGB8
:
613 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
614 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
615 return MESA_FORMAT_B8G8R8A8_SRGB
;
616 case MESA_FORMAT_ETC2_RGBA8_EAC
:
617 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
618 return MESA_FORMAT_R8G8B8A8_UNORM
;
619 case MESA_FORMAT_ETC2_R11_EAC
:
620 return MESA_FORMAT_R_UNORM16
;
621 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
622 return MESA_FORMAT_R_SNORM16
;
623 case MESA_FORMAT_ETC2_RG11_EAC
:
624 return MESA_FORMAT_R16G16_UNORM
;
625 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
626 return MESA_FORMAT_R16G16_SNORM
;
628 /* Non ETC1 / ETC2 format */
633 /** \brief Assert that the level and layer are valid for the miptree. */
635 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
643 assert(level
>= mt
->first_level
);
644 assert(level
<= mt
->last_level
);
646 if (mt
->surf
.size
> 0)
647 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
648 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
649 mt
->surf
.phys_level0_sa
.array_len
));
651 assert(layer
< mt
->level
[level
].depth
);
654 static enum isl_aux_state
**
655 create_aux_state_map(struct intel_mipmap_tree
*mt
,
656 enum isl_aux_state initial
)
658 const uint32_t levels
= mt
->last_level
+ 1;
660 uint32_t total_slices
= 0;
661 for (uint32_t level
= 0; level
< levels
; level
++)
662 total_slices
+= mt
->level
[level
].depth
;
664 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
666 /* We're going to allocate a single chunk of data for both the per-level
667 * reference array and the arrays of aux_state. This makes cleanup
668 * significantly easier.
670 const size_t total_size
= per_level_array_size
+
671 total_slices
* sizeof(enum isl_aux_state
);
672 void *data
= malloc(total_size
);
676 enum isl_aux_state
**per_level_arr
= data
;
677 enum isl_aux_state
*s
= data
+ per_level_array_size
;
678 for (uint32_t level
= 0; level
< levels
; level
++) {
679 per_level_arr
[level
] = s
;
680 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
683 assert((void *)s
== data
+ total_size
);
685 return per_level_arr
;
689 free_aux_state_map(enum isl_aux_state
**state
)
694 static struct intel_mipmap_tree
*
695 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
696 unsigned first_level
, unsigned last_level
,
697 unsigned width0
, unsigned height0
, unsigned depth0
,
698 unsigned num_samples
, enum isl_tiling isl_tiling
,
699 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
702 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
706 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
712 if (target
== GL_TEXTURE_CUBE_MAP
||
713 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
714 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
716 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
718 _mesa_enum_to_string(target
),
719 _mesa_get_format_name(format
),
720 num_samples
, width0
, height0
, depth0
,
721 first_level
, last_level
, mt
);
723 struct isl_surf_init_info init_info
= {
724 .dim
= get_isl_surf_dim(target
),
725 .format
= translate_tex_format(brw
, format
, false),
728 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
729 .levels
= last_level
- first_level
+ 1,
730 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
731 .samples
= MAX2(num_samples
, 1),
732 .usage
= isl_usage_flags
,
733 .tiling_flags
= 1u << isl_tiling
736 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
739 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
742 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
744 isl_tiling_to_bufmgr_tiling(isl_tiling
),
745 mt
->surf
.row_pitch
, alloc_flags
);
752 mt
->first_level
= first_level
;
753 mt
->last_level
= last_level
;
757 mt
->aux_state
= NULL
;
762 intel_miptree_release(&mt
);
766 static struct intel_mipmap_tree
*
767 miptree_create(struct brw_context
*brw
,
776 uint32_t layout_flags
)
778 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
779 return make_surface(brw
, target
, format
, first_level
, last_level
,
780 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
781 ISL_SURF_USAGE_STENCIL_BIT
|
782 ISL_SURF_USAGE_TEXTURE_BIT
,
783 BO_ALLOC_FOR_RENDER
, NULL
);
785 struct intel_mipmap_tree
*mt
;
786 mesa_format tex_format
= format
;
787 mesa_format etc_format
= MESA_FORMAT_NONE
;
788 uint32_t alloc_flags
= 0;
790 format
= intel_lower_compressed_format(brw
, format
);
792 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
794 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
795 mt
= intel_miptree_create_layout(brw
, target
, format
,
796 first_level
, last_level
, width0
,
797 height0
, depth0
, num_samples
,
802 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
803 mt
->tiling
= I915_TILING_Y
;
805 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
806 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
808 mt
->etc_format
= etc_format
;
810 if (format
== MESA_FORMAT_S_UINT8
) {
811 /* Align to size of W tile, 64x64. */
812 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
813 ALIGN(mt
->total_width
, 64),
814 ALIGN(mt
->total_height
, 64),
815 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
818 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
819 mt
->total_width
, mt
->total_height
,
820 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
824 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
825 mt
->bo
->cache_coherent
= false;
827 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
828 intel_miptree_choose_aux_usage(brw
, mt
);
833 struct intel_mipmap_tree
*
834 intel_miptree_create(struct brw_context
*brw
,
843 uint32_t layout_flags
)
845 struct intel_mipmap_tree
*mt
= miptree_create(
847 first_level
, last_level
,
848 width0
, height0
, depth0
, num_samples
,
851 /* If the BO is too large to fit in the aperture, we need to use the
852 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
853 * handle Y-tiling, so we need to fall back to X.
855 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
856 mt
->tiling
== I915_TILING_Y
) {
857 const uint32_t alloc_flags
=
858 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
859 BO_ALLOC_FOR_RENDER
: 0;
860 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
861 mt
->total_width
, mt
->total_height
);
863 mt
->tiling
= I915_TILING_X
;
864 brw_bo_unreference(mt
->bo
);
865 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
866 mt
->total_width
, mt
->total_height
, mt
->cpp
,
867 mt
->tiling
, &mt
->pitch
, alloc_flags
);
873 intel_miptree_release(&mt
);
877 if (!intel_miptree_alloc_aux(brw
, mt
)) {
878 intel_miptree_release(&mt
);
885 struct intel_mipmap_tree
*
886 intel_miptree_create_for_bo(struct brw_context
*brw
,
894 uint32_t layout_flags
)
896 struct intel_mipmap_tree
*mt
;
897 uint32_t tiling
, swizzle
;
898 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
900 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
901 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
902 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
903 ISL_SURF_USAGE_STENCIL_BIT
|
904 ISL_SURF_USAGE_TEXTURE_BIT
,
905 BO_ALLOC_FOR_RENDER
, bo
);
909 assert(bo
->size
>= mt
->surf
.size
);
911 brw_bo_reference(bo
);
915 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
917 /* Nothing will be able to use this miptree with the BO if the offset isn't
920 if (tiling
!= I915_TILING_NONE
)
921 assert(offset
% 4096 == 0);
923 /* miptrees can't handle negative pitch. If you need flipping of images,
924 * that's outside of the scope of the mt.
928 /* The BO already has a tiling format and we shouldn't confuse the lower
929 * layers by making it try to find a tiling format again.
931 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
932 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
934 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
935 mt
= intel_miptree_create_layout(brw
, target
, format
,
937 width
, height
, depth
, 0,
942 brw_bo_reference(bo
);
948 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
949 intel_miptree_choose_aux_usage(brw
, mt
);
954 static struct intel_mipmap_tree
*
955 miptree_create_for_planar_image(struct brw_context
*brw
,
956 __DRIimage
*image
, GLenum target
)
958 struct intel_image_format
*f
= image
->planar_format
;
959 struct intel_mipmap_tree
*planar_mt
= NULL
;
961 for (int i
= 0; i
< f
->nplanes
; i
++) {
962 const int index
= f
->planes
[i
].buffer_index
;
963 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
964 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
965 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
966 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
968 /* Disable creation of the texture's aux buffers because the driver
969 * exposes no EGL API to manage them. That is, there is no API for
970 * resolving the aux buffer's content to the main buffer nor for
971 * invalidating the aux buffer's content.
973 struct intel_mipmap_tree
*mt
=
974 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
975 image
->offsets
[index
],
977 image
->strides
[index
],
978 MIPTREE_LAYOUT_DISABLE_AUX
);
983 mt
->total_width
= width
;
984 mt
->total_height
= height
;
989 planar_mt
->plane
[i
- 1] = mt
;
995 struct intel_mipmap_tree
*
996 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
997 __DRIimage
*image
, GLenum target
,
998 enum isl_colorspace colorspace
,
999 bool is_winsys_image
)
1001 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1002 assert(colorspace
== ISL_COLORSPACE_NONE
||
1003 colorspace
== ISL_COLORSPACE_YUV
);
1004 return miptree_create_for_planar_image(brw
, image
, target
);
1007 mesa_format format
= image
->format
;
1008 switch (colorspace
) {
1009 case ISL_COLORSPACE_NONE
:
1010 /* Keep the image format unmodified */
1013 case ISL_COLORSPACE_LINEAR
:
1014 format
=_mesa_get_srgb_format_linear(format
);
1017 case ISL_COLORSPACE_SRGB
:
1018 format
=_mesa_get_linear_format_srgb(format
);
1022 unreachable("Inalid colorspace for non-planar image");
1025 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1026 /* The texture storage paths in core Mesa detect if the driver does not
1027 * support the user-requested format, and then searches for a
1028 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1029 * do the fallbacks here for important formats.
1031 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1032 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1033 * the Chrome OS compositor consumes as dma_buf EGLImages.
1035 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1038 if (!brw
->ctx
.TextureFormatSupported
[format
])
1041 /* If this image comes in from a window system, we have different
1042 * requirements than if it comes in via an EGL import operation. Window
1043 * system images can use any form of auxiliary compression we wish because
1044 * they get "flushed" before being handed off to the window system and we
1045 * have the opportunity to do resolves. Window system buffers also may be
1046 * used for scanout so we need to flag that appropriately.
1048 const uint32_t mt_layout_flags
=
1049 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1051 /* Disable creation of the texture's aux buffers because the driver exposes
1052 * no EGL API to manage them. That is, there is no API for resolving the aux
1053 * buffer's content to the main buffer nor for invalidating the aux buffer's
1056 struct intel_mipmap_tree
*mt
=
1057 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1058 image
->offset
, image
->width
, image
->height
, 1,
1059 image
->pitch
, mt_layout_flags
);
1063 mt
->target
= target
;
1064 mt
->level
[0].level_x
= image
->tile_x
;
1065 mt
->level
[0].level_y
= image
->tile_y
;
1066 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1067 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1068 mt
->total_width
+= image
->tile_x
;
1069 mt
->total_height
+= image
->tile_y
;
1071 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1072 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1073 * trouble resolving back to destination image due to alignment issues.
1075 if (!brw
->has_surface_tile_offset
) {
1076 uint32_t draw_x
, draw_y
;
1077 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1079 if (draw_x
!= 0 || draw_y
!= 0) {
1080 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1081 intel_miptree_release(&mt
);
1086 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1087 intel_miptree_release(&mt
);
1095 * For a singlesample renderbuffer, this simply wraps the given BO with a
1098 * For a multisample renderbuffer, this wraps the window system's
1099 * (singlesample) BO with a singlesample miptree attached to the
1100 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1101 * that will contain the actual rendering (which is lazily resolved to
1102 * irb->singlesample_mt).
1105 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1106 struct intel_renderbuffer
*irb
,
1107 struct intel_mipmap_tree
*singlesample_mt
,
1108 uint32_t width
, uint32_t height
,
1111 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1112 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1113 mesa_format format
= rb
->Format
;
1114 int num_samples
= rb
->NumSamples
;
1116 /* Only the front and back buffers, which are color buffers, are allocated
1117 * through the image loader.
1119 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1120 _mesa_get_format_base_format(format
) == GL_RGBA
);
1122 assert(singlesample_mt
);
1124 if (num_samples
== 0) {
1125 intel_miptree_release(&irb
->mt
);
1126 irb
->mt
= singlesample_mt
;
1128 assert(!irb
->singlesample_mt
);
1130 intel_miptree_release(&irb
->singlesample_mt
);
1131 irb
->singlesample_mt
= singlesample_mt
;
1134 irb
->mt
->logical_width0
!= width
||
1135 irb
->mt
->logical_height0
!= height
) {
1136 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1141 if (!multisample_mt
)
1144 irb
->need_downsample
= false;
1145 intel_miptree_release(&irb
->mt
);
1146 irb
->mt
= multisample_mt
;
1152 intel_miptree_release(&irb
->mt
);
1156 struct intel_mipmap_tree
*
1157 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1161 uint32_t num_samples
)
1163 struct intel_mipmap_tree
*mt
;
1165 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1166 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1167 MIPTREE_LAYOUT_TILING_ANY
|
1168 MIPTREE_LAYOUT_FOR_SCANOUT
;
1170 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1171 width
, height
, depth
, num_samples
,
1179 intel_miptree_release(&mt
);
1184 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1185 struct intel_mipmap_tree
*src
)
1190 intel_miptree_release(dst
);
1194 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1201 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1203 if (aux_buf
== NULL
)
1206 brw_bo_unreference(aux_buf
->bo
);
1212 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1217 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1218 if (--(*mt
)->refcount
<= 0) {
1221 DBG("%s deleting %p\n", __func__
, *mt
);
1223 brw_bo_unreference((*mt
)->bo
);
1224 intel_miptree_release(&(*mt
)->stencil_mt
);
1225 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1226 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1227 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1228 free_aux_state_map((*mt
)->aux_state
);
1230 intel_miptree_release(&(*mt
)->plane
[0]);
1231 intel_miptree_release(&(*mt
)->plane
[1]);
1233 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1234 free((*mt
)->level
[i
].slice
);
1244 intel_get_image_dims(struct gl_texture_image
*image
,
1245 int *width
, int *height
, int *depth
)
1247 switch (image
->TexObject
->Target
) {
1248 case GL_TEXTURE_1D_ARRAY
:
1249 /* For a 1D Array texture the OpenGL API will treat the image height as
1250 * the number of array slices. For Intel hardware, we treat the 1D array
1251 * as a 2D Array with a height of 1. So, here we want to swap image
1254 assert(image
->Depth
== 1);
1255 *width
= image
->Width
;
1257 *depth
= image
->Height
;
1259 case GL_TEXTURE_CUBE_MAP
:
1260 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1261 * though we really have 6 slices.
1263 assert(image
->Depth
== 1);
1264 *width
= image
->Width
;
1265 *height
= image
->Height
;
1269 *width
= image
->Width
;
1270 *height
= image
->Height
;
1271 *depth
= image
->Depth
;
1277 * Can the image be pulled into a unified mipmap tree? This mirrors
1278 * the completeness test in a lot of ways.
1280 * Not sure whether I want to pass gl_texture_image here.
1283 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1284 struct gl_texture_image
*image
)
1286 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1287 GLuint level
= intelImage
->base
.Base
.Level
;
1288 int width
, height
, depth
;
1290 /* glTexImage* choose the texture object based on the target passed in, and
1291 * objects can't change targets over their lifetimes, so this should be
1294 assert(image
->TexObject
->Target
== mt
->target
);
1296 mesa_format mt_format
= mt
->format
;
1297 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1298 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1299 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1300 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1301 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1302 mt_format
= mt
->etc_format
;
1304 if (image
->TexFormat
!= mt_format
)
1307 intel_get_image_dims(image
, &width
, &height
, &depth
);
1309 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1312 if (mt
->surf
.size
> 0) {
1313 if (level
>= mt
->surf
.levels
)
1316 const unsigned level_depth
=
1317 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1318 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1319 mt
->surf
.logical_level0_px
.array_len
;
1321 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1322 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1323 depth
== level_depth
&&
1324 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1327 int level_depth
= mt
->level
[level
].depth
;
1328 if (mt
->num_samples
> 1) {
1329 switch (mt
->msaa_layout
) {
1330 case INTEL_MSAA_LAYOUT_NONE
:
1331 case INTEL_MSAA_LAYOUT_IMS
:
1333 case INTEL_MSAA_LAYOUT_UMS
:
1334 case INTEL_MSAA_LAYOUT_CMS
:
1335 level_depth
/= mt
->num_samples
;
1340 /* Test image dimensions against the base level image adjusted for
1341 * minification. This will also catch images not present in the
1342 * tree, changed targets, etc.
1344 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1345 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1346 depth
!= level_depth
) {
1350 if (image
->NumSamples
!= mt
->num_samples
)
1358 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1360 GLuint x
, GLuint y
, GLuint d
)
1362 mt
->level
[level
].depth
= d
;
1363 mt
->level
[level
].level_x
= x
;
1364 mt
->level
[level
].level_y
= y
;
1366 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1369 assert(mt
->level
[level
].slice
);
1371 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1372 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1377 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1378 GLuint level
, GLuint img
,
1381 if (img
== 0 && level
== 0)
1382 assert(x
== 0 && y
== 0);
1384 assert(img
< mt
->level
[level
].depth
);
1386 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1387 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1389 DBG("%s level %d img %d pos %d,%d\n",
1390 __func__
, level
, img
,
1391 mt
->level
[level
].slice
[img
].x_offset
,
1392 mt
->level
[level
].slice
[img
].y_offset
);
1396 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1397 GLuint level
, GLuint slice
,
1398 GLuint
*x
, GLuint
*y
)
1400 if (mt
->surf
.size
> 0) {
1401 uint32_t x_offset_sa
, y_offset_sa
;
1403 /* Given level is relative to level zero while the miptree may be
1404 * represent just a subset of all levels starting from 'first_level'.
1406 assert(level
>= mt
->first_level
);
1407 level
-= mt
->first_level
;
1409 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1410 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1411 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1412 &x_offset_sa
, &y_offset_sa
);
1419 assert(slice
< mt
->level
[level
].depth
);
1421 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1422 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1427 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1428 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1429 * and tile_h is set to 1.
1432 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1433 uint32_t *tile_w
, uint32_t *tile_h
)
1444 case I915_TILING_NONE
:
1449 unreachable("not reached");
1455 * This function computes masks that may be used to select the bits of the X
1456 * and Y coordinates that indicate the offset within a tile. If the BO is
1457 * untiled, the masks are set to 0.
1460 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1461 uint32_t *mask_x
, uint32_t *mask_y
)
1463 uint32_t tile_w_bytes
, tile_h
;
1465 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1467 *mask_x
= tile_w_bytes
/ cpp
- 1;
1468 *mask_y
= tile_h
- 1;
1472 * Compute the offset (in bytes) from the start of the BO to the given x
1473 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1474 * multiples of the tile size.
1477 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1478 uint32_t x
, uint32_t y
)
1481 uint32_t pitch
= mt
->pitch
;
1482 uint32_t tiling
= mt
->tiling
;
1486 unreachable("not reached");
1487 case I915_TILING_NONE
:
1488 return y
* pitch
+ x
* cpp
;
1490 assert((x
% (512 / cpp
)) == 0);
1491 assert((y
% 8) == 0);
1492 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1494 assert((x
% (128 / cpp
)) == 0);
1495 assert((y
% 32) == 0);
1496 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1501 * Rendering with tiled buffers requires that the base address of the buffer
1502 * be aligned to a page boundary. For renderbuffers, and sometimes with
1503 * textures, we may want the surface to point at a texture image level that
1504 * isn't at a page boundary.
1506 * This function returns an appropriately-aligned base offset
1507 * according to the tiling restrictions, plus any required x/y offset
1511 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1512 GLuint level
, GLuint slice
,
1517 uint32_t mask_x
, mask_y
;
1519 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1520 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1522 *tile_x
= x
& mask_x
;
1523 *tile_y
= y
& mask_y
;
1525 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1529 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1530 struct intel_mipmap_tree
*src_mt
,
1531 unsigned src_level
, unsigned src_layer
,
1532 struct intel_mipmap_tree
*dst_mt
,
1533 unsigned dst_level
, unsigned dst_layer
,
1534 unsigned width
, unsigned height
)
1537 ptrdiff_t src_stride
, dst_stride
;
1538 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1539 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1541 intel_miptree_map(brw
, src_mt
,
1542 src_level
, src_layer
,
1545 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1548 intel_miptree_map(brw
, dst_mt
,
1549 dst_level
, dst_layer
,
1552 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1556 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1557 _mesa_get_format_name(src_mt
->format
),
1558 src_mt
, src
, src_stride
,
1559 _mesa_get_format_name(dst_mt
->format
),
1560 dst_mt
, dst
, dst_stride
,
1563 int row_size
= cpp
* width
;
1564 if (src_stride
== row_size
&&
1565 dst_stride
== row_size
) {
1566 memcpy(dst
, src
, row_size
* height
);
1568 for (int i
= 0; i
< height
; i
++) {
1569 memcpy(dst
, src
, row_size
);
1575 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1576 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1578 /* Don't forget to copy the stencil data over, too. We could have skipped
1579 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1580 * shuffling the two data sources in/out of temporary storage instead of
1581 * the direct mapping we get this way.
1583 if (dst_mt
->stencil_mt
) {
1584 assert(src_mt
->stencil_mt
);
1585 intel_miptree_copy_slice_sw(brw
,
1586 src_mt
->stencil_mt
, src_level
, src_layer
,
1587 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1593 intel_miptree_copy_slice(struct brw_context
*brw
,
1594 struct intel_mipmap_tree
*src_mt
,
1595 unsigned src_level
, unsigned src_layer
,
1596 struct intel_mipmap_tree
*dst_mt
,
1597 unsigned dst_level
, unsigned dst_layer
)
1600 mesa_format format
= src_mt
->format
;
1601 uint32_t width
, height
;
1603 if (src_mt
->surf
.size
> 0) {
1604 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1605 src_level
- src_mt
->first_level
);
1606 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1607 src_level
- src_mt
->first_level
);
1609 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1610 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1611 src_level
- src_mt
->first_level
));
1613 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1615 width
= minify(src_mt
->physical_width0
,
1616 src_level
- src_mt
->first_level
);
1617 height
= minify(src_mt
->physical_height0
,
1618 src_level
- src_mt
->first_level
);
1619 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1622 assert(src_mt
->format
== dst_mt
->format
);
1624 if (dst_mt
->compressed
) {
1626 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1627 height
= ALIGN_NPOT(height
, j
) / j
;
1628 width
= ALIGN_NPOT(width
, i
) / i
;
1631 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1632 * below won't apply since we can't do the depth's Y tiling or the
1633 * stencil's W tiling in the blitter.
1635 if (src_mt
->stencil_mt
) {
1636 intel_miptree_copy_slice_sw(brw
,
1637 src_mt
, src_level
, src_layer
,
1638 dst_mt
, dst_level
, dst_layer
,
1643 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1644 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1646 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1649 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1650 _mesa_get_format_name(src_mt
->format
),
1651 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1652 _mesa_get_format_name(dst_mt
->format
),
1653 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1656 if (!intel_miptree_blit(brw
,
1657 src_mt
, src_level
, src_layer
, 0, 0, false,
1658 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1659 width
, height
, GL_COPY
)) {
1660 perf_debug("miptree validate blit for %s failed\n",
1661 _mesa_get_format_name(format
));
1663 intel_miptree_copy_slice_sw(brw
,
1664 src_mt
, src_level
, src_layer
,
1665 dst_mt
, dst_level
, dst_layer
,
1671 * Copies the image's current data to the given miptree, and associates that
1672 * miptree with the image.
1674 * If \c invalidate is true, then the actual image data does not need to be
1675 * copied, but the image still needs to be associated to the new miptree (this
1676 * is set to true if we're about to clear the image).
1679 intel_miptree_copy_teximage(struct brw_context
*brw
,
1680 struct intel_texture_image
*intelImage
,
1681 struct intel_mipmap_tree
*dst_mt
,
1684 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1685 struct intel_texture_object
*intel_obj
=
1686 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1687 int level
= intelImage
->base
.Base
.Level
;
1688 const unsigned face
= intelImage
->base
.Base
.Face
;
1689 unsigned start_layer
, end_layer
;
1691 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1693 assert(intelImage
->base
.Base
.Height
);
1695 end_layer
= intelImage
->base
.Base
.Height
- 1;
1696 } else if (face
> 0) {
1700 assert(intelImage
->base
.Base
.Depth
);
1702 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1706 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1707 intel_miptree_copy_slice(brw
,
1713 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1714 intel_obj
->needs_validate
= true;
1718 intel_miptree_init_mcs(struct brw_context
*brw
,
1719 struct intel_mipmap_tree
*mt
,
1722 assert(mt
->mcs_buf
!= NULL
);
1724 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1726 * When MCS buffer is enabled and bound to MSRT, it is required that it
1727 * is cleared prior to any rendering.
1729 * Since we don't use the MCS buffer for any purpose other than rendering,
1730 * it makes sense to just clear it immediately upon allocation.
1732 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1734 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1735 if (unlikely(map
== NULL
)) {
1736 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1737 brw_bo_unreference(mt
->mcs_buf
->bo
);
1742 memset(data
, init_value
, mt
->mcs_buf
->size
);
1743 brw_bo_unmap(mt
->mcs_buf
->bo
);
1746 static struct intel_miptree_aux_buffer
*
1747 intel_alloc_aux_buffer(struct brw_context
*brw
,
1749 const struct isl_surf
*aux_surf
,
1750 uint32_t alloc_flags
,
1751 struct intel_mipmap_tree
*mt
)
1753 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1757 buf
->size
= aux_surf
->size
;
1758 buf
->pitch
= aux_surf
->row_pitch
;
1759 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1761 /* ISL has stricter set of alignment rules then the drm allocator.
1762 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1763 * trying to recalculate based on different format block sizes.
1765 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1766 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1772 buf
->surf
= *aux_surf
;
1778 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1779 struct intel_mipmap_tree
*mt
,
1782 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1783 assert(mt
->mcs_buf
== NULL
);
1784 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1786 /* Multisampled miptrees are only supported for single level. */
1787 assert(mt
->first_level
== 0);
1788 enum isl_aux_state
**aux_state
=
1789 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1793 struct isl_surf temp_main_surf
;
1794 struct isl_surf temp_mcs_surf
;
1796 /* Create first an ISL presentation for the main color surface and let ISL
1797 * calculate equivalent MCS surface against it.
1799 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1800 MAYBE_UNUSED
bool ok
=
1801 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1804 /* Buffer needs to be initialised requiring the buffer to be immediately
1805 * mapped to cpu space for writing. Therefore do not use the gpu access
1806 * flag which can cause an unnecessary delay if the backing pages happened
1807 * to be just used by the GPU.
1809 const uint32_t alloc_flags
= 0;
1810 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1811 &temp_mcs_surf
, alloc_flags
, mt
);
1817 mt
->aux_state
= aux_state
;
1819 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1825 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1826 struct intel_mipmap_tree
*mt
)
1828 assert(mt
->mcs_buf
== NULL
);
1829 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1830 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1832 struct isl_surf temp_main_surf
;
1833 struct isl_surf temp_ccs_surf
;
1835 /* Create first an ISL presentation for the main color surface and let ISL
1836 * calculate equivalent CCS surface against it.
1838 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1839 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1842 assert(temp_ccs_surf
.size
&&
1843 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1845 enum isl_aux_state
**aux_state
=
1846 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1850 /* In case of compression mcs buffer needs to be initialised requiring the
1851 * buffer to be immediately mapped to cpu space for writing. Therefore do
1852 * not use the gpu access flag which can cause an unnecessary delay if the
1853 * backing pages happened to be just used by the GPU.
1855 const uint32_t alloc_flags
=
1856 mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
? 0 : BO_ALLOC_FOR_RENDER
;
1857 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1858 &temp_ccs_surf
, alloc_flags
, mt
);
1864 mt
->aux_state
= aux_state
;
1866 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1867 * used for lossless compression which requires similar initialisation
1868 * as multi-sample compression.
1870 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1871 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1872 * resolve. Initialize it accordingly in case the first renderer is
1873 * cpu (or other none compression aware party).
1875 * This is also explicitly stated in the spec (MCS Buffer for Render
1877 * "If Software wants to enable Color Compression without Fast clear,
1878 * Software needs to initialize MCS with zeros."
1880 intel_miptree_init_mcs(brw
, mt
, 0);
1887 * Helper for intel_miptree_alloc_hiz() that sets
1888 * \c mt->level[level].has_hiz. Return true if and only if
1889 * \c has_hiz was set.
1892 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1893 struct intel_mipmap_tree
*mt
,
1896 assert(mt
->hiz_buf
);
1898 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1899 uint32_t width
= minify(mt
->physical_width0
, level
);
1900 uint32_t height
= minify(mt
->physical_height0
, level
);
1902 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1903 * and the height is 4 aligned. This allows our HiZ support
1904 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1905 * we can grow the width & height to allow the HiZ op to
1906 * force the proper size alignments.
1908 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1909 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1914 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1915 mt
->level
[level
].has_hiz
= true;
1920 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1921 struct intel_mipmap_tree
*mt
)
1923 assert(mt
->hiz_buf
== NULL
);
1924 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1926 enum isl_aux_state
**aux_state
=
1927 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1931 struct isl_surf temp_main_surf
;
1932 struct isl_surf temp_hiz_surf
;
1934 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1935 MAYBE_UNUSED
bool ok
=
1936 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1939 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1940 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1941 &temp_hiz_surf
, alloc_flags
, mt
);
1948 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1949 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1951 mt
->aux_state
= aux_state
;
1958 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1960 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1961 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1962 * compress clear color so we wait until an actual fast-clear to allocate it.
1965 intel_miptree_alloc_aux(struct brw_context
*brw
,
1966 struct intel_mipmap_tree
*mt
)
1968 switch (mt
->aux_usage
) {
1969 case ISL_AUX_USAGE_NONE
:
1972 case ISL_AUX_USAGE_HIZ
:
1973 assert(!_mesa_is_format_color_format(mt
->format
));
1974 if (!intel_miptree_alloc_hiz(brw
, mt
))
1978 case ISL_AUX_USAGE_MCS
:
1979 assert(_mesa_is_format_color_format(mt
->format
));
1980 assert(mt
->num_samples
> 1);
1981 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->num_samples
))
1985 case ISL_AUX_USAGE_CCS_D
:
1986 /* Since CCS_D can only compress clear color so we wait until an actual
1987 * fast-clear to allocate it.
1991 case ISL_AUX_USAGE_CCS_E
:
1992 assert(_mesa_is_format_color_format(mt
->format
));
1993 assert(mt
->num_samples
<= 1);
1994 if (!intel_miptree_alloc_ccs(brw
, mt
))
1999 unreachable("Invalid aux usage");
2004 * Can the miptree sample using the hiz buffer?
2007 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2008 struct intel_mipmap_tree
*mt
)
2010 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2011 * so keep things conservative for now and never enable it unless we're SKL+.
2021 /* It seems the hardware won't fallback to the depth buffer if some of the
2022 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2023 * of the texture to be HiZ enabled.
2025 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2026 if (!intel_miptree_level_has_hiz(mt
, level
))
2030 /* If compressed multisampling is enabled, then we use it for the auxiliary
2033 * From the BDW PRM (Volume 2d: Command Reference: Structures
2034 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2036 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2037 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2039 * There is no such blurb for 1D textures, but there is sufficient evidence
2040 * that this is broken on SKL+.
2042 return (mt
->num_samples
<= 1 &&
2043 mt
->target
!= GL_TEXTURE_3D
&&
2044 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2048 * Does the miptree slice have hiz enabled?
2051 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2053 intel_miptree_check_level_layer(mt
, level
, 0);
2054 return mt
->level
[level
].has_hiz
;
2058 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2059 unsigned start_level
, unsigned num_levels
,
2060 unsigned start_layer
, unsigned num_layers
)
2062 assert(_mesa_is_format_color_format(mt
->format
));
2067 /* Clamp the level range to fit the miptree */
2068 assert(start_level
+ num_levels
>= start_level
);
2069 const uint32_t last_level
=
2070 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2071 start_level
= MAX2(mt
->first_level
, start_level
);
2072 num_levels
= last_level
- start_level
+ 1;
2074 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2075 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2076 for (unsigned a
= 0; a
< level_layers
; a
++) {
2077 enum isl_aux_state aux_state
=
2078 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2079 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2080 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2089 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2090 const struct intel_mipmap_tree
*mt
,
2091 unsigned level
, unsigned layer
)
2097 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2098 assert(brw
->gen
>= 8 ||
2099 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2101 /* Compression of arrayed msaa surfaces is supported. */
2102 if (mt
->num_samples
> 1)
2105 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2106 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2112 static enum blorp_fast_clear_op
2113 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2114 bool ccs_supported
, bool fast_clear_supported
)
2116 assert(ccs_supported
== fast_clear_supported
);
2118 switch (aux_state
) {
2119 case ISL_AUX_STATE_CLEAR
:
2120 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2122 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2124 return BLORP_FAST_CLEAR_OP_NONE
;
2126 case ISL_AUX_STATE_PASS_THROUGH
:
2127 return BLORP_FAST_CLEAR_OP_NONE
;
2129 case ISL_AUX_STATE_RESOLVED
:
2130 case ISL_AUX_STATE_AUX_INVALID
:
2131 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2135 unreachable("Invalid aux state for CCS_D");
2138 static enum blorp_fast_clear_op
2139 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2140 bool ccs_supported
, bool fast_clear_supported
)
2142 switch (aux_state
) {
2143 case ISL_AUX_STATE_CLEAR
:
2144 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2146 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2147 else if (!fast_clear_supported
)
2148 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2150 return BLORP_FAST_CLEAR_OP_NONE
;
2152 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2154 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2156 return BLORP_FAST_CLEAR_OP_NONE
;
2158 case ISL_AUX_STATE_PASS_THROUGH
:
2159 return BLORP_FAST_CLEAR_OP_NONE
;
2161 case ISL_AUX_STATE_RESOLVED
:
2162 case ISL_AUX_STATE_AUX_INVALID
:
2166 unreachable("Invalid aux state for CCS_E");
2170 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2171 struct intel_mipmap_tree
*mt
,
2172 uint32_t level
, uint32_t layer
,
2174 bool fast_clear_supported
)
2176 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2178 enum blorp_fast_clear_op resolve_op
;
2179 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2180 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2181 fast_clear_supported
);
2183 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2184 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2185 fast_clear_supported
);
2188 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2189 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2190 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2192 switch (resolve_op
) {
2193 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2194 /* The CCS full resolve operation destroys the CCS and sets it to the
2195 * pass-through state. (You can also think of this as being both a
2196 * resolve and an ambiguate in one operation.)
2198 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2199 ISL_AUX_STATE_PASS_THROUGH
);
2202 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2203 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2204 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2208 unreachable("Invalid resolve op");
2214 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2215 struct intel_mipmap_tree
*mt
,
2216 uint32_t level
, uint32_t layer
,
2217 bool written_with_ccs
)
2219 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2221 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2222 switch (aux_state
) {
2223 case ISL_AUX_STATE_CLEAR
:
2224 assert(written_with_ccs
);
2225 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2226 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2229 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2230 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2231 assert(written_with_ccs
);
2232 break; /* Nothing to do */
2234 case ISL_AUX_STATE_PASS_THROUGH
:
2235 if (written_with_ccs
) {
2236 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2237 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2243 case ISL_AUX_STATE_RESOLVED
:
2244 case ISL_AUX_STATE_AUX_INVALID
:
2245 unreachable("Invalid aux state for CCS_E");
2248 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2249 /* CCS_D is a bit simpler */
2250 switch (aux_state
) {
2251 case ISL_AUX_STATE_CLEAR
:
2252 assert(written_with_ccs
);
2253 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2254 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2257 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2258 assert(written_with_ccs
);
2259 break; /* Nothing to do */
2261 case ISL_AUX_STATE_PASS_THROUGH
:
2265 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2266 case ISL_AUX_STATE_RESOLVED
:
2267 case ISL_AUX_STATE_AUX_INVALID
:
2268 unreachable("Invalid aux state for CCS_D");
2274 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2275 struct intel_mipmap_tree
*mt
,
2276 uint32_t level
, uint32_t layer
,
2277 bool written_with_aux
)
2279 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2280 case ISL_AUX_STATE_CLEAR
:
2281 assert(written_with_aux
);
2282 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2283 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2286 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2287 assert(written_with_aux
);
2288 break; /* Nothing to do */
2290 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2291 case ISL_AUX_STATE_RESOLVED
:
2292 case ISL_AUX_STATE_PASS_THROUGH
:
2293 case ISL_AUX_STATE_AUX_INVALID
:
2294 unreachable("Invalid aux state for MCS");
2299 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2300 struct intel_mipmap_tree
*mt
,
2301 uint32_t level
, uint32_t layer
,
2302 bool hiz_supported
, bool fast_clear_supported
)
2304 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2305 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2306 case ISL_AUX_STATE_CLEAR
:
2307 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2308 if (!hiz_supported
|| !fast_clear_supported
)
2309 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2312 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2314 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2317 case ISL_AUX_STATE_PASS_THROUGH
:
2318 case ISL_AUX_STATE_RESOLVED
:
2321 case ISL_AUX_STATE_AUX_INVALID
:
2323 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2327 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2328 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2331 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2332 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2333 ISL_AUX_STATE_RESOLVED
);
2336 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2337 /* The HiZ resolve operation is actually an ambiguate */
2338 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2339 ISL_AUX_STATE_PASS_THROUGH
);
2343 unreachable("Invalid HiZ op");
2349 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2350 struct intel_mipmap_tree
*mt
,
2351 uint32_t level
, uint32_t layer
,
2352 bool written_with_hiz
)
2354 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2355 case ISL_AUX_STATE_CLEAR
:
2356 assert(written_with_hiz
);
2357 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2358 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2361 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2362 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2363 assert(written_with_hiz
);
2364 break; /* Nothing to do */
2366 case ISL_AUX_STATE_RESOLVED
:
2367 if (written_with_hiz
) {
2368 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2369 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2371 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2372 ISL_AUX_STATE_AUX_INVALID
);
2376 case ISL_AUX_STATE_PASS_THROUGH
:
2377 if (written_with_hiz
) {
2378 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2379 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2383 case ISL_AUX_STATE_AUX_INVALID
:
2384 assert(!written_with_hiz
);
2389 static inline uint32_t
2390 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2391 uint32_t start_level
, uint32_t num_levels
)
2393 assert(start_level
>= mt
->first_level
);
2394 assert(start_level
<= mt
->last_level
);
2396 if (num_levels
== INTEL_REMAINING_LAYERS
)
2397 num_levels
= mt
->last_level
- start_level
+ 1;
2398 /* Check for overflow */
2399 assert(start_level
+ num_levels
>= start_level
);
2400 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2405 static inline uint32_t
2406 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2407 uint32_t start_layer
, uint32_t num_layers
)
2409 assert(level
<= mt
->last_level
);
2410 uint32_t total_num_layers
;
2412 if (mt
->surf
.size
> 0)
2413 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2414 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2415 mt
->surf
.phys_level0_sa
.array_len
;
2417 total_num_layers
= mt
->level
[level
].depth
;
2419 assert(start_layer
< total_num_layers
);
2420 if (num_layers
== INTEL_REMAINING_LAYERS
)
2421 num_layers
= total_num_layers
- start_layer
;
2422 /* Check for overflow */
2423 assert(start_layer
+ num_layers
>= start_layer
);
2424 assert(start_layer
+ num_layers
<= total_num_layers
);
2430 intel_miptree_prepare_access(struct brw_context
*brw
,
2431 struct intel_mipmap_tree
*mt
,
2432 uint32_t start_level
, uint32_t num_levels
,
2433 uint32_t start_layer
, uint32_t num_layers
,
2434 bool aux_supported
, bool fast_clear_supported
)
2436 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2438 if (_mesa_is_format_color_format(mt
->format
)) {
2442 if (mt
->num_samples
> 1) {
2443 /* Nothing to do for MSAA */
2444 assert(aux_supported
&& fast_clear_supported
);
2446 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2447 const uint32_t level
= start_level
+ l
;
2448 const uint32_t level_layers
=
2449 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2450 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2451 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2452 start_layer
+ a
, aux_supported
,
2453 fast_clear_supported
);
2457 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2458 /* Nothing to do for stencil */
2463 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2464 const uint32_t level
= start_level
+ l
;
2465 if (!intel_miptree_level_has_hiz(mt
, level
))
2468 const uint32_t level_layers
=
2469 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2470 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2471 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2473 fast_clear_supported
);
2480 intel_miptree_finish_write(struct brw_context
*brw
,
2481 struct intel_mipmap_tree
*mt
, uint32_t level
,
2482 uint32_t start_layer
, uint32_t num_layers
,
2483 bool written_with_aux
)
2485 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2487 if (_mesa_is_format_color_format(mt
->format
)) {
2491 if (mt
->num_samples
> 1) {
2492 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2493 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2497 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2498 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2502 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2503 /* Nothing to do for stencil */
2505 if (!intel_miptree_level_has_hiz(mt
, level
))
2508 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2509 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2516 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2517 uint32_t level
, uint32_t layer
)
2519 intel_miptree_check_level_layer(mt
, level
, layer
);
2521 if (_mesa_is_format_color_format(mt
->format
)) {
2522 assert(mt
->mcs_buf
!= NULL
);
2523 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2524 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2525 unreachable("Cannot get aux state for stencil");
2527 assert(intel_miptree_level_has_hiz(mt
, level
));
2530 return mt
->aux_state
[level
][layer
];
2534 intel_miptree_set_aux_state(struct brw_context
*brw
,
2535 struct intel_mipmap_tree
*mt
, uint32_t level
,
2536 uint32_t start_layer
, uint32_t num_layers
,
2537 enum isl_aux_state aux_state
)
2539 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2541 if (_mesa_is_format_color_format(mt
->format
)) {
2542 assert(mt
->mcs_buf
!= NULL
);
2543 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2544 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2545 unreachable("Cannot get aux state for stencil");
2547 assert(intel_miptree_level_has_hiz(mt
, level
));
2550 for (unsigned a
= 0; a
< num_layers
; a
++)
2551 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2554 /* On Gen9 color buffers may be compressed by the hardware (lossless
2555 * compression). There are, however, format restrictions and care needs to be
2556 * taken that the sampler engine is capable for re-interpreting a buffer with
2557 * format different the buffer was originally written with.
2559 * For example, SRGB formats are not compressible and the sampler engine isn't
2560 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2561 * color buffer needs to be resolved so that the sampling surface can be
2562 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2566 can_texture_with_ccs(struct brw_context
*brw
,
2567 struct intel_mipmap_tree
*mt
,
2568 mesa_format view_format
)
2570 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2573 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2574 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2576 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2577 isl_mt_format
, isl_view_format
)) {
2578 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2579 _mesa_get_format_name(view_format
),
2580 _mesa_get_format_name(mt
->format
));
2588 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2589 struct intel_mipmap_tree
*mt
,
2590 mesa_format view_format
,
2591 uint32_t start_level
, uint32_t num_levels
,
2592 uint32_t start_layer
, uint32_t num_layers
,
2593 bool *aux_supported_out
)
2595 bool aux_supported
, clear_supported
;
2596 if (_mesa_is_format_color_format(mt
->format
)) {
2597 if (mt
->num_samples
> 1) {
2598 aux_supported
= clear_supported
= true;
2600 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2602 /* Clear color is specified as ints or floats and the conversion is
2603 * done by the sampler. If we have a texture view, we would have to
2604 * perform the clear color conversion manually. Just disable clear
2607 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2609 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2610 aux_supported
= clear_supported
= false;
2612 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2615 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2616 start_layer
, num_layers
,
2617 aux_supported
, clear_supported
);
2618 if (aux_supported_out
)
2619 *aux_supported_out
= aux_supported
;
2623 intel_miptree_prepare_texture(struct brw_context
*brw
,
2624 struct intel_mipmap_tree
*mt
,
2625 mesa_format view_format
,
2626 bool *aux_supported_out
)
2628 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2629 0, INTEL_REMAINING_LEVELS
,
2630 0, INTEL_REMAINING_LAYERS
,
2635 intel_miptree_prepare_image(struct brw_context
*brw
,
2636 struct intel_mipmap_tree
*mt
)
2638 /* The data port doesn't understand any compression */
2639 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2640 0, INTEL_REMAINING_LAYERS
, false, false);
2644 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2645 struct intel_mipmap_tree
*mt
, uint32_t level
,
2646 uint32_t start_layer
, uint32_t num_layers
)
2648 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2649 start_layer
, num_layers
, NULL
);
2653 intel_miptree_prepare_render(struct brw_context
*brw
,
2654 struct intel_mipmap_tree
*mt
, uint32_t level
,
2655 uint32_t start_layer
, uint32_t layer_count
,
2658 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2659 * the single-sampled color renderbuffers because the CCS buffer isn't
2660 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2661 * enabled because otherwise the surface state will be programmed with
2662 * the linear equivalent format anyway.
2664 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2665 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2667 /* Lossless compression is not supported for SRGB formats, it
2668 * should be impossible to get here with such surfaces.
2670 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2671 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2677 intel_miptree_finish_render(struct brw_context
*brw
,
2678 struct intel_mipmap_tree
*mt
, uint32_t level
,
2679 uint32_t start_layer
, uint32_t layer_count
)
2681 assert(_mesa_is_format_color_format(mt
->format
));
2682 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2683 mt
->mcs_buf
!= NULL
);
2687 intel_miptree_prepare_depth(struct brw_context
*brw
,
2688 struct intel_mipmap_tree
*mt
, uint32_t level
,
2689 uint32_t start_layer
, uint32_t layer_count
)
2691 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2692 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2696 intel_miptree_finish_depth(struct brw_context
*brw
,
2697 struct intel_mipmap_tree
*mt
, uint32_t level
,
2698 uint32_t start_layer
, uint32_t layer_count
,
2701 if (depth_written
) {
2702 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2703 mt
->hiz_buf
!= NULL
);
2708 * Make it possible to share the BO backing the given miptree with another
2709 * process or another miptree.
2711 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2712 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2713 * ensure that no MCS buffer gets allocated in the future.
2715 * HiZ is similarly unsafe with shared buffers.
2718 intel_miptree_make_shareable(struct brw_context
*brw
,
2719 struct intel_mipmap_tree
*mt
)
2721 /* MCS buffers are also used for multisample buffers, but we can't resolve
2722 * away a multisample MCS buffer because it's an integral part of how the
2723 * pixel data is stored. Fortunately this code path should never be
2724 * reached for multisample buffers.
2726 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2728 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2729 0, INTEL_REMAINING_LAYERS
, false, false);
2732 brw_bo_unreference(mt
->mcs_buf
->bo
);
2736 /* Any pending MCS/CCS operations are no longer needed. Trying to
2737 * execute any will likely crash due to the missing aux buffer. So let's
2738 * delete all pending ops.
2740 free(mt
->aux_state
);
2741 mt
->aux_state
= NULL
;
2745 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2748 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2749 mt
->level
[l
].has_hiz
= false;
2752 /* Any pending HiZ operations are no longer needed. Trying to execute
2753 * any will likely crash due to the missing aux buffer. So let's delete
2756 free(mt
->aux_state
);
2757 mt
->aux_state
= NULL
;
2760 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2765 * \brief Get pointer offset into stencil buffer.
2767 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2768 * must decode the tile's layout in software.
2771 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2773 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2775 * Even though the returned offset is always positive, the return type is
2777 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2778 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2781 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2783 uint32_t tile_size
= 4096;
2784 uint32_t tile_width
= 64;
2785 uint32_t tile_height
= 64;
2786 uint32_t row_size
= 64 * stride
;
2788 uint32_t tile_x
= x
/ tile_width
;
2789 uint32_t tile_y
= y
/ tile_height
;
2791 /* The byte's address relative to the tile's base addres. */
2792 uint32_t byte_x
= x
% tile_width
;
2793 uint32_t byte_y
= y
% tile_height
;
2795 uintptr_t u
= tile_y
* row_size
2796 + tile_x
* tile_size
2797 + 512 * (byte_x
/ 8)
2799 + 32 * ((byte_y
/ 4) % 2)
2800 + 16 * ((byte_x
/ 4) % 2)
2801 + 8 * ((byte_y
/ 2) % 2)
2802 + 4 * ((byte_x
/ 2) % 2)
2807 /* adjust for bit6 swizzling */
2808 if (((byte_x
/ 8) % 2) == 1) {
2809 if (((byte_y
/ 8) % 2) == 0) {
2821 intel_miptree_updownsample(struct brw_context
*brw
,
2822 struct intel_mipmap_tree
*src
,
2823 struct intel_mipmap_tree
*dst
)
2825 unsigned src_w
, src_h
, dst_w
, dst_h
;
2827 if (src
->surf
.size
> 0) {
2828 src_w
= src
->surf
.logical_level0_px
.width
;
2829 src_h
= src
->surf
.logical_level0_px
.height
;
2831 src_w
= src
->logical_width0
;
2832 src_h
= src
->logical_height0
;
2835 if (dst
->surf
.size
> 0) {
2836 dst_w
= dst
->surf
.logical_level0_px
.width
;
2837 dst_h
= dst
->surf
.logical_level0_px
.height
;
2839 dst_w
= dst
->logical_width0
;
2840 dst_h
= dst
->logical_height0
;
2843 brw_blorp_blit_miptrees(brw
,
2844 src
, 0 /* level */, 0 /* layer */,
2845 src
->format
, SWIZZLE_XYZW
,
2846 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2849 GL_NEAREST
, false, false /*mirror x, y*/,
2852 if (src
->stencil_mt
) {
2853 if (src
->stencil_mt
->surf
.size
> 0) {
2854 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2855 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2857 src_w
= src
->stencil_mt
->logical_width0
;
2858 src_h
= src
->stencil_mt
->logical_height0
;
2861 if (dst
->stencil_mt
->surf
.size
> 0) {
2862 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2863 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2865 dst_w
= dst
->stencil_mt
->logical_width0
;
2866 dst_h
= dst
->stencil_mt
->logical_height0
;
2869 brw_blorp_blit_miptrees(brw
,
2870 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2871 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2872 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2873 dst
->stencil_mt
->format
,
2876 GL_NEAREST
, false, false /*mirror x, y*/,
2877 false, false /* decode/encode srgb */);
2882 intel_update_r8stencil(struct brw_context
*brw
,
2883 struct intel_mipmap_tree
*mt
)
2885 assert(brw
->gen
>= 7);
2886 struct intel_mipmap_tree
*src
=
2887 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2888 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2891 if (!mt
->r8stencil_mt
) {
2892 const uint32_t r8stencil_flags
=
2893 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2894 MIPTREE_LAYOUT_DISABLE_AUX
;
2895 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2896 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2898 MESA_FORMAT_R_UINT8
,
2901 src
->logical_width0
,
2902 src
->logical_height0
,
2903 src
->logical_depth0
,
2906 assert(mt
->r8stencil_mt
);
2909 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2911 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2912 const unsigned depth
= src
->level
[level
].depth
;
2914 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2915 brw_blorp_copy_miptrees(brw
,
2919 minify(src
->logical_width0
, level
),
2920 minify(src
->logical_height0
, level
));
2924 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2925 src
->r8stencil_needs_update
= false;
2929 intel_miptree_map_raw(struct brw_context
*brw
,
2930 struct intel_mipmap_tree
*mt
,
2933 struct brw_bo
*bo
= mt
->bo
;
2935 if (brw_batch_references(&brw
->batch
, bo
))
2936 intel_batchbuffer_flush(brw
);
2938 return brw_bo_map(brw
, bo
, mode
);
2942 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2944 brw_bo_unmap(mt
->bo
);
2948 intel_miptree_map_gtt(struct brw_context
*brw
,
2949 struct intel_mipmap_tree
*mt
,
2950 struct intel_miptree_map
*map
,
2951 unsigned int level
, unsigned int slice
)
2953 unsigned int bw
, bh
;
2955 unsigned int image_x
, image_y
;
2956 intptr_t x
= map
->x
;
2957 intptr_t y
= map
->y
;
2959 /* For compressed formats, the stride is the number of bytes per
2960 * row of blocks. intel_miptree_get_image_offset() already does
2963 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2964 assert(y
% bh
== 0);
2965 assert(x
% bw
== 0);
2969 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2976 /* Note that in the case of cube maps, the caller must have passed the
2977 * slice number referencing the face.
2979 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2983 map
->stride
= mt
->pitch
;
2984 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2987 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2988 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2989 map
->x
, map
->y
, map
->w
, map
->h
,
2990 mt
, _mesa_get_format_name(mt
->format
),
2991 x
, y
, map
->ptr
, map
->stride
);
2995 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2997 intel_miptree_unmap_raw(mt
);
3001 intel_miptree_map_blit(struct brw_context
*brw
,
3002 struct intel_mipmap_tree
*mt
,
3003 struct intel_miptree_map
*map
,
3004 unsigned int level
, unsigned int slice
)
3006 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3007 /* first_level */ 0,
3011 MIPTREE_LAYOUT_TILING_NONE
);
3013 if (!map
->linear_mt
) {
3014 fprintf(stderr
, "Failed to allocate blit temporary\n");
3017 map
->stride
= map
->linear_mt
->pitch
;
3019 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3020 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3021 * invalidate is set, since we'll be writing the whole rectangle from our
3022 * temporary buffer back out.
3024 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3025 if (!intel_miptree_copy(brw
,
3026 mt
, level
, slice
, map
->x
, map
->y
,
3027 map
->linear_mt
, 0, 0, 0, 0,
3029 fprintf(stderr
, "Failed to blit\n");
3034 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3036 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3037 map
->x
, map
->y
, map
->w
, map
->h
,
3038 mt
, _mesa_get_format_name(mt
->format
),
3039 level
, slice
, map
->ptr
, map
->stride
);
3044 intel_miptree_release(&map
->linear_mt
);
3050 intel_miptree_unmap_blit(struct brw_context
*brw
,
3051 struct intel_mipmap_tree
*mt
,
3052 struct intel_miptree_map
*map
,
3056 struct gl_context
*ctx
= &brw
->ctx
;
3058 intel_miptree_unmap_raw(map
->linear_mt
);
3060 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3061 bool ok
= intel_miptree_copy(brw
,
3062 map
->linear_mt
, 0, 0, 0, 0,
3063 mt
, level
, slice
, map
->x
, map
->y
,
3065 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3068 intel_miptree_release(&map
->linear_mt
);
3072 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3074 #if defined(USE_SSE41)
3076 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3077 struct intel_mipmap_tree
*mt
,
3078 struct intel_miptree_map
*map
,
3079 unsigned int level
, unsigned int slice
)
3081 assert(map
->mode
& GL_MAP_READ_BIT
);
3082 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3084 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3085 map
->x
, map
->y
, map
->w
, map
->h
,
3086 mt
, _mesa_get_format_name(mt
->format
),
3087 level
, slice
, map
->ptr
, map
->stride
);
3089 /* Map the original image */
3092 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3096 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3102 src
+= image_y
* mt
->pitch
;
3103 src
+= image_x
* mt
->cpp
;
3105 /* Due to the pixel offsets for the particular image being mapped, our
3106 * src pointer may not be 16-byte aligned. However, if the pitch is
3107 * divisible by 16, then the amount by which it's misaligned will remain
3108 * consistent from row to row.
3110 assert((mt
->pitch
% 16) == 0);
3111 const int misalignment
= ((uintptr_t) src
) & 15;
3113 /* Create an untiled temporary buffer for the mapping. */
3114 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3116 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3118 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3119 /* Offset the destination so it has the same misalignment as src. */
3120 map
->ptr
= map
->buffer
+ misalignment
;
3122 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3124 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3125 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3126 void *src_ptr
= src
+ y
* mt
->pitch
;
3128 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3131 intel_miptree_unmap_raw(mt
);
3135 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3136 struct intel_mipmap_tree
*mt
,
3137 struct intel_miptree_map
*map
,
3141 _mesa_align_free(map
->buffer
);
3148 intel_miptree_map_s8(struct brw_context
*brw
,
3149 struct intel_mipmap_tree
*mt
,
3150 struct intel_miptree_map
*map
,
3151 unsigned int level
, unsigned int slice
)
3153 map
->stride
= map
->w
;
3154 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3158 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3159 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3160 * invalidate is set, since we'll be writing the whole rectangle from our
3161 * temporary buffer back out.
3163 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3164 /* ISL uses a stencil pitch value that is expected by hardware whereas
3165 * traditional miptree uses half of that. Below the value gets supplied
3166 * to intel_offset_S8() which expects the legacy interpretation.
3168 const unsigned pitch
= mt
->surf
.size
> 0 ?
3169 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3170 uint8_t *untiled_s8_map
= map
->ptr
;
3171 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3172 unsigned int image_x
, image_y
;
3174 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3176 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3177 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3178 ptrdiff_t offset
= intel_offset_S8(pitch
,
3179 x
+ image_x
+ map
->x
,
3180 y
+ image_y
+ map
->y
,
3181 brw
->has_swizzling
);
3182 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3186 intel_miptree_unmap_raw(mt
);
3188 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3189 map
->x
, map
->y
, map
->w
, map
->h
,
3190 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3192 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3193 map
->x
, map
->y
, map
->w
, map
->h
,
3194 mt
, map
->ptr
, map
->stride
);
3199 intel_miptree_unmap_s8(struct brw_context
*brw
,
3200 struct intel_mipmap_tree
*mt
,
3201 struct intel_miptree_map
*map
,
3205 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3206 /* ISL uses a stencil pitch value that is expected by hardware whereas
3207 * traditional miptree uses half of that. Below the value gets supplied
3208 * to intel_offset_S8() which expects the legacy interpretation.
3210 const unsigned pitch
= mt
->surf
.size
> 0 ?
3211 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3212 unsigned int image_x
, image_y
;
3213 uint8_t *untiled_s8_map
= map
->ptr
;
3214 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3216 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3218 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3219 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3220 ptrdiff_t offset
= intel_offset_S8(pitch
,
3221 image_x
+ x
+ map
->x
,
3222 image_y
+ y
+ map
->y
,
3223 brw
->has_swizzling
);
3224 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3228 intel_miptree_unmap_raw(mt
);
3235 intel_miptree_map_etc(struct brw_context
*brw
,
3236 struct intel_mipmap_tree
*mt
,
3237 struct intel_miptree_map
*map
,
3241 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3242 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3243 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3246 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3247 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3249 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3250 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3251 map
->w
, map
->h
, 1));
3252 map
->ptr
= map
->buffer
;
3256 intel_miptree_unmap_etc(struct brw_context
*brw
,
3257 struct intel_mipmap_tree
*mt
,
3258 struct intel_miptree_map
*map
,
3264 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3269 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3270 + image_y
* mt
->pitch
3271 + image_x
* mt
->cpp
;
3273 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3274 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3275 map
->ptr
, map
->stride
,
3278 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3279 map
->ptr
, map
->stride
,
3280 map
->w
, map
->h
, mt
->etc_format
);
3282 intel_miptree_unmap_raw(mt
);
3287 * Mapping function for packed depth/stencil miptrees backed by real separate
3288 * miptrees for depth and stencil.
3290 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3291 * separate from the depth buffer. Yet at the GL API level, we have to expose
3292 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3293 * be able to map that memory for texture storage and glReadPixels-type
3294 * operations. We give Mesa core that access by mallocing a temporary and
3295 * copying the data between the actual backing store and the temporary.
3298 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3299 struct intel_mipmap_tree
*mt
,
3300 struct intel_miptree_map
*map
,
3301 unsigned int level
, unsigned int slice
)
3303 struct intel_mipmap_tree
*z_mt
= mt
;
3304 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3305 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3306 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3308 map
->stride
= map
->w
* packed_bpp
;
3309 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3313 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3314 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3315 * invalidate is set, since we'll be writing the whole rectangle from our
3316 * temporary buffer back out.
3318 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3319 /* ISL uses a stencil pitch value that is expected by hardware whereas
3320 * traditional miptree uses half of that. Below the value gets supplied
3321 * to intel_offset_S8() which expects the legacy interpretation.
3323 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3324 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3325 uint32_t *packed_map
= map
->ptr
;
3326 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3327 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3328 unsigned int s_image_x
, s_image_y
;
3329 unsigned int z_image_x
, z_image_y
;
3331 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3332 &s_image_x
, &s_image_y
);
3333 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3334 &z_image_x
, &z_image_y
);
3336 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3337 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3338 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3339 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3342 brw
->has_swizzling
);
3343 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3345 (map_x
+ z_image_x
));
3346 uint8_t s
= s_map
[s_offset
];
3347 uint32_t z
= z_map
[z_offset
];
3349 if (map_z32f_x24s8
) {
3350 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3351 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3353 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3358 intel_miptree_unmap_raw(s_mt
);
3359 intel_miptree_unmap_raw(z_mt
);
3361 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3363 map
->x
, map
->y
, map
->w
, map
->h
,
3364 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3365 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3366 map
->ptr
, map
->stride
);
3368 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3369 map
->x
, map
->y
, map
->w
, map
->h
,
3370 mt
, map
->ptr
, map
->stride
);
3375 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3376 struct intel_mipmap_tree
*mt
,
3377 struct intel_miptree_map
*map
,
3381 struct intel_mipmap_tree
*z_mt
= mt
;
3382 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3383 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3385 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3386 /* ISL uses a stencil pitch value that is expected by hardware whereas
3387 * traditional miptree uses half of that. Below the value gets supplied
3388 * to intel_offset_S8() which expects the legacy interpretation.
3390 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3391 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3392 uint32_t *packed_map
= map
->ptr
;
3393 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3394 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3395 unsigned int s_image_x
, s_image_y
;
3396 unsigned int z_image_x
, z_image_y
;
3398 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3399 &s_image_x
, &s_image_y
);
3400 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3401 &z_image_x
, &z_image_y
);
3403 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3404 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3405 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3406 x
+ s_image_x
+ map
->x
,
3407 y
+ s_image_y
+ map
->y
,
3408 brw
->has_swizzling
);
3409 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3411 (x
+ z_image_x
+ map
->x
));
3413 if (map_z32f_x24s8
) {
3414 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3415 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3417 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3418 s_map
[s_offset
] = packed
>> 24;
3419 z_map
[z_offset
] = packed
;
3424 intel_miptree_unmap_raw(s_mt
);
3425 intel_miptree_unmap_raw(z_mt
);
3427 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3429 map
->x
, map
->y
, map
->w
, map
->h
,
3430 z_mt
, _mesa_get_format_name(z_mt
->format
),
3431 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3432 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3433 map
->ptr
, map
->stride
);
3440 * Create and attach a map to the miptree at (level, slice). Return the
3443 static struct intel_miptree_map
*
3444 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3453 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3458 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3459 mt
->level
[level
].slice
[slice
].map
= map
;
3471 * Release the map at (level, slice).
3474 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3478 struct intel_miptree_map
**map
;
3480 map
= &mt
->level
[level
].slice
[slice
].map
;
3486 can_blit_slice(struct intel_mipmap_tree
*mt
,
3487 unsigned int level
, unsigned int slice
)
3489 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3490 if (mt
->pitch
>= 32768)
3497 use_intel_mipree_map_blit(struct brw_context
*brw
,
3498 struct intel_mipmap_tree
*mt
,
3504 /* It's probably not worth swapping to the blit ring because of
3505 * all the overhead involved.
3507 !(mode
& GL_MAP_WRITE_BIT
) &&
3509 (mt
->tiling
== I915_TILING_X
||
3510 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3511 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3512 /* Fast copy blit on skl+ supports all tiling formats. */
3514 can_blit_slice(mt
, level
, slice
))
3517 if (mt
->tiling
!= I915_TILING_NONE
&&
3518 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3519 assert(can_blit_slice(mt
, level
, slice
));
3527 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3528 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3529 * arithmetic overflow.
3531 * If you call this function and use \a out_stride, then you're doing pointer
3532 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3533 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3534 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3535 * which usually have type uint32_t or GLuint.
3538 intel_miptree_map(struct brw_context
*brw
,
3539 struct intel_mipmap_tree
*mt
,
3548 ptrdiff_t *out_stride
)
3550 struct intel_miptree_map
*map
;
3552 assert(mt
->num_samples
<= 1);
3554 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3561 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3562 map
->mode
& GL_MAP_WRITE_BIT
);
3564 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3565 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3566 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3567 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3568 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3569 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3570 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3571 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3572 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3573 #if defined(USE_SSE41)
3574 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3575 !mt
->compressed
&& cpu_has_sse4_1
&&
3576 (mt
->pitch
% 16 == 0)) {
3577 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3580 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3583 *out_ptr
= map
->ptr
;
3584 *out_stride
= map
->stride
;
3586 if (map
->ptr
== NULL
)
3587 intel_miptree_release_map(mt
, level
, slice
);
3591 intel_miptree_unmap(struct brw_context
*brw
,
3592 struct intel_mipmap_tree
*mt
,
3596 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3598 assert(mt
->num_samples
<= 1);
3603 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3604 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3606 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3607 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3608 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3609 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3610 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3611 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3612 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3613 } else if (map
->linear_mt
) {
3614 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3615 #if defined(USE_SSE41)
3616 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3617 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3620 intel_miptree_unmap_gtt(mt
);
3623 intel_miptree_release_map(mt
, level
, slice
);
3627 get_isl_surf_dim(GLenum target
)
3631 case GL_TEXTURE_1D_ARRAY
:
3632 return ISL_SURF_DIM_1D
;
3635 case GL_TEXTURE_2D_ARRAY
:
3636 case GL_TEXTURE_RECTANGLE
:
3637 case GL_TEXTURE_CUBE_MAP
:
3638 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3639 case GL_TEXTURE_2D_MULTISAMPLE
:
3640 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3641 case GL_TEXTURE_EXTERNAL_OES
:
3642 return ISL_SURF_DIM_2D
;
3645 return ISL_SURF_DIM_3D
;
3648 unreachable("Invalid texture target");
3652 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3653 GLenum target
, enum miptree_array_layout array_layout
)
3655 if (array_layout
== GEN6_HIZ_STENCIL
)
3656 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3660 case GL_TEXTURE_1D_ARRAY
:
3661 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3662 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3665 case GL_TEXTURE_2D_ARRAY
:
3666 case GL_TEXTURE_RECTANGLE
:
3667 case GL_TEXTURE_2D_MULTISAMPLE
:
3668 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3669 case GL_TEXTURE_EXTERNAL_OES
:
3670 return ISL_DIM_LAYOUT_GEN4_2D
;
3672 case GL_TEXTURE_CUBE_MAP
:
3673 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3674 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3675 ISL_DIM_LAYOUT_GEN4_2D
);
3678 return (devinfo
->gen
>= 9 ?
3679 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3682 unreachable("Invalid texture target");
3686 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3688 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3689 return ISL_TILING_W
;
3691 switch (mt
->tiling
) {
3692 case I915_TILING_NONE
:
3693 return ISL_TILING_LINEAR
;
3695 return ISL_TILING_X
;
3697 return ISL_TILING_Y0
;
3699 unreachable("Invalid tiling mode");
3705 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3706 const struct intel_mipmap_tree
*mt
,
3707 struct isl_surf
*surf
)
3709 surf
->dim
= get_isl_surf_dim(mt
->target
);
3710 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3711 mt
->tiling
, mt
->target
,
3714 if (mt
->num_samples
> 1) {
3715 switch (mt
->msaa_layout
) {
3716 case INTEL_MSAA_LAYOUT_IMS
:
3717 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3719 case INTEL_MSAA_LAYOUT_UMS
:
3720 case INTEL_MSAA_LAYOUT_CMS
:
3721 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3724 unreachable("Invalid MSAA layout");
3727 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3730 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3732 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3733 /* The ISL definition of row_pitch matches the surface state pitch field
3734 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3735 * the factor of 2 for W-tiling in row_pitch.
3737 surf
->row_pitch
= 2 * mt
->pitch
;
3739 surf
->row_pitch
= mt
->pitch
;
3742 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3744 if (brw
->gen
>= 9) {
3745 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3746 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3747 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3749 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3750 * alignment in terms of surface elements like we want.
3752 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3755 /* On earlier gens it's stored in pixels. */
3757 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3758 surf
->image_alignment_el
=
3759 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3762 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3763 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3764 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3765 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3766 surf
->logical_level0_px
.array_len
= 1;
3768 surf
->logical_level0_px
.depth
= 1;
3769 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3772 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3773 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3774 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3775 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3776 surf
->phys_level0_sa
.array_len
= 1;
3778 surf
->phys_level0_sa
.depth
= 1;
3779 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3782 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3783 surf
->samples
= MAX2(mt
->num_samples
, 1);
3785 surf
->size
= 0; /* TODO */
3786 surf
->alignment
= 0; /* TODO */
3788 switch (surf
->dim_layout
) {
3789 case ISL_DIM_LAYOUT_GEN4_2D
:
3790 case ISL_DIM_LAYOUT_GEN4_3D
:
3791 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3792 if (brw
->gen
>= 9) {
3793 surf
->array_pitch_el_rows
= mt
->qpitch
;
3796 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3797 assert(mt
->qpitch
% bh
== 0);
3798 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3801 case ISL_DIM_LAYOUT_GEN9_1D
:
3802 surf
->array_pitch_el_rows
= 1;
3806 switch (mt
->array_layout
) {
3807 case ALL_LOD_IN_EACH_SLICE
:
3808 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3810 case ALL_SLICES_AT_EACH_LOD
:
3811 case GEN6_HIZ_STENCIL
:
3812 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3815 unreachable("Invalid array layout");
3818 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3819 switch (base_format
) {
3820 case GL_DEPTH_COMPONENT
:
3821 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3823 case GL_STENCIL_INDEX
:
3824 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3826 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3828 case GL_DEPTH_STENCIL
:
3829 /* In this case we only texture from the depth part */
3830 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3831 ISL_SURF_USAGE_TEXTURE_BIT
;
3834 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3835 if (brw
->mesa_format_supports_render
[mt
->format
])
3836 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3840 if (_mesa_is_cube_map_texture(mt
->target
))
3841 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3845 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3846 const struct intel_mipmap_tree
*mt
)
3849 return ISL_AUX_USAGE_HIZ
;
3852 return ISL_AUX_USAGE_NONE
;
3854 return mt
->aux_usage
;