1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_resolve_map.h"
35 #include "intel_tex.h"
36 #include "intel_blit.h"
37 #include "intel_fbo.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
73 * This field must be set to 0 for all SINT MSRTs when all RT channels
76 * In practice this means that we have to disable MCS for all signed
77 * integer MSAA buffers. The alternative, to disable MCS only when one
78 * of the render target channels is disabled, is impractical because it
79 * would require converting between CMS and UMS MSAA layouts on the fly,
82 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
83 return INTEL_MSAA_LAYOUT_UMS
;
85 return INTEL_MSAA_LAYOUT_CMS
;
92 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
93 * scaled-down bitfield representation of the color buffer which is capable of
94 * recording when blocks of the color buffer are equal to the clear value.
95 * This function returns the block size that will be used by the MCS buffer
96 * corresponding to a certain color miptree.
98 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
99 * beneath the "Fast Color Clear" bullet (p327):
101 * The following table describes the RT alignment
115 * This alignment has the following uses:
117 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
118 * buffer contains 128 blocks horizontally and 256 blocks vertically.
120 * - For figuring out alignment restrictions for a fast clear operation. Fast
121 * clear operations must always clear aligned multiples of 16 blocks
122 * horizontally and 32 blocks vertically.
124 * - For scaling down the coordinates sent through the render pipeline during
125 * a fast clear. X coordinates must be scaled down by 8 times the block
126 * width, and Y coordinates by 16 times the block height.
128 * - For scaling down the coordinates sent through the render pipeline during
129 * a "Render Target Resolve" operation. X coordinates must be scaled down
130 * by half the block width, and Y coordinates by half the block height.
133 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*mt
,
135 unsigned *width_px
, unsigned *height
)
137 switch (mt
->tiling
) {
139 unreachable("Non-MSRT MCS requires X or Y tiling");
140 /* In release builds, fall through */
142 *width_px
= 32 / mt
->cpp
;
146 *width_px
= 64 / mt
->cpp
;
153 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
156 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
157 * beneath the "Fast Color Clear" bullet (p326):
159 * - Support is limited to tiled render targets.
160 * - Support is for non-mip-mapped and non-array surface types only.
162 * And then later, on p327:
164 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
168 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
169 struct intel_mipmap_tree
*mt
)
171 /* MCS support does not exist prior to Gen7 */
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->tiling
!= I915_TILING_X
&&
184 mt
->tiling
!= I915_TILING_Y
)
186 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
188 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
190 if (mt
->physical_depth0
!= 1)
193 /* There's no point in using an MCS buffer if the surface isn't in a
196 if (!brw
->format_supported_as_render_target
[mt
->format
])
204 * Determine depth format corresponding to a depth+stencil format,
205 * for separate stencil.
208 intel_depth_format_for_depthstencil_format(mesa_format format
) {
210 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
211 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
212 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
213 return MESA_FORMAT_Z_FLOAT32
;
221 * @param for_bo Indicates that the caller is
222 * intel_miptree_create_for_bo(). If true, then do not create
225 struct intel_mipmap_tree
*
226 intel_miptree_create_layout(struct brw_context
*brw
,
236 bool force_all_slices_at_each_lod
)
238 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
242 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
243 _mesa_lookup_enum_by_nr(target
),
244 _mesa_get_format_name(format
),
245 first_level
, last_level
, depth0
, mt
);
247 if (target
== GL_TEXTURE_1D_ARRAY
) {
248 /* For a 1D Array texture the OpenGL API will treat the height0
249 * parameter as the number of array slices. For Intel hardware, we treat
250 * the 1D array as a 2D Array with a height of 1.
252 * So, when we first come through this path to create a 1D Array
253 * texture, height0 stores the number of slices, and depth0 is 1. In
254 * this case, we want to swap height0 and depth0.
256 * Since some miptrees will be created based on the base miptree, we may
257 * come through this path and see height0 as 1 and depth0 being the
258 * number of slices. In this case we don't need to do the swap.
260 assert(height0
== 1 || depth0
== 1);
269 mt
->first_level
= first_level
;
270 mt
->last_level
= last_level
;
271 mt
->logical_width0
= width0
;
272 mt
->logical_height0
= height0
;
273 mt
->logical_depth0
= depth0
;
274 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
275 exec_list_make_empty(&mt
->hiz_map
);
277 /* The cpp is bytes per (1, blockheight)-sized block for compressed
278 * textures. This is why you'll see divides by blockheight all over
281 _mesa_get_format_block_size(format
, &bw
, &bh
);
282 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
283 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
285 mt
->num_samples
= num_samples
;
286 mt
->compressed
= _mesa_is_format_compressed(format
);
287 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
290 if (num_samples
> 1) {
291 /* Adjust width/height/depth for MSAA */
292 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
293 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
294 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
296 * "Any of the other messages (sample*, LOD, load4) used with a
297 * (4x) multisampled surface will in-effect sample a surface with
298 * double the height and width as that indicated in the surface
299 * state. Each pixel position on the original-sized surface is
300 * replaced with a 2x2 of samples with the following arrangement:
305 * Thus, when sampling from a multisampled texture, it behaves as
306 * though the layout in memory for (x,y,sample) is:
308 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
309 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
311 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
312 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
314 * However, the actual layout of multisampled data in memory is:
316 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
317 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
319 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
320 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
322 * This pattern repeats for each 2x2 pixel block.
324 * As a result, when calculating the size of our 4-sample buffer for
325 * an odd width or height, we have to align before scaling up because
326 * sample 3 is in that bottom right 2x2 block.
328 switch (num_samples
) {
330 assert(brw
->gen
>= 8);
331 width0
= ALIGN(width0
, 2) * 2;
332 height0
= ALIGN(height0
, 2);
335 width0
= ALIGN(width0
, 2) * 2;
336 height0
= ALIGN(height0
, 2) * 2;
339 width0
= ALIGN(width0
, 2) * 4;
340 height0
= ALIGN(height0
, 2) * 2;
343 /* num_samples should already have been quantized to 0, 1, 2, 4, or
346 unreachable("not reached");
349 /* Non-interleaved */
350 depth0
*= num_samples
;
354 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
355 * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
356 * TODO: can we use it elsewhere?
358 switch (mt
->msaa_layout
) {
359 case INTEL_MSAA_LAYOUT_NONE
:
360 case INTEL_MSAA_LAYOUT_IMS
:
361 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
363 case INTEL_MSAA_LAYOUT_UMS
:
364 case INTEL_MSAA_LAYOUT_CMS
:
365 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
369 if (target
== GL_TEXTURE_CUBE_MAP
) {
374 mt
->physical_width0
= width0
;
375 mt
->physical_height0
= height0
;
376 mt
->physical_depth0
= depth0
;
379 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
380 (brw
->must_use_separate_stencil
||
381 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
382 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
383 mt
->stencil_mt
= intel_miptree_create(brw
,
393 INTEL_MIPTREE_TILING_ANY
,
394 force_all_slices_at_each_lod
);
395 if (!mt
->stencil_mt
) {
396 intel_miptree_release(&mt
);
400 /* Fix up the Z miptree format for how we're splitting out separate
401 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
403 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
406 if (format
== mt
->format
) {
407 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
408 _mesa_get_format_name(mt
->format
));
412 if (force_all_slices_at_each_lod
)
413 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
415 brw_miptree_layout(brw
, mt
);
421 * \brief Helper function for intel_miptree_create().
424 intel_miptree_choose_tiling(struct brw_context
*brw
,
427 uint32_t num_samples
,
428 enum intel_miptree_tiling_mode requested
,
429 struct intel_mipmap_tree
*mt
)
431 if (format
== MESA_FORMAT_S_UINT8
) {
432 /* The stencil buffer is W tiled. However, we request from the kernel a
433 * non-tiled buffer because the GTT is incapable of W fencing.
435 return I915_TILING_NONE
;
438 /* Some usages may want only one type of tiling, like depth miptrees (Y
439 * tiled), or temporary BOs for uploading data once (linear).
442 case INTEL_MIPTREE_TILING_ANY
:
444 case INTEL_MIPTREE_TILING_Y
:
445 return I915_TILING_Y
;
446 case INTEL_MIPTREE_TILING_NONE
:
447 return I915_TILING_NONE
;
450 if (num_samples
> 1) {
451 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
454 * [DevSNB+]: For multi-sample render targets, this field must be
455 * 1. MSRTs can only be tiled.
457 * Our usual reason for preferring X tiling (fast blits using the
458 * blitting engine) doesn't apply to MSAA, since we'll generally be
459 * downsampling or upsampling when blitting between the MSAA buffer
460 * and another buffer, and the blitting engine doesn't support that.
461 * So use Y tiling, since it makes better use of the cache.
463 return I915_TILING_Y
;
466 GLenum base_format
= _mesa_get_format_base_format(format
);
467 if (base_format
== GL_DEPTH_COMPONENT
||
468 base_format
== GL_DEPTH_STENCIL_EXT
)
469 return I915_TILING_Y
;
471 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
473 /* If the width is much smaller than a tile, don't bother tiling. */
474 if (minimum_pitch
< 64)
475 return I915_TILING_NONE
;
477 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
478 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
479 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
480 mt
->total_width
, mt
->total_height
);
481 return I915_TILING_NONE
;
484 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
486 return I915_TILING_X
;
488 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
489 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
491 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
492 * all the way back to 965, but is explicitly permitted on Gen7.
494 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
495 return I915_TILING_X
;
497 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
498 * messages), on p64, under the heading "Surface Vertical Alignment":
500 * This field must be set to VALIGN_4 for all tiled Y Render Target
503 * So if the surface is renderable and uses a vertical alignment of 2,
504 * force it to be X tiled. This is somewhat conservative (it's possible
505 * that the client won't ever render to this surface), but it's difficult
506 * to know that ahead of time. And besides, since we use a vertical
507 * alignment of 4 as often as we can, this shouldn't happen very often.
509 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
510 brw
->format_supported_as_render_target
[format
]) {
511 return I915_TILING_X
;
514 return I915_TILING_Y
| I915_TILING_X
;
519 * Choose an appropriate uncompressed format for a requested
520 * compressed format, if unsupported.
523 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
525 /* No need to lower ETC formats on these platforms,
526 * they are supported natively.
528 if (brw
->gen
>= 8 || brw
->is_baytrail
)
532 case MESA_FORMAT_ETC1_RGB8
:
533 return MESA_FORMAT_R8G8B8X8_UNORM
;
534 case MESA_FORMAT_ETC2_RGB8
:
535 return MESA_FORMAT_R8G8B8X8_UNORM
;
536 case MESA_FORMAT_ETC2_SRGB8
:
537 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
538 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
539 return MESA_FORMAT_B8G8R8A8_SRGB
;
540 case MESA_FORMAT_ETC2_RGBA8_EAC
:
541 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
542 return MESA_FORMAT_R8G8B8A8_UNORM
;
543 case MESA_FORMAT_ETC2_R11_EAC
:
544 return MESA_FORMAT_R_UNORM16
;
545 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
546 return MESA_FORMAT_R_SNORM16
;
547 case MESA_FORMAT_ETC2_RG11_EAC
:
548 return MESA_FORMAT_R16G16_UNORM
;
549 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
550 return MESA_FORMAT_R16G16_SNORM
;
552 /* Non ETC1 / ETC2 format */
558 struct intel_mipmap_tree
*
559 intel_miptree_create(struct brw_context
*brw
,
567 bool expect_accelerated_upload
,
569 enum intel_miptree_tiling_mode requested_tiling
,
570 bool force_all_slices_at_each_lod
)
572 struct intel_mipmap_tree
*mt
;
573 mesa_format tex_format
= format
;
574 mesa_format etc_format
= MESA_FORMAT_NONE
;
575 GLuint total_width
, total_height
;
577 format
= intel_lower_compressed_format(brw
, format
);
579 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
581 mt
= intel_miptree_create_layout(brw
, target
, format
,
582 first_level
, last_level
, width0
,
585 force_all_slices_at_each_lod
);
587 * pitch == 0 || height == 0 indicates the null texture
589 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
590 intel_miptree_release(&mt
);
594 total_width
= mt
->total_width
;
595 total_height
= mt
->total_height
;
597 if (format
== MESA_FORMAT_S_UINT8
) {
598 /* Align to size of W tile, 64x64. */
599 total_width
= ALIGN(total_width
, 64);
600 total_height
= ALIGN(total_height
, 64);
603 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
604 num_samples
, requested_tiling
,
608 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
610 mt
->tiling
= I915_TILING_Y
;
616 mt
->etc_format
= etc_format
;
617 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
618 total_width
, total_height
, mt
->cpp
,
620 (expect_accelerated_upload
?
621 BO_ALLOC_FOR_RENDER
: 0));
624 /* If the BO is too large to fit in the aperture, we need to use the
625 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
626 * so we need to fall back to X.
628 if (y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
629 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
630 mt
->total_width
, mt
->total_height
);
632 mt
->tiling
= I915_TILING_X
;
633 drm_intel_bo_unreference(mt
->bo
);
634 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
635 total_width
, total_height
, mt
->cpp
,
637 (expect_accelerated_upload
?
638 BO_ALLOC_FOR_RENDER
: 0));
645 intel_miptree_release(&mt
);
650 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
651 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
652 intel_miptree_release(&mt
);
657 /* If this miptree is capable of supporting fast color clears, set
658 * fast_clear_state appropriately to ensure that fast clears will occur.
659 * Allocation of the MCS miptree will be deferred until the first fast
660 * clear actually occurs.
662 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
663 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
668 struct intel_mipmap_tree
*
669 intel_miptree_create_for_bo(struct brw_context
*brw
,
677 struct intel_mipmap_tree
*mt
;
678 uint32_t tiling
, swizzle
;
680 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
682 /* Nothing will be able to use this miptree with the BO if the offset isn't
685 if (tiling
!= I915_TILING_NONE
)
686 assert(offset
% 4096 == 0);
688 /* miptrees can't handle negative pitch. If you need flipping of images,
689 * that's outside of the scope of the mt.
693 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
702 drm_intel_bo_reference(bo
);
712 * For a singlesample renderbuffer, this simply wraps the given BO with a
715 * For a multisample renderbuffer, this wraps the window system's
716 * (singlesample) BO with a singlesample miptree attached to the
717 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
718 * that will contain the actual rendering (which is lazily resolved to
719 * irb->singlesample_mt).
722 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
723 struct intel_renderbuffer
*irb
,
725 uint32_t width
, uint32_t height
,
728 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
729 struct intel_mipmap_tree
*multisample_mt
= NULL
;
730 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
731 mesa_format format
= rb
->Format
;
732 int num_samples
= rb
->NumSamples
;
734 /* Only the front and back buffers, which are color buffers, are allocated
735 * through the image loader.
737 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
738 _mesa_get_format_base_format(format
) == GL_RGBA
);
740 singlesample_mt
= intel_miptree_create_for_bo(intel
,
747 if (!singlesample_mt
)
750 /* If this miptree is capable of supporting fast color clears, set
751 * mcs_state appropriately to ensure that fast clears will occur.
752 * Allocation of the MCS miptree will be deferred until the first fast
753 * clear actually occurs.
755 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
756 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
758 if (num_samples
== 0) {
759 intel_miptree_release(&irb
->mt
);
760 irb
->mt
= singlesample_mt
;
762 assert(!irb
->singlesample_mt
);
764 intel_miptree_release(&irb
->singlesample_mt
);
765 irb
->singlesample_mt
= singlesample_mt
;
768 irb
->mt
->logical_width0
!= width
||
769 irb
->mt
->logical_height0
!= height
) {
770 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
778 irb
->need_downsample
= false;
779 intel_miptree_release(&irb
->mt
);
780 irb
->mt
= multisample_mt
;
786 intel_miptree_release(&irb
->singlesample_mt
);
787 intel_miptree_release(&irb
->mt
);
791 struct intel_mipmap_tree
*
792 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
796 uint32_t num_samples
)
798 struct intel_mipmap_tree
*mt
;
801 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
803 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
804 width
, height
, depth
, true, num_samples
,
805 INTEL_MIPTREE_TILING_ANY
, false);
809 if (brw_is_hiz_depth_format(brw
, format
)) {
810 ok
= intel_miptree_alloc_hiz(brw
, mt
);
818 intel_miptree_release(&mt
);
823 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
824 struct intel_mipmap_tree
*src
)
829 intel_miptree_release(dst
);
833 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
841 intel_miptree_release(struct intel_mipmap_tree
**mt
)
846 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
847 if (--(*mt
)->refcount
<= 0) {
850 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
852 drm_intel_bo_unreference((*mt
)->bo
);
853 intel_miptree_release(&(*mt
)->stencil_mt
);
854 intel_miptree_release(&(*mt
)->hiz_mt
);
855 intel_miptree_release(&(*mt
)->mcs_mt
);
856 intel_resolve_map_clear(&(*mt
)->hiz_map
);
858 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
859 free((*mt
)->level
[i
].slice
);
868 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
869 int *width
, int *height
, int *depth
)
871 switch (image
->TexObject
->Target
) {
872 case GL_TEXTURE_1D_ARRAY
:
873 *width
= image
->Width
;
875 *depth
= image
->Height
;
878 *width
= image
->Width
;
879 *height
= image
->Height
;
880 *depth
= image
->Depth
;
886 * Can the image be pulled into a unified mipmap tree? This mirrors
887 * the completeness test in a lot of ways.
889 * Not sure whether I want to pass gl_texture_image here.
892 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
893 struct gl_texture_image
*image
)
895 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
896 GLuint level
= intelImage
->base
.Base
.Level
;
897 int width
, height
, depth
;
899 /* glTexImage* choose the texture object based on the target passed in, and
900 * objects can't change targets over their lifetimes, so this should be
903 assert(image
->TexObject
->Target
== mt
->target
);
905 mesa_format mt_format
= mt
->format
;
906 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
907 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
908 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
909 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
910 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
911 mt_format
= mt
->etc_format
;
913 if (image
->TexFormat
!= mt_format
)
916 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
918 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
921 int level_depth
= mt
->level
[level
].depth
;
922 if (mt
->num_samples
> 1) {
923 switch (mt
->msaa_layout
) {
924 case INTEL_MSAA_LAYOUT_NONE
:
925 case INTEL_MSAA_LAYOUT_IMS
:
927 case INTEL_MSAA_LAYOUT_UMS
:
928 case INTEL_MSAA_LAYOUT_CMS
:
929 level_depth
/= mt
->num_samples
;
934 /* Test image dimensions against the base level image adjusted for
935 * minification. This will also catch images not present in the
936 * tree, changed targets, etc.
938 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
939 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
940 depth
!= level_depth
) {
944 if (image
->NumSamples
!= mt
->num_samples
)
952 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
954 GLuint x
, GLuint y
, GLuint d
)
956 mt
->level
[level
].depth
= d
;
957 mt
->level
[level
].level_x
= x
;
958 mt
->level
[level
].level_y
= y
;
960 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
963 assert(mt
->level
[level
].slice
== NULL
);
965 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
966 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
967 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
972 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
973 GLuint level
, GLuint img
,
976 if (img
== 0 && level
== 0)
977 assert(x
== 0 && y
== 0);
979 assert(img
< mt
->level
[level
].depth
);
981 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
982 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
984 DBG("%s level %d img %d pos %d,%d\n",
985 __FUNCTION__
, level
, img
,
986 mt
->level
[level
].slice
[img
].x_offset
,
987 mt
->level
[level
].slice
[img
].y_offset
);
991 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
992 GLuint level
, GLuint slice
,
993 GLuint
*x
, GLuint
*y
)
995 assert(slice
< mt
->level
[level
].depth
);
997 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
998 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1002 * This function computes masks that may be used to select the bits of the X
1003 * and Y coordinates that indicate the offset within a tile. If the BO is
1004 * untiled, the masks are set to 0.
1007 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1008 uint32_t *mask_x
, uint32_t *mask_y
,
1009 bool map_stencil_as_y_tiled
)
1012 uint32_t tiling
= mt
->tiling
;
1014 if (map_stencil_as_y_tiled
)
1015 tiling
= I915_TILING_Y
;
1019 unreachable("not reached");
1020 case I915_TILING_NONE
:
1021 *mask_x
= *mask_y
= 0;
1024 *mask_x
= 512 / cpp
- 1;
1028 *mask_x
= 128 / cpp
- 1;
1035 * Compute the offset (in bytes) from the start of the BO to the given x
1036 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1037 * multiples of the tile size.
1040 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1041 uint32_t x
, uint32_t y
,
1042 bool map_stencil_as_y_tiled
)
1045 uint32_t pitch
= mt
->pitch
;
1046 uint32_t tiling
= mt
->tiling
;
1048 if (map_stencil_as_y_tiled
) {
1049 tiling
= I915_TILING_Y
;
1051 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1052 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1053 * the resulting surface is twice the pitch of the original miptree,
1054 * since each row in the Y-tiled view corresponds to two rows in the
1055 * actual W-tiled surface. So we need to correct the pitch before
1056 * computing the offsets.
1063 unreachable("not reached");
1064 case I915_TILING_NONE
:
1065 return y
* pitch
+ x
* cpp
;
1067 assert((x
% (512 / cpp
)) == 0);
1068 assert((y
% 8) == 0);
1069 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1071 assert((x
% (128 / cpp
)) == 0);
1072 assert((y
% 32) == 0);
1073 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1078 * Rendering with tiled buffers requires that the base address of the buffer
1079 * be aligned to a page boundary. For renderbuffers, and sometimes with
1080 * textures, we may want the surface to point at a texture image level that
1081 * isn't at a page boundary.
1083 * This function returns an appropriately-aligned base offset
1084 * according to the tiling restrictions, plus any required x/y offset
1088 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1089 GLuint level
, GLuint slice
,
1094 uint32_t mask_x
, mask_y
;
1096 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1097 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1099 *tile_x
= x
& mask_x
;
1100 *tile_y
= y
& mask_y
;
1102 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1106 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1107 struct intel_mipmap_tree
*dst_mt
,
1108 struct intel_mipmap_tree
*src_mt
,
1115 int src_stride
, dst_stride
;
1116 int cpp
= dst_mt
->cpp
;
1118 intel_miptree_map(brw
, src_mt
,
1122 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1125 intel_miptree_map(brw
, dst_mt
,
1129 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1133 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1134 _mesa_get_format_name(src_mt
->format
),
1135 src_mt
, src
, src_stride
,
1136 _mesa_get_format_name(dst_mt
->format
),
1137 dst_mt
, dst
, dst_stride
,
1140 int row_size
= cpp
* width
;
1141 if (src_stride
== row_size
&&
1142 dst_stride
== row_size
) {
1143 memcpy(dst
, src
, row_size
* height
);
1145 for (int i
= 0; i
< height
; i
++) {
1146 memcpy(dst
, src
, row_size
);
1152 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1153 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1155 /* Don't forget to copy the stencil data over, too. We could have skipped
1156 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1157 * shuffling the two data sources in/out of temporary storage instead of
1158 * the direct mapping we get this way.
1160 if (dst_mt
->stencil_mt
) {
1161 assert(src_mt
->stencil_mt
);
1162 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1163 level
, slice
, width
, height
);
1168 intel_miptree_copy_slice(struct brw_context
*brw
,
1169 struct intel_mipmap_tree
*dst_mt
,
1170 struct intel_mipmap_tree
*src_mt
,
1176 mesa_format format
= src_mt
->format
;
1177 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1178 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1186 assert(depth
< src_mt
->level
[level
].depth
);
1187 assert(src_mt
->format
== dst_mt
->format
);
1189 if (dst_mt
->compressed
) {
1190 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1191 width
= ALIGN(width
, dst_mt
->align_w
);
1194 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1195 * below won't apply since we can't do the depth's Y tiling or the
1196 * stencil's W tiling in the blitter.
1198 if (src_mt
->stencil_mt
) {
1199 intel_miptree_copy_slice_sw(brw
,
1206 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1207 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1208 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1210 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1211 _mesa_get_format_name(src_mt
->format
),
1212 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1213 _mesa_get_format_name(dst_mt
->format
),
1214 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1217 if (!intel_miptree_blit(brw
,
1218 src_mt
, level
, slice
, 0, 0, false,
1219 dst_mt
, level
, slice
, 0, 0, false,
1220 width
, height
, GL_COPY
)) {
1221 perf_debug("miptree validate blit for %s failed\n",
1222 _mesa_get_format_name(format
));
1224 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1230 * Copies the image's current data to the given miptree, and associates that
1231 * miptree with the image.
1233 * If \c invalidate is true, then the actual image data does not need to be
1234 * copied, but the image still needs to be associated to the new miptree (this
1235 * is set to true if we're about to clear the image).
1238 intel_miptree_copy_teximage(struct brw_context
*brw
,
1239 struct intel_texture_image
*intelImage
,
1240 struct intel_mipmap_tree
*dst_mt
,
1243 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1244 struct intel_texture_object
*intel_obj
=
1245 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1246 int level
= intelImage
->base
.Base
.Level
;
1247 int face
= intelImage
->base
.Base
.Face
;
1248 GLuint depth
= intelImage
->base
.Base
.Depth
;
1251 for (int slice
= 0; slice
< depth
; slice
++) {
1252 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1256 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1257 intel_obj
->needs_validate
= true;
1261 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1262 struct intel_mipmap_tree
*mt
,
1265 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1266 assert(mt
->mcs_mt
== NULL
);
1268 /* Choose the correct format for the MCS buffer. All that really matters
1269 * is that we allocate the right buffer size, since we'll always be
1270 * accessing this miptree using MCS-specific hardware mechanisms, which
1271 * infer the correct format based on num_samples.
1274 switch (num_samples
) {
1277 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1280 format
= MESA_FORMAT_R_UNORM8
;
1283 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1284 * for each sample, plus 8 padding bits).
1286 format
= MESA_FORMAT_R_UINT32
;
1289 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1292 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1294 * "The MCS surface must be stored as Tile Y."
1296 mt
->mcs_mt
= intel_miptree_create(brw
,
1302 mt
->logical_height0
,
1305 0 /* num_samples */,
1306 INTEL_MIPTREE_TILING_Y
,
1309 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1311 * When MCS buffer is enabled and bound to MSRT, it is required that it
1312 * is cleared prior to any rendering.
1314 * Since we don't use the MCS buffer for any purpose other than rendering,
1315 * it makes sense to just clear it immediately upon allocation.
1317 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1319 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1320 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1321 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1322 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1329 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1330 struct intel_mipmap_tree
*mt
)
1332 assert(mt
->mcs_mt
== NULL
);
1334 /* The format of the MCS buffer is opaque to the driver; all that matters
1335 * is that we get its size and pitch right. We'll pretend that the format
1336 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1337 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1338 * the block width and then a further factor of 4. Since an MCS tile
1339 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1340 * we'll need to scale the height down by the block height and then a
1341 * further factor of 8.
1343 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1344 unsigned block_width_px
;
1345 unsigned block_height
;
1346 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1347 unsigned width_divisor
= block_width_px
* 4;
1348 unsigned height_divisor
= block_height
* 8;
1349 unsigned mcs_width
=
1350 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1351 unsigned mcs_height
=
1352 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1353 assert(mt
->logical_depth0
== 1);
1354 mt
->mcs_mt
= intel_miptree_create(brw
,
1363 0 /* num_samples */,
1364 INTEL_MIPTREE_TILING_Y
,
1372 * Helper for intel_miptree_alloc_hiz() that sets
1373 * \c mt->level[level].has_hiz. Return true if and only if
1374 * \c has_hiz was set.
1377 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1378 struct intel_mipmap_tree
*mt
,
1383 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1384 uint32_t width
= minify(mt
->physical_width0
, level
);
1385 uint32_t height
= minify(mt
->physical_height0
, level
);
1387 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1388 * and the height is 4 aligned. This allows our HiZ support
1389 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1390 * we can grow the width & height to allow the HiZ op to
1391 * force the proper size alignments.
1393 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1394 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1399 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1400 mt
->level
[level
].has_hiz
= true;
1407 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1408 struct intel_mipmap_tree
*mt
)
1410 assert(mt
->hiz_mt
== NULL
);
1411 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1412 mt
->hiz_mt
= intel_miptree_create(brw
,
1418 mt
->logical_height0
,
1422 INTEL_MIPTREE_TILING_ANY
,
1423 force_all_slices_at_each_lod
);
1428 /* Mark that all slices need a HiZ resolve. */
1429 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1430 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1433 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1434 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1435 exec_node_init(&m
->link
);
1438 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1440 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1448 * Does the miptree slice have hiz enabled?
1451 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1453 intel_miptree_check_level_layer(mt
, level
, 0);
1454 return mt
->level
[level
].has_hiz
;
1458 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1462 if (!intel_miptree_level_has_hiz(mt
, level
))
1465 intel_resolve_map_set(&mt
->hiz_map
,
1466 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1471 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1475 if (!intel_miptree_level_has_hiz(mt
, level
))
1478 intel_resolve_map_set(&mt
->hiz_map
,
1479 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1483 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1487 uint32_t end_layer
= mt
->level
[level
].depth
;
1489 for (layer
= 0; layer
< end_layer
; layer
++) {
1490 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1495 intel_miptree_slice_resolve(struct brw_context
*brw
,
1496 struct intel_mipmap_tree
*mt
,
1499 enum gen6_hiz_op need
)
1501 intel_miptree_check_level_layer(mt
, level
, layer
);
1503 struct intel_resolve_map
*item
=
1504 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1506 if (!item
|| item
->need
!= need
)
1509 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1510 intel_resolve_map_remove(item
);
1515 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1516 struct intel_mipmap_tree
*mt
,
1520 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1521 GEN6_HIZ_OP_HIZ_RESOLVE
);
1525 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1526 struct intel_mipmap_tree
*mt
,
1530 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1531 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1535 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1536 struct intel_mipmap_tree
*mt
,
1537 enum gen6_hiz_op need
)
1539 bool did_resolve
= false;
1541 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1542 if (map
->need
!= need
)
1545 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1546 intel_resolve_map_remove(map
);
1554 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1555 struct intel_mipmap_tree
*mt
)
1557 return intel_miptree_all_slices_resolve(brw
, mt
,
1558 GEN6_HIZ_OP_HIZ_RESOLVE
);
1562 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1563 struct intel_mipmap_tree
*mt
)
1565 return intel_miptree_all_slices_resolve(brw
, mt
,
1566 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1571 intel_miptree_resolve_color(struct brw_context
*brw
,
1572 struct intel_mipmap_tree
*mt
)
1574 switch (mt
->fast_clear_state
) {
1575 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1576 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1577 /* No resolve needed */
1579 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1580 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1581 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1582 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1583 brw_meta_resolve_color(brw
, mt
);
1590 * Make it possible to share the BO backing the given miptree with another
1591 * process or another miptree.
1593 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1594 * then discard the MCS buffer, if present. We also set the fast_clear_state
1595 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1596 * allocated in the future.
1599 intel_miptree_make_shareable(struct brw_context
*brw
,
1600 struct intel_mipmap_tree
*mt
)
1602 /* MCS buffers are also used for multisample buffers, but we can't resolve
1603 * away a multisample MCS buffer because it's an integral part of how the
1604 * pixel data is stored. Fortunately this code path should never be
1605 * reached for multisample buffers.
1607 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1610 intel_miptree_resolve_color(brw
, mt
);
1611 intel_miptree_release(&mt
->mcs_mt
);
1612 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1618 * \brief Get pointer offset into stencil buffer.
1620 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1621 * must decode the tile's layout in software.
1624 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1626 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1628 * Even though the returned offset is always positive, the return type is
1630 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1631 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1634 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1636 uint32_t tile_size
= 4096;
1637 uint32_t tile_width
= 64;
1638 uint32_t tile_height
= 64;
1639 uint32_t row_size
= 64 * stride
;
1641 uint32_t tile_x
= x
/ tile_width
;
1642 uint32_t tile_y
= y
/ tile_height
;
1644 /* The byte's address relative to the tile's base addres. */
1645 uint32_t byte_x
= x
% tile_width
;
1646 uint32_t byte_y
= y
% tile_height
;
1648 uintptr_t u
= tile_y
* row_size
1649 + tile_x
* tile_size
1650 + 512 * (byte_x
/ 8)
1652 + 32 * ((byte_y
/ 4) % 2)
1653 + 16 * ((byte_x
/ 4) % 2)
1654 + 8 * ((byte_y
/ 2) % 2)
1655 + 4 * ((byte_x
/ 2) % 2)
1660 /* adjust for bit6 swizzling */
1661 if (((byte_x
/ 8) % 2) == 1) {
1662 if (((byte_y
/ 8) % 2) == 0) {
1674 intel_miptree_updownsample(struct brw_context
*brw
,
1675 struct intel_mipmap_tree
*src
,
1676 struct intel_mipmap_tree
*dst
)
1679 brw_blorp_blit_miptrees(brw
,
1680 src
, 0 /* level */, 0 /* layer */,
1681 dst
, 0 /* level */, 0 /* layer */,
1683 src
->logical_width0
, src
->logical_height0
,
1685 dst
->logical_width0
, dst
->logical_height0
,
1686 GL_NEAREST
, false, false /*mirror x, y*/);
1687 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1688 brw_meta_stencil_updownsample(brw
, src
, dst
);
1690 brw_meta_updownsample(brw
, src
, dst
);
1693 if (src
->stencil_mt
) {
1694 if (brw
->gen
>= 8) {
1695 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1699 brw_blorp_blit_miptrees(brw
,
1700 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1701 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1703 src
->logical_width0
, src
->logical_height0
,
1705 dst
->logical_width0
, dst
->logical_height0
,
1706 GL_NEAREST
, false, false /*mirror x, y*/);
1711 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1713 /* CPU accesses to color buffers don't understand fast color clears, so
1714 * resolve any pending fast color clears before we map.
1716 intel_miptree_resolve_color(brw
, mt
);
1718 drm_intel_bo
*bo
= mt
->bo
;
1720 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1721 intel_batchbuffer_flush(brw
);
1723 if (mt
->tiling
!= I915_TILING_NONE
)
1724 brw_bo_map_gtt(brw
, bo
, "miptree");
1726 brw_bo_map(brw
, bo
, true, "miptree");
1732 intel_miptree_unmap_raw(struct brw_context
*brw
,
1733 struct intel_mipmap_tree
*mt
)
1735 drm_intel_bo_unmap(mt
->bo
);
1739 intel_miptree_map_gtt(struct brw_context
*brw
,
1740 struct intel_mipmap_tree
*mt
,
1741 struct intel_miptree_map
*map
,
1742 unsigned int level
, unsigned int slice
)
1744 unsigned int bw
, bh
;
1746 unsigned int image_x
, image_y
;
1750 /* For compressed formats, the stride is the number of bytes per
1751 * row of blocks. intel_miptree_get_image_offset() already does
1754 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1755 assert(y
% bh
== 0);
1758 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1763 /* Note that in the case of cube maps, the caller must have passed the
1764 * slice number referencing the face.
1766 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1770 map
->stride
= mt
->pitch
;
1771 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1774 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1775 map
->x
, map
->y
, map
->w
, map
->h
,
1776 mt
, _mesa_get_format_name(mt
->format
),
1777 x
, y
, map
->ptr
, map
->stride
);
1781 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1782 struct intel_mipmap_tree
*mt
,
1783 struct intel_miptree_map
*map
,
1787 intel_miptree_unmap_raw(brw
, mt
);
1791 intel_miptree_map_blit(struct brw_context
*brw
,
1792 struct intel_mipmap_tree
*mt
,
1793 struct intel_miptree_map
*map
,
1794 unsigned int level
, unsigned int slice
)
1796 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1800 INTEL_MIPTREE_TILING_NONE
,
1803 fprintf(stderr
, "Failed to allocate blit temporary\n");
1806 map
->stride
= map
->mt
->pitch
;
1808 if (!intel_miptree_blit(brw
,
1810 map
->x
, map
->y
, false,
1813 map
->w
, map
->h
, GL_COPY
)) {
1814 fprintf(stderr
, "Failed to blit\n");
1818 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1820 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1821 map
->x
, map
->y
, map
->w
, map
->h
,
1822 mt
, _mesa_get_format_name(mt
->format
),
1823 level
, slice
, map
->ptr
, map
->stride
);
1828 intel_miptree_release(&map
->mt
);
1834 intel_miptree_unmap_blit(struct brw_context
*brw
,
1835 struct intel_mipmap_tree
*mt
,
1836 struct intel_miptree_map
*map
,
1840 struct gl_context
*ctx
= &brw
->ctx
;
1842 intel_miptree_unmap_raw(brw
, map
->mt
);
1844 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1845 bool ok
= intel_miptree_blit(brw
,
1849 map
->x
, map
->y
, false,
1850 map
->w
, map
->h
, GL_COPY
);
1851 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1854 intel_miptree_release(&map
->mt
);
1858 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1860 #if defined(USE_SSE41)
1862 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1863 struct intel_mipmap_tree
*mt
,
1864 struct intel_miptree_map
*map
,
1865 unsigned int level
, unsigned int slice
)
1867 assert(map
->mode
& GL_MAP_READ_BIT
);
1868 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1870 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1871 map
->x
, map
->y
, map
->w
, map
->h
,
1872 mt
, _mesa_get_format_name(mt
->format
),
1873 level
, slice
, map
->ptr
, map
->stride
);
1875 /* Map the original image */
1878 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1882 void *src
= intel_miptree_map_raw(brw
, mt
);
1885 src
+= image_y
* mt
->pitch
;
1886 src
+= image_x
* mt
->cpp
;
1888 /* Due to the pixel offsets for the particular image being mapped, our
1889 * src pointer may not be 16-byte aligned. However, if the pitch is
1890 * divisible by 16, then the amount by which it's misaligned will remain
1891 * consistent from row to row.
1893 assert((mt
->pitch
% 16) == 0);
1894 const int misalignment
= ((uintptr_t) src
) & 15;
1896 /* Create an untiled temporary buffer for the mapping. */
1897 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1899 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1901 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
1902 /* Offset the destination so it has the same misalignment as src. */
1903 map
->ptr
= map
->buffer
+ misalignment
;
1905 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1907 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1908 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1909 void *src_ptr
= src
+ y
* mt
->pitch
;
1911 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1914 intel_miptree_unmap_raw(brw
, mt
);
1918 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1919 struct intel_mipmap_tree
*mt
,
1920 struct intel_miptree_map
*map
,
1924 _mesa_align_free(map
->buffer
);
1931 intel_miptree_map_s8(struct brw_context
*brw
,
1932 struct intel_mipmap_tree
*mt
,
1933 struct intel_miptree_map
*map
,
1934 unsigned int level
, unsigned int slice
)
1936 map
->stride
= map
->w
;
1937 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1941 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1942 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1943 * invalidate is set, since we'll be writing the whole rectangle from our
1944 * temporary buffer back out.
1946 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1947 uint8_t *untiled_s8_map
= map
->ptr
;
1948 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1949 unsigned int image_x
, image_y
;
1951 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1953 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1954 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1955 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1956 x
+ image_x
+ map
->x
,
1957 y
+ image_y
+ map
->y
,
1958 brw
->has_swizzling
);
1959 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1963 intel_miptree_unmap_raw(brw
, mt
);
1965 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1966 map
->x
, map
->y
, map
->w
, map
->h
,
1967 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1969 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1970 map
->x
, map
->y
, map
->w
, map
->h
,
1971 mt
, map
->ptr
, map
->stride
);
1976 intel_miptree_unmap_s8(struct brw_context
*brw
,
1977 struct intel_mipmap_tree
*mt
,
1978 struct intel_miptree_map
*map
,
1982 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1983 unsigned int image_x
, image_y
;
1984 uint8_t *untiled_s8_map
= map
->ptr
;
1985 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1987 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1989 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1990 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1991 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1994 brw
->has_swizzling
);
1995 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1999 intel_miptree_unmap_raw(brw
, mt
);
2006 intel_miptree_map_etc(struct brw_context
*brw
,
2007 struct intel_mipmap_tree
*mt
,
2008 struct intel_miptree_map
*map
,
2012 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2013 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2014 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2017 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2018 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2020 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2021 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2022 map
->w
, map
->h
, 1));
2023 map
->ptr
= map
->buffer
;
2027 intel_miptree_unmap_etc(struct brw_context
*brw
,
2028 struct intel_mipmap_tree
*mt
,
2029 struct intel_miptree_map
*map
,
2035 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2040 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2041 + image_y
* mt
->pitch
2042 + image_x
* mt
->cpp
;
2044 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2045 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2046 map
->ptr
, map
->stride
,
2049 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2050 map
->ptr
, map
->stride
,
2051 map
->w
, map
->h
, mt
->etc_format
);
2053 intel_miptree_unmap_raw(brw
, mt
);
2058 * Mapping function for packed depth/stencil miptrees backed by real separate
2059 * miptrees for depth and stencil.
2061 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2062 * separate from the depth buffer. Yet at the GL API level, we have to expose
2063 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2064 * be able to map that memory for texture storage and glReadPixels-type
2065 * operations. We give Mesa core that access by mallocing a temporary and
2066 * copying the data between the actual backing store and the temporary.
2069 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2070 struct intel_mipmap_tree
*mt
,
2071 struct intel_miptree_map
*map
,
2072 unsigned int level
, unsigned int slice
)
2074 struct intel_mipmap_tree
*z_mt
= mt
;
2075 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2076 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2077 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2079 map
->stride
= map
->w
* packed_bpp
;
2080 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2084 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2085 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2086 * invalidate is set, since we'll be writing the whole rectangle from our
2087 * temporary buffer back out.
2089 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2090 uint32_t *packed_map
= map
->ptr
;
2091 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2092 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2093 unsigned int s_image_x
, s_image_y
;
2094 unsigned int z_image_x
, z_image_y
;
2096 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2097 &s_image_x
, &s_image_y
);
2098 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2099 &z_image_x
, &z_image_y
);
2101 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2102 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2103 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2104 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2107 brw
->has_swizzling
);
2108 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2110 (map_x
+ z_image_x
));
2111 uint8_t s
= s_map
[s_offset
];
2112 uint32_t z
= z_map
[z_offset
];
2114 if (map_z32f_x24s8
) {
2115 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2116 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2118 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2123 intel_miptree_unmap_raw(brw
, s_mt
);
2124 intel_miptree_unmap_raw(brw
, z_mt
);
2126 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2128 map
->x
, map
->y
, map
->w
, map
->h
,
2129 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2130 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2131 map
->ptr
, map
->stride
);
2133 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2134 map
->x
, map
->y
, map
->w
, map
->h
,
2135 mt
, map
->ptr
, map
->stride
);
2140 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2141 struct intel_mipmap_tree
*mt
,
2142 struct intel_miptree_map
*map
,
2146 struct intel_mipmap_tree
*z_mt
= mt
;
2147 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2148 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2150 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2151 uint32_t *packed_map
= map
->ptr
;
2152 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2153 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2154 unsigned int s_image_x
, s_image_y
;
2155 unsigned int z_image_x
, z_image_y
;
2157 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2158 &s_image_x
, &s_image_y
);
2159 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2160 &z_image_x
, &z_image_y
);
2162 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2163 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2164 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2165 x
+ s_image_x
+ map
->x
,
2166 y
+ s_image_y
+ map
->y
,
2167 brw
->has_swizzling
);
2168 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2170 (x
+ z_image_x
+ map
->x
));
2172 if (map_z32f_x24s8
) {
2173 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2174 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2176 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2177 s_map
[s_offset
] = packed
>> 24;
2178 z_map
[z_offset
] = packed
;
2183 intel_miptree_unmap_raw(brw
, s_mt
);
2184 intel_miptree_unmap_raw(brw
, z_mt
);
2186 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2188 map
->x
, map
->y
, map
->w
, map
->h
,
2189 z_mt
, _mesa_get_format_name(z_mt
->format
),
2190 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2191 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2192 map
->ptr
, map
->stride
);
2199 * Create and attach a map to the miptree at (level, slice). Return the
2202 static struct intel_miptree_map
*
2203 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2212 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2217 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2218 mt
->level
[level
].slice
[slice
].map
= map
;
2230 * Release the map at (level, slice).
2233 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2237 struct intel_miptree_map
**map
;
2239 map
= &mt
->level
[level
].slice
[slice
].map
;
2245 can_blit_slice(struct intel_mipmap_tree
*mt
,
2246 unsigned int level
, unsigned int slice
)
2250 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2251 if (image_x
>= 32768 || image_y
>= 32768)
2254 if (mt
->pitch
>= 32768)
2261 intel_miptree_map(struct brw_context
*brw
,
2262 struct intel_mipmap_tree
*mt
,
2273 struct intel_miptree_map
*map
;
2275 assert(mt
->num_samples
<= 1);
2277 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2284 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2285 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2286 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2289 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2290 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2291 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2292 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2293 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2294 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2295 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2297 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2298 else if (brw
->has_llc
&&
2299 !(mode
& GL_MAP_WRITE_BIT
) &&
2301 (mt
->tiling
== I915_TILING_X
||
2302 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2303 can_blit_slice(mt
, level
, slice
)) {
2304 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2305 } else if (mt
->tiling
!= I915_TILING_NONE
&&
2306 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2307 assert(can_blit_slice(mt
, level
, slice
));
2308 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2309 #if defined(USE_SSE41)
2310 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2311 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2314 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2317 *out_ptr
= map
->ptr
;
2318 *out_stride
= map
->stride
;
2320 if (map
->ptr
== NULL
)
2321 intel_miptree_release_map(mt
, level
, slice
);
2325 intel_miptree_unmap(struct brw_context
*brw
,
2326 struct intel_mipmap_tree
*mt
,
2330 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2332 assert(mt
->num_samples
<= 1);
2337 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2338 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2340 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2341 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2342 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2343 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2344 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2345 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2346 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2347 } else if (map
->mt
) {
2348 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2349 #if defined(USE_SSE41)
2350 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2351 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2354 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2357 intel_miptree_release_map(mt
, level
, slice
);