1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 * Determine which MSAA layout should be used by the MSAA surface being
54 * created, based on the chip generation and the surface type.
56 static enum intel_msaa_layout
57 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
59 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
61 return INTEL_MSAA_LAYOUT_IMS
;
63 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
64 switch (_mesa_get_format_base_format(format
)) {
65 case GL_DEPTH_COMPONENT
:
66 case GL_STENCIL_INDEX
:
67 case GL_DEPTH_STENCIL
:
68 return INTEL_MSAA_LAYOUT_IMS
;
70 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
72 * This field must be set to 0 for all SINT MSRTs when all RT channels
75 * In practice this means that we have to disable MCS for all signed
76 * integer MSAA buffers. The alternative, to disable MCS only when one
77 * of the render target channels is disabled, is impractical because it
78 * would require converting between CMS and UMS MSAA layouts on the fly,
81 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
82 return INTEL_MSAA_LAYOUT_UMS
;
84 return INTEL_MSAA_LAYOUT_CMS
;
91 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
92 * scaled-down bitfield representation of the color buffer which is capable of
93 * recording when blocks of the color buffer are equal to the clear value.
94 * This function returns the block size that will be used by the MCS buffer
95 * corresponding to a certain color miptree.
97 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
98 * beneath the "Fast Color Clear" bullet (p327):
100 * The following table describes the RT alignment
114 * This alignment has the following uses:
116 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
117 * buffer contains 128 blocks horizontally and 256 blocks vertically.
119 * - For figuring out alignment restrictions for a fast clear operation. Fast
120 * clear operations must always clear aligned multiples of 16 blocks
121 * horizontally and 32 blocks vertically.
123 * - For scaling down the coordinates sent through the render pipeline during
124 * a fast clear. X coordinates must be scaled down by 8 times the block
125 * width, and Y coordinates by 16 times the block height.
127 * - For scaling down the coordinates sent through the render pipeline during
128 * a "Render Target Resolve" operation. X coordinates must be scaled down
129 * by half the block width, and Y coordinates by half the block height.
132 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
133 struct intel_mipmap_tree
*mt
,
134 unsigned *width_px
, unsigned *height
)
136 switch (mt
->tiling
) {
138 unreachable("Non-MSRT MCS requires X or Y tiling");
139 /* In release builds, fall through */
141 *width_px
= 32 / mt
->cpp
;
145 *width_px
= 64 / mt
->cpp
;
152 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
155 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
156 * beneath the "Fast Color Clear" bullet (p326):
158 * - Support is limited to tiled render targets.
159 * - Support is for non-mip-mapped and non-array surface types only.
161 * And then later, on p327:
163 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
167 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
168 struct intel_mipmap_tree
*mt
)
170 /* MCS support does not exist prior to Gen7 */
174 /* MCS is only supported for color buffers */
175 switch (_mesa_get_format_base_format(mt
->format
)) {
176 case GL_DEPTH_COMPONENT
:
177 case GL_DEPTH_STENCIL
:
178 case GL_STENCIL_INDEX
:
182 if (mt
->tiling
!= I915_TILING_X
&&
183 mt
->tiling
!= I915_TILING_Y
)
185 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
187 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
189 if (mt
->physical_depth0
!= 1)
192 /* There's no point in using an MCS buffer if the surface isn't in a
195 if (!brw
->format_supported_as_render_target
[mt
->format
])
203 * Determine depth format corresponding to a depth+stencil format,
204 * for separate stencil.
207 intel_depth_format_for_depthstencil_format(mesa_format format
) {
209 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
210 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
211 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
212 return MESA_FORMAT_Z_FLOAT32
;
220 * @param for_bo Indicates that the caller is
221 * intel_miptree_create_for_bo(). If true, then do not create
224 struct intel_mipmap_tree
*
225 intel_miptree_create_layout(struct brw_context
*brw
,
235 bool force_all_slices_at_each_lod
)
237 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
241 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
242 _mesa_lookup_enum_by_nr(target
),
243 _mesa_get_format_name(format
),
244 first_level
, last_level
, depth0
, mt
);
246 if (target
== GL_TEXTURE_1D_ARRAY
) {
247 /* For a 1D Array texture the OpenGL API will treat the height0
248 * parameter as the number of array slices. For Intel hardware, we treat
249 * the 1D array as a 2D Array with a height of 1.
251 * So, when we first come through this path to create a 1D Array
252 * texture, height0 stores the number of slices, and depth0 is 1. In
253 * this case, we want to swap height0 and depth0.
255 * Since some miptrees will be created based on the base miptree, we may
256 * come through this path and see height0 as 1 and depth0 being the
257 * number of slices. In this case we don't need to do the swap.
259 assert(height0
== 1 || depth0
== 1);
268 mt
->first_level
= first_level
;
269 mt
->last_level
= last_level
;
270 mt
->logical_width0
= width0
;
271 mt
->logical_height0
= height0
;
272 mt
->logical_depth0
= depth0
;
273 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
274 exec_list_make_empty(&mt
->hiz_map
);
276 /* The cpp is bytes per (1, blockheight)-sized block for compressed
277 * textures. This is why you'll see divides by blockheight all over
280 _mesa_get_format_block_size(format
, &bw
, &bh
);
281 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
282 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
284 mt
->num_samples
= num_samples
;
285 mt
->compressed
= _mesa_is_format_compressed(format
);
286 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
289 if (num_samples
> 1) {
290 /* Adjust width/height/depth for MSAA */
291 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
292 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
293 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
294 * "If the surface is multisampled and it is a depth or stencil
295 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
296 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
299 * +----------------------------------------------------------------+
300 * | Num Multisamples | W_l = | H_l = |
301 * +----------------------------------------------------------------+
302 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
303 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
304 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
305 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
306 * +----------------------------------------------------------------+
309 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
310 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
311 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
313 * Another more complicated explanation for these adjustments comes
314 * from the Sandybridge PRM, volume 4, part 1, page 31:
316 * "Any of the other messages (sample*, LOD, load4) used with a
317 * (4x) multisampled surface will in-effect sample a surface with
318 * double the height and width as that indicated in the surface
319 * state. Each pixel position on the original-sized surface is
320 * replaced with a 2x2 of samples with the following arrangement:
325 * Thus, when sampling from a multisampled texture, it behaves as
326 * though the layout in memory for (x,y,sample) is:
328 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
329 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
331 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
332 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
334 * However, the actual layout of multisampled data in memory is:
336 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
337 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
339 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
340 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
342 * This pattern repeats for each 2x2 pixel block.
344 * As a result, when calculating the size of our 4-sample buffer for
345 * an odd width or height, we have to align before scaling up because
346 * sample 3 is in that bottom right 2x2 block.
348 switch (num_samples
) {
350 assert(brw
->gen
>= 8);
351 width0
= ALIGN(width0
, 2) * 2;
352 height0
= ALIGN(height0
, 2);
355 width0
= ALIGN(width0
, 2) * 2;
356 height0
= ALIGN(height0
, 2) * 2;
359 width0
= ALIGN(width0
, 2) * 4;
360 height0
= ALIGN(height0
, 2) * 2;
363 /* num_samples should already have been quantized to 0, 1, 2, 4, or
366 unreachable("not reached");
369 /* Non-interleaved */
370 depth0
*= num_samples
;
374 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
375 * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
376 * TODO: can we use it elsewhere?
378 switch (mt
->msaa_layout
) {
379 case INTEL_MSAA_LAYOUT_NONE
:
380 case INTEL_MSAA_LAYOUT_IMS
:
381 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
383 case INTEL_MSAA_LAYOUT_UMS
:
384 case INTEL_MSAA_LAYOUT_CMS
:
385 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
389 if (target
== GL_TEXTURE_CUBE_MAP
) {
394 mt
->physical_width0
= width0
;
395 mt
->physical_height0
= height0
;
396 mt
->physical_depth0
= depth0
;
399 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
400 (brw
->must_use_separate_stencil
||
401 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
402 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
403 mt
->stencil_mt
= intel_miptree_create(brw
,
413 INTEL_MIPTREE_TILING_ANY
,
414 force_all_slices_at_each_lod
);
415 if (!mt
->stencil_mt
) {
416 intel_miptree_release(&mt
);
420 /* Fix up the Z miptree format for how we're splitting out separate
421 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
423 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
426 if (format
== mt
->format
) {
427 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
428 _mesa_get_format_name(mt
->format
));
432 if (force_all_slices_at_each_lod
)
433 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
435 brw_miptree_layout(brw
, mt
);
441 * \brief Helper function for intel_miptree_create().
444 intel_miptree_choose_tiling(struct brw_context
*brw
,
447 uint32_t num_samples
,
448 enum intel_miptree_tiling_mode requested
,
449 struct intel_mipmap_tree
*mt
)
451 if (format
== MESA_FORMAT_S_UINT8
) {
452 /* The stencil buffer is W tiled. However, we request from the kernel a
453 * non-tiled buffer because the GTT is incapable of W fencing.
455 return I915_TILING_NONE
;
458 /* Some usages may want only one type of tiling, like depth miptrees (Y
459 * tiled), or temporary BOs for uploading data once (linear).
462 case INTEL_MIPTREE_TILING_ANY
:
464 case INTEL_MIPTREE_TILING_Y
:
465 return I915_TILING_Y
;
466 case INTEL_MIPTREE_TILING_NONE
:
467 return I915_TILING_NONE
;
470 if (num_samples
> 1) {
471 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
474 * [DevSNB+]: For multi-sample render targets, this field must be
475 * 1. MSRTs can only be tiled.
477 * Our usual reason for preferring X tiling (fast blits using the
478 * blitting engine) doesn't apply to MSAA, since we'll generally be
479 * downsampling or upsampling when blitting between the MSAA buffer
480 * and another buffer, and the blitting engine doesn't support that.
481 * So use Y tiling, since it makes better use of the cache.
483 return I915_TILING_Y
;
486 GLenum base_format
= _mesa_get_format_base_format(format
);
487 if (base_format
== GL_DEPTH_COMPONENT
||
488 base_format
== GL_DEPTH_STENCIL_EXT
)
489 return I915_TILING_Y
;
491 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
492 * in fact it leads to a less efficient use of memory space and bandwidth
493 * due to tile alignment.
495 if (mt
->logical_height0
== 1)
496 return I915_TILING_NONE
;
498 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
500 /* If the width is much smaller than a tile, don't bother tiling. */
501 if (minimum_pitch
< 64)
502 return I915_TILING_NONE
;
504 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
505 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
506 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
507 mt
->total_width
, mt
->total_height
);
508 return I915_TILING_NONE
;
511 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
513 return I915_TILING_X
;
515 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
516 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
518 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
519 * all the way back to 965, but is permitted on Gen7+.
521 if (brw
->gen
< 7 && mt
->cpp
>= 16)
522 return I915_TILING_X
;
524 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
525 * messages), on p64, under the heading "Surface Vertical Alignment":
527 * This field must be set to VALIGN_4 for all tiled Y Render Target
530 * So if the surface is renderable and uses a vertical alignment of 2,
531 * force it to be X tiled. This is somewhat conservative (it's possible
532 * that the client won't ever render to this surface), but it's difficult
533 * to know that ahead of time. And besides, since we use a vertical
534 * alignment of 4 as often as we can, this shouldn't happen very often.
536 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
537 brw
->format_supported_as_render_target
[format
]) {
538 return I915_TILING_X
;
541 return I915_TILING_Y
| I915_TILING_X
;
546 * Choose an appropriate uncompressed format for a requested
547 * compressed format, if unsupported.
550 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
552 /* No need to lower ETC formats on these platforms,
553 * they are supported natively.
555 if (brw
->gen
>= 8 || brw
->is_baytrail
)
559 case MESA_FORMAT_ETC1_RGB8
:
560 return MESA_FORMAT_R8G8B8X8_UNORM
;
561 case MESA_FORMAT_ETC2_RGB8
:
562 return MESA_FORMAT_R8G8B8X8_UNORM
;
563 case MESA_FORMAT_ETC2_SRGB8
:
564 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
565 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
566 return MESA_FORMAT_B8G8R8A8_SRGB
;
567 case MESA_FORMAT_ETC2_RGBA8_EAC
:
568 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
569 return MESA_FORMAT_R8G8B8A8_UNORM
;
570 case MESA_FORMAT_ETC2_R11_EAC
:
571 return MESA_FORMAT_R_UNORM16
;
572 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
573 return MESA_FORMAT_R_SNORM16
;
574 case MESA_FORMAT_ETC2_RG11_EAC
:
575 return MESA_FORMAT_R16G16_UNORM
;
576 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
577 return MESA_FORMAT_R16G16_SNORM
;
579 /* Non ETC1 / ETC2 format */
585 struct intel_mipmap_tree
*
586 intel_miptree_create(struct brw_context
*brw
,
594 bool expect_accelerated_upload
,
596 enum intel_miptree_tiling_mode requested_tiling
,
597 bool force_all_slices_at_each_lod
)
599 struct intel_mipmap_tree
*mt
;
600 mesa_format tex_format
= format
;
601 mesa_format etc_format
= MESA_FORMAT_NONE
;
602 GLuint total_width
, total_height
;
604 format
= intel_lower_compressed_format(brw
, format
);
606 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
608 mt
= intel_miptree_create_layout(brw
, target
, format
,
609 first_level
, last_level
, width0
,
612 force_all_slices_at_each_lod
);
614 * pitch == 0 || height == 0 indicates the null texture
616 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
617 intel_miptree_release(&mt
);
621 total_width
= mt
->total_width
;
622 total_height
= mt
->total_height
;
624 if (format
== MESA_FORMAT_S_UINT8
) {
625 /* Align to size of W tile, 64x64. */
626 total_width
= ALIGN(total_width
, 64);
627 total_height
= ALIGN(total_height
, 64);
630 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
631 num_samples
, requested_tiling
,
635 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
637 mt
->tiling
= I915_TILING_Y
;
643 mt
->etc_format
= etc_format
;
644 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
645 total_width
, total_height
, mt
->cpp
,
647 (expect_accelerated_upload
?
648 BO_ALLOC_FOR_RENDER
: 0));
651 /* If the BO is too large to fit in the aperture, we need to use the
652 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
653 * handle Y-tiling, so we need to fall back to X.
655 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
656 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
657 mt
->total_width
, mt
->total_height
);
659 mt
->tiling
= I915_TILING_X
;
660 drm_intel_bo_unreference(mt
->bo
);
661 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
662 total_width
, total_height
, mt
->cpp
,
664 (expect_accelerated_upload
?
665 BO_ALLOC_FOR_RENDER
: 0));
672 intel_miptree_release(&mt
);
677 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
678 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
679 intel_miptree_release(&mt
);
684 /* If this miptree is capable of supporting fast color clears, set
685 * fast_clear_state appropriately to ensure that fast clears will occur.
686 * Allocation of the MCS miptree will be deferred until the first fast
687 * clear actually occurs.
689 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
690 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
695 struct intel_mipmap_tree
*
696 intel_miptree_create_for_bo(struct brw_context
*brw
,
705 struct intel_mipmap_tree
*mt
;
706 uint32_t tiling
, swizzle
;
709 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
711 /* Nothing will be able to use this miptree with the BO if the offset isn't
714 if (tiling
!= I915_TILING_NONE
)
715 assert(offset
% 4096 == 0);
717 /* miptrees can't handle negative pitch. If you need flipping of images,
718 * that's outside of the scope of the mt.
722 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
724 mt
= intel_miptree_create_layout(brw
, target
, format
,
726 width
, height
, depth
,
733 drm_intel_bo_reference(bo
);
743 * For a singlesample renderbuffer, this simply wraps the given BO with a
746 * For a multisample renderbuffer, this wraps the window system's
747 * (singlesample) BO with a singlesample miptree attached to the
748 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
749 * that will contain the actual rendering (which is lazily resolved to
750 * irb->singlesample_mt).
753 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
754 struct intel_renderbuffer
*irb
,
756 uint32_t width
, uint32_t height
,
759 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
760 struct intel_mipmap_tree
*multisample_mt
= NULL
;
761 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
762 mesa_format format
= rb
->Format
;
763 int num_samples
= rb
->NumSamples
;
765 /* Only the front and back buffers, which are color buffers, are allocated
766 * through the image loader.
768 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
769 _mesa_get_format_base_format(format
) == GL_RGBA
);
771 singlesample_mt
= intel_miptree_create_for_bo(intel
,
779 if (!singlesample_mt
)
782 /* If this miptree is capable of supporting fast color clears, set
783 * mcs_state appropriately to ensure that fast clears will occur.
784 * Allocation of the MCS miptree will be deferred until the first fast
785 * clear actually occurs.
787 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
788 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
790 if (num_samples
== 0) {
791 intel_miptree_release(&irb
->mt
);
792 irb
->mt
= singlesample_mt
;
794 assert(!irb
->singlesample_mt
);
796 intel_miptree_release(&irb
->singlesample_mt
);
797 irb
->singlesample_mt
= singlesample_mt
;
800 irb
->mt
->logical_width0
!= width
||
801 irb
->mt
->logical_height0
!= height
) {
802 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
810 irb
->need_downsample
= false;
811 intel_miptree_release(&irb
->mt
);
812 irb
->mt
= multisample_mt
;
818 intel_miptree_release(&irb
->singlesample_mt
);
819 intel_miptree_release(&irb
->mt
);
823 struct intel_mipmap_tree
*
824 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
828 uint32_t num_samples
)
830 struct intel_mipmap_tree
*mt
;
833 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
835 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
836 width
, height
, depth
, true, num_samples
,
837 INTEL_MIPTREE_TILING_ANY
, false);
841 if (brw_is_hiz_depth_format(brw
, format
)) {
842 ok
= intel_miptree_alloc_hiz(brw
, mt
);
850 intel_miptree_release(&mt
);
855 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
856 struct intel_mipmap_tree
*src
)
861 intel_miptree_release(dst
);
865 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
873 intel_miptree_release(struct intel_mipmap_tree
**mt
)
878 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
879 if (--(*mt
)->refcount
<= 0) {
882 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
884 drm_intel_bo_unreference((*mt
)->bo
);
885 intel_miptree_release(&(*mt
)->stencil_mt
);
886 if ((*mt
)->hiz_buf
) {
887 if ((*mt
)->hiz_buf
->mt
)
888 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
890 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
891 free((*mt
)->hiz_buf
);
893 intel_miptree_release(&(*mt
)->mcs_mt
);
894 intel_resolve_map_clear(&(*mt
)->hiz_map
);
896 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
897 free((*mt
)->level
[i
].slice
);
906 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
907 int *width
, int *height
, int *depth
)
909 switch (image
->TexObject
->Target
) {
910 case GL_TEXTURE_1D_ARRAY
:
911 *width
= image
->Width
;
913 *depth
= image
->Height
;
916 *width
= image
->Width
;
917 *height
= image
->Height
;
918 *depth
= image
->Depth
;
924 * Can the image be pulled into a unified mipmap tree? This mirrors
925 * the completeness test in a lot of ways.
927 * Not sure whether I want to pass gl_texture_image here.
930 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
931 struct gl_texture_image
*image
)
933 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
934 GLuint level
= intelImage
->base
.Base
.Level
;
935 int width
, height
, depth
;
937 /* glTexImage* choose the texture object based on the target passed in, and
938 * objects can't change targets over their lifetimes, so this should be
941 assert(image
->TexObject
->Target
== mt
->target
);
943 mesa_format mt_format
= mt
->format
;
944 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
945 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
946 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
947 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
948 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
949 mt_format
= mt
->etc_format
;
951 if (image
->TexFormat
!= mt_format
)
954 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
956 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
959 int level_depth
= mt
->level
[level
].depth
;
960 if (mt
->num_samples
> 1) {
961 switch (mt
->msaa_layout
) {
962 case INTEL_MSAA_LAYOUT_NONE
:
963 case INTEL_MSAA_LAYOUT_IMS
:
965 case INTEL_MSAA_LAYOUT_UMS
:
966 case INTEL_MSAA_LAYOUT_CMS
:
967 level_depth
/= mt
->num_samples
;
972 /* Test image dimensions against the base level image adjusted for
973 * minification. This will also catch images not present in the
974 * tree, changed targets, etc.
976 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
977 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
978 depth
!= level_depth
) {
982 if (image
->NumSamples
!= mt
->num_samples
)
990 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
992 GLuint x
, GLuint y
, GLuint d
)
994 mt
->level
[level
].depth
= d
;
995 mt
->level
[level
].level_x
= x
;
996 mt
->level
[level
].level_y
= y
;
998 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
1001 assert(mt
->level
[level
].slice
== NULL
);
1003 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1004 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1005 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1010 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1011 GLuint level
, GLuint img
,
1014 if (img
== 0 && level
== 0)
1015 assert(x
== 0 && y
== 0);
1017 assert(img
< mt
->level
[level
].depth
);
1019 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1020 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1022 DBG("%s level %d img %d pos %d,%d\n",
1023 __FUNCTION__
, level
, img
,
1024 mt
->level
[level
].slice
[img
].x_offset
,
1025 mt
->level
[level
].slice
[img
].y_offset
);
1029 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1030 GLuint level
, GLuint slice
,
1031 GLuint
*x
, GLuint
*y
)
1033 assert(slice
< mt
->level
[level
].depth
);
1035 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1036 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1040 * This function computes masks that may be used to select the bits of the X
1041 * and Y coordinates that indicate the offset within a tile. If the BO is
1042 * untiled, the masks are set to 0.
1045 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1046 uint32_t *mask_x
, uint32_t *mask_y
,
1047 bool map_stencil_as_y_tiled
)
1050 uint32_t tiling
= mt
->tiling
;
1052 if (map_stencil_as_y_tiled
)
1053 tiling
= I915_TILING_Y
;
1057 unreachable("not reached");
1058 case I915_TILING_NONE
:
1059 *mask_x
= *mask_y
= 0;
1062 *mask_x
= 512 / cpp
- 1;
1066 *mask_x
= 128 / cpp
- 1;
1073 * Compute the offset (in bytes) from the start of the BO to the given x
1074 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1075 * multiples of the tile size.
1078 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1079 uint32_t x
, uint32_t y
,
1080 bool map_stencil_as_y_tiled
)
1083 uint32_t pitch
= mt
->pitch
;
1084 uint32_t tiling
= mt
->tiling
;
1086 if (map_stencil_as_y_tiled
) {
1087 tiling
= I915_TILING_Y
;
1089 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1090 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1091 * the resulting surface is twice the pitch of the original miptree,
1092 * since each row in the Y-tiled view corresponds to two rows in the
1093 * actual W-tiled surface. So we need to correct the pitch before
1094 * computing the offsets.
1101 unreachable("not reached");
1102 case I915_TILING_NONE
:
1103 return y
* pitch
+ x
* cpp
;
1105 assert((x
% (512 / cpp
)) == 0);
1106 assert((y
% 8) == 0);
1107 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1109 assert((x
% (128 / cpp
)) == 0);
1110 assert((y
% 32) == 0);
1111 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1116 * Rendering with tiled buffers requires that the base address of the buffer
1117 * be aligned to a page boundary. For renderbuffers, and sometimes with
1118 * textures, we may want the surface to point at a texture image level that
1119 * isn't at a page boundary.
1121 * This function returns an appropriately-aligned base offset
1122 * according to the tiling restrictions, plus any required x/y offset
1126 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1127 GLuint level
, GLuint slice
,
1132 uint32_t mask_x
, mask_y
;
1134 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1135 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1137 *tile_x
= x
& mask_x
;
1138 *tile_y
= y
& mask_y
;
1140 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1144 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1145 struct intel_mipmap_tree
*dst_mt
,
1146 struct intel_mipmap_tree
*src_mt
,
1153 ptrdiff_t src_stride
, dst_stride
;
1154 int cpp
= dst_mt
->cpp
;
1156 intel_miptree_map(brw
, src_mt
,
1160 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1163 intel_miptree_map(brw
, dst_mt
,
1167 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1171 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1172 _mesa_get_format_name(src_mt
->format
),
1173 src_mt
, src
, src_stride
,
1174 _mesa_get_format_name(dst_mt
->format
),
1175 dst_mt
, dst
, dst_stride
,
1178 int row_size
= cpp
* width
;
1179 if (src_stride
== row_size
&&
1180 dst_stride
== row_size
) {
1181 memcpy(dst
, src
, row_size
* height
);
1183 for (int i
= 0; i
< height
; i
++) {
1184 memcpy(dst
, src
, row_size
);
1190 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1191 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1193 /* Don't forget to copy the stencil data over, too. We could have skipped
1194 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1195 * shuffling the two data sources in/out of temporary storage instead of
1196 * the direct mapping we get this way.
1198 if (dst_mt
->stencil_mt
) {
1199 assert(src_mt
->stencil_mt
);
1200 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1201 level
, slice
, width
, height
);
1206 intel_miptree_copy_slice(struct brw_context
*brw
,
1207 struct intel_mipmap_tree
*dst_mt
,
1208 struct intel_mipmap_tree
*src_mt
,
1214 mesa_format format
= src_mt
->format
;
1215 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1216 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1224 assert(depth
< src_mt
->level
[level
].depth
);
1225 assert(src_mt
->format
== dst_mt
->format
);
1227 if (dst_mt
->compressed
) {
1228 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1229 width
= ALIGN(width
, dst_mt
->align_w
);
1232 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1233 * below won't apply since we can't do the depth's Y tiling or the
1234 * stencil's W tiling in the blitter.
1236 if (src_mt
->stencil_mt
) {
1237 intel_miptree_copy_slice_sw(brw
,
1244 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1245 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1246 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1248 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1249 _mesa_get_format_name(src_mt
->format
),
1250 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1251 _mesa_get_format_name(dst_mt
->format
),
1252 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1255 if (!intel_miptree_blit(brw
,
1256 src_mt
, level
, slice
, 0, 0, false,
1257 dst_mt
, level
, slice
, 0, 0, false,
1258 width
, height
, GL_COPY
)) {
1259 perf_debug("miptree validate blit for %s failed\n",
1260 _mesa_get_format_name(format
));
1262 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1268 * Copies the image's current data to the given miptree, and associates that
1269 * miptree with the image.
1271 * If \c invalidate is true, then the actual image data does not need to be
1272 * copied, but the image still needs to be associated to the new miptree (this
1273 * is set to true if we're about to clear the image).
1276 intel_miptree_copy_teximage(struct brw_context
*brw
,
1277 struct intel_texture_image
*intelImage
,
1278 struct intel_mipmap_tree
*dst_mt
,
1281 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1282 struct intel_texture_object
*intel_obj
=
1283 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1284 int level
= intelImage
->base
.Base
.Level
;
1285 int face
= intelImage
->base
.Base
.Face
;
1288 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1289 depth
= intelImage
->base
.Base
.Height
;
1291 depth
= intelImage
->base
.Base
.Depth
;
1294 for (int slice
= 0; slice
< depth
; slice
++) {
1295 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1299 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1300 intel_obj
->needs_validate
= true;
1304 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1305 struct intel_mipmap_tree
*mt
,
1308 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1309 assert(mt
->mcs_mt
== NULL
);
1311 /* Choose the correct format for the MCS buffer. All that really matters
1312 * is that we allocate the right buffer size, since we'll always be
1313 * accessing this miptree using MCS-specific hardware mechanisms, which
1314 * infer the correct format based on num_samples.
1317 switch (num_samples
) {
1320 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1323 format
= MESA_FORMAT_R_UNORM8
;
1326 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1327 * for each sample, plus 8 padding bits).
1329 format
= MESA_FORMAT_R_UINT32
;
1332 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1335 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1337 * "The MCS surface must be stored as Tile Y."
1339 mt
->mcs_mt
= intel_miptree_create(brw
,
1345 mt
->logical_height0
,
1348 0 /* num_samples */,
1349 INTEL_MIPTREE_TILING_Y
,
1352 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1354 * When MCS buffer is enabled and bound to MSRT, it is required that it
1355 * is cleared prior to any rendering.
1357 * Since we don't use the MCS buffer for any purpose other than rendering,
1358 * it makes sense to just clear it immediately upon allocation.
1360 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1362 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1363 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1364 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1365 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1372 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1373 struct intel_mipmap_tree
*mt
)
1375 assert(mt
->mcs_mt
== NULL
);
1377 /* The format of the MCS buffer is opaque to the driver; all that matters
1378 * is that we get its size and pitch right. We'll pretend that the format
1379 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1380 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1381 * the block width and then a further factor of 4. Since an MCS tile
1382 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1383 * we'll need to scale the height down by the block height and then a
1384 * further factor of 8.
1386 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1387 unsigned block_width_px
;
1388 unsigned block_height
;
1389 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1390 unsigned width_divisor
= block_width_px
* 4;
1391 unsigned height_divisor
= block_height
* 8;
1392 unsigned mcs_width
=
1393 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1394 unsigned mcs_height
=
1395 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1396 assert(mt
->logical_depth0
== 1);
1397 mt
->mcs_mt
= intel_miptree_create(brw
,
1406 0 /* num_samples */,
1407 INTEL_MIPTREE_TILING_Y
,
1415 * Helper for intel_miptree_alloc_hiz() that sets
1416 * \c mt->level[level].has_hiz. Return true if and only if
1417 * \c has_hiz was set.
1420 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1421 struct intel_mipmap_tree
*mt
,
1424 assert(mt
->hiz_buf
);
1426 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1427 uint32_t width
= minify(mt
->physical_width0
, level
);
1428 uint32_t height
= minify(mt
->physical_height0
, level
);
1430 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1431 * and the height is 4 aligned. This allows our HiZ support
1432 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1433 * we can grow the width & height to allow the HiZ op to
1434 * force the proper size alignments.
1436 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1437 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1442 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1443 mt
->level
[level
].has_hiz
= true;
1449 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1450 * buffer dimensions and allocates a bo for the hiz buffer.
1452 static struct intel_miptree_aux_buffer
*
1453 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1454 struct intel_mipmap_tree
*mt
)
1456 unsigned z_width
= mt
->logical_width0
;
1457 unsigned z_height
= mt
->logical_height0
;
1458 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1459 unsigned hz_width
, hz_height
;
1460 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1465 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1466 * adjustments required for Z_Height and Z_Width based on multisampling.
1468 switch (mt
->num_samples
) {
1482 unreachable("unsupported sample count");
1485 const unsigned vertical_align
= 8; /* 'j' in the docs */
1486 const unsigned H0
= z_height
;
1487 const unsigned h0
= ALIGN(H0
, vertical_align
);
1488 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1489 const unsigned Z0
= z_depth
;
1491 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1492 hz_width
= ALIGN(z_width
, 16);
1494 if (mt
->target
== GL_TEXTURE_3D
) {
1498 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1499 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1500 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1501 hz_height
+= h_i
* Z_i
;
1502 H_i
= minify(H_i
, 1);
1503 Z_i
= minify(Z_i
, 1);
1506 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1508 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1510 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1511 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1512 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1513 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1514 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1516 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1517 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1521 unsigned long pitch
;
1522 uint32_t tiling
= I915_TILING_Y
;
1523 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1524 hz_width
, hz_height
, 1,
1526 BO_ALLOC_FOR_RENDER
);
1530 } else if (tiling
!= I915_TILING_Y
) {
1531 drm_intel_bo_unreference(buf
->bo
);
1542 static struct intel_miptree_aux_buffer
*
1543 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1544 struct intel_mipmap_tree
*mt
)
1546 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1547 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1552 buf
->mt
= intel_miptree_create(brw
,
1558 mt
->logical_height0
,
1562 INTEL_MIPTREE_TILING_ANY
,
1563 force_all_slices_at_each_lod
);
1569 buf
->bo
= buf
->mt
->bo
;
1570 buf
->pitch
= buf
->mt
->pitch
;
1571 buf
->qpitch
= buf
->mt
->qpitch
;
1578 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1579 struct intel_mipmap_tree
*mt
)
1581 assert(mt
->hiz_buf
== NULL
);
1583 if (brw
->gen
== 7) {
1584 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1586 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1592 /* Mark that all slices need a HiZ resolve. */
1593 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1594 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1597 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1598 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1599 exec_node_init(&m
->link
);
1602 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1604 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1612 * Does the miptree slice have hiz enabled?
1615 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1617 intel_miptree_check_level_layer(mt
, level
, 0);
1618 return mt
->level
[level
].has_hiz
;
1622 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1626 if (!intel_miptree_level_has_hiz(mt
, level
))
1629 intel_resolve_map_set(&mt
->hiz_map
,
1630 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1635 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1639 if (!intel_miptree_level_has_hiz(mt
, level
))
1642 intel_resolve_map_set(&mt
->hiz_map
,
1643 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1647 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1651 uint32_t end_layer
= mt
->level
[level
].depth
;
1653 for (layer
= 0; layer
< end_layer
; layer
++) {
1654 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1659 intel_miptree_slice_resolve(struct brw_context
*brw
,
1660 struct intel_mipmap_tree
*mt
,
1663 enum gen6_hiz_op need
)
1665 intel_miptree_check_level_layer(mt
, level
, layer
);
1667 struct intel_resolve_map
*item
=
1668 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1670 if (!item
|| item
->need
!= need
)
1673 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1674 intel_resolve_map_remove(item
);
1679 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1680 struct intel_mipmap_tree
*mt
,
1684 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1685 GEN6_HIZ_OP_HIZ_RESOLVE
);
1689 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1690 struct intel_mipmap_tree
*mt
,
1694 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1695 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1699 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1700 struct intel_mipmap_tree
*mt
,
1701 enum gen6_hiz_op need
)
1703 bool did_resolve
= false;
1705 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1706 if (map
->need
!= need
)
1709 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1710 intel_resolve_map_remove(map
);
1718 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1719 struct intel_mipmap_tree
*mt
)
1721 return intel_miptree_all_slices_resolve(brw
, mt
,
1722 GEN6_HIZ_OP_HIZ_RESOLVE
);
1726 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1727 struct intel_mipmap_tree
*mt
)
1729 return intel_miptree_all_slices_resolve(brw
, mt
,
1730 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1735 intel_miptree_resolve_color(struct brw_context
*brw
,
1736 struct intel_mipmap_tree
*mt
)
1738 switch (mt
->fast_clear_state
) {
1739 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1740 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1741 /* No resolve needed */
1743 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1744 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1745 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1746 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1747 brw_meta_resolve_color(brw
, mt
);
1754 * Make it possible to share the BO backing the given miptree with another
1755 * process or another miptree.
1757 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1758 * then discard the MCS buffer, if present. We also set the fast_clear_state
1759 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1760 * allocated in the future.
1763 intel_miptree_make_shareable(struct brw_context
*brw
,
1764 struct intel_mipmap_tree
*mt
)
1766 /* MCS buffers are also used for multisample buffers, but we can't resolve
1767 * away a multisample MCS buffer because it's an integral part of how the
1768 * pixel data is stored. Fortunately this code path should never be
1769 * reached for multisample buffers.
1771 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1774 intel_miptree_resolve_color(brw
, mt
);
1775 intel_miptree_release(&mt
->mcs_mt
);
1776 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1782 * \brief Get pointer offset into stencil buffer.
1784 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1785 * must decode the tile's layout in software.
1788 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1790 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1792 * Even though the returned offset is always positive, the return type is
1794 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1795 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1798 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1800 uint32_t tile_size
= 4096;
1801 uint32_t tile_width
= 64;
1802 uint32_t tile_height
= 64;
1803 uint32_t row_size
= 64 * stride
;
1805 uint32_t tile_x
= x
/ tile_width
;
1806 uint32_t tile_y
= y
/ tile_height
;
1808 /* The byte's address relative to the tile's base addres. */
1809 uint32_t byte_x
= x
% tile_width
;
1810 uint32_t byte_y
= y
% tile_height
;
1812 uintptr_t u
= tile_y
* row_size
1813 + tile_x
* tile_size
1814 + 512 * (byte_x
/ 8)
1816 + 32 * ((byte_y
/ 4) % 2)
1817 + 16 * ((byte_x
/ 4) % 2)
1818 + 8 * ((byte_y
/ 2) % 2)
1819 + 4 * ((byte_x
/ 2) % 2)
1824 /* adjust for bit6 swizzling */
1825 if (((byte_x
/ 8) % 2) == 1) {
1826 if (((byte_y
/ 8) % 2) == 0) {
1838 intel_miptree_updownsample(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*src
,
1840 struct intel_mipmap_tree
*dst
)
1843 brw_blorp_blit_miptrees(brw
,
1844 src
, 0 /* level */, 0 /* layer */, src
->format
,
1845 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
1847 src
->logical_width0
, src
->logical_height0
,
1849 dst
->logical_width0
, dst
->logical_height0
,
1850 GL_NEAREST
, false, false /*mirror x, y*/);
1851 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1852 brw_meta_stencil_updownsample(brw
, src
, dst
);
1854 brw_meta_updownsample(brw
, src
, dst
);
1857 if (src
->stencil_mt
) {
1858 if (brw
->gen
>= 8) {
1859 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1863 brw_blorp_blit_miptrees(brw
,
1864 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1865 src
->stencil_mt
->format
,
1866 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1867 dst
->stencil_mt
->format
,
1869 src
->logical_width0
, src
->logical_height0
,
1871 dst
->logical_width0
, dst
->logical_height0
,
1872 GL_NEAREST
, false, false /*mirror x, y*/);
1877 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1879 /* CPU accesses to color buffers don't understand fast color clears, so
1880 * resolve any pending fast color clears before we map.
1882 intel_miptree_resolve_color(brw
, mt
);
1884 drm_intel_bo
*bo
= mt
->bo
;
1886 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1887 intel_batchbuffer_flush(brw
);
1889 if (mt
->tiling
!= I915_TILING_NONE
)
1890 brw_bo_map_gtt(brw
, bo
, "miptree");
1892 brw_bo_map(brw
, bo
, true, "miptree");
1898 intel_miptree_unmap_raw(struct brw_context
*brw
,
1899 struct intel_mipmap_tree
*mt
)
1901 drm_intel_bo_unmap(mt
->bo
);
1905 intel_miptree_map_gtt(struct brw_context
*brw
,
1906 struct intel_mipmap_tree
*mt
,
1907 struct intel_miptree_map
*map
,
1908 unsigned int level
, unsigned int slice
)
1910 unsigned int bw
, bh
;
1912 unsigned int image_x
, image_y
;
1913 intptr_t x
= map
->x
;
1914 intptr_t y
= map
->y
;
1916 /* For compressed formats, the stride is the number of bytes per
1917 * row of blocks. intel_miptree_get_image_offset() already does
1920 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1921 assert(y
% bh
== 0);
1924 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1929 /* Note that in the case of cube maps, the caller must have passed the
1930 * slice number referencing the face.
1932 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1936 map
->stride
= mt
->pitch
;
1937 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1940 DBG("%s: %d,%d %dx%d from mt %p (%s) "
1941 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __FUNCTION__
,
1942 map
->x
, map
->y
, map
->w
, map
->h
,
1943 mt
, _mesa_get_format_name(mt
->format
),
1944 x
, y
, map
->ptr
, map
->stride
);
1948 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1949 struct intel_mipmap_tree
*mt
,
1950 struct intel_miptree_map
*map
,
1954 intel_miptree_unmap_raw(brw
, mt
);
1958 intel_miptree_map_blit(struct brw_context
*brw
,
1959 struct intel_mipmap_tree
*mt
,
1960 struct intel_miptree_map
*map
,
1961 unsigned int level
, unsigned int slice
)
1963 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1967 INTEL_MIPTREE_TILING_NONE
,
1970 fprintf(stderr
, "Failed to allocate blit temporary\n");
1973 map
->stride
= map
->mt
->pitch
;
1975 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1976 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1977 * invalidate is set, since we'll be writing the whole rectangle from our
1978 * temporary buffer back out.
1980 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1981 if (!intel_miptree_blit(brw
,
1983 map
->x
, map
->y
, false,
1986 map
->w
, map
->h
, GL_COPY
)) {
1987 fprintf(stderr
, "Failed to blit\n");
1992 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1994 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1995 map
->x
, map
->y
, map
->w
, map
->h
,
1996 mt
, _mesa_get_format_name(mt
->format
),
1997 level
, slice
, map
->ptr
, map
->stride
);
2002 intel_miptree_release(&map
->mt
);
2008 intel_miptree_unmap_blit(struct brw_context
*brw
,
2009 struct intel_mipmap_tree
*mt
,
2010 struct intel_miptree_map
*map
,
2014 struct gl_context
*ctx
= &brw
->ctx
;
2016 intel_miptree_unmap_raw(brw
, map
->mt
);
2018 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2019 bool ok
= intel_miptree_blit(brw
,
2023 map
->x
, map
->y
, false,
2024 map
->w
, map
->h
, GL_COPY
);
2025 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2028 intel_miptree_release(&map
->mt
);
2032 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2034 #if defined(USE_SSE41)
2036 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2037 struct intel_mipmap_tree
*mt
,
2038 struct intel_miptree_map
*map
,
2039 unsigned int level
, unsigned int slice
)
2041 assert(map
->mode
& GL_MAP_READ_BIT
);
2042 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2044 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
2045 map
->x
, map
->y
, map
->w
, map
->h
,
2046 mt
, _mesa_get_format_name(mt
->format
),
2047 level
, slice
, map
->ptr
, map
->stride
);
2049 /* Map the original image */
2052 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2056 void *src
= intel_miptree_map_raw(brw
, mt
);
2059 src
+= image_y
* mt
->pitch
;
2060 src
+= image_x
* mt
->cpp
;
2062 /* Due to the pixel offsets for the particular image being mapped, our
2063 * src pointer may not be 16-byte aligned. However, if the pitch is
2064 * divisible by 16, then the amount by which it's misaligned will remain
2065 * consistent from row to row.
2067 assert((mt
->pitch
% 16) == 0);
2068 const int misalignment
= ((uintptr_t) src
) & 15;
2070 /* Create an untiled temporary buffer for the mapping. */
2071 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2073 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2075 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2076 /* Offset the destination so it has the same misalignment as src. */
2077 map
->ptr
= map
->buffer
+ misalignment
;
2079 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2081 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2082 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2083 void *src_ptr
= src
+ y
* mt
->pitch
;
2085 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2088 intel_miptree_unmap_raw(brw
, mt
);
2092 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2093 struct intel_mipmap_tree
*mt
,
2094 struct intel_miptree_map
*map
,
2098 _mesa_align_free(map
->buffer
);
2105 intel_miptree_map_s8(struct brw_context
*brw
,
2106 struct intel_mipmap_tree
*mt
,
2107 struct intel_miptree_map
*map
,
2108 unsigned int level
, unsigned int slice
)
2110 map
->stride
= map
->w
;
2111 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2115 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2116 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2117 * invalidate is set, since we'll be writing the whole rectangle from our
2118 * temporary buffer back out.
2120 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2121 uint8_t *untiled_s8_map
= map
->ptr
;
2122 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2123 unsigned int image_x
, image_y
;
2125 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2127 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2128 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2129 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2130 x
+ image_x
+ map
->x
,
2131 y
+ image_y
+ map
->y
,
2132 brw
->has_swizzling
);
2133 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2137 intel_miptree_unmap_raw(brw
, mt
);
2139 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
2140 map
->x
, map
->y
, map
->w
, map
->h
,
2141 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2143 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2144 map
->x
, map
->y
, map
->w
, map
->h
,
2145 mt
, map
->ptr
, map
->stride
);
2150 intel_miptree_unmap_s8(struct brw_context
*brw
,
2151 struct intel_mipmap_tree
*mt
,
2152 struct intel_miptree_map
*map
,
2156 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2157 unsigned int image_x
, image_y
;
2158 uint8_t *untiled_s8_map
= map
->ptr
;
2159 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2161 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2163 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2164 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2165 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2168 brw
->has_swizzling
);
2169 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2173 intel_miptree_unmap_raw(brw
, mt
);
2180 intel_miptree_map_etc(struct brw_context
*brw
,
2181 struct intel_mipmap_tree
*mt
,
2182 struct intel_miptree_map
*map
,
2186 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2187 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2188 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2191 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2192 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2194 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2195 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2196 map
->w
, map
->h
, 1));
2197 map
->ptr
= map
->buffer
;
2201 intel_miptree_unmap_etc(struct brw_context
*brw
,
2202 struct intel_mipmap_tree
*mt
,
2203 struct intel_miptree_map
*map
,
2209 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2214 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2215 + image_y
* mt
->pitch
2216 + image_x
* mt
->cpp
;
2218 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2219 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2220 map
->ptr
, map
->stride
,
2223 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2224 map
->ptr
, map
->stride
,
2225 map
->w
, map
->h
, mt
->etc_format
);
2227 intel_miptree_unmap_raw(brw
, mt
);
2232 * Mapping function for packed depth/stencil miptrees backed by real separate
2233 * miptrees for depth and stencil.
2235 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2236 * separate from the depth buffer. Yet at the GL API level, we have to expose
2237 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2238 * be able to map that memory for texture storage and glReadPixels-type
2239 * operations. We give Mesa core that access by mallocing a temporary and
2240 * copying the data between the actual backing store and the temporary.
2243 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2244 struct intel_mipmap_tree
*mt
,
2245 struct intel_miptree_map
*map
,
2246 unsigned int level
, unsigned int slice
)
2248 struct intel_mipmap_tree
*z_mt
= mt
;
2249 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2250 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2251 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2253 map
->stride
= map
->w
* packed_bpp
;
2254 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2258 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2259 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2260 * invalidate is set, since we'll be writing the whole rectangle from our
2261 * temporary buffer back out.
2263 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2264 uint32_t *packed_map
= map
->ptr
;
2265 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2266 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2267 unsigned int s_image_x
, s_image_y
;
2268 unsigned int z_image_x
, z_image_y
;
2270 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2271 &s_image_x
, &s_image_y
);
2272 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2273 &z_image_x
, &z_image_y
);
2275 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2276 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2277 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2278 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2281 brw
->has_swizzling
);
2282 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2284 (map_x
+ z_image_x
));
2285 uint8_t s
= s_map
[s_offset
];
2286 uint32_t z
= z_map
[z_offset
];
2288 if (map_z32f_x24s8
) {
2289 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2290 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2292 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2297 intel_miptree_unmap_raw(brw
, s_mt
);
2298 intel_miptree_unmap_raw(brw
, z_mt
);
2300 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2302 map
->x
, map
->y
, map
->w
, map
->h
,
2303 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2304 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2305 map
->ptr
, map
->stride
);
2307 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2308 map
->x
, map
->y
, map
->w
, map
->h
,
2309 mt
, map
->ptr
, map
->stride
);
2314 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2315 struct intel_mipmap_tree
*mt
,
2316 struct intel_miptree_map
*map
,
2320 struct intel_mipmap_tree
*z_mt
= mt
;
2321 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2322 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2324 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2325 uint32_t *packed_map
= map
->ptr
;
2326 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2327 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2328 unsigned int s_image_x
, s_image_y
;
2329 unsigned int z_image_x
, z_image_y
;
2331 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2332 &s_image_x
, &s_image_y
);
2333 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2334 &z_image_x
, &z_image_y
);
2336 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2337 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2338 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2339 x
+ s_image_x
+ map
->x
,
2340 y
+ s_image_y
+ map
->y
,
2341 brw
->has_swizzling
);
2342 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2344 (x
+ z_image_x
+ map
->x
));
2346 if (map_z32f_x24s8
) {
2347 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2348 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2350 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2351 s_map
[s_offset
] = packed
>> 24;
2352 z_map
[z_offset
] = packed
;
2357 intel_miptree_unmap_raw(brw
, s_mt
);
2358 intel_miptree_unmap_raw(brw
, z_mt
);
2360 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2362 map
->x
, map
->y
, map
->w
, map
->h
,
2363 z_mt
, _mesa_get_format_name(z_mt
->format
),
2364 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2365 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2366 map
->ptr
, map
->stride
);
2373 * Create and attach a map to the miptree at (level, slice). Return the
2376 static struct intel_miptree_map
*
2377 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2386 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2391 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2392 mt
->level
[level
].slice
[slice
].map
= map
;
2404 * Release the map at (level, slice).
2407 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2411 struct intel_miptree_map
**map
;
2413 map
= &mt
->level
[level
].slice
[slice
].map
;
2419 can_blit_slice(struct intel_mipmap_tree
*mt
,
2420 unsigned int level
, unsigned int slice
)
2424 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2425 if (image_x
>= 32768 || image_y
>= 32768)
2428 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2429 if (mt
->pitch
>= 32768)
2436 use_intel_mipree_map_blit(struct brw_context
*brw
,
2437 struct intel_mipmap_tree
*mt
,
2443 /* It's probably not worth swapping to the blit ring because of
2444 * all the overhead involved.
2446 !(mode
& GL_MAP_WRITE_BIT
) &&
2448 (mt
->tiling
== I915_TILING_X
||
2449 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2450 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2451 can_blit_slice(mt
, level
, slice
))
2454 if (mt
->tiling
!= I915_TILING_NONE
&&
2455 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2456 assert(can_blit_slice(mt
, level
, slice
));
2464 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2465 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2466 * arithmetic overflow.
2468 * If you call this function and use \a out_stride, then you're doing pointer
2469 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2470 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2471 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2472 * which usually have type uint32_t or GLuint.
2475 intel_miptree_map(struct brw_context
*brw
,
2476 struct intel_mipmap_tree
*mt
,
2485 ptrdiff_t *out_stride
)
2487 struct intel_miptree_map
*map
;
2489 assert(mt
->num_samples
<= 1);
2491 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2498 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2499 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2500 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2503 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2504 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2505 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2506 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2507 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2508 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2509 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2510 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2511 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2512 #if defined(USE_SSE41)
2513 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2514 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2517 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2520 *out_ptr
= map
->ptr
;
2521 *out_stride
= map
->stride
;
2523 if (map
->ptr
== NULL
)
2524 intel_miptree_release_map(mt
, level
, slice
);
2528 intel_miptree_unmap(struct brw_context
*brw
,
2529 struct intel_mipmap_tree
*mt
,
2533 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2535 assert(mt
->num_samples
<= 1);
2540 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2541 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2543 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2544 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2545 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2546 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2547 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2548 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2549 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2550 } else if (map
->mt
) {
2551 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2552 #if defined(USE_SSE41)
2553 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2554 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2557 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2560 intel_miptree_release_map(mt
, level
, slice
);