2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return isl_format_supports_lossless_compression(&brw
->screen
->devinfo
,
271 /* On Gen9 support for color buffer compression was extended to single
272 * sampled surfaces. This is a helper considering both auxiliary buffer
273 * type and number of samples telling if the given miptree represents
274 * the new single sampled case - also called lossless compression.
277 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
278 const struct intel_mipmap_tree
*mt
)
280 /* Only available from Gen9 onwards. */
284 /* Compression always requires auxiliary buffer. */
288 /* Single sample compression is represented re-using msaa compression
289 * layout type: "Compressed Multisampled Surfaces".
291 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
294 /* And finally distinguish between msaa and single sample case. */
295 return mt
->num_samples
<= 1;
299 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
300 const struct intel_mipmap_tree
*mt
)
302 /* For now compression is only enabled for integer formats even though
303 * there exist supported floating point formats also. This is a heuristic
304 * decision based on current public benchmarks. In none of the cases these
305 * formats provided any improvement but a few cases were seen to regress.
306 * Hence these are left to to be enabled in the future when they are known
309 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
312 /* Fast clear mechanism and lossless compression go hand in hand. */
313 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
316 /* Fast clear can be also used to clear srgb surfaces by using equivalent
317 * linear format. This trick, however, can't be extended to be used with
318 * lossless compression and therefore a check is needed to see if the format
321 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
325 * Determine depth format corresponding to a depth+stencil format,
326 * for separate stencil.
329 intel_depth_format_for_depthstencil_format(mesa_format format
) {
331 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
332 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
333 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
334 return MESA_FORMAT_Z_FLOAT32
;
342 * @param for_bo Indicates that the caller is
343 * intel_miptree_create_for_bo(). If true, then do not create
346 static struct intel_mipmap_tree
*
347 intel_miptree_create_layout(struct brw_context
*brw
,
356 uint32_t layout_flags
)
358 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
362 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
363 _mesa_enum_to_string(target
),
364 _mesa_get_format_name(format
),
365 first_level
, last_level
, depth0
, mt
);
367 if (target
== GL_TEXTURE_1D_ARRAY
)
368 assert(height0
== 1);
372 mt
->first_level
= first_level
;
373 mt
->last_level
= last_level
;
374 mt
->logical_width0
= width0
;
375 mt
->logical_height0
= height0
;
376 mt
->logical_depth0
= depth0
;
377 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
378 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
379 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
380 exec_list_make_empty(&mt
->hiz_map
);
381 mt
->cpp
= _mesa_get_format_bytes(format
);
382 mt
->num_samples
= num_samples
;
383 mt
->compressed
= _mesa_is_format_compressed(format
);
384 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
387 int depth_multiply
= 1;
388 if (num_samples
> 1) {
389 /* Adjust width/height/depth for MSAA */
390 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
391 mt
->disable_aux_buffers
);
392 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
393 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
394 * "If the surface is multisampled and it is a depth or stencil
395 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
396 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
399 * +----------------------------------------------------------------+
400 * | Num Multisamples | W_l = | H_l = |
401 * +----------------------------------------------------------------+
402 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
403 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
404 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
405 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
406 * +----------------------------------------------------------------+
409 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
410 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
411 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
413 * Another more complicated explanation for these adjustments comes
414 * from the Sandybridge PRM, volume 4, part 1, page 31:
416 * "Any of the other messages (sample*, LOD, load4) used with a
417 * (4x) multisampled surface will in-effect sample a surface with
418 * double the height and width as that indicated in the surface
419 * state. Each pixel position on the original-sized surface is
420 * replaced with a 2x2 of samples with the following arrangement:
425 * Thus, when sampling from a multisampled texture, it behaves as
426 * though the layout in memory for (x,y,sample) is:
428 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
429 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
431 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
432 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
434 * However, the actual layout of multisampled data in memory is:
436 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
437 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
439 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
440 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
442 * This pattern repeats for each 2x2 pixel block.
444 * As a result, when calculating the size of our 4-sample buffer for
445 * an odd width or height, we have to align before scaling up because
446 * sample 3 is in that bottom right 2x2 block.
448 switch (num_samples
) {
450 assert(brw
->gen
>= 8);
451 width0
= ALIGN(width0
, 2) * 2;
452 height0
= ALIGN(height0
, 2);
455 width0
= ALIGN(width0
, 2) * 2;
456 height0
= ALIGN(height0
, 2) * 2;
459 width0
= ALIGN(width0
, 2) * 4;
460 height0
= ALIGN(height0
, 2) * 2;
463 width0
= ALIGN(width0
, 2) * 4;
464 height0
= ALIGN(height0
, 2) * 4;
467 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
470 unreachable("not reached");
473 /* Non-interleaved */
474 depth_multiply
= num_samples
;
475 depth0
*= depth_multiply
;
479 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
480 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
481 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
482 * used on Gen8 to make it pick a qpitch value which doesn't include space
483 * for the mipmaps. On Gen9 this is not necessary because it will
484 * automatically pick a packed qpitch value whenever mt->first_level ==
486 * TODO: can we use it elsewhere?
487 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
490 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
492 switch (mt
->msaa_layout
) {
493 case INTEL_MSAA_LAYOUT_NONE
:
494 case INTEL_MSAA_LAYOUT_IMS
:
495 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
497 case INTEL_MSAA_LAYOUT_UMS
:
498 case INTEL_MSAA_LAYOUT_CMS
:
499 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
504 if (target
== GL_TEXTURE_CUBE_MAP
)
505 assert(depth0
== 6 * depth_multiply
);
507 mt
->physical_width0
= width0
;
508 mt
->physical_height0
= height0
;
509 mt
->physical_depth0
= depth0
;
511 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
512 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
513 (brw
->must_use_separate_stencil
||
514 (brw
->has_separate_stencil
&&
515 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
516 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
518 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
519 MIPTREE_LAYOUT_TILING_ANY
;
522 mt
->stencil_mt
= intel_miptree_create(brw
,
533 if (!mt
->stencil_mt
) {
534 intel_miptree_release(&mt
);
537 mt
->stencil_mt
->r8stencil_needs_update
= true;
539 /* Fix up the Z miptree format for how we're splitting out separate
540 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
542 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
545 if (format
== mt
->format
) {
546 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
547 _mesa_get_format_name(mt
->format
));
551 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
552 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
555 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
556 * multisampled or have an AUX buffer attached to it.
558 * GEN | MSRT | AUX_CCS_* or AUX_MCS
559 * -------------------------------------------
560 * 9 | HALIGN_16 | HALIGN_16
561 * 8 | HALIGN_ANY | HALIGN_16
565 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
566 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
567 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
568 } else if (brw
->gen
>= 9 && num_samples
> 1) {
569 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
571 const UNUSED
bool is_lossless_compressed_aux
=
572 brw
->gen
>= 9 && num_samples
== 1 &&
573 mt
->format
== MESA_FORMAT_R_UINT32
;
575 /* For now, nothing else has this requirement */
576 assert(is_lossless_compressed_aux
||
577 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
580 brw_miptree_layout(brw
, mt
, layout_flags
);
582 if (mt
->disable_aux_buffers
)
583 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
590 * Choose an appropriate uncompressed format for a requested
591 * compressed format, if unsupported.
594 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
596 /* No need to lower ETC formats on these platforms,
597 * they are supported natively.
599 if (brw
->gen
>= 8 || brw
->is_baytrail
)
603 case MESA_FORMAT_ETC1_RGB8
:
604 return MESA_FORMAT_R8G8B8X8_UNORM
;
605 case MESA_FORMAT_ETC2_RGB8
:
606 return MESA_FORMAT_R8G8B8X8_UNORM
;
607 case MESA_FORMAT_ETC2_SRGB8
:
608 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
609 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
610 return MESA_FORMAT_B8G8R8A8_SRGB
;
611 case MESA_FORMAT_ETC2_RGBA8_EAC
:
612 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
613 return MESA_FORMAT_R8G8B8A8_UNORM
;
614 case MESA_FORMAT_ETC2_R11_EAC
:
615 return MESA_FORMAT_R_UNORM16
;
616 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
617 return MESA_FORMAT_R_SNORM16
;
618 case MESA_FORMAT_ETC2_RG11_EAC
:
619 return MESA_FORMAT_R16G16_UNORM
;
620 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
621 return MESA_FORMAT_R16G16_SNORM
;
623 /* Non ETC1 / ETC2 format */
628 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
630 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
631 unsigned long *pitch
)
633 uint32_t tile_width
, tile_height
;
634 unsigned long stride
, size
, aligned_y
;
636 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
637 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
638 &tile_width
, &tile_height
);
640 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
641 stride
= mt
->total_width
* mt
->cpp
;
642 stride
= ALIGN(stride
, tile_width
);
643 size
= stride
* aligned_y
;
645 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
646 assert(size
% 4096 == 0);
649 assert(size
% (64 * 1024) == 0);
650 *alignment
= 64 * 1024;
656 static struct intel_mipmap_tree
*
657 miptree_create(struct brw_context
*brw
,
666 uint32_t layout_flags
)
668 struct intel_mipmap_tree
*mt
;
669 mesa_format tex_format
= format
;
670 mesa_format etc_format
= MESA_FORMAT_NONE
;
671 uint32_t alloc_flags
= 0;
673 format
= intel_lower_compressed_format(brw
, format
);
675 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
677 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
678 mt
= intel_miptree_create_layout(brw
, target
, format
,
679 first_level
, last_level
, width0
,
680 height0
, depth0
, num_samples
,
683 * pitch == 0 || height == 0 indicates the null texture
685 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
686 intel_miptree_release(&mt
);
690 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
691 mt
->tiling
= I915_TILING_Y
;
693 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
694 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
697 mt
->etc_format
= etc_format
;
699 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
700 unsigned alignment
= 0;
702 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
704 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
707 if (format
== MESA_FORMAT_S_UINT8
) {
708 /* Align to size of W tile, 64x64. */
709 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
710 ALIGN(mt
->total_width
, 64),
711 ALIGN(mt
->total_height
, 64),
712 mt
->cpp
, &mt
->tiling
, &pitch
,
715 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
716 mt
->total_width
, mt
->total_height
,
717 mt
->cpp
, &mt
->tiling
, &pitch
,
727 struct intel_mipmap_tree
*
728 intel_miptree_create(struct brw_context
*brw
,
737 uint32_t layout_flags
)
739 struct intel_mipmap_tree
*mt
= miptree_create(
741 first_level
, last_level
,
742 width0
, height0
, depth0
, num_samples
,
745 /* If the BO is too large to fit in the aperture, we need to use the
746 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
747 * handle Y-tiling, so we need to fall back to X.
749 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
750 mt
->tiling
== I915_TILING_Y
) {
751 unsigned long pitch
= mt
->pitch
;
752 const uint32_t alloc_flags
=
753 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
754 BO_ALLOC_FOR_RENDER
: 0;
755 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
756 mt
->total_width
, mt
->total_height
);
758 mt
->tiling
= I915_TILING_X
;
759 drm_intel_bo_unreference(mt
->bo
);
760 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
761 mt
->total_width
, mt
->total_height
, mt
->cpp
,
762 &mt
->tiling
, &pitch
, alloc_flags
);
769 intel_miptree_release(&mt
);
774 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
775 assert(mt
->num_samples
> 1);
776 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
777 intel_miptree_release(&mt
);
782 /* If this miptree is capable of supporting fast color clears, set
783 * fast_clear_state appropriately to ensure that fast clears will occur.
784 * Allocation of the MCS miptree will be deferred until the first fast
785 * clear actually occurs or when compressed single sampled buffer is
786 * written by the GPU for the first time.
788 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
789 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
790 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
791 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
793 /* On Gen9+ clients are not currently capable of consuming compressed
794 * single-sampled buffers. Disabling compression allows us to skip
797 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
798 const bool is_lossless_compressed
=
799 unlikely(!lossless_compression_disabled
) &&
800 brw
->gen
>= 9 && !mt
->is_scanout
&&
801 intel_miptree_supports_lossless_compressed(brw
, mt
);
803 if (is_lossless_compressed
) {
804 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
811 struct intel_mipmap_tree
*
812 intel_miptree_create_for_bo(struct brw_context
*brw
,
820 uint32_t layout_flags
)
822 struct intel_mipmap_tree
*mt
;
823 uint32_t tiling
, swizzle
;
826 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
828 /* Nothing will be able to use this miptree with the BO if the offset isn't
831 if (tiling
!= I915_TILING_NONE
)
832 assert(offset
% 4096 == 0);
834 /* miptrees can't handle negative pitch. If you need flipping of images,
835 * that's outside of the scope of the mt.
839 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
841 /* The BO already has a tiling format and we shouldn't confuse the lower
842 * layers by making it try to find a tiling format again.
844 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
845 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
847 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
848 mt
= intel_miptree_create_layout(brw
, target
, format
,
850 width
, height
, depth
, 0,
855 drm_intel_bo_reference(bo
);
865 * For a singlesample renderbuffer, this simply wraps the given BO with a
868 * For a multisample renderbuffer, this wraps the window system's
869 * (singlesample) BO with a singlesample miptree attached to the
870 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
871 * that will contain the actual rendering (which is lazily resolved to
872 * irb->singlesample_mt).
875 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
876 struct intel_renderbuffer
*irb
,
878 uint32_t width
, uint32_t height
,
881 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
882 struct intel_mipmap_tree
*multisample_mt
= NULL
;
883 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
884 mesa_format format
= rb
->Format
;
885 int num_samples
= rb
->NumSamples
;
887 /* Only the front and back buffers, which are color buffers, are allocated
888 * through the image loader.
890 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
891 _mesa_get_format_base_format(format
) == GL_RGBA
);
893 singlesample_mt
= intel_miptree_create_for_bo(intel
,
901 MIPTREE_LAYOUT_FOR_SCANOUT
);
902 if (!singlesample_mt
)
905 /* If this miptree is capable of supporting fast color clears, set
906 * mcs_state appropriately to ensure that fast clears will occur.
907 * Allocation of the MCS miptree will be deferred until the first fast
908 * clear actually occurs.
910 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
911 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
912 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
915 if (num_samples
== 0) {
916 intel_miptree_release(&irb
->mt
);
917 irb
->mt
= singlesample_mt
;
919 assert(!irb
->singlesample_mt
);
921 intel_miptree_release(&irb
->singlesample_mt
);
922 irb
->singlesample_mt
= singlesample_mt
;
925 irb
->mt
->logical_width0
!= width
||
926 irb
->mt
->logical_height0
!= height
) {
927 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
935 irb
->need_downsample
= false;
936 intel_miptree_release(&irb
->mt
);
937 irb
->mt
= multisample_mt
;
943 intel_miptree_release(&irb
->singlesample_mt
);
944 intel_miptree_release(&irb
->mt
);
948 struct intel_mipmap_tree
*
949 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
953 uint32_t num_samples
)
955 struct intel_mipmap_tree
*mt
;
958 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
959 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
960 MIPTREE_LAYOUT_TILING_ANY
|
961 MIPTREE_LAYOUT_FOR_SCANOUT
;
963 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
964 width
, height
, depth
, num_samples
,
969 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
970 ok
= intel_miptree_alloc_hiz(brw
, mt
);
978 intel_miptree_release(&mt
);
983 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
984 struct intel_mipmap_tree
*src
)
989 intel_miptree_release(dst
);
993 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1001 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1006 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1007 if (--(*mt
)->refcount
<= 0) {
1010 DBG("%s deleting %p\n", __func__
, *mt
);
1012 drm_intel_bo_unreference((*mt
)->bo
);
1013 intel_miptree_release(&(*mt
)->stencil_mt
);
1014 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1015 if ((*mt
)->hiz_buf
) {
1016 if ((*mt
)->hiz_buf
->mt
)
1017 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1019 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1020 free((*mt
)->hiz_buf
);
1022 intel_miptree_release(&(*mt
)->mcs_mt
);
1023 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1025 intel_miptree_release(&(*mt
)->plane
[0]);
1026 intel_miptree_release(&(*mt
)->plane
[1]);
1028 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1029 free((*mt
)->level
[i
].slice
);
1039 intel_get_image_dims(struct gl_texture_image
*image
,
1040 int *width
, int *height
, int *depth
)
1042 switch (image
->TexObject
->Target
) {
1043 case GL_TEXTURE_1D_ARRAY
:
1044 /* For a 1D Array texture the OpenGL API will treat the image height as
1045 * the number of array slices. For Intel hardware, we treat the 1D array
1046 * as a 2D Array with a height of 1. So, here we want to swap image
1049 assert(image
->Depth
== 1);
1050 *width
= image
->Width
;
1052 *depth
= image
->Height
;
1054 case GL_TEXTURE_CUBE_MAP
:
1055 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1056 * though we really have 6 slices.
1058 assert(image
->Depth
== 1);
1059 *width
= image
->Width
;
1060 *height
= image
->Height
;
1064 *width
= image
->Width
;
1065 *height
= image
->Height
;
1066 *depth
= image
->Depth
;
1072 * Can the image be pulled into a unified mipmap tree? This mirrors
1073 * the completeness test in a lot of ways.
1075 * Not sure whether I want to pass gl_texture_image here.
1078 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1079 struct gl_texture_image
*image
)
1081 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1082 GLuint level
= intelImage
->base
.Base
.Level
;
1083 int width
, height
, depth
;
1085 /* glTexImage* choose the texture object based on the target passed in, and
1086 * objects can't change targets over their lifetimes, so this should be
1089 assert(image
->TexObject
->Target
== mt
->target
);
1091 mesa_format mt_format
= mt
->format
;
1092 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1093 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1094 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1095 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1096 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1097 mt_format
= mt
->etc_format
;
1099 if (image
->TexFormat
!= mt_format
)
1102 intel_get_image_dims(image
, &width
, &height
, &depth
);
1104 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1107 int level_depth
= mt
->level
[level
].depth
;
1108 if (mt
->num_samples
> 1) {
1109 switch (mt
->msaa_layout
) {
1110 case INTEL_MSAA_LAYOUT_NONE
:
1111 case INTEL_MSAA_LAYOUT_IMS
:
1113 case INTEL_MSAA_LAYOUT_UMS
:
1114 case INTEL_MSAA_LAYOUT_CMS
:
1115 level_depth
/= mt
->num_samples
;
1120 /* Test image dimensions against the base level image adjusted for
1121 * minification. This will also catch images not present in the
1122 * tree, changed targets, etc.
1124 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1125 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1126 depth
!= level_depth
) {
1130 if (image
->NumSamples
!= mt
->num_samples
)
1138 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1140 GLuint x
, GLuint y
, GLuint d
)
1142 mt
->level
[level
].depth
= d
;
1143 mt
->level
[level
].level_x
= x
;
1144 mt
->level
[level
].level_y
= y
;
1146 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1149 assert(mt
->level
[level
].slice
== NULL
);
1151 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1152 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1153 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1158 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1159 GLuint level
, GLuint img
,
1162 if (img
== 0 && level
== 0)
1163 assert(x
== 0 && y
== 0);
1165 assert(img
< mt
->level
[level
].depth
);
1167 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1168 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1170 DBG("%s level %d img %d pos %d,%d\n",
1171 __func__
, level
, img
,
1172 mt
->level
[level
].slice
[img
].x_offset
,
1173 mt
->level
[level
].slice
[img
].y_offset
);
1177 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1178 GLuint level
, GLuint slice
,
1179 GLuint
*x
, GLuint
*y
)
1181 assert(slice
< mt
->level
[level
].depth
);
1183 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1184 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1189 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1190 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1191 * and tile_h is set to 1.
1194 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1195 uint32_t *tile_w
, uint32_t *tile_h
)
1197 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1207 case I915_TILING_NONE
:
1212 unreachable("not reached");
1215 uint32_t aspect_ratio
= 1;
1216 assert(_mesa_is_pow_two(cpp
));
1231 unreachable("not reached");
1234 if (cpp
== 2 || cpp
== 8)
1237 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1240 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1246 * This function computes masks that may be used to select the bits of the X
1247 * and Y coordinates that indicate the offset within a tile. If the BO is
1248 * untiled, the masks are set to 0.
1251 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1252 uint32_t *mask_x
, uint32_t *mask_y
)
1254 uint32_t tile_w_bytes
, tile_h
;
1256 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1258 *mask_x
= tile_w_bytes
/ cpp
- 1;
1259 *mask_y
= tile_h
- 1;
1263 * Compute the offset (in bytes) from the start of the BO to the given x
1264 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1265 * multiples of the tile size.
1268 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1269 uint32_t x
, uint32_t y
,
1270 bool map_stencil_as_y_tiled
)
1273 uint32_t pitch
= mt
->pitch
;
1274 uint32_t tiling
= mt
->tiling
;
1276 if (map_stencil_as_y_tiled
) {
1277 tiling
= I915_TILING_Y
;
1279 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1280 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1281 * the resulting surface is twice the pitch of the original miptree,
1282 * since each row in the Y-tiled view corresponds to two rows in the
1283 * actual W-tiled surface. So we need to correct the pitch before
1284 * computing the offsets.
1291 unreachable("not reached");
1292 case I915_TILING_NONE
:
1293 return y
* pitch
+ x
* cpp
;
1295 assert((x
% (512 / cpp
)) == 0);
1296 assert((y
% 8) == 0);
1297 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1299 assert((x
% (128 / cpp
)) == 0);
1300 assert((y
% 32) == 0);
1301 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1306 * Rendering with tiled buffers requires that the base address of the buffer
1307 * be aligned to a page boundary. For renderbuffers, and sometimes with
1308 * textures, we may want the surface to point at a texture image level that
1309 * isn't at a page boundary.
1311 * This function returns an appropriately-aligned base offset
1312 * according to the tiling restrictions, plus any required x/y offset
1316 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1317 GLuint level
, GLuint slice
,
1322 uint32_t mask_x
, mask_y
;
1324 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, &mask_x
, &mask_y
);
1325 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1327 *tile_x
= x
& mask_x
;
1328 *tile_y
= y
& mask_y
;
1330 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1334 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1335 struct intel_mipmap_tree
*dst_mt
,
1336 struct intel_mipmap_tree
*src_mt
,
1343 ptrdiff_t src_stride
, dst_stride
;
1344 int cpp
= dst_mt
->cpp
;
1346 intel_miptree_map(brw
, src_mt
,
1350 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1353 intel_miptree_map(brw
, dst_mt
,
1357 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1361 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1362 _mesa_get_format_name(src_mt
->format
),
1363 src_mt
, src
, src_stride
,
1364 _mesa_get_format_name(dst_mt
->format
),
1365 dst_mt
, dst
, dst_stride
,
1368 int row_size
= cpp
* width
;
1369 if (src_stride
== row_size
&&
1370 dst_stride
== row_size
) {
1371 memcpy(dst
, src
, row_size
* height
);
1373 for (int i
= 0; i
< height
; i
++) {
1374 memcpy(dst
, src
, row_size
);
1380 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1381 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1383 /* Don't forget to copy the stencil data over, too. We could have skipped
1384 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1385 * shuffling the two data sources in/out of temporary storage instead of
1386 * the direct mapping we get this way.
1388 if (dst_mt
->stencil_mt
) {
1389 assert(src_mt
->stencil_mt
);
1390 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1391 level
, slice
, width
, height
);
1396 intel_miptree_copy_slice(struct brw_context
*brw
,
1397 struct intel_mipmap_tree
*dst_mt
,
1398 struct intel_mipmap_tree
*src_mt
,
1404 mesa_format format
= src_mt
->format
;
1405 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1406 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1414 assert(depth
< src_mt
->level
[level
].depth
);
1415 assert(src_mt
->format
== dst_mt
->format
);
1417 if (dst_mt
->compressed
) {
1419 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1420 height
= ALIGN_NPOT(height
, j
) / j
;
1421 width
= ALIGN_NPOT(width
, i
) / i
;
1424 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1425 * below won't apply since we can't do the depth's Y tiling or the
1426 * stencil's W tiling in the blitter.
1428 if (src_mt
->stencil_mt
) {
1429 intel_miptree_copy_slice_sw(brw
,
1436 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1437 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1438 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1440 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1441 _mesa_get_format_name(src_mt
->format
),
1442 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1443 _mesa_get_format_name(dst_mt
->format
),
1444 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1447 if (!intel_miptree_blit(brw
,
1448 src_mt
, level
, slice
, 0, 0, false,
1449 dst_mt
, level
, slice
, 0, 0, false,
1450 width
, height
, GL_COPY
)) {
1451 perf_debug("miptree validate blit for %s failed\n",
1452 _mesa_get_format_name(format
));
1454 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1460 * Copies the image's current data to the given miptree, and associates that
1461 * miptree with the image.
1463 * If \c invalidate is true, then the actual image data does not need to be
1464 * copied, but the image still needs to be associated to the new miptree (this
1465 * is set to true if we're about to clear the image).
1468 intel_miptree_copy_teximage(struct brw_context
*brw
,
1469 struct intel_texture_image
*intelImage
,
1470 struct intel_mipmap_tree
*dst_mt
,
1473 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1474 struct intel_texture_object
*intel_obj
=
1475 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1476 int level
= intelImage
->base
.Base
.Level
;
1477 int face
= intelImage
->base
.Base
.Face
;
1480 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1481 depth
= intelImage
->base
.Base
.Height
;
1483 depth
= intelImage
->base
.Base
.Depth
;
1486 for (int slice
= 0; slice
< depth
; slice
++) {
1487 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1491 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1492 intel_obj
->needs_validate
= true;
1496 intel_miptree_init_mcs(struct brw_context
*brw
,
1497 struct intel_mipmap_tree
*mt
,
1500 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1502 * When MCS buffer is enabled and bound to MSRT, it is required that it
1503 * is cleared prior to any rendering.
1505 * Since we don't use the MCS buffer for any purpose other than rendering,
1506 * it makes sense to just clear it immediately upon allocation.
1508 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1510 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1511 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1512 intel_miptree_unmap_raw(mt
->mcs_mt
);
1513 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1517 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1518 struct intel_mipmap_tree
*mt
,
1521 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1522 assert(mt
->mcs_mt
== NULL
);
1523 assert(!mt
->disable_aux_buffers
);
1525 /* Choose the correct format for the MCS buffer. All that really matters
1526 * is that we allocate the right buffer size, since we'll always be
1527 * accessing this miptree using MCS-specific hardware mechanisms, which
1528 * infer the correct format based on num_samples.
1531 switch (num_samples
) {
1534 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1537 format
= MESA_FORMAT_R_UNORM8
;
1540 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1541 * for each sample, plus 8 padding bits).
1543 format
= MESA_FORMAT_R_UINT32
;
1546 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1549 format
= MESA_FORMAT_RG_UINT32
;
1552 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1555 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1557 * "The MCS surface must be stored as Tile Y."
1559 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1560 MIPTREE_LAYOUT_TILING_Y
;
1561 mt
->mcs_mt
= miptree_create(brw
,
1567 mt
->logical_height0
,
1569 0 /* num_samples */,
1572 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1579 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1580 struct intel_mipmap_tree
*mt
,
1581 bool is_lossless_compressed
)
1583 assert(mt
->mcs_mt
== NULL
);
1584 assert(!mt
->disable_aux_buffers
);
1586 /* The format of the MCS buffer is opaque to the driver; all that matters
1587 * is that we get its size and pitch right. We'll pretend that the format
1588 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1589 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1590 * the block width and then a further factor of 4. Since an MCS tile
1591 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1592 * we'll need to scale the height down by the block height and then a
1593 * further factor of 8.
1595 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1596 unsigned block_width_px
;
1597 unsigned block_height
;
1598 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1599 unsigned width_divisor
= block_width_px
* 4;
1600 unsigned height_divisor
= block_height
* 8;
1602 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1604 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1605 * in the main surface. In Skylake, it's two bits. The extra bit
1606 * doubles the MCS height, not width, because in Skylake the MCS is always
1610 height_divisor
/= 2;
1612 unsigned mcs_width
=
1613 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1614 unsigned mcs_height
=
1615 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1616 assert(mt
->logical_depth0
== 1);
1617 uint32_t layout_flags
= MIPTREE_LAYOUT_TILING_Y
;
1619 if (brw
->gen
>= 8) {
1620 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1623 /* In case of compression mcs buffer needs to be initialised requiring the
1624 * buffer to be immediately mapped to cpu space for writing. Therefore do
1625 * not use the gpu access flag which can cause an unnecessary delay if the
1626 * backing pages happened to be just used by the GPU.
1628 if (!is_lossless_compressed
)
1629 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1631 mt
->mcs_mt
= miptree_create(brw
,
1639 0 /* num_samples */,
1642 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1643 * used for lossless compression which requires similar initialisation
1644 * as multi-sample compression.
1646 if (is_lossless_compressed
) {
1647 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1648 * resolve. Initialize it accordingly in case the first renderer is
1649 * cpu (or other none compression aware party).
1651 * This is also explicitly stated in the spec (MCS Buffer for Render
1653 * "If Software wants to enable Color Compression without Fast clear,
1654 * Software needs to initialize MCS with zeros."
1656 intel_miptree_init_mcs(brw
, mt
, 0);
1657 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1658 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1665 * Helper for intel_miptree_alloc_hiz() that sets
1666 * \c mt->level[level].has_hiz. Return true if and only if
1667 * \c has_hiz was set.
1670 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1671 struct intel_mipmap_tree
*mt
,
1674 assert(mt
->hiz_buf
);
1676 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1677 uint32_t width
= minify(mt
->physical_width0
, level
);
1678 uint32_t height
= minify(mt
->physical_height0
, level
);
1680 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1681 * and the height is 4 aligned. This allows our HiZ support
1682 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1683 * we can grow the width & height to allow the HiZ op to
1684 * force the proper size alignments.
1686 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1687 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1692 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1693 mt
->level
[level
].has_hiz
= true;
1699 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1700 * buffer dimensions and allocates a bo for the hiz buffer.
1702 static struct intel_miptree_aux_buffer
*
1703 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1704 struct intel_mipmap_tree
*mt
)
1706 unsigned z_width
= mt
->logical_width0
;
1707 unsigned z_height
= mt
->logical_height0
;
1708 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1709 unsigned hz_width
, hz_height
;
1710 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1715 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1716 * adjustments required for Z_Height and Z_Width based on multisampling.
1718 switch (mt
->num_samples
) {
1732 unreachable("unsupported sample count");
1735 const unsigned vertical_align
= 8; /* 'j' in the docs */
1736 const unsigned H0
= z_height
;
1737 const unsigned h0
= ALIGN(H0
, vertical_align
);
1738 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1739 const unsigned Z0
= z_depth
;
1741 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1742 hz_width
= ALIGN(z_width
, 16);
1744 if (mt
->target
== GL_TEXTURE_3D
) {
1748 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1749 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1750 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1751 hz_height
+= h_i
* Z_i
;
1752 H_i
= minify(H_i
, 1);
1753 Z_i
= minify(Z_i
, 1);
1756 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1758 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1760 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1761 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1762 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1765 unsigned long pitch
;
1766 uint32_t tiling
= I915_TILING_Y
;
1767 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1768 hz_width
, hz_height
, 1,
1770 BO_ALLOC_FOR_RENDER
);
1774 } else if (tiling
!= I915_TILING_Y
) {
1775 drm_intel_bo_unreference(buf
->bo
);
1787 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1788 * buffer dimensions and allocates a bo for the hiz buffer.
1790 static struct intel_miptree_aux_buffer
*
1791 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1792 struct intel_mipmap_tree
*mt
)
1794 unsigned z_width
= mt
->logical_width0
;
1795 unsigned z_height
= mt
->logical_height0
;
1796 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1797 unsigned hz_width
, hz_height
;
1798 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1803 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1804 * adjustments required for Z_Height and Z_Width based on multisampling.
1807 switch (mt
->num_samples
) {
1821 unreachable("unsupported sample count");
1825 const unsigned vertical_align
= 8; /* 'j' in the docs */
1826 const unsigned H0
= z_height
;
1827 const unsigned h0
= ALIGN(H0
, vertical_align
);
1828 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1829 const unsigned Z0
= z_depth
;
1831 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1832 hz_width
= ALIGN(z_width
, 16);
1836 unsigned sum_h_i
= 0;
1837 unsigned hz_height_3d_sum
= 0;
1838 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1839 unsigned i
= level
- mt
->first_level
;
1840 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1841 /* sum(i=2 to m; h_i) */
1845 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1846 hz_height_3d_sum
+= h_i
* Z_i
;
1847 H_i
= minify(H_i
, 1);
1848 Z_i
= minify(Z_i
, 1);
1850 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1851 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1853 if (mt
->target
== GL_TEXTURE_3D
) {
1854 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1855 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1857 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1858 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1861 unsigned long pitch
;
1862 uint32_t tiling
= I915_TILING_Y
;
1863 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1864 hz_width
, hz_height
, 1,
1866 BO_ALLOC_FOR_RENDER
);
1870 } else if (tiling
!= I915_TILING_Y
) {
1871 drm_intel_bo_unreference(buf
->bo
);
1882 static struct intel_miptree_aux_buffer
*
1883 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1884 struct intel_mipmap_tree
*mt
)
1886 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1887 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1890 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1895 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1896 buf
->mt
= intel_miptree_create(brw
,
1902 mt
->logical_height0
,
1911 buf
->bo
= buf
->mt
->bo
;
1912 buf
->pitch
= buf
->mt
->pitch
;
1913 buf
->qpitch
= buf
->mt
->qpitch
;
1919 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1920 struct intel_mipmap_tree
*mt
)
1925 if (mt
->hiz_buf
!= NULL
)
1928 if (mt
->disable_aux_buffers
)
1931 switch (mt
->format
) {
1932 case MESA_FORMAT_Z_FLOAT32
:
1933 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1934 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1935 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1936 case MESA_FORMAT_Z_UNORM16
:
1944 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1945 struct intel_mipmap_tree
*mt
)
1947 assert(mt
->hiz_buf
== NULL
);
1948 assert(!mt
->disable_aux_buffers
);
1950 if (brw
->gen
== 7) {
1951 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1952 } else if (brw
->gen
>= 8) {
1953 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1955 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1961 /* Mark that all slices need a HiZ resolve. */
1962 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1963 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1966 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1967 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1968 exec_node_init(&m
->link
);
1971 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
1973 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1981 * Does the miptree slice have hiz enabled?
1984 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1986 intel_miptree_check_level_layer(mt
, level
, 0);
1987 return mt
->level
[level
].has_hiz
;
1991 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1995 if (!intel_miptree_level_has_hiz(mt
, level
))
1998 intel_resolve_map_set(&mt
->hiz_map
,
1999 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2004 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2008 if (!intel_miptree_level_has_hiz(mt
, level
))
2011 intel_resolve_map_set(&mt
->hiz_map
,
2012 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2016 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2020 uint32_t end_layer
= mt
->level
[level
].depth
;
2022 for (layer
= 0; layer
< end_layer
; layer
++) {
2023 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2028 intel_miptree_slice_resolve(struct brw_context
*brw
,
2029 struct intel_mipmap_tree
*mt
,
2032 enum blorp_hiz_op need
)
2034 intel_miptree_check_level_layer(mt
, level
, layer
);
2036 struct intel_resolve_map
*item
=
2037 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2039 if (!item
|| item
->need
!= need
)
2042 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2043 intel_resolve_map_remove(item
);
2048 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2049 struct intel_mipmap_tree
*mt
,
2053 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2054 BLORP_HIZ_OP_HIZ_RESOLVE
);
2058 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2059 struct intel_mipmap_tree
*mt
,
2063 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2064 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2068 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2069 struct intel_mipmap_tree
*mt
,
2070 enum blorp_hiz_op need
)
2072 bool did_resolve
= false;
2074 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2075 if (map
->need
!= need
)
2078 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2079 intel_resolve_map_remove(map
);
2087 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2088 struct intel_mipmap_tree
*mt
)
2090 return intel_miptree_all_slices_resolve(brw
, mt
,
2091 BLORP_HIZ_OP_HIZ_RESOLVE
);
2095 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2096 struct intel_mipmap_tree
*mt
)
2098 return intel_miptree_all_slices_resolve(brw
, mt
,
2099 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2104 intel_miptree_resolve_color(struct brw_context
*brw
,
2105 struct intel_mipmap_tree
*mt
,
2108 /* From gen9 onwards there is new compression scheme for single sampled
2109 * surfaces called "lossless compressed". These don't need to be always
2112 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2113 intel_miptree_is_lossless_compressed(brw
, mt
))
2116 switch (mt
->fast_clear_state
) {
2117 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2118 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2119 /* No resolve needed */
2121 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2122 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2123 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2124 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2125 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2126 brw_blorp_resolve_color(brw
, mt
);
2132 unreachable("Invalid fast clear state");
2138 * Make it possible to share the BO backing the given miptree with another
2139 * process or another miptree.
2141 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2142 * then discard the MCS buffer, if present. We also set the fast_clear_state
2143 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2144 * allocated in the future.
2147 intel_miptree_make_shareable(struct brw_context
*brw
,
2148 struct intel_mipmap_tree
*mt
)
2150 /* MCS buffers are also used for multisample buffers, but we can't resolve
2151 * away a multisample MCS buffer because it's an integral part of how the
2152 * pixel data is stored. Fortunately this code path should never be
2153 * reached for multisample buffers.
2155 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2158 intel_miptree_resolve_color(brw
, mt
, 0);
2159 intel_miptree_release(&mt
->mcs_mt
);
2160 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2166 * \brief Get pointer offset into stencil buffer.
2168 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2169 * must decode the tile's layout in software.
2172 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2174 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2176 * Even though the returned offset is always positive, the return type is
2178 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2179 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2182 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2184 uint32_t tile_size
= 4096;
2185 uint32_t tile_width
= 64;
2186 uint32_t tile_height
= 64;
2187 uint32_t row_size
= 64 * stride
;
2189 uint32_t tile_x
= x
/ tile_width
;
2190 uint32_t tile_y
= y
/ tile_height
;
2192 /* The byte's address relative to the tile's base addres. */
2193 uint32_t byte_x
= x
% tile_width
;
2194 uint32_t byte_y
= y
% tile_height
;
2196 uintptr_t u
= tile_y
* row_size
2197 + tile_x
* tile_size
2198 + 512 * (byte_x
/ 8)
2200 + 32 * ((byte_y
/ 4) % 2)
2201 + 16 * ((byte_x
/ 4) % 2)
2202 + 8 * ((byte_y
/ 2) % 2)
2203 + 4 * ((byte_x
/ 2) % 2)
2208 /* adjust for bit6 swizzling */
2209 if (((byte_x
/ 8) % 2) == 1) {
2210 if (((byte_y
/ 8) % 2) == 0) {
2222 intel_miptree_updownsample(struct brw_context
*brw
,
2223 struct intel_mipmap_tree
*src
,
2224 struct intel_mipmap_tree
*dst
)
2226 brw_blorp_blit_miptrees(brw
,
2227 src
, 0 /* level */, 0 /* layer */,
2228 src
->format
, SWIZZLE_XYZW
,
2229 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2231 src
->logical_width0
, src
->logical_height0
,
2233 dst
->logical_width0
, dst
->logical_height0
,
2234 GL_NEAREST
, false, false /*mirror x, y*/,
2237 if (src
->stencil_mt
) {
2238 brw_blorp_blit_miptrees(brw
,
2239 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2240 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2241 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2242 dst
->stencil_mt
->format
,
2244 src
->logical_width0
, src
->logical_height0
,
2246 dst
->logical_width0
, dst
->logical_height0
,
2247 GL_NEAREST
, false, false /*mirror x, y*/,
2248 false, false /* decode/encode srgb */);
2253 intel_update_r8stencil(struct brw_context
*brw
,
2254 struct intel_mipmap_tree
*mt
)
2256 assert(brw
->gen
>= 7);
2257 struct intel_mipmap_tree
*src
=
2258 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2259 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2262 if (!mt
->r8stencil_mt
) {
2263 const uint32_t r8stencil_flags
=
2264 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2265 MIPTREE_LAYOUT_DISABLE_AUX
;
2266 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2267 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2269 MESA_FORMAT_R_UINT8
,
2272 src
->logical_width0
,
2273 src
->logical_height0
,
2274 src
->logical_depth0
,
2277 assert(mt
->r8stencil_mt
);
2280 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2282 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2283 const unsigned depth
= src
->level
[level
].depth
;
2284 const int layers_per_blit
=
2285 (dst
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
2286 dst
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
2287 dst
->num_samples
: 1;
2289 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2290 brw_blorp_blit_miptrees(brw
,
2292 src
->format
, SWIZZLE_X
,
2293 dst
, level
, layers_per_blit
* layer
,
2294 MESA_FORMAT_R_UNORM8
,
2296 src
->logical_width0
, src
->logical_height0
,
2298 dst
->logical_width0
, dst
->logical_height0
,
2299 GL_NEAREST
, false, false /*mirror x, y*/,
2300 false, false /* decode/encode srgb */);
2304 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2305 src
->r8stencil_needs_update
= false;
2309 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2311 /* CPU accesses to color buffers don't understand fast color clears, so
2312 * resolve any pending fast color clears before we map.
2314 intel_miptree_resolve_color(brw
, mt
, 0);
2316 drm_intel_bo
*bo
= mt
->bo
;
2318 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2319 intel_batchbuffer_flush(brw
);
2321 if (mt
->tiling
!= I915_TILING_NONE
)
2322 brw_bo_map_gtt(brw
, bo
, "miptree");
2324 brw_bo_map(brw
, bo
, true, "miptree");
2330 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2332 drm_intel_bo_unmap(mt
->bo
);
2336 intel_miptree_map_gtt(struct brw_context
*brw
,
2337 struct intel_mipmap_tree
*mt
,
2338 struct intel_miptree_map
*map
,
2339 unsigned int level
, unsigned int slice
)
2341 unsigned int bw
, bh
;
2343 unsigned int image_x
, image_y
;
2344 intptr_t x
= map
->x
;
2345 intptr_t y
= map
->y
;
2347 /* For compressed formats, the stride is the number of bytes per
2348 * row of blocks. intel_miptree_get_image_offset() already does
2351 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2352 assert(y
% bh
== 0);
2353 assert(x
% bw
== 0);
2357 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2362 /* Note that in the case of cube maps, the caller must have passed the
2363 * slice number referencing the face.
2365 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2369 map
->stride
= mt
->pitch
;
2370 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2373 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2374 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2375 map
->x
, map
->y
, map
->w
, map
->h
,
2376 mt
, _mesa_get_format_name(mt
->format
),
2377 x
, y
, map
->ptr
, map
->stride
);
2381 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2383 intel_miptree_unmap_raw(mt
);
2387 intel_miptree_map_blit(struct brw_context
*brw
,
2388 struct intel_mipmap_tree
*mt
,
2389 struct intel_miptree_map
*map
,
2390 unsigned int level
, unsigned int slice
)
2392 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2393 /* first_level */ 0,
2397 MIPTREE_LAYOUT_TILING_NONE
);
2399 if (!map
->linear_mt
) {
2400 fprintf(stderr
, "Failed to allocate blit temporary\n");
2403 map
->stride
= map
->linear_mt
->pitch
;
2405 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2406 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2407 * invalidate is set, since we'll be writing the whole rectangle from our
2408 * temporary buffer back out.
2410 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2411 if (!intel_miptree_blit(brw
,
2413 map
->x
, map
->y
, false,
2414 map
->linear_mt
, 0, 0,
2416 map
->w
, map
->h
, GL_COPY
)) {
2417 fprintf(stderr
, "Failed to blit\n");
2422 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2424 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2425 map
->x
, map
->y
, map
->w
, map
->h
,
2426 mt
, _mesa_get_format_name(mt
->format
),
2427 level
, slice
, map
->ptr
, map
->stride
);
2432 intel_miptree_release(&map
->linear_mt
);
2438 intel_miptree_unmap_blit(struct brw_context
*brw
,
2439 struct intel_mipmap_tree
*mt
,
2440 struct intel_miptree_map
*map
,
2444 struct gl_context
*ctx
= &brw
->ctx
;
2446 intel_miptree_unmap_raw(map
->linear_mt
);
2448 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2449 bool ok
= intel_miptree_blit(brw
,
2450 map
->linear_mt
, 0, 0,
2453 map
->x
, map
->y
, false,
2454 map
->w
, map
->h
, GL_COPY
);
2455 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2458 intel_miptree_release(&map
->linear_mt
);
2462 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2464 #if defined(USE_SSE41)
2466 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2467 struct intel_mipmap_tree
*mt
,
2468 struct intel_miptree_map
*map
,
2469 unsigned int level
, unsigned int slice
)
2471 assert(map
->mode
& GL_MAP_READ_BIT
);
2472 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2474 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2475 map
->x
, map
->y
, map
->w
, map
->h
,
2476 mt
, _mesa_get_format_name(mt
->format
),
2477 level
, slice
, map
->ptr
, map
->stride
);
2479 /* Map the original image */
2482 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2486 void *src
= intel_miptree_map_raw(brw
, mt
);
2492 src
+= image_y
* mt
->pitch
;
2493 src
+= image_x
* mt
->cpp
;
2495 /* Due to the pixel offsets for the particular image being mapped, our
2496 * src pointer may not be 16-byte aligned. However, if the pitch is
2497 * divisible by 16, then the amount by which it's misaligned will remain
2498 * consistent from row to row.
2500 assert((mt
->pitch
% 16) == 0);
2501 const int misalignment
= ((uintptr_t) src
) & 15;
2503 /* Create an untiled temporary buffer for the mapping. */
2504 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2506 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2508 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2509 /* Offset the destination so it has the same misalignment as src. */
2510 map
->ptr
= map
->buffer
+ misalignment
;
2512 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2514 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2515 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2516 void *src_ptr
= src
+ y
* mt
->pitch
;
2518 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2521 intel_miptree_unmap_raw(mt
);
2525 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2526 struct intel_mipmap_tree
*mt
,
2527 struct intel_miptree_map
*map
,
2531 _mesa_align_free(map
->buffer
);
2538 intel_miptree_map_s8(struct brw_context
*brw
,
2539 struct intel_mipmap_tree
*mt
,
2540 struct intel_miptree_map
*map
,
2541 unsigned int level
, unsigned int slice
)
2543 map
->stride
= map
->w
;
2544 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2548 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2549 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2550 * invalidate is set, since we'll be writing the whole rectangle from our
2551 * temporary buffer back out.
2553 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2554 uint8_t *untiled_s8_map
= map
->ptr
;
2555 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2556 unsigned int image_x
, image_y
;
2558 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2560 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2561 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2562 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2563 x
+ image_x
+ map
->x
,
2564 y
+ image_y
+ map
->y
,
2565 brw
->has_swizzling
);
2566 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2570 intel_miptree_unmap_raw(mt
);
2572 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2573 map
->x
, map
->y
, map
->w
, map
->h
,
2574 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2576 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2577 map
->x
, map
->y
, map
->w
, map
->h
,
2578 mt
, map
->ptr
, map
->stride
);
2583 intel_miptree_unmap_s8(struct brw_context
*brw
,
2584 struct intel_mipmap_tree
*mt
,
2585 struct intel_miptree_map
*map
,
2589 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2590 unsigned int image_x
, image_y
;
2591 uint8_t *untiled_s8_map
= map
->ptr
;
2592 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2594 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2596 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2597 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2598 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2599 image_x
+ x
+ map
->x
,
2600 image_y
+ y
+ map
->y
,
2601 brw
->has_swizzling
);
2602 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2606 intel_miptree_unmap_raw(mt
);
2613 intel_miptree_map_etc(struct brw_context
*brw
,
2614 struct intel_mipmap_tree
*mt
,
2615 struct intel_miptree_map
*map
,
2619 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2620 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2621 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2624 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2625 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2627 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2628 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2629 map
->w
, map
->h
, 1));
2630 map
->ptr
= map
->buffer
;
2634 intel_miptree_unmap_etc(struct brw_context
*brw
,
2635 struct intel_mipmap_tree
*mt
,
2636 struct intel_miptree_map
*map
,
2642 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2647 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2648 + image_y
* mt
->pitch
2649 + image_x
* mt
->cpp
;
2651 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2652 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2653 map
->ptr
, map
->stride
,
2656 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2657 map
->ptr
, map
->stride
,
2658 map
->w
, map
->h
, mt
->etc_format
);
2660 intel_miptree_unmap_raw(mt
);
2665 * Mapping function for packed depth/stencil miptrees backed by real separate
2666 * miptrees for depth and stencil.
2668 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2669 * separate from the depth buffer. Yet at the GL API level, we have to expose
2670 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2671 * be able to map that memory for texture storage and glReadPixels-type
2672 * operations. We give Mesa core that access by mallocing a temporary and
2673 * copying the data between the actual backing store and the temporary.
2676 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2677 struct intel_mipmap_tree
*mt
,
2678 struct intel_miptree_map
*map
,
2679 unsigned int level
, unsigned int slice
)
2681 struct intel_mipmap_tree
*z_mt
= mt
;
2682 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2683 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2684 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2686 map
->stride
= map
->w
* packed_bpp
;
2687 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2691 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2692 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2693 * invalidate is set, since we'll be writing the whole rectangle from our
2694 * temporary buffer back out.
2696 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2697 uint32_t *packed_map
= map
->ptr
;
2698 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2699 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2700 unsigned int s_image_x
, s_image_y
;
2701 unsigned int z_image_x
, z_image_y
;
2703 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2704 &s_image_x
, &s_image_y
);
2705 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2706 &z_image_x
, &z_image_y
);
2708 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2709 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2710 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2711 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2714 brw
->has_swizzling
);
2715 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2717 (map_x
+ z_image_x
));
2718 uint8_t s
= s_map
[s_offset
];
2719 uint32_t z
= z_map
[z_offset
];
2721 if (map_z32f_x24s8
) {
2722 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2723 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2725 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2730 intel_miptree_unmap_raw(s_mt
);
2731 intel_miptree_unmap_raw(z_mt
);
2733 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2735 map
->x
, map
->y
, map
->w
, map
->h
,
2736 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2737 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2738 map
->ptr
, map
->stride
);
2740 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2741 map
->x
, map
->y
, map
->w
, map
->h
,
2742 mt
, map
->ptr
, map
->stride
);
2747 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2748 struct intel_mipmap_tree
*mt
,
2749 struct intel_miptree_map
*map
,
2753 struct intel_mipmap_tree
*z_mt
= mt
;
2754 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2755 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2757 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2758 uint32_t *packed_map
= map
->ptr
;
2759 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2760 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2761 unsigned int s_image_x
, s_image_y
;
2762 unsigned int z_image_x
, z_image_y
;
2764 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2765 &s_image_x
, &s_image_y
);
2766 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2767 &z_image_x
, &z_image_y
);
2769 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2770 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2771 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2772 x
+ s_image_x
+ map
->x
,
2773 y
+ s_image_y
+ map
->y
,
2774 brw
->has_swizzling
);
2775 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2777 (x
+ z_image_x
+ map
->x
));
2779 if (map_z32f_x24s8
) {
2780 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2781 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2783 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2784 s_map
[s_offset
] = packed
>> 24;
2785 z_map
[z_offset
] = packed
;
2790 intel_miptree_unmap_raw(s_mt
);
2791 intel_miptree_unmap_raw(z_mt
);
2793 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2795 map
->x
, map
->y
, map
->w
, map
->h
,
2796 z_mt
, _mesa_get_format_name(z_mt
->format
),
2797 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2798 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2799 map
->ptr
, map
->stride
);
2806 * Create and attach a map to the miptree at (level, slice). Return the
2809 static struct intel_miptree_map
*
2810 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2819 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2824 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2825 mt
->level
[level
].slice
[slice
].map
= map
;
2837 * Release the map at (level, slice).
2840 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2844 struct intel_miptree_map
**map
;
2846 map
= &mt
->level
[level
].slice
[slice
].map
;
2852 can_blit_slice(struct intel_mipmap_tree
*mt
,
2853 unsigned int level
, unsigned int slice
)
2857 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2858 if (image_x
>= 32768 || image_y
>= 32768)
2861 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2862 if (mt
->pitch
>= 32768)
2869 use_intel_mipree_map_blit(struct brw_context
*brw
,
2870 struct intel_mipmap_tree
*mt
,
2876 /* It's probably not worth swapping to the blit ring because of
2877 * all the overhead involved. But, we must use blitter for the
2878 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2880 (!(mode
& GL_MAP_WRITE_BIT
) ||
2881 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2883 (mt
->tiling
== I915_TILING_X
||
2884 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2885 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2886 /* Fast copy blit on skl+ supports all tiling formats. */
2888 can_blit_slice(mt
, level
, slice
))
2891 if (mt
->tiling
!= I915_TILING_NONE
&&
2892 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2893 assert(can_blit_slice(mt
, level
, slice
));
2901 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2902 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2903 * arithmetic overflow.
2905 * If you call this function and use \a out_stride, then you're doing pointer
2906 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2907 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2908 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2909 * which usually have type uint32_t or GLuint.
2912 intel_miptree_map(struct brw_context
*brw
,
2913 struct intel_mipmap_tree
*mt
,
2922 ptrdiff_t *out_stride
)
2924 struct intel_miptree_map
*map
;
2926 assert(mt
->num_samples
<= 1);
2928 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2935 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2936 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2937 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2940 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2941 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2942 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2943 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2944 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2945 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2946 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2947 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2948 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2949 #if defined(USE_SSE41)
2950 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2951 !mt
->compressed
&& cpu_has_sse4_1
&&
2952 (mt
->pitch
% 16 == 0)) {
2953 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2956 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2957 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2958 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2961 *out_ptr
= map
->ptr
;
2962 *out_stride
= map
->stride
;
2964 if (map
->ptr
== NULL
)
2965 intel_miptree_release_map(mt
, level
, slice
);
2969 intel_miptree_unmap(struct brw_context
*brw
,
2970 struct intel_mipmap_tree
*mt
,
2974 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2976 assert(mt
->num_samples
<= 1);
2981 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2982 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2984 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2985 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2986 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2987 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2988 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2989 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2990 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2991 } else if (map
->linear_mt
) {
2992 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2993 #if defined(USE_SSE41)
2994 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2995 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2998 intel_miptree_unmap_gtt(mt
);
3001 intel_miptree_release_map(mt
, level
, slice
);
3005 get_isl_surf_dim(GLenum target
)
3009 case GL_TEXTURE_1D_ARRAY
:
3010 return ISL_SURF_DIM_1D
;
3013 case GL_TEXTURE_2D_ARRAY
:
3014 case GL_TEXTURE_RECTANGLE
:
3015 case GL_TEXTURE_CUBE_MAP
:
3016 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3017 case GL_TEXTURE_2D_MULTISAMPLE
:
3018 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3019 case GL_TEXTURE_EXTERNAL_OES
:
3020 return ISL_SURF_DIM_2D
;
3023 return ISL_SURF_DIM_3D
;
3026 unreachable("Invalid texture target");
3030 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3035 case GL_TEXTURE_1D_ARRAY
:
3036 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3037 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3040 case GL_TEXTURE_2D_ARRAY
:
3041 case GL_TEXTURE_RECTANGLE
:
3042 case GL_TEXTURE_2D_MULTISAMPLE
:
3043 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3044 case GL_TEXTURE_EXTERNAL_OES
:
3045 return ISL_DIM_LAYOUT_GEN4_2D
;
3047 case GL_TEXTURE_CUBE_MAP
:
3048 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3049 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3050 ISL_DIM_LAYOUT_GEN4_2D
);
3053 return (devinfo
->gen
>= 9 ?
3054 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3057 unreachable("Invalid texture target");
3061 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3062 const struct intel_mipmap_tree
*mt
,
3063 struct isl_surf
*surf
)
3065 surf
->dim
= get_isl_surf_dim(mt
->target
);
3066 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3067 mt
->tiling
, mt
->target
);
3069 if (mt
->num_samples
> 1) {
3070 switch (mt
->msaa_layout
) {
3071 case INTEL_MSAA_LAYOUT_IMS
:
3072 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3074 case INTEL_MSAA_LAYOUT_UMS
:
3075 case INTEL_MSAA_LAYOUT_CMS
:
3076 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3079 unreachable("Invalid MSAA layout");
3082 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3085 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3086 surf
->tiling
= ISL_TILING_W
;
3087 /* The ISL definition of row_pitch matches the surface state pitch field
3088 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3089 * the factor of 2 for W-tiling in row_pitch.
3091 surf
->row_pitch
= 2 * mt
->pitch
;
3093 switch (mt
->tiling
) {
3094 case I915_TILING_NONE
:
3095 surf
->tiling
= ISL_TILING_LINEAR
;
3098 surf
->tiling
= ISL_TILING_X
;
3101 switch (mt
->tr_mode
) {
3102 case INTEL_MIPTREE_TRMODE_NONE
:
3103 surf
->tiling
= ISL_TILING_Y0
;
3105 case INTEL_MIPTREE_TRMODE_YF
:
3106 surf
->tiling
= ISL_TILING_Yf
;
3108 case INTEL_MIPTREE_TRMODE_YS
:
3109 surf
->tiling
= ISL_TILING_Ys
;
3114 unreachable("Invalid tiling mode");
3117 surf
->row_pitch
= mt
->pitch
;
3120 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3122 if (brw
->gen
>= 9) {
3123 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3124 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3125 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3127 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3128 * alignment in terms of surface elements like we want.
3130 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3133 /* On earlier gens it's stored in pixels. */
3135 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3136 surf
->image_alignment_el
=
3137 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3140 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3141 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3142 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3143 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3144 surf
->logical_level0_px
.array_len
= 1;
3146 surf
->logical_level0_px
.depth
= 1;
3147 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3150 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3151 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3152 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3153 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3154 surf
->phys_level0_sa
.array_len
= 1;
3156 surf
->phys_level0_sa
.depth
= 1;
3157 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3160 surf
->levels
= mt
->last_level
+ 1;
3161 surf
->samples
= MAX2(mt
->num_samples
, 1);
3163 surf
->size
= 0; /* TODO */
3164 surf
->alignment
= 0; /* TODO */
3166 switch (surf
->dim_layout
) {
3167 case ISL_DIM_LAYOUT_GEN4_2D
:
3168 case ISL_DIM_LAYOUT_GEN4_3D
:
3169 if (brw
->gen
>= 9) {
3170 surf
->array_pitch_el_rows
= mt
->qpitch
;
3173 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3174 assert(mt
->qpitch
% bh
== 0);
3175 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3178 case ISL_DIM_LAYOUT_GEN9_1D
:
3179 surf
->array_pitch_el_rows
= 1;
3183 switch (mt
->array_layout
) {
3184 case ALL_LOD_IN_EACH_SLICE
:
3185 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3187 case ALL_SLICES_AT_EACH_LOD
:
3188 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3191 unreachable("Invalid array layout");
3194 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3195 switch (base_format
) {
3196 case GL_DEPTH_COMPONENT
:
3197 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3199 case GL_STENCIL_INDEX
:
3200 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3202 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3204 case GL_DEPTH_STENCIL
:
3205 /* In this case we only texture from the depth part */
3206 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3207 ISL_SURF_USAGE_TEXTURE_BIT
;
3210 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3211 if (brw
->format_supported_as_render_target
[mt
->format
])
3212 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3216 if (_mesa_is_cube_map_texture(mt
->target
))
3217 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3220 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3221 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3222 * PASS IT INTO isl_surf_fill_state.
3225 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3226 const struct intel_mipmap_tree
*mt
,
3227 struct isl_surf
*surf
,
3228 enum isl_aux_usage
*usage
)
3230 uint32_t aux_pitch
, aux_qpitch
;
3232 aux_pitch
= mt
->mcs_mt
->pitch
;
3233 aux_qpitch
= mt
->mcs_mt
->qpitch
;
3235 if (mt
->num_samples
> 1) {
3236 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3237 *usage
= ISL_AUX_USAGE_MCS
;
3238 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3239 assert(brw
->gen
>= 9);
3240 *usage
= ISL_AUX_USAGE_CCS_E
;
3241 } else if (mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_NO_MCS
) {
3242 *usage
= ISL_AUX_USAGE_CCS_D
;
3244 unreachable("Invalid MCS miptree");
3246 } else if (mt
->hiz_buf
) {
3247 if (mt
->hiz_buf
->mt
) {
3248 aux_pitch
= mt
->hiz_buf
->mt
->pitch
;
3249 aux_qpitch
= mt
->hiz_buf
->mt
->qpitch
;
3251 aux_pitch
= mt
->hiz_buf
->pitch
;
3252 aux_qpitch
= mt
->hiz_buf
->qpitch
;
3255 *usage
= ISL_AUX_USAGE_HIZ
;
3257 *usage
= ISL_AUX_USAGE_NONE
;
3261 /* Start with a copy of the original surface. */
3262 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3264 /* Figure out the format and tiling of the auxiliary surface */
3266 case ISL_AUX_USAGE_NONE
:
3267 unreachable("Invalid auxiliary usage");
3269 case ISL_AUX_USAGE_HIZ
:
3270 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3273 case ISL_AUX_USAGE_MCS
:
3276 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3277 * HALIGN 16 must be used."
3280 assert(mt
->halign
== 16);
3282 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3285 case ISL_AUX_USAGE_CCS_D
:
3286 case ISL_AUX_USAGE_CCS_E
:
3288 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3290 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3292 * From the hardware spec for GEN9:
3294 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3295 * HALIGN 16 must be used."
3297 assert(mt
->num_samples
<= 1);
3299 assert(mt
->halign
== 16);
3301 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3305 /* We want the pitch of the actual aux buffer. */
3306 surf
->row_pitch
= aux_pitch
;
3308 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3309 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3310 * in elements of the primary color surface so we have to divide by the
3311 * compression block height.
3313 surf
->array_pitch_el_rows
=
3314 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3317 union isl_color_value
3318 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3319 const struct intel_mipmap_tree
*mt
)
3321 union isl_color_value clear_color
;
3323 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3324 clear_color
.i32
[0] = mt
->depth_clear_value
;
3325 clear_color
.i32
[1] = 0;
3326 clear_color
.i32
[2] = 0;
3327 clear_color
.i32
[3] = 0;
3328 } else if (brw
->gen
>= 9) {
3329 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3330 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3331 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3332 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3333 } else if (_mesa_is_format_integer(mt
->format
)) {
3334 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3335 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3336 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3337 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3339 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3340 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3341 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3342 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;