2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
);
53 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
56 intel_miptree_alloc_mcs(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*mt
,
61 * Determine which MSAA layout should be used by the MSAA surface being
62 * created, based on the chip generation and the surface type.
64 static enum intel_msaa_layout
65 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
66 bool disable_aux_buffers
)
68 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
70 return INTEL_MSAA_LAYOUT_IMS
;
72 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
73 switch (_mesa_get_format_base_format(format
)) {
74 case GL_DEPTH_COMPONENT
:
75 case GL_STENCIL_INDEX
:
76 case GL_DEPTH_STENCIL
:
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
81 * This field must be set to 0 for all SINT MSRTs when all RT channels
84 * In practice this means that we have to disable MCS for all signed
85 * integer MSAA buffers. The alternative, to disable MCS only when one
86 * of the render target channels is disabled, is impractical because it
87 * would require converting between CMS and UMS MSAA layouts on the fly,
90 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
91 return INTEL_MSAA_LAYOUT_UMS
;
92 } else if (disable_aux_buffers
) {
93 /* We can't use the CMS layout because it uses an aux buffer, the MCS
94 * buffer. So fallback to UMS, which is identical to CMS without the
96 return INTEL_MSAA_LAYOUT_UMS
;
98 return INTEL_MSAA_LAYOUT_CMS
;
105 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
106 * scaled-down bitfield representation of the color buffer which is capable of
107 * recording when blocks of the color buffer are equal to the clear value.
108 * This function returns the block size that will be used by the MCS buffer
109 * corresponding to a certain color miptree.
111 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
112 * beneath the "Fast Color Clear" bullet (p327):
114 * The following table describes the RT alignment
128 * This alignment has the following uses:
130 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
131 * buffer contains 128 blocks horizontally and 256 blocks vertically.
133 * - For figuring out alignment restrictions for a fast clear operation. Fast
134 * clear operations must always clear aligned multiples of 16 blocks
135 * horizontally and 32 blocks vertically.
137 * - For scaling down the coordinates sent through the render pipeline during
138 * a fast clear. X coordinates must be scaled down by 8 times the block
139 * width, and Y coordinates by 16 times the block height.
141 * - For scaling down the coordinates sent through the render pipeline during
142 * a "Render Target Resolve" operation. X coordinates must be scaled down
143 * by half the block width, and Y coordinates by half the block height.
146 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
147 unsigned *width_px
, unsigned *height
)
149 switch (mt
->tiling
) {
151 unreachable("Non-MSRT MCS requires X or Y tiling");
152 /* In release builds, fall through */
154 *width_px
= 32 / mt
->cpp
;
158 *width_px
= 64 / mt
->cpp
;
164 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
166 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
167 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
171 * Gen9 changes the restriction to Y-tile only.
174 return tiling
== I915_TILING_Y
;
175 else if (brw
->gen
>= 7)
176 return tiling
!= I915_TILING_NONE
;
182 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
183 * can be used. This doesn't (and should not) inspect any of the properties of
186 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
187 * beneath the "Fast Color Clear" bullet (p326):
189 * - Support is for non-mip-mapped and non-array surface types only.
191 * And then later, on p327:
193 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
197 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
198 struct intel_mipmap_tree
*mt
)
200 /* MCS support does not exist prior to Gen7 */
205 /* FINISHME: Enable singlesample fast MCS clears on SKL after all GPU
206 * FINISHME: hangs are resolved.
208 perf_debug("singlesample fast MCS clears disabled on gen9");
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
267 * Determine depth format corresponding to a depth+stencil format,
268 * for separate stencil.
271 intel_depth_format_for_depthstencil_format(mesa_format format
) {
273 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
274 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
275 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
276 return MESA_FORMAT_Z_FLOAT32
;
284 * @param for_bo Indicates that the caller is
285 * intel_miptree_create_for_bo(). If true, then do not create
288 static struct intel_mipmap_tree
*
289 intel_miptree_create_layout(struct brw_context
*brw
,
298 uint32_t layout_flags
)
300 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
304 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
305 _mesa_enum_to_string(target
),
306 _mesa_get_format_name(format
),
307 first_level
, last_level
, depth0
, mt
);
309 if (target
== GL_TEXTURE_1D_ARRAY
) {
310 /* For a 1D Array texture the OpenGL API will treat the height0
311 * parameter as the number of array slices. For Intel hardware, we treat
312 * the 1D array as a 2D Array with a height of 1.
314 * So, when we first come through this path to create a 1D Array
315 * texture, height0 stores the number of slices, and depth0 is 1. In
316 * this case, we want to swap height0 and depth0.
318 * Since some miptrees will be created based on the base miptree, we may
319 * come through this path and see height0 as 1 and depth0 being the
320 * number of slices. In this case we don't need to do the swap.
322 assert(height0
== 1 || depth0
== 1);
331 mt
->first_level
= first_level
;
332 mt
->last_level
= last_level
;
333 mt
->logical_width0
= width0
;
334 mt
->logical_height0
= height0
;
335 mt
->logical_depth0
= depth0
;
336 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
337 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
338 exec_list_make_empty(&mt
->hiz_map
);
339 mt
->cpp
= _mesa_get_format_bytes(format
);
340 mt
->num_samples
= num_samples
;
341 mt
->compressed
= _mesa_is_format_compressed(format
);
342 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
345 if (num_samples
> 1) {
346 /* Adjust width/height/depth for MSAA */
347 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
348 mt
->disable_aux_buffers
);
349 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
350 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
351 * "If the surface is multisampled and it is a depth or stencil
352 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
353 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
356 * +----------------------------------------------------------------+
357 * | Num Multisamples | W_l = | H_l = |
358 * +----------------------------------------------------------------+
359 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
360 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
361 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
362 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
363 * +----------------------------------------------------------------+
366 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
367 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
368 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
370 * Another more complicated explanation for these adjustments comes
371 * from the Sandybridge PRM, volume 4, part 1, page 31:
373 * "Any of the other messages (sample*, LOD, load4) used with a
374 * (4x) multisampled surface will in-effect sample a surface with
375 * double the height and width as that indicated in the surface
376 * state. Each pixel position on the original-sized surface is
377 * replaced with a 2x2 of samples with the following arrangement:
382 * Thus, when sampling from a multisampled texture, it behaves as
383 * though the layout in memory for (x,y,sample) is:
385 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
386 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
388 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
389 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
391 * However, the actual layout of multisampled data in memory is:
393 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
394 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
396 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
397 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
399 * This pattern repeats for each 2x2 pixel block.
401 * As a result, when calculating the size of our 4-sample buffer for
402 * an odd width or height, we have to align before scaling up because
403 * sample 3 is in that bottom right 2x2 block.
405 switch (num_samples
) {
407 assert(brw
->gen
>= 8);
408 width0
= ALIGN(width0
, 2) * 2;
409 height0
= ALIGN(height0
, 2);
412 width0
= ALIGN(width0
, 2) * 2;
413 height0
= ALIGN(height0
, 2) * 2;
416 width0
= ALIGN(width0
, 2) * 4;
417 height0
= ALIGN(height0
, 2) * 2;
420 /* num_samples should already have been quantized to 0, 1, 2, 4, or
423 unreachable("not reached");
426 /* Non-interleaved */
427 depth0
*= num_samples
;
431 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
432 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
433 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
434 * used on Gen8 to make it pick a qpitch value which doesn't include space
435 * for the mipmaps. On Gen9 this is not necessary because it will
436 * automatically pick a packed qpitch value whenever mt->first_level ==
438 * TODO: can we use it elsewhere?
439 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
442 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
444 switch (mt
->msaa_layout
) {
445 case INTEL_MSAA_LAYOUT_NONE
:
446 case INTEL_MSAA_LAYOUT_IMS
:
447 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
449 case INTEL_MSAA_LAYOUT_UMS
:
450 case INTEL_MSAA_LAYOUT_CMS
:
451 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
456 if (target
== GL_TEXTURE_CUBE_MAP
) {
461 mt
->physical_width0
= width0
;
462 mt
->physical_height0
= height0
;
463 mt
->physical_depth0
= depth0
;
465 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
466 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
467 (brw
->must_use_separate_stencil
||
468 (brw
->has_separate_stencil
&&
469 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
470 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
472 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
473 MIPTREE_LAYOUT_TILING_ANY
;
476 mt
->stencil_mt
= intel_miptree_create(brw
,
487 if (!mt
->stencil_mt
) {
488 intel_miptree_release(&mt
);
492 /* Fix up the Z miptree format for how we're splitting out separate
493 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
495 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
498 if (format
== mt
->format
) {
499 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
500 _mesa_get_format_name(mt
->format
));
504 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
505 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
508 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
509 * multisampled or have an AUX buffer attached to it.
511 * GEN | MSRT | AUX_CCS_* or AUX_MCS
512 * -------------------------------------------
513 * 9 | HALIGN_16 | HALIGN_16
514 * 8 | HALIGN_ANY | HALIGN_16
518 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
519 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
520 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
521 } else if (brw
->gen
>= 9 && num_samples
> 1) {
522 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
524 /* For now, nothing else has this requirement */
525 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
528 brw_miptree_layout(brw
, mt
, layout_flags
);
530 if (mt
->disable_aux_buffers
)
531 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
538 * Choose an appropriate uncompressed format for a requested
539 * compressed format, if unsupported.
542 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
544 /* No need to lower ETC formats on these platforms,
545 * they are supported natively.
547 if (brw
->gen
>= 8 || brw
->is_baytrail
)
551 case MESA_FORMAT_ETC1_RGB8
:
552 return MESA_FORMAT_R8G8B8X8_UNORM
;
553 case MESA_FORMAT_ETC2_RGB8
:
554 return MESA_FORMAT_R8G8B8X8_UNORM
;
555 case MESA_FORMAT_ETC2_SRGB8
:
556 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
557 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
558 return MESA_FORMAT_B8G8R8A8_SRGB
;
559 case MESA_FORMAT_ETC2_RGBA8_EAC
:
560 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
561 return MESA_FORMAT_R8G8B8A8_UNORM
;
562 case MESA_FORMAT_ETC2_R11_EAC
:
563 return MESA_FORMAT_R_UNORM16
;
564 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
565 return MESA_FORMAT_R_SNORM16
;
566 case MESA_FORMAT_ETC2_RG11_EAC
:
567 return MESA_FORMAT_R16G16_UNORM
;
568 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
569 return MESA_FORMAT_R16G16_SNORM
;
571 /* Non ETC1 / ETC2 format */
576 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
578 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
579 unsigned long *pitch
)
581 uint32_t tile_width
, tile_height
;
582 unsigned long stride
, size
, aligned_y
;
584 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
585 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
586 &tile_width
, &tile_height
);
588 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
589 stride
= mt
->total_width
* mt
->cpp
;
590 stride
= ALIGN(stride
, tile_width
);
591 size
= stride
* aligned_y
;
593 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
594 assert(size
% 4096 == 0);
597 assert(size
% (64 * 1024) == 0);
598 *alignment
= 64 * 1024;
604 struct intel_mipmap_tree
*
605 intel_miptree_create(struct brw_context
*brw
,
614 uint32_t layout_flags
)
616 struct intel_mipmap_tree
*mt
;
617 mesa_format tex_format
= format
;
618 mesa_format etc_format
= MESA_FORMAT_NONE
;
619 GLuint total_width
, total_height
;
620 uint32_t alloc_flags
= 0;
622 format
= intel_lower_compressed_format(brw
, format
);
624 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
626 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
627 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
628 mt
= intel_miptree_create_layout(brw
, target
, format
,
629 first_level
, last_level
, width0
,
630 height0
, depth0
, num_samples
,
633 * pitch == 0 || height == 0 indicates the null texture
635 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
636 intel_miptree_release(&mt
);
640 total_width
= mt
->total_width
;
641 total_height
= mt
->total_height
;
643 if (format
== MESA_FORMAT_S_UINT8
) {
644 /* Align to size of W tile, 64x64. */
645 total_width
= ALIGN(total_width
, 64);
646 total_height
= ALIGN(total_height
, 64);
651 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
653 mt
->tiling
= I915_TILING_Y
;
656 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
657 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
660 mt
->etc_format
= etc_format
;
662 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
663 unsigned alignment
= 0;
665 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
667 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
670 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
671 total_width
, total_height
, mt
->cpp
,
678 /* If the BO is too large to fit in the aperture, we need to use the
679 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
680 * handle Y-tiling, so we need to fall back to X.
682 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
683 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
684 mt
->total_width
, mt
->total_height
);
686 mt
->tiling
= I915_TILING_X
;
687 drm_intel_bo_unreference(mt
->bo
);
688 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
689 total_width
, total_height
, mt
->cpp
,
690 &mt
->tiling
, &pitch
, alloc_flags
);
697 intel_miptree_release(&mt
);
702 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
703 assert(mt
->num_samples
> 1);
704 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
705 intel_miptree_release(&mt
);
710 /* If this miptree is capable of supporting fast color clears, set
711 * fast_clear_state appropriately to ensure that fast clears will occur.
712 * Allocation of the MCS miptree will be deferred until the first fast
713 * clear actually occurs.
715 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
716 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
717 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
718 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
724 struct intel_mipmap_tree
*
725 intel_miptree_create_for_bo(struct brw_context
*brw
,
733 uint32_t layout_flags
)
735 struct intel_mipmap_tree
*mt
;
736 uint32_t tiling
, swizzle
;
739 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
741 /* Nothing will be able to use this miptree with the BO if the offset isn't
744 if (tiling
!= I915_TILING_NONE
)
745 assert(offset
% 4096 == 0);
747 /* miptrees can't handle negative pitch. If you need flipping of images,
748 * that's outside of the scope of the mt.
752 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
754 /* The BO already has a tiling format and we shouldn't confuse the lower
755 * layers by making it try to find a tiling format again.
757 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
758 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
760 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
761 mt
= intel_miptree_create_layout(brw
, target
, format
,
763 width
, height
, depth
, 0,
768 drm_intel_bo_reference(bo
);
778 * For a singlesample renderbuffer, this simply wraps the given BO with a
781 * For a multisample renderbuffer, this wraps the window system's
782 * (singlesample) BO with a singlesample miptree attached to the
783 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
784 * that will contain the actual rendering (which is lazily resolved to
785 * irb->singlesample_mt).
788 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
789 struct intel_renderbuffer
*irb
,
791 uint32_t width
, uint32_t height
,
794 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
795 struct intel_mipmap_tree
*multisample_mt
= NULL
;
796 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
797 mesa_format format
= rb
->Format
;
798 int num_samples
= rb
->NumSamples
;
800 /* Only the front and back buffers, which are color buffers, are allocated
801 * through the image loader.
803 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
804 _mesa_get_format_base_format(format
) == GL_RGBA
);
806 singlesample_mt
= intel_miptree_create_for_bo(intel
,
815 if (!singlesample_mt
)
818 /* If this miptree is capable of supporting fast color clears, set
819 * mcs_state appropriately to ensure that fast clears will occur.
820 * Allocation of the MCS miptree will be deferred until the first fast
821 * clear actually occurs.
823 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
824 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
825 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
828 if (num_samples
== 0) {
829 intel_miptree_release(&irb
->mt
);
830 irb
->mt
= singlesample_mt
;
832 assert(!irb
->singlesample_mt
);
834 intel_miptree_release(&irb
->singlesample_mt
);
835 irb
->singlesample_mt
= singlesample_mt
;
838 irb
->mt
->logical_width0
!= width
||
839 irb
->mt
->logical_height0
!= height
) {
840 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
848 irb
->need_downsample
= false;
849 intel_miptree_release(&irb
->mt
);
850 irb
->mt
= multisample_mt
;
856 intel_miptree_release(&irb
->singlesample_mt
);
857 intel_miptree_release(&irb
->mt
);
861 struct intel_mipmap_tree
*
862 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
866 uint32_t num_samples
)
868 struct intel_mipmap_tree
*mt
;
871 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
872 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
873 MIPTREE_LAYOUT_TILING_ANY
;
876 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
877 width
, height
, depth
, num_samples
,
882 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
883 ok
= intel_miptree_alloc_hiz(brw
, mt
);
891 intel_miptree_release(&mt
);
896 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
897 struct intel_mipmap_tree
*src
)
902 intel_miptree_release(dst
);
906 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
914 intel_miptree_release(struct intel_mipmap_tree
**mt
)
919 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
920 if (--(*mt
)->refcount
<= 0) {
923 DBG("%s deleting %p\n", __func__
, *mt
);
925 drm_intel_bo_unreference((*mt
)->bo
);
926 intel_miptree_release(&(*mt
)->stencil_mt
);
927 if ((*mt
)->hiz_buf
) {
928 if ((*mt
)->hiz_buf
->mt
)
929 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
931 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
932 free((*mt
)->hiz_buf
);
934 intel_miptree_release(&(*mt
)->mcs_mt
);
935 intel_resolve_map_clear(&(*mt
)->hiz_map
);
937 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
938 free((*mt
)->level
[i
].slice
);
948 intel_get_image_dims(struct gl_texture_image
*image
,
949 int *width
, int *height
, int *depth
)
951 switch (image
->TexObject
->Target
) {
952 case GL_TEXTURE_1D_ARRAY
:
953 /* For a 1D Array texture the OpenGL API will treat the image height as
954 * the number of array slices. For Intel hardware, we treat the 1D array
955 * as a 2D Array with a height of 1. So, here we want to swap image
958 *width
= image
->Width
;
960 *depth
= image
->Height
;
963 *width
= image
->Width
;
964 *height
= image
->Height
;
965 *depth
= image
->Depth
;
971 * Can the image be pulled into a unified mipmap tree? This mirrors
972 * the completeness test in a lot of ways.
974 * Not sure whether I want to pass gl_texture_image here.
977 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
978 struct gl_texture_image
*image
)
980 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
981 GLuint level
= intelImage
->base
.Base
.Level
;
982 int width
, height
, depth
;
984 /* glTexImage* choose the texture object based on the target passed in, and
985 * objects can't change targets over their lifetimes, so this should be
988 assert(image
->TexObject
->Target
== mt
->target
);
990 mesa_format mt_format
= mt
->format
;
991 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
992 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
993 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
994 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
995 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
996 mt_format
= mt
->etc_format
;
998 if (image
->TexFormat
!= mt_format
)
1001 intel_get_image_dims(image
, &width
, &height
, &depth
);
1003 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1006 int level_depth
= mt
->level
[level
].depth
;
1007 if (mt
->num_samples
> 1) {
1008 switch (mt
->msaa_layout
) {
1009 case INTEL_MSAA_LAYOUT_NONE
:
1010 case INTEL_MSAA_LAYOUT_IMS
:
1012 case INTEL_MSAA_LAYOUT_UMS
:
1013 case INTEL_MSAA_LAYOUT_CMS
:
1014 level_depth
/= mt
->num_samples
;
1019 /* Test image dimensions against the base level image adjusted for
1020 * minification. This will also catch images not present in the
1021 * tree, changed targets, etc.
1023 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1024 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1025 depth
!= level_depth
) {
1029 if (image
->NumSamples
!= mt
->num_samples
)
1037 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1039 GLuint x
, GLuint y
, GLuint d
)
1041 mt
->level
[level
].depth
= d
;
1042 mt
->level
[level
].level_x
= x
;
1043 mt
->level
[level
].level_y
= y
;
1045 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1048 assert(mt
->level
[level
].slice
== NULL
);
1050 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1051 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1052 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1057 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1058 GLuint level
, GLuint img
,
1061 if (img
== 0 && level
== 0)
1062 assert(x
== 0 && y
== 0);
1064 assert(img
< mt
->level
[level
].depth
);
1066 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1067 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1069 DBG("%s level %d img %d pos %d,%d\n",
1070 __func__
, level
, img
,
1071 mt
->level
[level
].slice
[img
].x_offset
,
1072 mt
->level
[level
].slice
[img
].y_offset
);
1076 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1077 GLuint level
, GLuint slice
,
1078 GLuint
*x
, GLuint
*y
)
1080 assert(slice
< mt
->level
[level
].depth
);
1082 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1083 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1088 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1089 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1090 * and tile_h is set to 1.
1093 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1094 uint32_t *tile_w
, uint32_t *tile_h
)
1096 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1106 case I915_TILING_NONE
:
1111 unreachable("not reached");
1114 uint32_t aspect_ratio
= 1;
1115 assert(_mesa_is_pow_two(cpp
));
1130 unreachable("not reached");
1133 if (cpp
== 2 || cpp
== 8)
1136 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1139 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1145 * This function computes masks that may be used to select the bits of the X
1146 * and Y coordinates that indicate the offset within a tile. If the BO is
1147 * untiled, the masks are set to 0.
1150 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1151 bool map_stencil_as_y_tiled
,
1152 uint32_t *mask_x
, uint32_t *mask_y
)
1154 uint32_t tile_w_bytes
, tile_h
;
1155 if (map_stencil_as_y_tiled
)
1156 tiling
= I915_TILING_Y
;
1158 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1160 *mask_x
= tile_w_bytes
/ cpp
- 1;
1161 *mask_y
= tile_h
- 1;
1165 * Compute the offset (in bytes) from the start of the BO to the given x
1166 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1167 * multiples of the tile size.
1170 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1171 uint32_t x
, uint32_t y
,
1172 bool map_stencil_as_y_tiled
)
1175 uint32_t pitch
= mt
->pitch
;
1176 uint32_t tiling
= mt
->tiling
;
1178 if (map_stencil_as_y_tiled
) {
1179 tiling
= I915_TILING_Y
;
1181 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1182 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1183 * the resulting surface is twice the pitch of the original miptree,
1184 * since each row in the Y-tiled view corresponds to two rows in the
1185 * actual W-tiled surface. So we need to correct the pitch before
1186 * computing the offsets.
1193 unreachable("not reached");
1194 case I915_TILING_NONE
:
1195 return y
* pitch
+ x
* cpp
;
1197 assert((x
% (512 / cpp
)) == 0);
1198 assert((y
% 8) == 0);
1199 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1201 assert((x
% (128 / cpp
)) == 0);
1202 assert((y
% 32) == 0);
1203 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1208 * Rendering with tiled buffers requires that the base address of the buffer
1209 * be aligned to a page boundary. For renderbuffers, and sometimes with
1210 * textures, we may want the surface to point at a texture image level that
1211 * isn't at a page boundary.
1213 * This function returns an appropriately-aligned base offset
1214 * according to the tiling restrictions, plus any required x/y offset
1218 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1219 GLuint level
, GLuint slice
,
1224 uint32_t mask_x
, mask_y
;
1226 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1227 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1229 *tile_x
= x
& mask_x
;
1230 *tile_y
= y
& mask_y
;
1232 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1236 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1237 struct intel_mipmap_tree
*dst_mt
,
1238 struct intel_mipmap_tree
*src_mt
,
1245 ptrdiff_t src_stride
, dst_stride
;
1246 int cpp
= dst_mt
->cpp
;
1248 intel_miptree_map(brw
, src_mt
,
1252 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1255 intel_miptree_map(brw
, dst_mt
,
1259 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1263 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1264 _mesa_get_format_name(src_mt
->format
),
1265 src_mt
, src
, src_stride
,
1266 _mesa_get_format_name(dst_mt
->format
),
1267 dst_mt
, dst
, dst_stride
,
1270 int row_size
= cpp
* width
;
1271 if (src_stride
== row_size
&&
1272 dst_stride
== row_size
) {
1273 memcpy(dst
, src
, row_size
* height
);
1275 for (int i
= 0; i
< height
; i
++) {
1276 memcpy(dst
, src
, row_size
);
1282 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1283 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1285 /* Don't forget to copy the stencil data over, too. We could have skipped
1286 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1287 * shuffling the two data sources in/out of temporary storage instead of
1288 * the direct mapping we get this way.
1290 if (dst_mt
->stencil_mt
) {
1291 assert(src_mt
->stencil_mt
);
1292 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1293 level
, slice
, width
, height
);
1298 intel_miptree_copy_slice(struct brw_context
*brw
,
1299 struct intel_mipmap_tree
*dst_mt
,
1300 struct intel_mipmap_tree
*src_mt
,
1306 mesa_format format
= src_mt
->format
;
1307 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1308 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1316 assert(depth
< src_mt
->level
[level
].depth
);
1317 assert(src_mt
->format
== dst_mt
->format
);
1319 if (dst_mt
->compressed
) {
1321 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1322 height
= ALIGN_NPOT(height
, j
) / j
;
1323 width
= ALIGN_NPOT(width
, i
) / i
;
1326 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1327 * below won't apply since we can't do the depth's Y tiling or the
1328 * stencil's W tiling in the blitter.
1330 if (src_mt
->stencil_mt
) {
1331 intel_miptree_copy_slice_sw(brw
,
1338 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1339 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1340 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1342 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1343 _mesa_get_format_name(src_mt
->format
),
1344 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1345 _mesa_get_format_name(dst_mt
->format
),
1346 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1349 if (!intel_miptree_blit(brw
,
1350 src_mt
, level
, slice
, 0, 0, false,
1351 dst_mt
, level
, slice
, 0, 0, false,
1352 width
, height
, GL_COPY
)) {
1353 perf_debug("miptree validate blit for %s failed\n",
1354 _mesa_get_format_name(format
));
1356 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1362 * Copies the image's current data to the given miptree, and associates that
1363 * miptree with the image.
1365 * If \c invalidate is true, then the actual image data does not need to be
1366 * copied, but the image still needs to be associated to the new miptree (this
1367 * is set to true if we're about to clear the image).
1370 intel_miptree_copy_teximage(struct brw_context
*brw
,
1371 struct intel_texture_image
*intelImage
,
1372 struct intel_mipmap_tree
*dst_mt
,
1375 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1376 struct intel_texture_object
*intel_obj
=
1377 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1378 int level
= intelImage
->base
.Base
.Level
;
1379 int face
= intelImage
->base
.Base
.Face
;
1382 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1383 depth
= intelImage
->base
.Base
.Height
;
1385 depth
= intelImage
->base
.Base
.Depth
;
1388 for (int slice
= 0; slice
< depth
; slice
++) {
1389 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1393 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1394 intel_obj
->needs_validate
= true;
1398 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1399 struct intel_mipmap_tree
*mt
,
1402 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1403 assert(mt
->mcs_mt
== NULL
);
1404 assert(!mt
->disable_aux_buffers
);
1406 /* Choose the correct format for the MCS buffer. All that really matters
1407 * is that we allocate the right buffer size, since we'll always be
1408 * accessing this miptree using MCS-specific hardware mechanisms, which
1409 * infer the correct format based on num_samples.
1412 switch (num_samples
) {
1415 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1418 format
= MESA_FORMAT_R_UNORM8
;
1421 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1422 * for each sample, plus 8 padding bits).
1424 format
= MESA_FORMAT_R_UINT32
;
1427 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1430 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1432 * "The MCS surface must be stored as Tile Y."
1434 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1435 MIPTREE_LAYOUT_TILING_Y
;
1436 mt
->mcs_mt
= intel_miptree_create(brw
,
1442 mt
->logical_height0
,
1444 0 /* num_samples */,
1447 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1449 * When MCS buffer is enabled and bound to MSRT, it is required that it
1450 * is cleared prior to any rendering.
1452 * Since we don't use the MCS buffer for any purpose other than rendering,
1453 * it makes sense to just clear it immediately upon allocation.
1455 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1457 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1458 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1459 intel_miptree_unmap_raw(mt
->mcs_mt
);
1460 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1467 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1468 struct intel_mipmap_tree
*mt
)
1470 assert(mt
->mcs_mt
== NULL
);
1471 assert(!mt
->disable_aux_buffers
);
1473 /* The format of the MCS buffer is opaque to the driver; all that matters
1474 * is that we get its size and pitch right. We'll pretend that the format
1475 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1476 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1477 * the block width and then a further factor of 4. Since an MCS tile
1478 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1479 * we'll need to scale the height down by the block height and then a
1480 * further factor of 8.
1482 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1483 unsigned block_width_px
;
1484 unsigned block_height
;
1485 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1486 unsigned width_divisor
= block_width_px
* 4;
1487 unsigned height_divisor
= block_height
* 8;
1488 unsigned mcs_width
=
1489 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1490 unsigned mcs_height
=
1491 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1492 assert(mt
->logical_depth0
== 1);
1493 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1494 MIPTREE_LAYOUT_TILING_Y
;
1495 if (brw
->gen
>= 8) {
1496 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1498 mt
->mcs_mt
= intel_miptree_create(brw
,
1506 0 /* num_samples */,
1514 * Helper for intel_miptree_alloc_hiz() that sets
1515 * \c mt->level[level].has_hiz. Return true if and only if
1516 * \c has_hiz was set.
1519 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1520 struct intel_mipmap_tree
*mt
,
1523 assert(mt
->hiz_buf
);
1525 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1526 uint32_t width
= minify(mt
->physical_width0
, level
);
1527 uint32_t height
= minify(mt
->physical_height0
, level
);
1529 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1530 * and the height is 4 aligned. This allows our HiZ support
1531 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1532 * we can grow the width & height to allow the HiZ op to
1533 * force the proper size alignments.
1535 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1536 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1541 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1542 mt
->level
[level
].has_hiz
= true;
1548 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1549 * buffer dimensions and allocates a bo for the hiz buffer.
1551 static struct intel_miptree_aux_buffer
*
1552 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1553 struct intel_mipmap_tree
*mt
)
1555 unsigned z_width
= mt
->logical_width0
;
1556 unsigned z_height
= mt
->logical_height0
;
1557 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1558 unsigned hz_width
, hz_height
;
1559 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1564 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1565 * adjustments required for Z_Height and Z_Width based on multisampling.
1567 switch (mt
->num_samples
) {
1581 unreachable("unsupported sample count");
1584 const unsigned vertical_align
= 8; /* 'j' in the docs */
1585 const unsigned H0
= z_height
;
1586 const unsigned h0
= ALIGN(H0
, vertical_align
);
1587 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1588 const unsigned Z0
= z_depth
;
1590 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1591 hz_width
= ALIGN(z_width
, 16);
1593 if (mt
->target
== GL_TEXTURE_3D
) {
1597 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1598 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1599 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1600 hz_height
+= h_i
* Z_i
;
1601 H_i
= minify(H_i
, 1);
1602 Z_i
= minify(Z_i
, 1);
1605 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1607 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1609 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1610 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1611 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1612 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1613 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1615 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1616 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1620 unsigned long pitch
;
1621 uint32_t tiling
= I915_TILING_Y
;
1622 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1623 hz_width
, hz_height
, 1,
1625 BO_ALLOC_FOR_RENDER
);
1629 } else if (tiling
!= I915_TILING_Y
) {
1630 drm_intel_bo_unreference(buf
->bo
);
1642 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1643 * buffer dimensions and allocates a bo for the hiz buffer.
1645 static struct intel_miptree_aux_buffer
*
1646 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1647 struct intel_mipmap_tree
*mt
)
1649 unsigned z_width
= mt
->logical_width0
;
1650 unsigned z_height
= mt
->logical_height0
;
1651 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1652 unsigned hz_width
, hz_height
;
1653 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1658 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1659 * adjustments required for Z_Height and Z_Width based on multisampling.
1662 switch (mt
->num_samples
) {
1676 unreachable("unsupported sample count");
1680 const unsigned vertical_align
= 8; /* 'j' in the docs */
1681 const unsigned H0
= z_height
;
1682 const unsigned h0
= ALIGN(H0
, vertical_align
);
1683 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1684 const unsigned Z0
= z_depth
;
1686 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1687 hz_width
= ALIGN(z_width
, 16);
1691 unsigned sum_h_i
= 0;
1692 unsigned hz_height_3d_sum
= 0;
1693 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1694 unsigned i
= level
- mt
->first_level
;
1695 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1696 /* sum(i=2 to m; h_i) */
1700 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1701 hz_height_3d_sum
+= h_i
* Z_i
;
1702 H_i
= minify(H_i
, 1);
1703 Z_i
= minify(Z_i
, 1);
1705 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1706 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1708 if (mt
->target
== GL_TEXTURE_3D
) {
1709 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1710 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1712 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1713 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1714 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1715 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1716 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1718 * We can can just take our hz_height calculation from above, and
1719 * multiply by 6 for the cube map and cube map array types.
1725 unsigned long pitch
;
1726 uint32_t tiling
= I915_TILING_Y
;
1727 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1728 hz_width
, hz_height
, 1,
1730 BO_ALLOC_FOR_RENDER
);
1734 } else if (tiling
!= I915_TILING_Y
) {
1735 drm_intel_bo_unreference(buf
->bo
);
1746 static struct intel_miptree_aux_buffer
*
1747 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1748 struct intel_mipmap_tree
*mt
)
1750 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1751 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1754 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1759 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1760 buf
->mt
= intel_miptree_create(brw
,
1766 mt
->logical_height0
,
1775 buf
->bo
= buf
->mt
->bo
;
1776 buf
->pitch
= buf
->mt
->pitch
;
1777 buf
->qpitch
= buf
->mt
->qpitch
;
1783 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1784 struct intel_mipmap_tree
*mt
)
1789 if (mt
->hiz_buf
!= NULL
)
1792 if (mt
->disable_aux_buffers
)
1795 switch (mt
->format
) {
1796 case MESA_FORMAT_Z_FLOAT32
:
1797 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1798 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1799 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1800 case MESA_FORMAT_Z_UNORM16
:
1808 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1809 struct intel_mipmap_tree
*mt
)
1811 assert(mt
->hiz_buf
== NULL
);
1812 assert(!mt
->disable_aux_buffers
);
1814 if (brw
->gen
== 7) {
1815 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1816 } else if (brw
->gen
>= 8) {
1817 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1819 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1825 /* Mark that all slices need a HiZ resolve. */
1826 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1827 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1830 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1831 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1832 exec_node_init(&m
->link
);
1835 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1837 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1845 * Does the miptree slice have hiz enabled?
1848 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1850 intel_miptree_check_level_layer(mt
, level
, 0);
1851 return mt
->level
[level
].has_hiz
;
1855 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1859 if (!intel_miptree_level_has_hiz(mt
, level
))
1862 intel_resolve_map_set(&mt
->hiz_map
,
1863 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1868 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1872 if (!intel_miptree_level_has_hiz(mt
, level
))
1875 intel_resolve_map_set(&mt
->hiz_map
,
1876 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1880 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1884 uint32_t end_layer
= mt
->level
[level
].depth
;
1886 for (layer
= 0; layer
< end_layer
; layer
++) {
1887 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1892 intel_miptree_slice_resolve(struct brw_context
*brw
,
1893 struct intel_mipmap_tree
*mt
,
1896 enum gen6_hiz_op need
)
1898 intel_miptree_check_level_layer(mt
, level
, layer
);
1900 struct intel_resolve_map
*item
=
1901 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1903 if (!item
|| item
->need
!= need
)
1906 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1907 intel_resolve_map_remove(item
);
1912 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1913 struct intel_mipmap_tree
*mt
,
1917 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1918 GEN6_HIZ_OP_HIZ_RESOLVE
);
1922 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1923 struct intel_mipmap_tree
*mt
,
1927 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1928 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1932 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1933 struct intel_mipmap_tree
*mt
,
1934 enum gen6_hiz_op need
)
1936 bool did_resolve
= false;
1938 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1939 if (map
->need
!= need
)
1942 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1943 intel_resolve_map_remove(map
);
1951 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1952 struct intel_mipmap_tree
*mt
)
1954 return intel_miptree_all_slices_resolve(brw
, mt
,
1955 GEN6_HIZ_OP_HIZ_RESOLVE
);
1959 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1960 struct intel_mipmap_tree
*mt
)
1962 return intel_miptree_all_slices_resolve(brw
, mt
,
1963 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1968 intel_miptree_resolve_color(struct brw_context
*brw
,
1969 struct intel_mipmap_tree
*mt
)
1971 switch (mt
->fast_clear_state
) {
1972 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1973 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1974 /* No resolve needed */
1976 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1977 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1978 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1979 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1980 brw_meta_resolve_color(brw
, mt
);
1987 * Make it possible to share the BO backing the given miptree with another
1988 * process or another miptree.
1990 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1991 * then discard the MCS buffer, if present. We also set the fast_clear_state
1992 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1993 * allocated in the future.
1996 intel_miptree_make_shareable(struct brw_context
*brw
,
1997 struct intel_mipmap_tree
*mt
)
1999 /* MCS buffers are also used for multisample buffers, but we can't resolve
2000 * away a multisample MCS buffer because it's an integral part of how the
2001 * pixel data is stored. Fortunately this code path should never be
2002 * reached for multisample buffers.
2004 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2007 intel_miptree_resolve_color(brw
, mt
);
2008 intel_miptree_release(&mt
->mcs_mt
);
2009 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2015 * \brief Get pointer offset into stencil buffer.
2017 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2018 * must decode the tile's layout in software.
2021 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2023 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2025 * Even though the returned offset is always positive, the return type is
2027 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2028 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2031 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2033 uint32_t tile_size
= 4096;
2034 uint32_t tile_width
= 64;
2035 uint32_t tile_height
= 64;
2036 uint32_t row_size
= 64 * stride
;
2038 uint32_t tile_x
= x
/ tile_width
;
2039 uint32_t tile_y
= y
/ tile_height
;
2041 /* The byte's address relative to the tile's base addres. */
2042 uint32_t byte_x
= x
% tile_width
;
2043 uint32_t byte_y
= y
% tile_height
;
2045 uintptr_t u
= tile_y
* row_size
2046 + tile_x
* tile_size
2047 + 512 * (byte_x
/ 8)
2049 + 32 * ((byte_y
/ 4) % 2)
2050 + 16 * ((byte_x
/ 4) % 2)
2051 + 8 * ((byte_y
/ 2) % 2)
2052 + 4 * ((byte_x
/ 2) % 2)
2057 /* adjust for bit6 swizzling */
2058 if (((byte_x
/ 8) % 2) == 1) {
2059 if (((byte_y
/ 8) % 2) == 0) {
2071 intel_miptree_updownsample(struct brw_context
*brw
,
2072 struct intel_mipmap_tree
*src
,
2073 struct intel_mipmap_tree
*dst
)
2076 brw_blorp_blit_miptrees(brw
,
2077 src
, 0 /* level */, 0 /* layer */, src
->format
,
2078 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2080 src
->logical_width0
, src
->logical_height0
,
2082 dst
->logical_width0
, dst
->logical_height0
,
2083 GL_NEAREST
, false, false /*mirror x, y*/);
2084 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2085 brw_meta_stencil_updownsample(brw
, src
, dst
);
2087 brw_meta_updownsample(brw
, src
, dst
);
2090 if (src
->stencil_mt
) {
2091 if (brw
->gen
>= 8) {
2092 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2096 brw_blorp_blit_miptrees(brw
,
2097 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2098 src
->stencil_mt
->format
,
2099 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2100 dst
->stencil_mt
->format
,
2102 src
->logical_width0
, src
->logical_height0
,
2104 dst
->logical_width0
, dst
->logical_height0
,
2105 GL_NEAREST
, false, false /*mirror x, y*/);
2110 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2112 /* CPU accesses to color buffers don't understand fast color clears, so
2113 * resolve any pending fast color clears before we map.
2115 intel_miptree_resolve_color(brw
, mt
);
2117 drm_intel_bo
*bo
= mt
->bo
;
2119 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2120 intel_batchbuffer_flush(brw
);
2122 if (mt
->tiling
!= I915_TILING_NONE
)
2123 brw_bo_map_gtt(brw
, bo
, "miptree");
2125 brw_bo_map(brw
, bo
, true, "miptree");
2131 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2133 drm_intel_bo_unmap(mt
->bo
);
2137 intel_miptree_map_gtt(struct brw_context
*brw
,
2138 struct intel_mipmap_tree
*mt
,
2139 struct intel_miptree_map
*map
,
2140 unsigned int level
, unsigned int slice
)
2142 unsigned int bw
, bh
;
2144 unsigned int image_x
, image_y
;
2145 intptr_t x
= map
->x
;
2146 intptr_t y
= map
->y
;
2148 /* For compressed formats, the stride is the number of bytes per
2149 * row of blocks. intel_miptree_get_image_offset() already does
2152 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2153 assert(y
% bh
== 0);
2154 assert(x
% bw
== 0);
2158 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2163 /* Note that in the case of cube maps, the caller must have passed the
2164 * slice number referencing the face.
2166 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2170 map
->stride
= mt
->pitch
;
2171 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2174 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2175 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2176 map
->x
, map
->y
, map
->w
, map
->h
,
2177 mt
, _mesa_get_format_name(mt
->format
),
2178 x
, y
, map
->ptr
, map
->stride
);
2182 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2184 intel_miptree_unmap_raw(mt
);
2188 intel_miptree_map_blit(struct brw_context
*brw
,
2189 struct intel_mipmap_tree
*mt
,
2190 struct intel_miptree_map
*map
,
2191 unsigned int level
, unsigned int slice
)
2193 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2194 /* first_level */ 0,
2198 MIPTREE_LAYOUT_TILING_NONE
);
2200 if (!map
->linear_mt
) {
2201 fprintf(stderr
, "Failed to allocate blit temporary\n");
2204 map
->stride
= map
->linear_mt
->pitch
;
2206 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2207 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2208 * invalidate is set, since we'll be writing the whole rectangle from our
2209 * temporary buffer back out.
2211 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2212 if (!intel_miptree_blit(brw
,
2214 map
->x
, map
->y
, false,
2215 map
->linear_mt
, 0, 0,
2217 map
->w
, map
->h
, GL_COPY
)) {
2218 fprintf(stderr
, "Failed to blit\n");
2223 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2225 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2226 map
->x
, map
->y
, map
->w
, map
->h
,
2227 mt
, _mesa_get_format_name(mt
->format
),
2228 level
, slice
, map
->ptr
, map
->stride
);
2233 intel_miptree_release(&map
->linear_mt
);
2239 intel_miptree_unmap_blit(struct brw_context
*brw
,
2240 struct intel_mipmap_tree
*mt
,
2241 struct intel_miptree_map
*map
,
2245 struct gl_context
*ctx
= &brw
->ctx
;
2247 intel_miptree_unmap_raw(map
->linear_mt
);
2249 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2250 bool ok
= intel_miptree_blit(brw
,
2251 map
->linear_mt
, 0, 0,
2254 map
->x
, map
->y
, false,
2255 map
->w
, map
->h
, GL_COPY
);
2256 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2259 intel_miptree_release(&map
->linear_mt
);
2263 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2265 #if defined(USE_SSE41)
2267 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2268 struct intel_mipmap_tree
*mt
,
2269 struct intel_miptree_map
*map
,
2270 unsigned int level
, unsigned int slice
)
2272 assert(map
->mode
& GL_MAP_READ_BIT
);
2273 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2275 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2276 map
->x
, map
->y
, map
->w
, map
->h
,
2277 mt
, _mesa_get_format_name(mt
->format
),
2278 level
, slice
, map
->ptr
, map
->stride
);
2280 /* Map the original image */
2283 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2287 void *src
= intel_miptree_map_raw(brw
, mt
);
2290 src
+= image_y
* mt
->pitch
;
2291 src
+= image_x
* mt
->cpp
;
2293 /* Due to the pixel offsets for the particular image being mapped, our
2294 * src pointer may not be 16-byte aligned. However, if the pitch is
2295 * divisible by 16, then the amount by which it's misaligned will remain
2296 * consistent from row to row.
2298 assert((mt
->pitch
% 16) == 0);
2299 const int misalignment
= ((uintptr_t) src
) & 15;
2301 /* Create an untiled temporary buffer for the mapping. */
2302 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2304 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2306 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2307 /* Offset the destination so it has the same misalignment as src. */
2308 map
->ptr
= map
->buffer
+ misalignment
;
2310 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2312 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2313 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2314 void *src_ptr
= src
+ y
* mt
->pitch
;
2316 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2319 intel_miptree_unmap_raw(mt
);
2323 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2324 struct intel_mipmap_tree
*mt
,
2325 struct intel_miptree_map
*map
,
2329 _mesa_align_free(map
->buffer
);
2336 intel_miptree_map_s8(struct brw_context
*brw
,
2337 struct intel_mipmap_tree
*mt
,
2338 struct intel_miptree_map
*map
,
2339 unsigned int level
, unsigned int slice
)
2341 map
->stride
= map
->w
;
2342 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2346 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2347 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2348 * invalidate is set, since we'll be writing the whole rectangle from our
2349 * temporary buffer back out.
2351 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2352 uint8_t *untiled_s8_map
= map
->ptr
;
2353 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2354 unsigned int image_x
, image_y
;
2356 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2358 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2359 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2360 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2361 x
+ image_x
+ map
->x
,
2362 y
+ image_y
+ map
->y
,
2363 brw
->has_swizzling
);
2364 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2368 intel_miptree_unmap_raw(mt
);
2370 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2371 map
->x
, map
->y
, map
->w
, map
->h
,
2372 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2374 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2375 map
->x
, map
->y
, map
->w
, map
->h
,
2376 mt
, map
->ptr
, map
->stride
);
2381 intel_miptree_unmap_s8(struct brw_context
*brw
,
2382 struct intel_mipmap_tree
*mt
,
2383 struct intel_miptree_map
*map
,
2387 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2388 unsigned int image_x
, image_y
;
2389 uint8_t *untiled_s8_map
= map
->ptr
;
2390 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2392 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2394 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2395 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2396 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2399 brw
->has_swizzling
);
2400 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2404 intel_miptree_unmap_raw(mt
);
2411 intel_miptree_map_etc(struct brw_context
*brw
,
2412 struct intel_mipmap_tree
*mt
,
2413 struct intel_miptree_map
*map
,
2417 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2418 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2419 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2422 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2423 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2425 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2426 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2427 map
->w
, map
->h
, 1));
2428 map
->ptr
= map
->buffer
;
2432 intel_miptree_unmap_etc(struct brw_context
*brw
,
2433 struct intel_mipmap_tree
*mt
,
2434 struct intel_miptree_map
*map
,
2440 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2445 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2446 + image_y
* mt
->pitch
2447 + image_x
* mt
->cpp
;
2449 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2450 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2451 map
->ptr
, map
->stride
,
2454 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2455 map
->ptr
, map
->stride
,
2456 map
->w
, map
->h
, mt
->etc_format
);
2458 intel_miptree_unmap_raw(mt
);
2463 * Mapping function for packed depth/stencil miptrees backed by real separate
2464 * miptrees for depth and stencil.
2466 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2467 * separate from the depth buffer. Yet at the GL API level, we have to expose
2468 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2469 * be able to map that memory for texture storage and glReadPixels-type
2470 * operations. We give Mesa core that access by mallocing a temporary and
2471 * copying the data between the actual backing store and the temporary.
2474 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2475 struct intel_mipmap_tree
*mt
,
2476 struct intel_miptree_map
*map
,
2477 unsigned int level
, unsigned int slice
)
2479 struct intel_mipmap_tree
*z_mt
= mt
;
2480 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2481 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2482 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2484 map
->stride
= map
->w
* packed_bpp
;
2485 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2489 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2490 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2491 * invalidate is set, since we'll be writing the whole rectangle from our
2492 * temporary buffer back out.
2494 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2495 uint32_t *packed_map
= map
->ptr
;
2496 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2497 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2498 unsigned int s_image_x
, s_image_y
;
2499 unsigned int z_image_x
, z_image_y
;
2501 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2502 &s_image_x
, &s_image_y
);
2503 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2504 &z_image_x
, &z_image_y
);
2506 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2507 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2508 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2509 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2512 brw
->has_swizzling
);
2513 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2515 (map_x
+ z_image_x
));
2516 uint8_t s
= s_map
[s_offset
];
2517 uint32_t z
= z_map
[z_offset
];
2519 if (map_z32f_x24s8
) {
2520 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2521 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2523 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2528 intel_miptree_unmap_raw(s_mt
);
2529 intel_miptree_unmap_raw(z_mt
);
2531 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2533 map
->x
, map
->y
, map
->w
, map
->h
,
2534 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2535 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2536 map
->ptr
, map
->stride
);
2538 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2539 map
->x
, map
->y
, map
->w
, map
->h
,
2540 mt
, map
->ptr
, map
->stride
);
2545 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2546 struct intel_mipmap_tree
*mt
,
2547 struct intel_miptree_map
*map
,
2551 struct intel_mipmap_tree
*z_mt
= mt
;
2552 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2553 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2555 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2556 uint32_t *packed_map
= map
->ptr
;
2557 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2558 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2559 unsigned int s_image_x
, s_image_y
;
2560 unsigned int z_image_x
, z_image_y
;
2562 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2563 &s_image_x
, &s_image_y
);
2564 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2565 &z_image_x
, &z_image_y
);
2567 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2568 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2569 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2570 x
+ s_image_x
+ map
->x
,
2571 y
+ s_image_y
+ map
->y
,
2572 brw
->has_swizzling
);
2573 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2575 (x
+ z_image_x
+ map
->x
));
2577 if (map_z32f_x24s8
) {
2578 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2579 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2581 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2582 s_map
[s_offset
] = packed
>> 24;
2583 z_map
[z_offset
] = packed
;
2588 intel_miptree_unmap_raw(s_mt
);
2589 intel_miptree_unmap_raw(z_mt
);
2591 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2593 map
->x
, map
->y
, map
->w
, map
->h
,
2594 z_mt
, _mesa_get_format_name(z_mt
->format
),
2595 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2596 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2597 map
->ptr
, map
->stride
);
2604 * Create and attach a map to the miptree at (level, slice). Return the
2607 static struct intel_miptree_map
*
2608 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2617 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2622 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2623 mt
->level
[level
].slice
[slice
].map
= map
;
2635 * Release the map at (level, slice).
2638 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2642 struct intel_miptree_map
**map
;
2644 map
= &mt
->level
[level
].slice
[slice
].map
;
2650 can_blit_slice(struct intel_mipmap_tree
*mt
,
2651 unsigned int level
, unsigned int slice
)
2655 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2656 if (image_x
>= 32768 || image_y
>= 32768)
2659 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2660 if (mt
->pitch
>= 32768)
2667 use_intel_mipree_map_blit(struct brw_context
*brw
,
2668 struct intel_mipmap_tree
*mt
,
2674 /* It's probably not worth swapping to the blit ring because of
2675 * all the overhead involved.
2677 !(mode
& GL_MAP_WRITE_BIT
) &&
2679 (mt
->tiling
== I915_TILING_X
||
2680 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2681 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2682 can_blit_slice(mt
, level
, slice
))
2685 if (mt
->tiling
!= I915_TILING_NONE
&&
2686 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2687 assert(can_blit_slice(mt
, level
, slice
));
2695 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2696 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2697 * arithmetic overflow.
2699 * If you call this function and use \a out_stride, then you're doing pointer
2700 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2701 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2702 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2703 * which usually have type uint32_t or GLuint.
2706 intel_miptree_map(struct brw_context
*brw
,
2707 struct intel_mipmap_tree
*mt
,
2716 ptrdiff_t *out_stride
)
2718 struct intel_miptree_map
*map
;
2720 assert(mt
->num_samples
<= 1);
2722 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2729 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2730 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2731 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2734 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2735 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2736 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2737 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2738 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2739 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2740 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2741 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2742 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2743 #if defined(USE_SSE41)
2744 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2745 !mt
->compressed
&& cpu_has_sse4_1
&&
2746 (mt
->pitch
% 16 == 0)) {
2747 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2750 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2753 *out_ptr
= map
->ptr
;
2754 *out_stride
= map
->stride
;
2756 if (map
->ptr
== NULL
)
2757 intel_miptree_release_map(mt
, level
, slice
);
2761 intel_miptree_unmap(struct brw_context
*brw
,
2762 struct intel_mipmap_tree
*mt
,
2766 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2768 assert(mt
->num_samples
<= 1);
2773 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2774 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2776 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2777 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2778 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2779 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2780 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2781 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2782 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2783 } else if (map
->linear_mt
) {
2784 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2785 #if defined(USE_SSE41)
2786 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2787 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2790 intel_miptree_unmap_gtt(mt
);
2793 intel_miptree_release_map(mt
, level
, slice
);