1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_resolve_map.h"
35 #include "intel_tex.h"
36 #include "intel_blit.h"
37 #include "intel_fbo.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* Disable MCS on Broadwell for now. We can enable it once things
72 * are working without it.
75 perf_debug("Missing CMS support on Broadwell.\n");
76 return INTEL_MSAA_LAYOUT_UMS
;
79 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
81 * This field must be set to 0 for all SINT MSRTs when all RT channels
84 * In practice this means that we have to disable MCS for all signed
85 * integer MSAA buffers. The alternative, to disable MCS only when one
86 * of the render target channels is disabled, is impractical because it
87 * would require converting between CMS and UMS MSAA layouts on the fly,
90 if (_mesa_get_format_datatype(format
) == GL_INT
) {
91 /* TODO: is this workaround needed for future chipsets? */
92 assert(brw
->gen
== 7);
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->tiling
) {
149 assert(!"Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
163 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
170 * - Support is for non-mip-mapped and non-array surface types only.
172 * And then later, on p327:
174 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
178 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
179 struct intel_mipmap_tree
*mt
)
181 /* MCS support does not exist prior to Gen7 */
182 if (brw
->gen
< 7 || brw
->gen
>= 8)
185 /* MCS is only supported for color buffers */
186 switch (_mesa_get_format_base_format(mt
->format
)) {
187 case GL_DEPTH_COMPONENT
:
188 case GL_DEPTH_STENCIL
:
189 case GL_STENCIL_INDEX
:
193 if (mt
->tiling
!= I915_TILING_X
&&
194 mt
->tiling
!= I915_TILING_Y
)
196 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
198 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
200 if (mt
->physical_depth0
!= 1)
203 /* There's no point in using an MCS buffer if the surface isn't in a
206 if (!brw
->format_supported_as_render_target
[mt
->format
])
214 * Determine depth format corresponding to a depth+stencil format,
215 * for separate stencil.
218 intel_depth_format_for_depthstencil_format(mesa_format format
) {
220 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
221 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
222 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
223 return MESA_FORMAT_Z_FLOAT32
;
231 * @param for_bo Indicates that the caller is
232 * intel_miptree_create_for_bo(). If true, then do not create
235 struct intel_mipmap_tree
*
236 intel_miptree_create_layout(struct brw_context
*brw
,
247 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
251 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
252 _mesa_lookup_enum_by_nr(target
),
253 _mesa_get_format_name(format
),
254 first_level
, last_level
, depth0
, mt
);
258 mt
->first_level
= first_level
;
259 mt
->last_level
= last_level
;
260 mt
->logical_width0
= width0
;
261 mt
->logical_height0
= height0
;
262 mt
->logical_depth0
= depth0
;
263 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
265 /* The cpp is bytes per (1, blockheight)-sized block for compressed
266 * textures. This is why you'll see divides by blockheight all over
269 _mesa_get_format_block_size(format
, &bw
, &bh
);
270 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
271 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
273 mt
->num_samples
= num_samples
;
274 mt
->compressed
= _mesa_is_format_compressed(format
);
275 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
278 if (num_samples
> 1) {
279 /* Adjust width/height/depth for MSAA */
280 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
281 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
282 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
284 * "Any of the other messages (sample*, LOD, load4) used with a
285 * (4x) multisampled surface will in-effect sample a surface with
286 * double the height and width as that indicated in the surface
287 * state. Each pixel position on the original-sized surface is
288 * replaced with a 2x2 of samples with the following arrangement:
293 * Thus, when sampling from a multisampled texture, it behaves as
294 * though the layout in memory for (x,y,sample) is:
296 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
297 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
299 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
300 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
302 * However, the actual layout of multisampled data in memory is:
304 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
305 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
307 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
308 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
310 * This pattern repeats for each 2x2 pixel block.
312 * As a result, when calculating the size of our 4-sample buffer for
313 * an odd width or height, we have to align before scaling up because
314 * sample 3 is in that bottom right 2x2 block.
316 switch (num_samples
) {
318 assert(brw
->gen
>= 8);
319 width0
= ALIGN(width0
, 2) * 2;
320 height0
= ALIGN(height0
, 2);
323 width0
= ALIGN(width0
, 2) * 2;
324 height0
= ALIGN(height0
, 2) * 2;
327 width0
= ALIGN(width0
, 2) * 4;
328 height0
= ALIGN(height0
, 2) * 2;
331 /* num_samples should already have been quantized to 0, 1, 2, 4, or
337 /* Non-interleaved */
338 depth0
*= num_samples
;
342 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
345 switch (mt
->msaa_layout
) {
346 case INTEL_MSAA_LAYOUT_NONE
:
347 case INTEL_MSAA_LAYOUT_IMS
:
348 mt
->array_spacing_lod0
= false;
350 case INTEL_MSAA_LAYOUT_UMS
:
351 case INTEL_MSAA_LAYOUT_CMS
:
352 mt
->array_spacing_lod0
= true;
356 if (target
== GL_TEXTURE_CUBE_MAP
) {
361 mt
->physical_width0
= width0
;
362 mt
->physical_height0
= height0
;
363 mt
->physical_depth0
= depth0
;
366 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
367 (brw
->must_use_separate_stencil
||
368 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
369 mt
->stencil_mt
= intel_miptree_create(brw
,
379 INTEL_MIPTREE_TILING_ANY
);
380 if (!mt
->stencil_mt
) {
381 intel_miptree_release(&mt
);
385 /* Fix up the Z miptree format for how we're splitting out separate
386 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
388 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
391 if (format
== mt
->format
) {
392 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
393 _mesa_get_format_name(mt
->format
));
397 brw_miptree_layout(brw
, mt
);
403 * \brief Helper function for intel_miptree_create().
406 intel_miptree_choose_tiling(struct brw_context
*brw
,
409 uint32_t num_samples
,
410 enum intel_miptree_tiling_mode requested
,
411 struct intel_mipmap_tree
*mt
)
413 if (format
== MESA_FORMAT_S_UINT8
) {
414 /* The stencil buffer is W tiled. However, we request from the kernel a
415 * non-tiled buffer because the GTT is incapable of W fencing.
417 return I915_TILING_NONE
;
420 /* Some usages may want only one type of tiling, like depth miptrees (Y
421 * tiled), or temporary BOs for uploading data once (linear).
424 case INTEL_MIPTREE_TILING_ANY
:
426 case INTEL_MIPTREE_TILING_Y
:
427 return I915_TILING_Y
;
428 case INTEL_MIPTREE_TILING_NONE
:
429 return I915_TILING_NONE
;
432 if (num_samples
> 1) {
433 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
436 * [DevSNB+]: For multi-sample render targets, this field must be
437 * 1. MSRTs can only be tiled.
439 * Our usual reason for preferring X tiling (fast blits using the
440 * blitting engine) doesn't apply to MSAA, since we'll generally be
441 * downsampling or upsampling when blitting between the MSAA buffer
442 * and another buffer, and the blitting engine doesn't support that.
443 * So use Y tiling, since it makes better use of the cache.
445 return I915_TILING_Y
;
448 GLenum base_format
= _mesa_get_format_base_format(format
);
449 if (base_format
== GL_DEPTH_COMPONENT
||
450 base_format
== GL_DEPTH_STENCIL_EXT
)
451 return I915_TILING_Y
;
453 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
455 /* If the width is much smaller than a tile, don't bother tiling. */
456 if (minimum_pitch
< 64)
457 return I915_TILING_NONE
;
459 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
460 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
461 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
462 mt
->total_width
, mt
->total_height
);
463 return I915_TILING_NONE
;
466 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
468 return I915_TILING_X
;
470 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
471 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
473 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
474 * all the way back to 965, but is explicitly permitted on Gen7.
476 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
477 return I915_TILING_X
;
479 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
480 * messages), on p64, under the heading "Surface Vertical Alignment":
482 * This field must be set to VALIGN_4 for all tiled Y Render Target
485 * So if the surface is renderable and uses a vertical alignment of 2,
486 * force it to be X tiled. This is somewhat conservative (it's possible
487 * that the client won't ever render to this surface), but it's difficult
488 * to know that ahead of time. And besides, since we use a vertical
489 * alignment of 4 as often as we can, this shouldn't happen very often.
491 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
492 brw
->format_supported_as_render_target
[format
]) {
493 return I915_TILING_X
;
496 return I915_TILING_Y
| I915_TILING_X
;
501 * Choose an appropriate uncompressed format for a requested
502 * compressed format, if unsupported.
505 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
507 /* No need to lower ETC formats on these platforms,
508 * they are supported natively.
510 if (brw
->gen
>= 8 || brw
->is_baytrail
)
514 case MESA_FORMAT_ETC1_RGB8
:
515 return MESA_FORMAT_R8G8B8X8_UNORM
;
516 case MESA_FORMAT_ETC2_RGB8
:
517 return MESA_FORMAT_R8G8B8X8_UNORM
;
518 case MESA_FORMAT_ETC2_SRGB8
:
519 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
520 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
521 return MESA_FORMAT_B8G8R8A8_SRGB
;
522 case MESA_FORMAT_ETC2_RGBA8_EAC
:
523 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
524 return MESA_FORMAT_R8G8B8A8_UNORM
;
525 case MESA_FORMAT_ETC2_R11_EAC
:
526 return MESA_FORMAT_R_UNORM16
;
527 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
528 return MESA_FORMAT_R_SNORM16
;
529 case MESA_FORMAT_ETC2_RG11_EAC
:
530 return MESA_FORMAT_R16G16_UNORM
;
531 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
532 return MESA_FORMAT_R16G16_SNORM
;
534 /* Non ETC1 / ETC2 format */
540 struct intel_mipmap_tree
*
541 intel_miptree_create(struct brw_context
*brw
,
549 bool expect_accelerated_upload
,
551 enum intel_miptree_tiling_mode requested_tiling
)
553 struct intel_mipmap_tree
*mt
;
554 mesa_format tex_format
= format
;
555 mesa_format etc_format
= MESA_FORMAT_NONE
;
556 GLuint total_width
, total_height
;
558 format
= intel_lower_compressed_format(brw
, format
);
560 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
562 mt
= intel_miptree_create_layout(brw
, target
, format
,
563 first_level
, last_level
, width0
,
567 * pitch == 0 || height == 0 indicates the null texture
569 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
570 intel_miptree_release(&mt
);
574 total_width
= mt
->total_width
;
575 total_height
= mt
->total_height
;
577 if (format
== MESA_FORMAT_S_UINT8
) {
578 /* Align to size of W tile, 64x64. */
579 total_width
= ALIGN(total_width
, 64);
580 total_height
= ALIGN(total_height
, 64);
583 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
584 num_samples
, requested_tiling
,
588 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
590 mt
->tiling
= I915_TILING_Y
;
596 mt
->etc_format
= etc_format
;
597 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
598 total_width
, total_height
, mt
->cpp
,
600 (expect_accelerated_upload
?
601 BO_ALLOC_FOR_RENDER
: 0));
604 /* If the BO is too large to fit in the aperture, we need to use the
605 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
606 * so we need to fall back to X.
608 if (y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
609 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
610 mt
->total_width
, mt
->total_height
);
612 mt
->tiling
= I915_TILING_X
;
613 drm_intel_bo_unreference(mt
->bo
);
614 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
615 total_width
, total_height
, mt
->cpp
,
617 (expect_accelerated_upload
?
618 BO_ALLOC_FOR_RENDER
: 0));
625 intel_miptree_release(&mt
);
630 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
631 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
632 intel_miptree_release(&mt
);
637 /* If this miptree is capable of supporting fast color clears, set
638 * fast_clear_state appropriately to ensure that fast clears will occur.
639 * Allocation of the MCS miptree will be deferred until the first fast
640 * clear actually occurs.
642 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
643 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
648 struct intel_mipmap_tree
*
649 intel_miptree_create_for_bo(struct brw_context
*brw
,
657 struct intel_mipmap_tree
*mt
;
658 uint32_t tiling
, swizzle
;
660 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
662 /* Nothing will be able to use this miptree with the BO if the offset isn't
665 if (tiling
!= I915_TILING_NONE
)
666 assert(offset
% 4096 == 0);
668 /* miptrees can't handle negative pitch. If you need flipping of images,
669 * that's outside of the scope of the mt.
673 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
676 true, 0 /* num_samples */);
682 drm_intel_bo_reference(bo
);
692 * For a singlesample renderbuffer, this simply wraps the given BO with a
695 * For a multisample renderbuffer, this wraps the window system's
696 * (singlesample) BO with a singlesample miptree attached to the
697 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
698 * that will contain the actual rendering (which is lazily resolved to
699 * irb->singlesample_mt).
702 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
703 struct intel_renderbuffer
*irb
,
705 uint32_t width
, uint32_t height
,
708 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
709 struct intel_mipmap_tree
*multisample_mt
= NULL
;
710 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
711 mesa_format format
= rb
->Format
;
712 int num_samples
= rb
->NumSamples
;
714 /* Only the front and back buffers, which are color buffers, are allocated
715 * through the image loader.
717 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
718 _mesa_get_format_base_format(format
) == GL_RGBA
);
720 singlesample_mt
= intel_miptree_create_for_bo(intel
,
727 if (!singlesample_mt
)
730 /* If this miptree is capable of supporting fast color clears, set
731 * mcs_state appropriately to ensure that fast clears will occur.
732 * Allocation of the MCS miptree will be deferred until the first fast
733 * clear actually occurs.
735 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
736 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
738 if (num_samples
== 0) {
739 intel_miptree_release(&irb
->mt
);
740 irb
->mt
= singlesample_mt
;
742 assert(!irb
->singlesample_mt
);
744 intel_miptree_release(&irb
->singlesample_mt
);
745 irb
->singlesample_mt
= singlesample_mt
;
748 irb
->mt
->logical_width0
!= width
||
749 irb
->mt
->logical_height0
!= height
) {
750 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
758 irb
->need_downsample
= false;
759 intel_miptree_release(&irb
->mt
);
760 irb
->mt
= multisample_mt
;
766 intel_miptree_release(&irb
->singlesample_mt
);
767 intel_miptree_release(&irb
->mt
);
771 struct intel_mipmap_tree
*
772 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
776 uint32_t num_samples
)
778 struct intel_mipmap_tree
*mt
;
781 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
783 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
784 width
, height
, depth
, true, num_samples
,
785 INTEL_MIPTREE_TILING_ANY
);
789 if (brw_is_hiz_depth_format(brw
, format
)) {
790 ok
= intel_miptree_alloc_hiz(brw
, mt
);
798 intel_miptree_release(&mt
);
803 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
804 struct intel_mipmap_tree
*src
)
809 intel_miptree_release(dst
);
813 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
821 intel_miptree_release(struct intel_mipmap_tree
**mt
)
826 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
827 if (--(*mt
)->refcount
<= 0) {
830 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
832 drm_intel_bo_unreference((*mt
)->bo
);
833 intel_miptree_release(&(*mt
)->stencil_mt
);
834 intel_miptree_release(&(*mt
)->hiz_mt
);
835 intel_miptree_release(&(*mt
)->mcs_mt
);
836 intel_resolve_map_clear(&(*mt
)->hiz_map
);
838 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
839 free((*mt
)->level
[i
].slice
);
848 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
849 int *width
, int *height
, int *depth
)
851 switch (image
->TexObject
->Target
) {
852 case GL_TEXTURE_1D_ARRAY
:
853 *width
= image
->Width
;
855 *depth
= image
->Height
;
858 *width
= image
->Width
;
859 *height
= image
->Height
;
860 *depth
= image
->Depth
;
866 * Can the image be pulled into a unified mipmap tree? This mirrors
867 * the completeness test in a lot of ways.
869 * Not sure whether I want to pass gl_texture_image here.
872 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
873 struct gl_texture_image
*image
)
875 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
876 GLuint level
= intelImage
->base
.Base
.Level
;
877 int width
, height
, depth
;
879 /* glTexImage* choose the texture object based on the target passed in, and
880 * objects can't change targets over their lifetimes, so this should be
883 assert(image
->TexObject
->Target
== mt
->target
);
885 mesa_format mt_format
= mt
->format
;
886 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
887 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
888 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
889 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
890 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
891 mt_format
= mt
->etc_format
;
893 if (image
->TexFormat
!= mt_format
)
896 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
898 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
901 int level_depth
= mt
->level
[level
].depth
;
902 if (mt
->num_samples
> 1) {
903 switch (mt
->msaa_layout
) {
904 case INTEL_MSAA_LAYOUT_NONE
:
905 case INTEL_MSAA_LAYOUT_IMS
:
907 case INTEL_MSAA_LAYOUT_UMS
:
908 case INTEL_MSAA_LAYOUT_CMS
:
909 level_depth
/= mt
->num_samples
;
914 /* Test image dimensions against the base level image adjusted for
915 * minification. This will also catch images not present in the
916 * tree, changed targets, etc.
918 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
919 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
920 depth
!= level_depth
) {
924 if (image
->NumSamples
!= mt
->num_samples
)
932 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
934 GLuint x
, GLuint y
, GLuint d
)
936 mt
->level
[level
].depth
= d
;
937 mt
->level
[level
].level_x
= x
;
938 mt
->level
[level
].level_y
= y
;
940 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
943 assert(mt
->level
[level
].slice
== NULL
);
945 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
946 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
947 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
952 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
953 GLuint level
, GLuint img
,
956 if (img
== 0 && level
== 0)
957 assert(x
== 0 && y
== 0);
959 assert(img
< mt
->level
[level
].depth
);
961 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
962 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
964 DBG("%s level %d img %d pos %d,%d\n",
965 __FUNCTION__
, level
, img
,
966 mt
->level
[level
].slice
[img
].x_offset
,
967 mt
->level
[level
].slice
[img
].y_offset
);
971 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
972 GLuint level
, GLuint slice
,
973 GLuint
*x
, GLuint
*y
)
975 assert(slice
< mt
->level
[level
].depth
);
977 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
978 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
982 * This function computes masks that may be used to select the bits of the X
983 * and Y coordinates that indicate the offset within a tile. If the BO is
984 * untiled, the masks are set to 0.
987 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
988 uint32_t *mask_x
, uint32_t *mask_y
,
989 bool map_stencil_as_y_tiled
)
992 uint32_t tiling
= mt
->tiling
;
994 if (map_stencil_as_y_tiled
)
995 tiling
= I915_TILING_Y
;
1000 case I915_TILING_NONE
:
1001 *mask_x
= *mask_y
= 0;
1004 *mask_x
= 512 / cpp
- 1;
1008 *mask_x
= 128 / cpp
- 1;
1015 * Compute the offset (in bytes) from the start of the BO to the given x
1016 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1017 * multiples of the tile size.
1020 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1021 uint32_t x
, uint32_t y
,
1022 bool map_stencil_as_y_tiled
)
1025 uint32_t pitch
= mt
->pitch
;
1026 uint32_t tiling
= mt
->tiling
;
1028 if (map_stencil_as_y_tiled
) {
1029 tiling
= I915_TILING_Y
;
1031 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1032 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1033 * the resulting surface is twice the pitch of the original miptree,
1034 * since each row in the Y-tiled view corresponds to two rows in the
1035 * actual W-tiled surface. So we need to correct the pitch before
1036 * computing the offsets.
1044 case I915_TILING_NONE
:
1045 return y
* pitch
+ x
* cpp
;
1047 assert((x
% (512 / cpp
)) == 0);
1048 assert((y
% 8) == 0);
1049 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1051 assert((x
% (128 / cpp
)) == 0);
1052 assert((y
% 32) == 0);
1053 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1058 * Rendering with tiled buffers requires that the base address of the buffer
1059 * be aligned to a page boundary. For renderbuffers, and sometimes with
1060 * textures, we may want the surface to point at a texture image level that
1061 * isn't at a page boundary.
1063 * This function returns an appropriately-aligned base offset
1064 * according to the tiling restrictions, plus any required x/y offset
1068 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1069 GLuint level
, GLuint slice
,
1074 uint32_t mask_x
, mask_y
;
1076 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1077 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1079 *tile_x
= x
& mask_x
;
1080 *tile_y
= y
& mask_y
;
1082 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1086 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1087 struct intel_mipmap_tree
*dst_mt
,
1088 struct intel_mipmap_tree
*src_mt
,
1095 int src_stride
, dst_stride
;
1096 int cpp
= dst_mt
->cpp
;
1098 intel_miptree_map(brw
, src_mt
,
1102 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1105 intel_miptree_map(brw
, dst_mt
,
1109 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1113 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1114 _mesa_get_format_name(src_mt
->format
),
1115 src_mt
, src
, src_stride
,
1116 _mesa_get_format_name(dst_mt
->format
),
1117 dst_mt
, dst
, dst_stride
,
1120 int row_size
= cpp
* width
;
1121 if (src_stride
== row_size
&&
1122 dst_stride
== row_size
) {
1123 memcpy(dst
, src
, row_size
* height
);
1125 for (int i
= 0; i
< height
; i
++) {
1126 memcpy(dst
, src
, row_size
);
1132 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1133 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1135 /* Don't forget to copy the stencil data over, too. We could have skipped
1136 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1137 * shuffling the two data sources in/out of temporary storage instead of
1138 * the direct mapping we get this way.
1140 if (dst_mt
->stencil_mt
) {
1141 assert(src_mt
->stencil_mt
);
1142 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1143 level
, slice
, width
, height
);
1148 intel_miptree_copy_slice(struct brw_context
*brw
,
1149 struct intel_mipmap_tree
*dst_mt
,
1150 struct intel_mipmap_tree
*src_mt
,
1156 mesa_format format
= src_mt
->format
;
1157 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1158 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1166 assert(depth
< src_mt
->level
[level
].depth
);
1167 assert(src_mt
->format
== dst_mt
->format
);
1169 if (dst_mt
->compressed
) {
1170 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1171 width
= ALIGN(width
, dst_mt
->align_w
);
1174 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1175 * below won't apply since we can't do the depth's Y tiling or the
1176 * stencil's W tiling in the blitter.
1178 if (src_mt
->stencil_mt
) {
1179 intel_miptree_copy_slice_sw(brw
,
1186 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1187 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1188 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1190 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1191 _mesa_get_format_name(src_mt
->format
),
1192 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1193 _mesa_get_format_name(dst_mt
->format
),
1194 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1197 if (!intel_miptree_blit(brw
,
1198 src_mt
, level
, slice
, 0, 0, false,
1199 dst_mt
, level
, slice
, 0, 0, false,
1200 width
, height
, GL_COPY
)) {
1201 perf_debug("miptree validate blit for %s failed\n",
1202 _mesa_get_format_name(format
));
1204 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1210 * Copies the image's current data to the given miptree, and associates that
1211 * miptree with the image.
1213 * If \c invalidate is true, then the actual image data does not need to be
1214 * copied, but the image still needs to be associated to the new miptree (this
1215 * is set to true if we're about to clear the image).
1218 intel_miptree_copy_teximage(struct brw_context
*brw
,
1219 struct intel_texture_image
*intelImage
,
1220 struct intel_mipmap_tree
*dst_mt
,
1223 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1224 struct intel_texture_object
*intel_obj
=
1225 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1226 int level
= intelImage
->base
.Base
.Level
;
1227 int face
= intelImage
->base
.Base
.Face
;
1228 GLuint depth
= intelImage
->base
.Base
.Depth
;
1231 for (int slice
= 0; slice
< depth
; slice
++) {
1232 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1236 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1237 intel_obj
->needs_validate
= true;
1241 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1242 struct intel_mipmap_tree
*mt
,
1245 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1246 assert(mt
->mcs_mt
== NULL
);
1248 /* Choose the correct format for the MCS buffer. All that really matters
1249 * is that we allocate the right buffer size, since we'll always be
1250 * accessing this miptree using MCS-specific hardware mechanisms, which
1251 * infer the correct format based on num_samples.
1254 switch (num_samples
) {
1256 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1259 format
= MESA_FORMAT_R_UNORM8
;
1262 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1263 * for each sample, plus 8 padding bits).
1265 format
= MESA_FORMAT_R_UINT32
;
1268 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1272 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1274 * "The MCS surface must be stored as Tile Y."
1276 mt
->mcs_mt
= intel_miptree_create(brw
,
1282 mt
->logical_height0
,
1285 0 /* num_samples */,
1286 INTEL_MIPTREE_TILING_Y
);
1288 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1290 * When MCS buffer is enabled and bound to MSRT, it is required that it
1291 * is cleared prior to any rendering.
1293 * Since we don't use the MCS buffer for any purpose other than rendering,
1294 * it makes sense to just clear it immediately upon allocation.
1296 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1298 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1299 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1300 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1301 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1308 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1309 struct intel_mipmap_tree
*mt
)
1311 assert(mt
->mcs_mt
== NULL
);
1313 /* The format of the MCS buffer is opaque to the driver; all that matters
1314 * is that we get its size and pitch right. We'll pretend that the format
1315 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1316 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1317 * the block width and then a further factor of 4. Since an MCS tile
1318 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1319 * we'll need to scale the height down by the block height and then a
1320 * further factor of 8.
1322 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1323 unsigned block_width_px
;
1324 unsigned block_height
;
1325 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1326 unsigned width_divisor
= block_width_px
* 4;
1327 unsigned height_divisor
= block_height
* 8;
1328 unsigned mcs_width
=
1329 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1330 unsigned mcs_height
=
1331 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1332 assert(mt
->logical_depth0
== 1);
1333 mt
->mcs_mt
= intel_miptree_create(brw
,
1342 0 /* num_samples */,
1343 INTEL_MIPTREE_TILING_Y
);
1350 * Helper for intel_miptree_alloc_hiz() that sets
1351 * \c mt->level[level].has_hiz. Return true if and only if
1352 * \c has_hiz was set.
1355 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1356 struct intel_mipmap_tree
*mt
,
1361 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1362 uint32_t width
= minify(mt
->physical_width0
, level
);
1363 uint32_t height
= minify(mt
->physical_height0
, level
);
1365 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1366 * and the height is 4 aligned. This allows our HiZ support
1367 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1368 * we can grow the width & height to allow the HiZ op to
1369 * force the proper size alignments.
1371 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1376 mt
->level
[level
].has_hiz
= true;
1383 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1384 struct intel_mipmap_tree
*mt
)
1386 assert(mt
->hiz_mt
== NULL
);
1387 mt
->hiz_mt
= intel_miptree_create(brw
,
1393 mt
->logical_height0
,
1397 INTEL_MIPTREE_TILING_ANY
);
1402 /* Mark that all slices need a HiZ resolve. */
1403 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1404 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1405 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1408 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1409 head
->next
= malloc(sizeof(*head
->next
));
1410 head
->next
->prev
= head
;
1411 head
->next
->next
= NULL
;
1414 head
->level
= level
;
1415 head
->layer
= layer
;
1416 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1424 * Does the miptree slice have hiz enabled?
1427 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1429 intel_miptree_check_level_layer(mt
, level
, 0);
1430 return mt
->level
[level
].has_hiz
;
1434 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1438 if (!intel_miptree_level_has_hiz(mt
, level
))
1441 intel_resolve_map_set(&mt
->hiz_map
,
1442 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1447 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1451 if (!intel_miptree_level_has_hiz(mt
, level
))
1454 intel_resolve_map_set(&mt
->hiz_map
,
1455 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1459 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1463 uint32_t end_layer
= mt
->level
[level
].depth
;
1465 for (layer
= 0; layer
< end_layer
; layer
++) {
1466 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1471 intel_miptree_slice_resolve(struct brw_context
*brw
,
1472 struct intel_mipmap_tree
*mt
,
1475 enum gen6_hiz_op need
)
1477 intel_miptree_check_level_layer(mt
, level
, layer
);
1479 struct intel_resolve_map
*item
=
1480 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1482 if (!item
|| item
->need
!= need
)
1485 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1486 intel_resolve_map_remove(item
);
1491 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1492 struct intel_mipmap_tree
*mt
,
1496 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1497 GEN6_HIZ_OP_HIZ_RESOLVE
);
1501 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1502 struct intel_mipmap_tree
*mt
,
1506 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1507 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1511 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1512 struct intel_mipmap_tree
*mt
,
1513 enum gen6_hiz_op need
)
1515 bool did_resolve
= false;
1516 struct intel_resolve_map
*i
, *next
;
1518 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1520 if (i
->need
!= need
)
1523 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1524 intel_resolve_map_remove(i
);
1532 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1533 struct intel_mipmap_tree
*mt
)
1535 return intel_miptree_all_slices_resolve(brw
, mt
,
1536 GEN6_HIZ_OP_HIZ_RESOLVE
);
1540 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1541 struct intel_mipmap_tree
*mt
)
1543 return intel_miptree_all_slices_resolve(brw
, mt
,
1544 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1549 intel_miptree_resolve_color(struct brw_context
*brw
,
1550 struct intel_mipmap_tree
*mt
)
1552 switch (mt
->fast_clear_state
) {
1553 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1554 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1555 /* No resolve needed */
1557 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1558 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1559 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1560 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1561 brw_blorp_resolve_color(brw
, mt
);
1568 * Make it possible to share the BO backing the given miptree with another
1569 * process or another miptree.
1571 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1572 * then discard the MCS buffer, if present. We also set the fast_clear_state
1573 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1574 * allocated in the future.
1577 intel_miptree_make_shareable(struct brw_context
*brw
,
1578 struct intel_mipmap_tree
*mt
)
1580 /* MCS buffers are also used for multisample buffers, but we can't resolve
1581 * away a multisample MCS buffer because it's an integral part of how the
1582 * pixel data is stored. Fortunately this code path should never be
1583 * reached for multisample buffers.
1585 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1588 intel_miptree_resolve_color(brw
, mt
);
1589 intel_miptree_release(&mt
->mcs_mt
);
1590 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1596 * \brief Get pointer offset into stencil buffer.
1598 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1599 * must decode the tile's layout in software.
1602 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1604 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1606 * Even though the returned offset is always positive, the return type is
1608 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1609 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1612 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1614 uint32_t tile_size
= 4096;
1615 uint32_t tile_width
= 64;
1616 uint32_t tile_height
= 64;
1617 uint32_t row_size
= 64 * stride
;
1619 uint32_t tile_x
= x
/ tile_width
;
1620 uint32_t tile_y
= y
/ tile_height
;
1622 /* The byte's address relative to the tile's base addres. */
1623 uint32_t byte_x
= x
% tile_width
;
1624 uint32_t byte_y
= y
% tile_height
;
1626 uintptr_t u
= tile_y
* row_size
1627 + tile_x
* tile_size
1628 + 512 * (byte_x
/ 8)
1630 + 32 * ((byte_y
/ 4) % 2)
1631 + 16 * ((byte_x
/ 4) % 2)
1632 + 8 * ((byte_y
/ 2) % 2)
1633 + 4 * ((byte_x
/ 2) % 2)
1638 /* adjust for bit6 swizzling */
1639 if (((byte_x
/ 8) % 2) == 1) {
1640 if (((byte_y
/ 8) % 2) == 0) {
1652 intel_miptree_updownsample(struct brw_context
*brw
,
1653 struct intel_mipmap_tree
*src
,
1654 struct intel_mipmap_tree
*dst
)
1657 brw_blorp_blit_miptrees(brw
,
1658 src
, 0 /* level */, 0 /* layer */,
1659 dst
, 0 /* level */, 0 /* layer */,
1661 src
->logical_width0
, src
->logical_height0
,
1663 dst
->logical_width0
, dst
->logical_height0
,
1664 GL_NEAREST
, false, false /*mirror x, y*/);
1665 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1666 brw_meta_stencil_updownsample(brw
, src
, dst
);
1668 brw_meta_updownsample(brw
, src
, dst
);
1671 if (src
->stencil_mt
) {
1672 if (brw
->gen
>= 8) {
1673 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1677 brw_blorp_blit_miptrees(brw
,
1678 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1679 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1681 src
->logical_width0
, src
->logical_height0
,
1683 dst
->logical_width0
, dst
->logical_height0
,
1684 GL_NEAREST
, false, false /*mirror x, y*/);
1689 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1691 /* CPU accesses to color buffers don't understand fast color clears, so
1692 * resolve any pending fast color clears before we map.
1694 intel_miptree_resolve_color(brw
, mt
);
1696 drm_intel_bo
*bo
= mt
->bo
;
1698 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1699 intel_batchbuffer_flush(brw
);
1701 if (mt
->tiling
!= I915_TILING_NONE
)
1702 brw_bo_map_gtt(brw
, bo
, "miptree");
1704 brw_bo_map(brw
, bo
, true, "miptree");
1710 intel_miptree_unmap_raw(struct brw_context
*brw
,
1711 struct intel_mipmap_tree
*mt
)
1713 drm_intel_bo_unmap(mt
->bo
);
1717 intel_miptree_map_gtt(struct brw_context
*brw
,
1718 struct intel_mipmap_tree
*mt
,
1719 struct intel_miptree_map
*map
,
1720 unsigned int level
, unsigned int slice
)
1722 unsigned int bw
, bh
;
1724 unsigned int image_x
, image_y
;
1728 /* For compressed formats, the stride is the number of bytes per
1729 * row of blocks. intel_miptree_get_image_offset() already does
1732 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1733 assert(y
% bh
== 0);
1736 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1741 /* Note that in the case of cube maps, the caller must have passed the
1742 * slice number referencing the face.
1744 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1748 map
->stride
= mt
->pitch
;
1749 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1752 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1753 map
->x
, map
->y
, map
->w
, map
->h
,
1754 mt
, _mesa_get_format_name(mt
->format
),
1755 x
, y
, map
->ptr
, map
->stride
);
1759 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1760 struct intel_mipmap_tree
*mt
,
1761 struct intel_miptree_map
*map
,
1765 intel_miptree_unmap_raw(brw
, mt
);
1769 intel_miptree_map_blit(struct brw_context
*brw
,
1770 struct intel_mipmap_tree
*mt
,
1771 struct intel_miptree_map
*map
,
1772 unsigned int level
, unsigned int slice
)
1774 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1778 INTEL_MIPTREE_TILING_NONE
);
1780 fprintf(stderr
, "Failed to allocate blit temporary\n");
1783 map
->stride
= map
->mt
->pitch
;
1785 if (!intel_miptree_blit(brw
,
1787 map
->x
, map
->y
, false,
1790 map
->w
, map
->h
, GL_COPY
)) {
1791 fprintf(stderr
, "Failed to blit\n");
1795 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1797 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1798 map
->x
, map
->y
, map
->w
, map
->h
,
1799 mt
, _mesa_get_format_name(mt
->format
),
1800 level
, slice
, map
->ptr
, map
->stride
);
1805 intel_miptree_release(&map
->mt
);
1811 intel_miptree_unmap_blit(struct brw_context
*brw
,
1812 struct intel_mipmap_tree
*mt
,
1813 struct intel_miptree_map
*map
,
1817 struct gl_context
*ctx
= &brw
->ctx
;
1819 intel_miptree_unmap_raw(brw
, map
->mt
);
1821 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1822 bool ok
= intel_miptree_blit(brw
,
1826 map
->x
, map
->y
, false,
1827 map
->w
, map
->h
, GL_COPY
);
1828 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1831 intel_miptree_release(&map
->mt
);
1835 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1838 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*mt
,
1840 struct intel_miptree_map
*map
,
1841 unsigned int level
, unsigned int slice
)
1843 assert(map
->mode
& GL_MAP_READ_BIT
);
1844 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1846 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1847 map
->x
, map
->y
, map
->w
, map
->h
,
1848 mt
, _mesa_get_format_name(mt
->format
),
1849 level
, slice
, map
->ptr
, map
->stride
);
1851 /* Map the original image */
1854 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1858 void *src
= intel_miptree_map_raw(brw
, mt
);
1861 src
+= image_y
* mt
->pitch
;
1862 src
+= image_x
* mt
->cpp
;
1864 /* Due to the pixel offsets for the particular image being mapped, our
1865 * src pointer may not be 16-byte aligned. However, if the pitch is
1866 * divisible by 16, then the amount by which it's misaligned will remain
1867 * consistent from row to row.
1869 assert((mt
->pitch
% 16) == 0);
1870 const int misalignment
= ((uintptr_t) src
) & 15;
1872 /* Create an untiled temporary buffer for the mapping. */
1873 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1875 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1877 map
->buffer
= malloc(map
->stride
* map
->h
);
1878 /* Offset the destination so it has the same misalignment as src. */
1879 map
->ptr
= map
->buffer
+ misalignment
;
1881 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1883 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1884 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1885 void *src_ptr
= src
+ y
* mt
->pitch
;
1887 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1890 intel_miptree_unmap_raw(brw
, mt
);
1894 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1895 struct intel_mipmap_tree
*mt
,
1896 struct intel_miptree_map
*map
,
1906 intel_miptree_map_s8(struct brw_context
*brw
,
1907 struct intel_mipmap_tree
*mt
,
1908 struct intel_miptree_map
*map
,
1909 unsigned int level
, unsigned int slice
)
1911 map
->stride
= map
->w
;
1912 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1916 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1917 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1918 * invalidate is set, since we'll be writing the whole rectangle from our
1919 * temporary buffer back out.
1921 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1922 uint8_t *untiled_s8_map
= map
->ptr
;
1923 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1924 unsigned int image_x
, image_y
;
1926 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1928 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1929 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1930 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1931 x
+ image_x
+ map
->x
,
1932 y
+ image_y
+ map
->y
,
1933 brw
->has_swizzling
);
1934 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1938 intel_miptree_unmap_raw(brw
, mt
);
1940 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1941 map
->x
, map
->y
, map
->w
, map
->h
,
1942 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1944 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1945 map
->x
, map
->y
, map
->w
, map
->h
,
1946 mt
, map
->ptr
, map
->stride
);
1951 intel_miptree_unmap_s8(struct brw_context
*brw
,
1952 struct intel_mipmap_tree
*mt
,
1953 struct intel_miptree_map
*map
,
1957 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1958 unsigned int image_x
, image_y
;
1959 uint8_t *untiled_s8_map
= map
->ptr
;
1960 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1962 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1964 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1965 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1966 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1969 brw
->has_swizzling
);
1970 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1974 intel_miptree_unmap_raw(brw
, mt
);
1981 intel_miptree_map_etc(struct brw_context
*brw
,
1982 struct intel_mipmap_tree
*mt
,
1983 struct intel_miptree_map
*map
,
1987 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1988 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1989 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1992 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1993 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1995 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1996 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1997 map
->w
, map
->h
, 1));
1998 map
->ptr
= map
->buffer
;
2002 intel_miptree_unmap_etc(struct brw_context
*brw
,
2003 struct intel_mipmap_tree
*mt
,
2004 struct intel_miptree_map
*map
,
2010 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2015 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2016 + image_y
* mt
->pitch
2017 + image_x
* mt
->cpp
;
2019 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2020 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2021 map
->ptr
, map
->stride
,
2024 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2025 map
->ptr
, map
->stride
,
2026 map
->w
, map
->h
, mt
->etc_format
);
2028 intel_miptree_unmap_raw(brw
, mt
);
2033 * Mapping function for packed depth/stencil miptrees backed by real separate
2034 * miptrees for depth and stencil.
2036 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2037 * separate from the depth buffer. Yet at the GL API level, we have to expose
2038 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2039 * be able to map that memory for texture storage and glReadPixels-type
2040 * operations. We give Mesa core that access by mallocing a temporary and
2041 * copying the data between the actual backing store and the temporary.
2044 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2045 struct intel_mipmap_tree
*mt
,
2046 struct intel_miptree_map
*map
,
2047 unsigned int level
, unsigned int slice
)
2049 struct intel_mipmap_tree
*z_mt
= mt
;
2050 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2051 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2052 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2054 map
->stride
= map
->w
* packed_bpp
;
2055 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2059 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2060 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2061 * invalidate is set, since we'll be writing the whole rectangle from our
2062 * temporary buffer back out.
2064 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2065 uint32_t *packed_map
= map
->ptr
;
2066 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2067 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2068 unsigned int s_image_x
, s_image_y
;
2069 unsigned int z_image_x
, z_image_y
;
2071 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2072 &s_image_x
, &s_image_y
);
2073 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2074 &z_image_x
, &z_image_y
);
2076 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2077 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2078 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2079 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2082 brw
->has_swizzling
);
2083 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2085 (map_x
+ z_image_x
));
2086 uint8_t s
= s_map
[s_offset
];
2087 uint32_t z
= z_map
[z_offset
];
2089 if (map_z32f_x24s8
) {
2090 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2091 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2093 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2098 intel_miptree_unmap_raw(brw
, s_mt
);
2099 intel_miptree_unmap_raw(brw
, z_mt
);
2101 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2103 map
->x
, map
->y
, map
->w
, map
->h
,
2104 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2105 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2106 map
->ptr
, map
->stride
);
2108 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2109 map
->x
, map
->y
, map
->w
, map
->h
,
2110 mt
, map
->ptr
, map
->stride
);
2115 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2116 struct intel_mipmap_tree
*mt
,
2117 struct intel_miptree_map
*map
,
2121 struct intel_mipmap_tree
*z_mt
= mt
;
2122 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2123 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2125 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2126 uint32_t *packed_map
= map
->ptr
;
2127 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2128 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2129 unsigned int s_image_x
, s_image_y
;
2130 unsigned int z_image_x
, z_image_y
;
2132 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2133 &s_image_x
, &s_image_y
);
2134 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2135 &z_image_x
, &z_image_y
);
2137 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2138 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2139 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2140 x
+ s_image_x
+ map
->x
,
2141 y
+ s_image_y
+ map
->y
,
2142 brw
->has_swizzling
);
2143 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2147 if (map_z32f_x24s8
) {
2148 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2149 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2151 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2152 s_map
[s_offset
] = packed
>> 24;
2153 z_map
[z_offset
] = packed
;
2158 intel_miptree_unmap_raw(brw
, s_mt
);
2159 intel_miptree_unmap_raw(brw
, z_mt
);
2161 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2163 map
->x
, map
->y
, map
->w
, map
->h
,
2164 z_mt
, _mesa_get_format_name(z_mt
->format
),
2165 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2166 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2167 map
->ptr
, map
->stride
);
2174 * Create and attach a map to the miptree at (level, slice). Return the
2177 static struct intel_miptree_map
*
2178 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2187 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2192 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2193 mt
->level
[level
].slice
[slice
].map
= map
;
2205 * Release the map at (level, slice).
2208 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2212 struct intel_miptree_map
**map
;
2214 map
= &mt
->level
[level
].slice
[slice
].map
;
2220 can_blit_slice(struct intel_mipmap_tree
*mt
,
2221 unsigned int level
, unsigned int slice
)
2225 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2226 if (image_x
>= 32768 || image_y
>= 32768)
2229 if (mt
->pitch
>= 32768)
2236 intel_miptree_map(struct brw_context
*brw
,
2237 struct intel_mipmap_tree
*mt
,
2248 struct intel_miptree_map
*map
;
2250 assert(mt
->num_samples
<= 1);
2252 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2259 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2260 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2261 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2264 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2265 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2266 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2267 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2268 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2269 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2270 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2272 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2273 else if (brw
->has_llc
&&
2274 !(mode
& GL_MAP_WRITE_BIT
) &&
2276 (mt
->tiling
== I915_TILING_X
||
2277 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2278 can_blit_slice(mt
, level
, slice
)) {
2279 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2280 } else if (mt
->tiling
!= I915_TILING_NONE
&&
2281 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2282 assert(can_blit_slice(mt
, level
, slice
));
2283 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2284 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2285 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2287 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2290 *out_ptr
= map
->ptr
;
2291 *out_stride
= map
->stride
;
2293 if (map
->ptr
== NULL
)
2294 intel_miptree_release_map(mt
, level
, slice
);
2298 intel_miptree_unmap(struct brw_context
*brw
,
2299 struct intel_mipmap_tree
*mt
,
2303 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2305 assert(mt
->num_samples
<= 1);
2310 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2311 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2313 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2314 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2315 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2316 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2317 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2318 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2319 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2320 } else if (map
->mt
) {
2321 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2322 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2323 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2325 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2328 intel_miptree_release_map(mt
, level
, slice
);