2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
,
125 enum isl_tiling tiling
)
127 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
128 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
130 * - Support is limited to tiled render targets.
132 * Gen9 changes the restriction to Y-tile only.
135 return tiling
== ISL_TILING_Y0
;
136 else if (brw
->gen
>= 7)
137 return tiling
!= ISL_TILING_LINEAR
;
143 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
144 * can be used. This doesn't (and should not) inspect any of the properties of
147 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
148 * beneath the "Fast Color Clear" bullet (p326):
150 * - Support is for non-mip-mapped and non-array surface types only.
152 * And then later, on p327:
154 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
157 * From the Skylake documentation, it is made clear that X-tiling is no longer
160 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
164 intel_miptree_supports_ccs(struct brw_context
*brw
,
165 const struct intel_mipmap_tree
*mt
)
167 /* MCS support does not exist prior to Gen7 */
171 /* This function applies only to non-multisampled render targets. */
172 if (mt
->surf
.samples
> 1)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
186 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
187 const bool arrayed
= mt
->physical_depth0
!= 1;
190 /* Multisample surfaces with the CMS layout are not layered surfaces,
191 * yet still have physical_depth0 > 1. Assert that we don't
192 * accidentally reject a multisampled surface here. We should have
193 * rejected it earlier by explicitly checking the sample count.
195 assert(mt
->surf
.samples
== 1);
198 /* Handle the hardware restrictions...
200 * All GENs have the following restriction: "MCS buffer for non-MSRT is
201 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
203 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
204 * Non-MultiSampler Render Target Restrictions) Support is for
205 * non-mip-mapped and non-array surface types only.
207 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
208 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
209 * surfaces are supported with MCS buffer layout with these alignments in
210 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
212 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
213 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
214 * surfaces are supported with MCS buffer layout with these alignments in
215 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
217 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
220 /* There's no point in using an MCS buffer if the surface isn't in a
223 if (!brw
->mesa_format_supports_render
[mt
->format
])
227 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
228 const enum isl_format isl_format
=
229 brw_isl_format_for_mesa_format(linear_format
);
230 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
236 intel_tiling_supports_hiz(const struct brw_context
*brw
,
237 enum isl_tiling tiling
)
242 return tiling
== ISL_TILING_Y0
;
246 intel_miptree_supports_hiz(const struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
252 switch (mt
->format
) {
253 case MESA_FORMAT_Z_FLOAT32
:
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
256 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
257 case MESA_FORMAT_Z_UNORM16
:
265 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
266 const struct intel_mipmap_tree
*mt
)
268 /* For now compression is only enabled for integer formats even though
269 * there exist supported floating point formats also. This is a heuristic
270 * decision based on current public benchmarks. In none of the cases these
271 * formats provided any improvement but a few cases were seen to regress.
272 * Hence these are left to to be enabled in the future when they are known
275 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
278 if (!intel_miptree_supports_ccs(brw
, mt
))
281 /* Fast clear can be also used to clear srgb surfaces by using equivalent
282 * linear format. This trick, however, can't be extended to be used with
283 * lossless compression and therefore a check is needed to see if the format
286 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
290 * Determine depth format corresponding to a depth+stencil format,
291 * for separate stencil.
294 intel_depth_format_for_depthstencil_format(mesa_format format
) {
296 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
297 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
298 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
299 return MESA_FORMAT_Z_FLOAT32
;
306 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
307 unsigned depth0
, struct intel_mipmap_level
*table
)
309 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
311 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
313 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
314 if (!table
[level
].slice
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++)
322 free(table
[level
].slice
);
328 needs_separate_stencil(const struct brw_context
*brw
,
329 struct intel_mipmap_tree
*mt
,
330 mesa_format format
, uint32_t layout_flags
)
333 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
336 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
339 if (brw
->must_use_separate_stencil
)
342 return brw
->has_separate_stencil
&&
343 intel_miptree_supports_hiz(brw
, mt
);
347 * @param for_bo Indicates that the caller is
348 * intel_miptree_create_for_bo(). If true, then do not create
351 static struct intel_mipmap_tree
*
352 intel_miptree_create_layout(struct brw_context
*brw
,
361 uint32_t layout_flags
)
363 assert(num_samples
> 0);
365 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
369 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
370 _mesa_enum_to_string(target
),
371 _mesa_get_format_name(format
),
372 first_level
, last_level
, depth0
, mt
);
374 if (target
== GL_TEXTURE_1D_ARRAY
)
375 assert(height0
== 1);
379 mt
->first_level
= first_level
;
380 mt
->last_level
= last_level
;
381 mt
->logical_width0
= width0
;
382 mt
->logical_height0
= height0
;
383 mt
->logical_depth0
= depth0
;
384 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
385 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
386 mt
->supports_fast_clear
= false;
387 mt
->aux_state
= NULL
;
388 mt
->cpp
= _mesa_get_format_bytes(format
);
389 mt
->surf
.samples
= num_samples
;
390 mt
->compressed
= _mesa_is_format_compressed(format
);
391 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
394 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
395 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
397 int depth_multiply
= 1;
398 if (num_samples
> 1) {
399 /* Adjust width/height/depth for MSAA */
400 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
401 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
402 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
403 * "If the surface is multisampled and it is a depth or stencil
404 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
405 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
408 * +----------------------------------------------------------------+
409 * | Num Multisamples | W_l = | H_l = |
410 * +----------------------------------------------------------------+
411 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
412 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
413 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
414 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
415 * +----------------------------------------------------------------+
418 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
419 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
420 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
422 * Another more complicated explanation for these adjustments comes
423 * from the Sandybridge PRM, volume 4, part 1, page 31:
425 * "Any of the other messages (sample*, LOD, load4) used with a
426 * (4x) multisampled surface will in-effect sample a surface with
427 * double the height and width as that indicated in the surface
428 * state. Each pixel position on the original-sized surface is
429 * replaced with a 2x2 of samples with the following arrangement:
434 * Thus, when sampling from a multisampled texture, it behaves as
435 * though the layout in memory for (x,y,sample) is:
437 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
438 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
440 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
441 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
443 * However, the actual layout of multisampled data in memory is:
445 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
446 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
448 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
449 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
451 * This pattern repeats for each 2x2 pixel block.
453 * As a result, when calculating the size of our 4-sample buffer for
454 * an odd width or height, we have to align before scaling up because
455 * sample 3 is in that bottom right 2x2 block.
457 switch (num_samples
) {
459 assert(brw
->gen
>= 8);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2);
464 width0
= ALIGN(width0
, 2) * 2;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 2;
472 width0
= ALIGN(width0
, 2) * 4;
473 height0
= ALIGN(height0
, 2) * 4;
476 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
479 unreachable("not reached");
482 /* Non-interleaved */
483 depth_multiply
= num_samples
;
484 depth0
*= depth_multiply
;
488 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->surf
.msaa_layout
) {
508 case ISL_MSAA_LAYOUT_NONE
:
509 case ISL_MSAA_LAYOUT_INTERLEAVED
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case ISL_MSAA_LAYOUT_ARRAY
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
519 assert(depth0
== 6 * depth_multiply
);
521 mt
->physical_width0
= width0
;
522 mt
->physical_height0
= height0
;
523 mt
->physical_depth0
= depth0
;
525 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
)) {
526 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
528 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
531 mt
->stencil_mt
= intel_miptree_create(brw
,
542 if (!mt
->stencil_mt
) {
543 intel_miptree_release(&mt
);
546 mt
->stencil_mt
->r8stencil_needs_update
= true;
548 /* Fix up the Z miptree format for how we're splitting out separate
549 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
551 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
554 if (format
== mt
->format
) {
555 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
556 _mesa_get_format_name(mt
->format
));
560 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
561 mt
->array_layout
= GEN6_HIZ_STENCIL
;
564 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
565 * multisampled or have an AUX buffer attached to it.
567 * GEN | MSRT | AUX_CCS_* or AUX_MCS
568 * -------------------------------------------
569 * 9 | HALIGN_16 | HALIGN_16
570 * 8 | HALIGN_ANY | HALIGN_16
574 if (intel_miptree_supports_ccs(brw
, mt
)) {
575 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
576 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
577 } else if (brw
->gen
>= 9 && num_samples
> 1) {
578 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
580 const UNUSED
bool is_lossless_compressed_aux
=
581 brw
->gen
>= 9 && num_samples
== 1 &&
582 mt
->format
== MESA_FORMAT_R_UINT32
;
584 /* For now, nothing else has this requirement */
585 assert(is_lossless_compressed_aux
||
586 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
589 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
590 intel_miptree_release(&mt
);
599 * Choose the aux usage for this miptree. This function must be called fairly
600 * late in the miptree create process after we have a tiling.
603 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
604 struct intel_mipmap_tree
*mt
)
606 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
608 const unsigned no_flags
= 0;
609 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
610 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
611 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
612 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
613 intel_miptree_supports_ccs(brw
, mt
)) {
614 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
615 brw
->gen
>= 9 && !mt
->is_scanout
&&
616 intel_miptree_supports_ccs_e(brw
, mt
)) {
617 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
619 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
621 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
622 intel_miptree_supports_hiz(brw
, mt
)) {
623 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
626 /* We can do fast-clear on all auxiliary surface types that are
627 * allocated through the normal texture creation paths.
629 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
630 mt
->supports_fast_clear
= true;
635 * Choose an appropriate uncompressed format for a requested
636 * compressed format, if unsupported.
639 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
641 /* No need to lower ETC formats on these platforms,
642 * they are supported natively.
644 if (brw
->gen
>= 8 || brw
->is_baytrail
)
648 case MESA_FORMAT_ETC1_RGB8
:
649 return MESA_FORMAT_R8G8B8X8_UNORM
;
650 case MESA_FORMAT_ETC2_RGB8
:
651 return MESA_FORMAT_R8G8B8X8_UNORM
;
652 case MESA_FORMAT_ETC2_SRGB8
:
653 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
654 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
655 return MESA_FORMAT_B8G8R8A8_SRGB
;
656 case MESA_FORMAT_ETC2_RGBA8_EAC
:
657 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
658 return MESA_FORMAT_R8G8B8A8_UNORM
;
659 case MESA_FORMAT_ETC2_R11_EAC
:
660 return MESA_FORMAT_R_UNORM16
;
661 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
662 return MESA_FORMAT_R_SNORM16
;
663 case MESA_FORMAT_ETC2_RG11_EAC
:
664 return MESA_FORMAT_R16G16_UNORM
;
665 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
666 return MESA_FORMAT_R16G16_SNORM
;
668 /* Non ETC1 / ETC2 format */
674 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
676 /* In case of physical dimensions one needs to consider also the layout.
677 * See isl_calc_phys_level0_extent_sa().
679 if (surf
->dim
!= ISL_SURF_DIM_3D
)
680 return surf
->phys_level0_sa
.array_len
;
682 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
683 return minify(surf
->phys_level0_sa
.array_len
, level
);
685 return minify(surf
->phys_level0_sa
.depth
, level
);
688 /** \brief Assert that the level and layer are valid for the miptree. */
690 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
698 assert(level
>= mt
->first_level
);
699 assert(level
<= mt
->last_level
);
701 if (mt
->surf
.size
> 0)
702 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
704 assert(layer
< mt
->level
[level
].depth
);
707 static enum isl_aux_state
**
708 create_aux_state_map(struct intel_mipmap_tree
*mt
,
709 enum isl_aux_state initial
)
711 const uint32_t levels
= mt
->last_level
+ 1;
713 uint32_t total_slices
= 0;
714 for (uint32_t level
= 0; level
< levels
; level
++) {
715 if (mt
->surf
.size
> 0)
716 total_slices
+= get_num_phys_layers(&mt
->surf
, level
);
718 total_slices
+= mt
->level
[level
].depth
;
721 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
723 /* We're going to allocate a single chunk of data for both the per-level
724 * reference array and the arrays of aux_state. This makes cleanup
725 * significantly easier.
727 const size_t total_size
= per_level_array_size
+
728 total_slices
* sizeof(enum isl_aux_state
);
729 void *data
= malloc(total_size
);
733 enum isl_aux_state
**per_level_arr
= data
;
734 enum isl_aux_state
*s
= data
+ per_level_array_size
;
735 for (uint32_t level
= 0; level
< levels
; level
++) {
736 per_level_arr
[level
] = s
;
738 unsigned level_depth
;
739 if (mt
->surf
.size
> 0)
740 level_depth
= get_num_phys_layers(&mt
->surf
, level
);
742 level_depth
= mt
->level
[level
].depth
;
744 for (uint32_t a
= 0; a
< level_depth
; a
++)
747 assert((void *)s
== data
+ total_size
);
749 return per_level_arr
;
753 free_aux_state_map(enum isl_aux_state
**state
)
758 static struct intel_mipmap_tree
*
759 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
760 unsigned first_level
, unsigned last_level
,
761 unsigned width0
, unsigned height0
, unsigned depth0
,
762 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
763 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
764 unsigned row_pitch
, struct brw_bo
*bo
)
766 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
770 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
778 if (target
== GL_TEXTURE_CUBE_MAP
||
779 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
780 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
782 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
784 _mesa_enum_to_string(target
),
785 _mesa_get_format_name(format
),
786 num_samples
, width0
, height0
, depth0
,
787 first_level
, last_level
, mt
);
789 struct isl_surf_init_info init_info
= {
790 .dim
= get_isl_surf_dim(target
),
791 .format
= translate_tex_format(brw
, format
, false),
794 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
795 .levels
= last_level
- first_level
+ 1,
796 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
797 .samples
= num_samples
,
798 .row_pitch
= row_pitch
,
799 .usage
= isl_usage_flags
,
800 .tiling_flags
= tiling_flags
,
803 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
806 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
809 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
811 isl_tiling_to_i915_tiling(
813 mt
->surf
.row_pitch
, alloc_flags
);
820 mt
->first_level
= first_level
;
821 mt
->last_level
= last_level
;
824 mt
->aux_state
= NULL
;
825 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
830 intel_miptree_release(&mt
);
834 static struct intel_mipmap_tree
*
835 miptree_create(struct brw_context
*brw
,
844 uint32_t layout_flags
)
846 if (format
== MESA_FORMAT_S_UINT8
)
847 return make_surface(brw
, target
, format
, first_level
, last_level
,
848 width0
, height0
, depth0
, num_samples
,
850 ISL_SURF_USAGE_STENCIL_BIT
|
851 ISL_SURF_USAGE_TEXTURE_BIT
,
852 BO_ALLOC_FOR_RENDER
, 0, NULL
);
854 struct intel_mipmap_tree
*mt
;
855 mesa_format tex_format
= format
;
856 mesa_format etc_format
= MESA_FORMAT_NONE
;
857 uint32_t alloc_flags
= 0;
859 format
= intel_lower_compressed_format(brw
, format
);
861 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
863 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
864 mt
= intel_miptree_create_layout(brw
, target
, format
,
865 first_level
, last_level
, width0
,
866 height0
, depth0
, num_samples
,
871 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
872 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
874 mt
->etc_format
= etc_format
;
876 if (format
== MESA_FORMAT_S_UINT8
) {
877 /* Align to size of W tile, 64x64. */
878 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
879 ALIGN(mt
->total_width
, 64),
880 ALIGN(mt
->total_height
, 64),
882 isl_tiling_to_i915_tiling(
887 /* The stencil buffer has quirky pitch requirements. From the
888 * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
889 * dword 1 bits 16:0 - Surface Pitch):
891 * The pitch must be set to 2x the value computed based on width, as
892 * the stencil buffer is stored with two rows interleaved.
894 * While the Ivybridge PRM lacks this comment, the BSpec contains the
895 * same text, and experiments indicate that this is necessary.
897 mt
->surf
.row_pitch
*= 2;
899 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
900 mt
->total_width
, mt
->total_height
,
902 isl_tiling_to_i915_tiling(
908 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
909 mt
->bo
->cache_coherent
= false;
911 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
912 intel_miptree_choose_aux_usage(brw
, mt
);
917 struct intel_mipmap_tree
*
918 intel_miptree_create(struct brw_context
*brw
,
927 uint32_t layout_flags
)
929 assert(num_samples
> 0);
931 struct intel_mipmap_tree
*mt
= miptree_create(
933 first_level
, last_level
,
934 width0
, height0
, depth0
, num_samples
,
939 /* If the BO is too large to fit in the aperture, we need to use the
940 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
941 * handle Y-tiling, so we need to fall back to X.
943 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
944 mt
->surf
.tiling
== ISL_TILING_Y0
) {
945 const uint32_t alloc_flags
=
946 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
947 BO_ALLOC_FOR_RENDER
: 0;
948 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
949 mt
->total_width
, mt
->total_height
);
951 mt
->surf
.tiling
= ISL_TILING_X
;
952 brw_bo_unreference(mt
->bo
);
953 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
954 mt
->total_width
, mt
->total_height
, mt
->cpp
,
955 isl_tiling_to_i915_tiling(
957 &mt
->surf
.row_pitch
, alloc_flags
);
963 intel_miptree_release(&mt
);
967 if (!intel_miptree_alloc_aux(brw
, mt
)) {
968 intel_miptree_release(&mt
);
975 struct intel_mipmap_tree
*
976 intel_miptree_create_for_bo(struct brw_context
*brw
,
984 uint32_t layout_flags
)
986 struct intel_mipmap_tree
*mt
;
987 uint32_t tiling
, swizzle
;
988 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
990 if (format
== MESA_FORMAT_S_UINT8
) {
991 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
992 0, 0, width
, height
, depth
, 1,
994 ISL_SURF_USAGE_STENCIL_BIT
|
995 ISL_SURF_USAGE_TEXTURE_BIT
,
996 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1000 assert(bo
->size
>= mt
->surf
.size
);
1002 brw_bo_reference(bo
);
1006 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
1008 /* Nothing will be able to use this miptree with the BO if the offset isn't
1011 if (tiling
!= I915_TILING_NONE
)
1012 assert(offset
% 4096 == 0);
1014 /* miptrees can't handle negative pitch. If you need flipping of images,
1015 * that's outside of the scope of the mt.
1019 /* The BO already has a tiling format and we shouldn't confuse the lower
1020 * layers by making it try to find a tiling format again.
1022 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
1023 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
1025 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
1026 mt
= intel_miptree_create_layout(brw
, target
, format
,
1028 width
, height
, depth
,
1029 1 /* num_samples */,
1034 brw_bo_reference(bo
);
1036 mt
->surf
.row_pitch
= pitch
;
1037 mt
->offset
= offset
;
1038 mt
->surf
.tiling
= isl_tiling_from_i915_tiling(tiling
);
1040 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1041 intel_miptree_choose_aux_usage(brw
, mt
);
1046 static struct intel_mipmap_tree
*
1047 miptree_create_for_planar_image(struct brw_context
*brw
,
1048 __DRIimage
*image
, GLenum target
)
1050 struct intel_image_format
*f
= image
->planar_format
;
1051 struct intel_mipmap_tree
*planar_mt
= NULL
;
1053 for (int i
= 0; i
< f
->nplanes
; i
++) {
1054 const int index
= f
->planes
[i
].buffer_index
;
1055 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1056 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1057 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1058 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1060 /* Disable creation of the texture's aux buffers because the driver
1061 * exposes no EGL API to manage them. That is, there is no API for
1062 * resolving the aux buffer's content to the main buffer nor for
1063 * invalidating the aux buffer's content.
1065 struct intel_mipmap_tree
*mt
=
1066 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1067 image
->offsets
[index
],
1069 image
->strides
[index
],
1070 MIPTREE_LAYOUT_DISABLE_AUX
);
1074 mt
->target
= target
;
1079 planar_mt
->plane
[i
- 1] = mt
;
1085 struct intel_mipmap_tree
*
1086 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1087 __DRIimage
*image
, GLenum target
,
1088 enum isl_colorspace colorspace
,
1089 bool is_winsys_image
)
1091 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1092 assert(colorspace
== ISL_COLORSPACE_NONE
||
1093 colorspace
== ISL_COLORSPACE_YUV
);
1094 return miptree_create_for_planar_image(brw
, image
, target
);
1097 mesa_format format
= image
->format
;
1098 switch (colorspace
) {
1099 case ISL_COLORSPACE_NONE
:
1100 /* Keep the image format unmodified */
1103 case ISL_COLORSPACE_LINEAR
:
1104 format
=_mesa_get_srgb_format_linear(format
);
1107 case ISL_COLORSPACE_SRGB
:
1108 format
=_mesa_get_linear_format_srgb(format
);
1112 unreachable("Inalid colorspace for non-planar image");
1115 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1116 /* The texture storage paths in core Mesa detect if the driver does not
1117 * support the user-requested format, and then searches for a
1118 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1119 * do the fallbacks here for important formats.
1121 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1122 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1123 * the Chrome OS compositor consumes as dma_buf EGLImages.
1125 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1128 if (!brw
->ctx
.TextureFormatSupported
[format
])
1131 /* If this image comes in from a window system, we have different
1132 * requirements than if it comes in via an EGL import operation. Window
1133 * system images can use any form of auxiliary compression we wish because
1134 * they get "flushed" before being handed off to the window system and we
1135 * have the opportunity to do resolves. Window system buffers also may be
1136 * used for scanout so we need to flag that appropriately.
1138 const uint32_t mt_layout_flags
=
1139 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1141 /* Disable creation of the texture's aux buffers because the driver exposes
1142 * no EGL API to manage them. That is, there is no API for resolving the aux
1143 * buffer's content to the main buffer nor for invalidating the aux buffer's
1146 struct intel_mipmap_tree
*mt
=
1147 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1148 image
->offset
, image
->width
, image
->height
, 1,
1149 image
->pitch
, mt_layout_flags
);
1153 mt
->target
= target
;
1154 mt
->level
[0].level_x
= image
->tile_x
;
1155 mt
->level
[0].level_y
= image
->tile_y
;
1156 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1157 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1159 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1160 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1161 * trouble resolving back to destination image due to alignment issues.
1163 if (!brw
->has_surface_tile_offset
) {
1164 uint32_t draw_x
, draw_y
;
1165 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1167 if (draw_x
!= 0 || draw_y
!= 0) {
1168 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1169 intel_miptree_release(&mt
);
1174 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1175 intel_miptree_release(&mt
);
1183 * For a singlesample renderbuffer, this simply wraps the given BO with a
1186 * For a multisample renderbuffer, this wraps the window system's
1187 * (singlesample) BO with a singlesample miptree attached to the
1188 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1189 * that will contain the actual rendering (which is lazily resolved to
1190 * irb->singlesample_mt).
1193 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1194 struct intel_renderbuffer
*irb
,
1195 struct intel_mipmap_tree
*singlesample_mt
,
1196 uint32_t width
, uint32_t height
,
1199 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1200 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1201 mesa_format format
= rb
->Format
;
1202 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1204 /* Only the front and back buffers, which are color buffers, are allocated
1205 * through the image loader.
1207 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1208 _mesa_get_format_base_format(format
) == GL_RGBA
);
1210 assert(singlesample_mt
);
1212 if (num_samples
== 1) {
1213 intel_miptree_release(&irb
->mt
);
1214 irb
->mt
= singlesample_mt
;
1216 assert(!irb
->singlesample_mt
);
1218 intel_miptree_release(&irb
->singlesample_mt
);
1219 irb
->singlesample_mt
= singlesample_mt
;
1222 irb
->mt
->logical_width0
!= width
||
1223 irb
->mt
->logical_height0
!= height
) {
1224 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1229 if (!multisample_mt
)
1232 irb
->need_downsample
= false;
1233 intel_miptree_release(&irb
->mt
);
1234 irb
->mt
= multisample_mt
;
1240 intel_miptree_release(&irb
->mt
);
1244 struct intel_mipmap_tree
*
1245 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1249 uint32_t num_samples
)
1251 struct intel_mipmap_tree
*mt
;
1253 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1254 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1255 MIPTREE_LAYOUT_TILING_ANY
|
1256 MIPTREE_LAYOUT_FOR_SCANOUT
;
1258 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1259 width
, height
, depth
, num_samples
,
1267 intel_miptree_release(&mt
);
1272 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1273 struct intel_mipmap_tree
*src
)
1278 intel_miptree_release(dst
);
1282 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1289 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1291 if (aux_buf
== NULL
)
1294 brw_bo_unreference(aux_buf
->bo
);
1300 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1305 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1306 if (--(*mt
)->refcount
<= 0) {
1309 DBG("%s deleting %p\n", __func__
, *mt
);
1311 brw_bo_unreference((*mt
)->bo
);
1312 intel_miptree_release(&(*mt
)->stencil_mt
);
1313 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1314 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1315 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1316 free_aux_state_map((*mt
)->aux_state
);
1318 intel_miptree_release(&(*mt
)->plane
[0]);
1319 intel_miptree_release(&(*mt
)->plane
[1]);
1321 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1322 free((*mt
)->level
[i
].slice
);
1332 intel_get_image_dims(struct gl_texture_image
*image
,
1333 int *width
, int *height
, int *depth
)
1335 switch (image
->TexObject
->Target
) {
1336 case GL_TEXTURE_1D_ARRAY
:
1337 /* For a 1D Array texture the OpenGL API will treat the image height as
1338 * the number of array slices. For Intel hardware, we treat the 1D array
1339 * as a 2D Array with a height of 1. So, here we want to swap image
1342 assert(image
->Depth
== 1);
1343 *width
= image
->Width
;
1345 *depth
= image
->Height
;
1347 case GL_TEXTURE_CUBE_MAP
:
1348 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1349 * though we really have 6 slices.
1351 assert(image
->Depth
== 1);
1352 *width
= image
->Width
;
1353 *height
= image
->Height
;
1357 *width
= image
->Width
;
1358 *height
= image
->Height
;
1359 *depth
= image
->Depth
;
1365 * Can the image be pulled into a unified mipmap tree? This mirrors
1366 * the completeness test in a lot of ways.
1368 * Not sure whether I want to pass gl_texture_image here.
1371 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1372 struct gl_texture_image
*image
)
1374 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1375 GLuint level
= intelImage
->base
.Base
.Level
;
1376 int width
, height
, depth
;
1378 /* glTexImage* choose the texture object based on the target passed in, and
1379 * objects can't change targets over their lifetimes, so this should be
1382 assert(image
->TexObject
->Target
== mt
->target
);
1384 mesa_format mt_format
= mt
->format
;
1385 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1386 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1387 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1388 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1389 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1390 mt_format
= mt
->etc_format
;
1392 if (image
->TexFormat
!= mt_format
)
1395 intel_get_image_dims(image
, &width
, &height
, &depth
);
1397 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1400 if (mt
->surf
.size
> 0) {
1401 if (level
>= mt
->surf
.levels
)
1404 const unsigned level_depth
=
1405 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1406 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1407 mt
->surf
.logical_level0_px
.array_len
;
1409 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1410 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1411 depth
== level_depth
&&
1412 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1415 int level_depth
= mt
->level
[level
].depth
;
1416 if (mt
->surf
.samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1417 level_depth
/= mt
->surf
.samples
;
1419 /* Test image dimensions against the base level image adjusted for
1420 * minification. This will also catch images not present in the
1421 * tree, changed targets, etc.
1423 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1424 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1425 depth
!= level_depth
) {
1429 /* Core uses sample number of zero to indicate single-sampled. */
1430 if (MAX2(image
->NumSamples
, 1) != mt
->surf
.samples
)
1438 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1440 GLuint x
, GLuint y
, GLuint d
)
1442 mt
->level
[level
].depth
= d
;
1443 mt
->level
[level
].level_x
= x
;
1444 mt
->level
[level
].level_y
= y
;
1446 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1449 assert(mt
->level
[level
].slice
);
1451 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1452 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1457 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1458 GLuint level
, GLuint img
,
1461 if (img
== 0 && level
== 0)
1462 assert(x
== 0 && y
== 0);
1464 assert(img
< mt
->level
[level
].depth
);
1466 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1467 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1469 DBG("%s level %d img %d pos %d,%d\n",
1470 __func__
, level
, img
,
1471 mt
->level
[level
].slice
[img
].x_offset
,
1472 mt
->level
[level
].slice
[img
].y_offset
);
1476 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1477 GLuint level
, GLuint slice
,
1478 GLuint
*x
, GLuint
*y
)
1480 if (level
== 0 && slice
== 0) {
1481 *x
= mt
->level
[0].level_x
;
1482 *y
= mt
->level
[0].level_y
;
1486 if (mt
->surf
.size
> 0) {
1487 uint32_t x_offset_sa
, y_offset_sa
;
1489 /* Miptree itself can have an offset only if it represents a single
1490 * slice in an imported buffer object.
1491 * See intel_miptree_create_for_dri_image().
1493 assert(mt
->level
[0].level_x
== 0);
1494 assert(mt
->level
[0].level_y
== 0);
1496 /* Given level is relative to level zero while the miptree may be
1497 * represent just a subset of all levels starting from 'first_level'.
1499 assert(level
>= mt
->first_level
);
1500 level
-= mt
->first_level
;
1502 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1503 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1504 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1505 &x_offset_sa
, &y_offset_sa
);
1512 assert(slice
< mt
->level
[level
].depth
);
1514 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1515 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1520 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1521 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1522 * and tile_h is set to 1.
1525 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1526 uint32_t *tile_w
, uint32_t *tile_h
)
1537 case ISL_TILING_LINEAR
:
1542 unreachable("not reached");
1548 * This function computes masks that may be used to select the bits of the X
1549 * and Y coordinates that indicate the offset within a tile. If the BO is
1550 * untiled, the masks are set to 0.
1553 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1554 uint32_t *mask_x
, uint32_t *mask_y
)
1556 uint32_t tile_w_bytes
, tile_h
;
1558 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1560 *mask_x
= tile_w_bytes
/ cpp
- 1;
1561 *mask_y
= tile_h
- 1;
1565 * Compute the offset (in bytes) from the start of the BO to the given x
1566 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1567 * multiples of the tile size.
1570 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1571 uint32_t x
, uint32_t y
)
1574 uint32_t pitch
= mt
->surf
.row_pitch
;
1576 switch (mt
->surf
.tiling
) {
1578 unreachable("not reached");
1579 case ISL_TILING_LINEAR
:
1580 return y
* pitch
+ x
* cpp
;
1582 assert((x
% (512 / cpp
)) == 0);
1583 assert((y
% 8) == 0);
1584 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1586 assert((x
% (128 / cpp
)) == 0);
1587 assert((y
% 32) == 0);
1588 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1593 * Rendering with tiled buffers requires that the base address of the buffer
1594 * be aligned to a page boundary. For renderbuffers, and sometimes with
1595 * textures, we may want the surface to point at a texture image level that
1596 * isn't at a page boundary.
1598 * This function returns an appropriately-aligned base offset
1599 * according to the tiling restrictions, plus any required x/y offset
1603 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1604 GLuint level
, GLuint slice
,
1609 uint32_t mask_x
, mask_y
;
1611 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1612 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1614 *tile_x
= x
& mask_x
;
1615 *tile_y
= y
& mask_y
;
1617 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1621 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1622 struct intel_mipmap_tree
*src_mt
,
1623 unsigned src_level
, unsigned src_layer
,
1624 struct intel_mipmap_tree
*dst_mt
,
1625 unsigned dst_level
, unsigned dst_layer
,
1626 unsigned width
, unsigned height
)
1629 ptrdiff_t src_stride
, dst_stride
;
1630 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1631 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1633 intel_miptree_map(brw
, src_mt
,
1634 src_level
, src_layer
,
1637 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1640 intel_miptree_map(brw
, dst_mt
,
1641 dst_level
, dst_layer
,
1644 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1648 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1649 _mesa_get_format_name(src_mt
->format
),
1650 src_mt
, src
, src_stride
,
1651 _mesa_get_format_name(dst_mt
->format
),
1652 dst_mt
, dst
, dst_stride
,
1655 int row_size
= cpp
* width
;
1656 if (src_stride
== row_size
&&
1657 dst_stride
== row_size
) {
1658 memcpy(dst
, src
, row_size
* height
);
1660 for (int i
= 0; i
< height
; i
++) {
1661 memcpy(dst
, src
, row_size
);
1667 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1668 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1670 /* Don't forget to copy the stencil data over, too. We could have skipped
1671 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1672 * shuffling the two data sources in/out of temporary storage instead of
1673 * the direct mapping we get this way.
1675 if (dst_mt
->stencil_mt
) {
1676 assert(src_mt
->stencil_mt
);
1677 intel_miptree_copy_slice_sw(brw
,
1678 src_mt
->stencil_mt
, src_level
, src_layer
,
1679 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1685 intel_miptree_copy_slice(struct brw_context
*brw
,
1686 struct intel_mipmap_tree
*src_mt
,
1687 unsigned src_level
, unsigned src_layer
,
1688 struct intel_mipmap_tree
*dst_mt
,
1689 unsigned dst_level
, unsigned dst_layer
)
1692 mesa_format format
= src_mt
->format
;
1693 uint32_t width
, height
;
1695 if (src_mt
->surf
.size
> 0) {
1696 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1697 src_level
- src_mt
->first_level
);
1698 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1699 src_level
- src_mt
->first_level
);
1702 get_num_phys_layers(&src_mt
->surf
,
1703 src_level
- src_mt
->first_level
));
1705 width
= minify(src_mt
->physical_width0
,
1706 src_level
- src_mt
->first_level
);
1707 height
= minify(src_mt
->physical_height0
,
1708 src_level
- src_mt
->first_level
);
1709 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1712 assert(src_mt
->format
== dst_mt
->format
);
1714 if (dst_mt
->compressed
) {
1716 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1717 height
= ALIGN_NPOT(height
, j
) / j
;
1718 width
= ALIGN_NPOT(width
, i
) / i
;
1721 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1722 * below won't apply since we can't do the depth's Y tiling or the
1723 * stencil's W tiling in the blitter.
1725 if (src_mt
->stencil_mt
) {
1726 intel_miptree_copy_slice_sw(brw
,
1727 src_mt
, src_level
, src_layer
,
1728 dst_mt
, dst_level
, dst_layer
,
1733 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1734 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1736 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1739 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1740 _mesa_get_format_name(src_mt
->format
),
1741 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1742 _mesa_get_format_name(dst_mt
->format
),
1743 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1746 if (!intel_miptree_blit(brw
,
1747 src_mt
, src_level
, src_layer
, 0, 0, false,
1748 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1749 width
, height
, GL_COPY
)) {
1750 perf_debug("miptree validate blit for %s failed\n",
1751 _mesa_get_format_name(format
));
1753 intel_miptree_copy_slice_sw(brw
,
1754 src_mt
, src_level
, src_layer
,
1755 dst_mt
, dst_level
, dst_layer
,
1761 * Copies the image's current data to the given miptree, and associates that
1762 * miptree with the image.
1764 * If \c invalidate is true, then the actual image data does not need to be
1765 * copied, but the image still needs to be associated to the new miptree (this
1766 * is set to true if we're about to clear the image).
1769 intel_miptree_copy_teximage(struct brw_context
*brw
,
1770 struct intel_texture_image
*intelImage
,
1771 struct intel_mipmap_tree
*dst_mt
,
1774 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1775 struct intel_texture_object
*intel_obj
=
1776 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1777 int level
= intelImage
->base
.Base
.Level
;
1778 const unsigned face
= intelImage
->base
.Base
.Face
;
1779 unsigned start_layer
, end_layer
;
1781 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1783 assert(intelImage
->base
.Base
.Height
);
1785 end_layer
= intelImage
->base
.Base
.Height
- 1;
1786 } else if (face
> 0) {
1790 assert(intelImage
->base
.Base
.Depth
);
1792 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1796 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1797 intel_miptree_copy_slice(brw
,
1803 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1804 intel_obj
->needs_validate
= true;
1808 intel_miptree_init_mcs(struct brw_context
*brw
,
1809 struct intel_mipmap_tree
*mt
,
1812 assert(mt
->mcs_buf
!= NULL
);
1814 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1816 * When MCS buffer is enabled and bound to MSRT, it is required that it
1817 * is cleared prior to any rendering.
1819 * Since we don't use the MCS buffer for any purpose other than rendering,
1820 * it makes sense to just clear it immediately upon allocation.
1822 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1824 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1825 if (unlikely(map
== NULL
)) {
1826 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1827 brw_bo_unreference(mt
->mcs_buf
->bo
);
1832 memset(data
, init_value
, mt
->mcs_buf
->size
);
1833 brw_bo_unmap(mt
->mcs_buf
->bo
);
1836 static struct intel_miptree_aux_buffer
*
1837 intel_alloc_aux_buffer(struct brw_context
*brw
,
1839 const struct isl_surf
*aux_surf
,
1840 uint32_t alloc_flags
,
1841 struct intel_mipmap_tree
*mt
)
1843 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1847 buf
->size
= aux_surf
->size
;
1848 buf
->pitch
= aux_surf
->row_pitch
;
1849 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1851 /* ISL has stricter set of alignment rules then the drm allocator.
1852 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1853 * trying to recalculate based on different format block sizes.
1855 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1856 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1862 buf
->surf
= *aux_surf
;
1868 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1869 struct intel_mipmap_tree
*mt
,
1872 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1873 assert(mt
->mcs_buf
== NULL
);
1874 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1876 /* Multisampled miptrees are only supported for single level. */
1877 assert(mt
->first_level
== 0);
1878 enum isl_aux_state
**aux_state
=
1879 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1883 struct isl_surf temp_main_surf
;
1884 struct isl_surf temp_mcs_surf
;
1886 /* Create first an ISL presentation for the main color surface and let ISL
1887 * calculate equivalent MCS surface against it.
1889 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1890 MAYBE_UNUSED
bool ok
=
1891 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1894 /* Buffer needs to be initialised requiring the buffer to be immediately
1895 * mapped to cpu space for writing. Therefore do not use the gpu access
1896 * flag which can cause an unnecessary delay if the backing pages happened
1897 * to be just used by the GPU.
1899 const uint32_t alloc_flags
= 0;
1900 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1901 &temp_mcs_surf
, alloc_flags
, mt
);
1907 mt
->aux_state
= aux_state
;
1909 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1915 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1916 struct intel_mipmap_tree
*mt
)
1918 assert(mt
->mcs_buf
== NULL
);
1919 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1920 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1922 struct isl_surf temp_main_surf
;
1923 struct isl_surf temp_ccs_surf
;
1925 /* Create first an ISL presentation for the main color surface and let ISL
1926 * calculate equivalent CCS surface against it.
1928 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1929 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1933 assert(temp_ccs_surf
.size
&&
1934 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1936 enum isl_aux_state
**aux_state
=
1937 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1941 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1942 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1944 * "If Software wants to enable Color Compression without Fast clear,
1945 * Software needs to initialize MCS with zeros."
1947 * A CCS value of 0 indicates that the corresponding block is in the
1948 * pass-through state which is what we want.
1950 * For CCS_D, on the other hand, we don't care as we're about to perform a
1951 * fast-clear operation. In that case, being hot in caches more useful.
1953 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1954 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1955 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1956 &temp_ccs_surf
, alloc_flags
, mt
);
1962 mt
->aux_state
= aux_state
;
1968 * Helper for intel_miptree_alloc_hiz() that sets
1969 * \c mt->level[level].has_hiz. Return true if and only if
1970 * \c has_hiz was set.
1973 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1974 struct intel_mipmap_tree
*mt
,
1977 assert(mt
->hiz_buf
);
1979 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1980 uint32_t width
= minify(mt
->physical_width0
, level
);
1981 uint32_t height
= minify(mt
->physical_height0
, level
);
1983 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1984 * and the height is 4 aligned. This allows our HiZ support
1985 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1986 * we can grow the width & height to allow the HiZ op to
1987 * force the proper size alignments.
1989 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1990 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1995 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1996 mt
->level
[level
].has_hiz
= true;
2001 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2002 struct intel_mipmap_tree
*mt
)
2004 assert(mt
->hiz_buf
== NULL
);
2005 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
2007 enum isl_aux_state
**aux_state
=
2008 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
2012 struct isl_surf temp_main_surf
;
2013 struct isl_surf temp_hiz_surf
;
2015 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
2016 MAYBE_UNUSED
bool ok
=
2017 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
2020 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
2021 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
2022 &temp_hiz_surf
, alloc_flags
, mt
);
2029 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2030 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2032 mt
->aux_state
= aux_state
;
2039 * Allocate the initial aux surface for a miptree based on mt->aux_usage
2041 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
2042 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
2043 * compress clear color so we wait until an actual fast-clear to allocate it.
2046 intel_miptree_alloc_aux(struct brw_context
*brw
,
2047 struct intel_mipmap_tree
*mt
)
2049 switch (mt
->aux_usage
) {
2050 case ISL_AUX_USAGE_NONE
:
2053 case ISL_AUX_USAGE_HIZ
:
2054 assert(!_mesa_is_format_color_format(mt
->format
));
2055 if (!intel_miptree_alloc_hiz(brw
, mt
))
2059 case ISL_AUX_USAGE_MCS
:
2060 assert(_mesa_is_format_color_format(mt
->format
));
2061 assert(mt
->surf
.samples
> 1);
2062 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
2066 case ISL_AUX_USAGE_CCS_D
:
2067 /* Since CCS_D can only compress clear color so we wait until an actual
2068 * fast-clear to allocate it.
2072 case ISL_AUX_USAGE_CCS_E
:
2073 assert(_mesa_is_format_color_format(mt
->format
));
2074 assert(mt
->surf
.samples
== 1);
2075 if (!intel_miptree_alloc_ccs(brw
, mt
))
2080 unreachable("Invalid aux usage");
2085 * Can the miptree sample using the hiz buffer?
2088 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2089 struct intel_mipmap_tree
*mt
)
2091 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2092 * so keep things conservative for now and never enable it unless we're SKL+.
2102 /* It seems the hardware won't fallback to the depth buffer if some of the
2103 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2104 * of the texture to be HiZ enabled.
2106 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2107 if (!intel_miptree_level_has_hiz(mt
, level
))
2111 /* If compressed multisampling is enabled, then we use it for the auxiliary
2114 * From the BDW PRM (Volume 2d: Command Reference: Structures
2115 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2117 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2118 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2120 * There is no such blurb for 1D textures, but there is sufficient evidence
2121 * that this is broken on SKL+.
2123 return (mt
->surf
.samples
== 1 &&
2124 mt
->target
!= GL_TEXTURE_3D
&&
2125 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2129 * Does the miptree slice have hiz enabled?
2132 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2134 intel_miptree_check_level_layer(mt
, level
, 0);
2135 return mt
->level
[level
].has_hiz
;
2139 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2140 unsigned start_level
, unsigned num_levels
,
2141 unsigned start_layer
, unsigned num_layers
)
2143 assert(_mesa_is_format_color_format(mt
->format
));
2148 /* Clamp the level range to fit the miptree */
2149 assert(start_level
+ num_levels
>= start_level
);
2150 const uint32_t last_level
=
2151 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2152 start_level
= MAX2(mt
->first_level
, start_level
);
2153 num_levels
= last_level
- start_level
+ 1;
2155 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2156 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2157 for (unsigned a
= 0; a
< level_layers
; a
++) {
2158 enum isl_aux_state aux_state
=
2159 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2160 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2161 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2170 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2171 const struct intel_mipmap_tree
*mt
,
2172 unsigned level
, unsigned layer
)
2178 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2179 assert(brw
->gen
>= 8 ||
2180 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2182 /* Compression of arrayed msaa surfaces is supported. */
2183 if (mt
->surf
.samples
> 1)
2186 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2187 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2193 static enum blorp_fast_clear_op
2194 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2195 bool ccs_supported
, bool fast_clear_supported
)
2197 assert(ccs_supported
== fast_clear_supported
);
2199 switch (aux_state
) {
2200 case ISL_AUX_STATE_CLEAR
:
2201 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2203 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2205 return BLORP_FAST_CLEAR_OP_NONE
;
2207 case ISL_AUX_STATE_PASS_THROUGH
:
2208 return BLORP_FAST_CLEAR_OP_NONE
;
2210 case ISL_AUX_STATE_RESOLVED
:
2211 case ISL_AUX_STATE_AUX_INVALID
:
2212 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2216 unreachable("Invalid aux state for CCS_D");
2219 static enum blorp_fast_clear_op
2220 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2221 bool ccs_supported
, bool fast_clear_supported
)
2223 switch (aux_state
) {
2224 case ISL_AUX_STATE_CLEAR
:
2225 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2227 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2228 else if (!fast_clear_supported
)
2229 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2231 return BLORP_FAST_CLEAR_OP_NONE
;
2233 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2235 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2237 return BLORP_FAST_CLEAR_OP_NONE
;
2239 case ISL_AUX_STATE_PASS_THROUGH
:
2240 return BLORP_FAST_CLEAR_OP_NONE
;
2242 case ISL_AUX_STATE_RESOLVED
:
2243 case ISL_AUX_STATE_AUX_INVALID
:
2247 unreachable("Invalid aux state for CCS_E");
2251 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2252 struct intel_mipmap_tree
*mt
,
2253 uint32_t level
, uint32_t layer
,
2255 bool fast_clear_supported
)
2257 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2259 enum blorp_fast_clear_op resolve_op
;
2260 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2261 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2262 fast_clear_supported
);
2264 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2265 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2266 fast_clear_supported
);
2269 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2270 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2271 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2273 switch (resolve_op
) {
2274 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2275 /* The CCS full resolve operation destroys the CCS and sets it to the
2276 * pass-through state. (You can also think of this as being both a
2277 * resolve and an ambiguate in one operation.)
2279 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2280 ISL_AUX_STATE_PASS_THROUGH
);
2283 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2284 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2285 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2289 unreachable("Invalid resolve op");
2295 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2296 struct intel_mipmap_tree
*mt
,
2297 uint32_t level
, uint32_t layer
,
2298 bool written_with_ccs
)
2300 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2302 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2303 switch (aux_state
) {
2304 case ISL_AUX_STATE_CLEAR
:
2305 assert(written_with_ccs
);
2306 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2307 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2310 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2311 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2312 assert(written_with_ccs
);
2313 break; /* Nothing to do */
2315 case ISL_AUX_STATE_PASS_THROUGH
:
2316 if (written_with_ccs
) {
2317 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2318 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2324 case ISL_AUX_STATE_RESOLVED
:
2325 case ISL_AUX_STATE_AUX_INVALID
:
2326 unreachable("Invalid aux state for CCS_E");
2329 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2330 /* CCS_D is a bit simpler */
2331 switch (aux_state
) {
2332 case ISL_AUX_STATE_CLEAR
:
2333 assert(written_with_ccs
);
2334 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2335 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2338 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2339 assert(written_with_ccs
);
2340 break; /* Nothing to do */
2342 case ISL_AUX_STATE_PASS_THROUGH
:
2346 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2347 case ISL_AUX_STATE_RESOLVED
:
2348 case ISL_AUX_STATE_AUX_INVALID
:
2349 unreachable("Invalid aux state for CCS_D");
2355 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 uint32_t level
, uint32_t layer
,
2358 bool written_with_aux
)
2360 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2361 case ISL_AUX_STATE_CLEAR
:
2362 assert(written_with_aux
);
2363 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2364 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2367 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2368 assert(written_with_aux
);
2369 break; /* Nothing to do */
2371 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2372 case ISL_AUX_STATE_RESOLVED
:
2373 case ISL_AUX_STATE_PASS_THROUGH
:
2374 case ISL_AUX_STATE_AUX_INVALID
:
2375 unreachable("Invalid aux state for MCS");
2380 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2381 struct intel_mipmap_tree
*mt
,
2382 uint32_t level
, uint32_t layer
,
2383 bool hiz_supported
, bool fast_clear_supported
)
2385 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2386 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2387 case ISL_AUX_STATE_CLEAR
:
2388 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2389 if (!hiz_supported
|| !fast_clear_supported
)
2390 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2393 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2395 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2398 case ISL_AUX_STATE_PASS_THROUGH
:
2399 case ISL_AUX_STATE_RESOLVED
:
2402 case ISL_AUX_STATE_AUX_INVALID
:
2404 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2408 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2409 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2412 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2413 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2414 ISL_AUX_STATE_RESOLVED
);
2417 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2418 /* The HiZ resolve operation is actually an ambiguate */
2419 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2420 ISL_AUX_STATE_PASS_THROUGH
);
2424 unreachable("Invalid HiZ op");
2430 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2431 struct intel_mipmap_tree
*mt
,
2432 uint32_t level
, uint32_t layer
,
2433 bool written_with_hiz
)
2435 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2436 case ISL_AUX_STATE_CLEAR
:
2437 assert(written_with_hiz
);
2438 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2439 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2442 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2443 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2444 assert(written_with_hiz
);
2445 break; /* Nothing to do */
2447 case ISL_AUX_STATE_RESOLVED
:
2448 if (written_with_hiz
) {
2449 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2450 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2452 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2453 ISL_AUX_STATE_AUX_INVALID
);
2457 case ISL_AUX_STATE_PASS_THROUGH
:
2458 if (written_with_hiz
) {
2459 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2460 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2464 case ISL_AUX_STATE_AUX_INVALID
:
2465 assert(!written_with_hiz
);
2470 static inline uint32_t
2471 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2472 uint32_t start_level
, uint32_t num_levels
)
2474 assert(start_level
>= mt
->first_level
);
2475 assert(start_level
<= mt
->last_level
);
2477 if (num_levels
== INTEL_REMAINING_LAYERS
)
2478 num_levels
= mt
->last_level
- start_level
+ 1;
2479 /* Check for overflow */
2480 assert(start_level
+ num_levels
>= start_level
);
2481 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2486 static inline uint32_t
2487 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2488 uint32_t start_layer
, uint32_t num_layers
)
2490 assert(level
<= mt
->last_level
);
2491 uint32_t total_num_layers
;
2493 if (mt
->surf
.size
> 0)
2494 total_num_layers
= get_num_phys_layers(&mt
->surf
, level
);
2496 total_num_layers
= mt
->level
[level
].depth
;
2498 assert(start_layer
< total_num_layers
);
2499 if (num_layers
== INTEL_REMAINING_LAYERS
)
2500 num_layers
= total_num_layers
- start_layer
;
2501 /* Check for overflow */
2502 assert(start_layer
+ num_layers
>= start_layer
);
2503 assert(start_layer
+ num_layers
<= total_num_layers
);
2509 intel_miptree_prepare_access(struct brw_context
*brw
,
2510 struct intel_mipmap_tree
*mt
,
2511 uint32_t start_level
, uint32_t num_levels
,
2512 uint32_t start_layer
, uint32_t num_layers
,
2513 bool aux_supported
, bool fast_clear_supported
)
2515 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2517 if (_mesa_is_format_color_format(mt
->format
)) {
2521 if (mt
->surf
.samples
> 1) {
2522 /* Nothing to do for MSAA */
2523 assert(aux_supported
&& fast_clear_supported
);
2525 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2526 const uint32_t level
= start_level
+ l
;
2527 const uint32_t level_layers
=
2528 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2529 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2530 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2531 start_layer
+ a
, aux_supported
,
2532 fast_clear_supported
);
2536 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2537 /* Nothing to do for stencil */
2542 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2543 const uint32_t level
= start_level
+ l
;
2544 if (!intel_miptree_level_has_hiz(mt
, level
))
2547 const uint32_t level_layers
=
2548 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2549 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2550 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2552 fast_clear_supported
);
2559 intel_miptree_finish_write(struct brw_context
*brw
,
2560 struct intel_mipmap_tree
*mt
, uint32_t level
,
2561 uint32_t start_layer
, uint32_t num_layers
,
2562 bool written_with_aux
)
2564 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2566 if (_mesa_is_format_color_format(mt
->format
)) {
2570 if (mt
->surf
.samples
> 1) {
2571 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2572 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2576 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2577 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2581 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2582 /* Nothing to do for stencil */
2584 if (!intel_miptree_level_has_hiz(mt
, level
))
2587 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2588 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2595 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2596 uint32_t level
, uint32_t layer
)
2598 intel_miptree_check_level_layer(mt
, level
, layer
);
2600 if (_mesa_is_format_color_format(mt
->format
)) {
2601 assert(mt
->mcs_buf
!= NULL
);
2602 assert(mt
->surf
.samples
== 1 ||
2603 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2604 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2605 unreachable("Cannot get aux state for stencil");
2607 assert(intel_miptree_level_has_hiz(mt
, level
));
2610 return mt
->aux_state
[level
][layer
];
2614 intel_miptree_set_aux_state(struct brw_context
*brw
,
2615 struct intel_mipmap_tree
*mt
, uint32_t level
,
2616 uint32_t start_layer
, uint32_t num_layers
,
2617 enum isl_aux_state aux_state
)
2619 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2621 if (_mesa_is_format_color_format(mt
->format
)) {
2622 assert(mt
->mcs_buf
!= NULL
);
2623 assert(mt
->surf
.samples
== 1 ||
2624 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2625 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2626 unreachable("Cannot get aux state for stencil");
2628 assert(intel_miptree_level_has_hiz(mt
, level
));
2631 for (unsigned a
= 0; a
< num_layers
; a
++)
2632 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2635 /* On Gen9 color buffers may be compressed by the hardware (lossless
2636 * compression). There are, however, format restrictions and care needs to be
2637 * taken that the sampler engine is capable for re-interpreting a buffer with
2638 * format different the buffer was originally written with.
2640 * For example, SRGB formats are not compressible and the sampler engine isn't
2641 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2642 * color buffer needs to be resolved so that the sampling surface can be
2643 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2647 can_texture_with_ccs(struct brw_context
*brw
,
2648 struct intel_mipmap_tree
*mt
,
2649 mesa_format view_format
)
2651 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2654 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2655 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2657 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2658 isl_mt_format
, isl_view_format
)) {
2659 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2660 _mesa_get_format_name(view_format
),
2661 _mesa_get_format_name(mt
->format
));
2669 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2670 struct intel_mipmap_tree
*mt
,
2671 mesa_format view_format
,
2672 uint32_t start_level
, uint32_t num_levels
,
2673 uint32_t start_layer
, uint32_t num_layers
,
2674 bool *aux_supported_out
)
2676 bool aux_supported
, clear_supported
;
2677 if (_mesa_is_format_color_format(mt
->format
)) {
2678 if (mt
->surf
.samples
> 1) {
2679 aux_supported
= clear_supported
= true;
2681 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2683 /* Clear color is specified as ints or floats and the conversion is
2684 * done by the sampler. If we have a texture view, we would have to
2685 * perform the clear color conversion manually. Just disable clear
2688 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2690 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2691 aux_supported
= clear_supported
= false;
2693 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2696 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2697 start_layer
, num_layers
,
2698 aux_supported
, clear_supported
);
2699 if (aux_supported_out
)
2700 *aux_supported_out
= aux_supported
;
2704 intel_miptree_prepare_texture(struct brw_context
*brw
,
2705 struct intel_mipmap_tree
*mt
,
2706 mesa_format view_format
,
2707 bool *aux_supported_out
)
2709 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2710 0, INTEL_REMAINING_LEVELS
,
2711 0, INTEL_REMAINING_LAYERS
,
2716 intel_miptree_prepare_image(struct brw_context
*brw
,
2717 struct intel_mipmap_tree
*mt
)
2719 /* The data port doesn't understand any compression */
2720 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2721 0, INTEL_REMAINING_LAYERS
, false, false);
2725 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2726 struct intel_mipmap_tree
*mt
, uint32_t level
,
2727 uint32_t start_layer
, uint32_t num_layers
)
2729 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2730 start_layer
, num_layers
, NULL
);
2734 intel_miptree_prepare_render(struct brw_context
*brw
,
2735 struct intel_mipmap_tree
*mt
, uint32_t level
,
2736 uint32_t start_layer
, uint32_t layer_count
,
2739 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2740 * the single-sampled color renderbuffers because the CCS buffer isn't
2741 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2742 * enabled because otherwise the surface state will be programmed with
2743 * the linear equivalent format anyway.
2745 if (brw
->gen
== 9 && srgb_enabled
&& mt
->surf
.samples
== 1 &&
2746 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2748 /* Lossless compression is not supported for SRGB formats, it
2749 * should be impossible to get here with such surfaces.
2751 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2752 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2758 intel_miptree_finish_render(struct brw_context
*brw
,
2759 struct intel_mipmap_tree
*mt
, uint32_t level
,
2760 uint32_t start_layer
, uint32_t layer_count
)
2762 assert(_mesa_is_format_color_format(mt
->format
));
2763 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2764 mt
->mcs_buf
!= NULL
);
2768 intel_miptree_prepare_depth(struct brw_context
*brw
,
2769 struct intel_mipmap_tree
*mt
, uint32_t level
,
2770 uint32_t start_layer
, uint32_t layer_count
)
2772 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2773 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2777 intel_miptree_finish_depth(struct brw_context
*brw
,
2778 struct intel_mipmap_tree
*mt
, uint32_t level
,
2779 uint32_t start_layer
, uint32_t layer_count
,
2782 if (depth_written
) {
2783 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2784 mt
->hiz_buf
!= NULL
);
2789 * Make it possible to share the BO backing the given miptree with another
2790 * process or another miptree.
2792 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2793 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2794 * ensure that no MCS buffer gets allocated in the future.
2796 * HiZ is similarly unsafe with shared buffers.
2799 intel_miptree_make_shareable(struct brw_context
*brw
,
2800 struct intel_mipmap_tree
*mt
)
2802 /* MCS buffers are also used for multisample buffers, but we can't resolve
2803 * away a multisample MCS buffer because it's an integral part of how the
2804 * pixel data is stored. Fortunately this code path should never be
2805 * reached for multisample buffers.
2807 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2808 mt
->surf
.samples
== 1);
2810 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2811 0, INTEL_REMAINING_LAYERS
, false, false);
2814 brw_bo_unreference(mt
->mcs_buf
->bo
);
2818 /* Any pending MCS/CCS operations are no longer needed. Trying to
2819 * execute any will likely crash due to the missing aux buffer. So let's
2820 * delete all pending ops.
2822 free(mt
->aux_state
);
2823 mt
->aux_state
= NULL
;
2827 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2830 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2831 mt
->level
[l
].has_hiz
= false;
2834 /* Any pending HiZ operations are no longer needed. Trying to execute
2835 * any will likely crash due to the missing aux buffer. So let's delete
2838 free(mt
->aux_state
);
2839 mt
->aux_state
= NULL
;
2842 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2847 * \brief Get pointer offset into stencil buffer.
2849 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2850 * must decode the tile's layout in software.
2853 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2855 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2857 * Even though the returned offset is always positive, the return type is
2859 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2860 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2863 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2865 uint32_t tile_size
= 4096;
2866 uint32_t tile_width
= 64;
2867 uint32_t tile_height
= 64;
2868 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2870 uint32_t tile_x
= x
/ tile_width
;
2871 uint32_t tile_y
= y
/ tile_height
;
2873 /* The byte's address relative to the tile's base addres. */
2874 uint32_t byte_x
= x
% tile_width
;
2875 uint32_t byte_y
= y
% tile_height
;
2877 uintptr_t u
= tile_y
* row_size
2878 + tile_x
* tile_size
2879 + 512 * (byte_x
/ 8)
2881 + 32 * ((byte_y
/ 4) % 2)
2882 + 16 * ((byte_x
/ 4) % 2)
2883 + 8 * ((byte_y
/ 2) % 2)
2884 + 4 * ((byte_x
/ 2) % 2)
2889 /* adjust for bit6 swizzling */
2890 if (((byte_x
/ 8) % 2) == 1) {
2891 if (((byte_y
/ 8) % 2) == 0) {
2903 intel_miptree_updownsample(struct brw_context
*brw
,
2904 struct intel_mipmap_tree
*src
,
2905 struct intel_mipmap_tree
*dst
)
2907 unsigned src_w
, src_h
, dst_w
, dst_h
;
2909 if (src
->surf
.size
> 0) {
2910 src_w
= src
->surf
.logical_level0_px
.width
;
2911 src_h
= src
->surf
.logical_level0_px
.height
;
2913 src_w
= src
->logical_width0
;
2914 src_h
= src
->logical_height0
;
2917 if (dst
->surf
.size
> 0) {
2918 dst_w
= dst
->surf
.logical_level0_px
.width
;
2919 dst_h
= dst
->surf
.logical_level0_px
.height
;
2921 dst_w
= dst
->logical_width0
;
2922 dst_h
= dst
->logical_height0
;
2925 brw_blorp_blit_miptrees(brw
,
2926 src
, 0 /* level */, 0 /* layer */,
2927 src
->format
, SWIZZLE_XYZW
,
2928 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2931 GL_NEAREST
, false, false /*mirror x, y*/,
2934 if (src
->stencil_mt
) {
2935 if (src
->stencil_mt
->surf
.size
> 0) {
2936 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2937 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2939 src_w
= src
->stencil_mt
->logical_width0
;
2940 src_h
= src
->stencil_mt
->logical_height0
;
2943 if (dst
->stencil_mt
->surf
.size
> 0) {
2944 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2945 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2947 dst_w
= dst
->stencil_mt
->logical_width0
;
2948 dst_h
= dst
->stencil_mt
->logical_height0
;
2951 brw_blorp_blit_miptrees(brw
,
2952 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2953 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2954 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2955 dst
->stencil_mt
->format
,
2958 GL_NEAREST
, false, false /*mirror x, y*/,
2959 false, false /* decode/encode srgb */);
2964 intel_update_r8stencil(struct brw_context
*brw
,
2965 struct intel_mipmap_tree
*mt
)
2967 assert(brw
->gen
>= 7);
2968 struct intel_mipmap_tree
*src
=
2969 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2970 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2973 assert(src
->surf
.size
> 0);
2975 if (!mt
->r8stencil_mt
) {
2976 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2977 mt
->r8stencil_mt
= make_surface(
2980 MESA_FORMAT_R_UINT8
,
2981 src
->first_level
, src
->last_level
,
2982 src
->surf
.logical_level0_px
.width
,
2983 src
->surf
.logical_level0_px
.height
,
2984 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2985 src
->surf
.logical_level0_px
.depth
:
2986 src
->surf
.logical_level0_px
.array_len
,
2989 ISL_SURF_USAGE_TEXTURE_BIT
,
2990 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2991 assert(mt
->r8stencil_mt
);
2994 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2996 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2997 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2998 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2999 src
->surf
.phys_level0_sa
.array_len
;
3001 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3002 brw_blorp_copy_miptrees(brw
,
3006 minify(src
->surf
.logical_level0_px
.width
,
3008 minify(src
->surf
.logical_level0_px
.height
,
3013 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3014 src
->r8stencil_needs_update
= false;
3018 intel_miptree_map_raw(struct brw_context
*brw
,
3019 struct intel_mipmap_tree
*mt
,
3022 struct brw_bo
*bo
= mt
->bo
;
3024 if (brw_batch_references(&brw
->batch
, bo
))
3025 intel_batchbuffer_flush(brw
);
3027 return brw_bo_map(brw
, bo
, mode
);
3031 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3033 brw_bo_unmap(mt
->bo
);
3037 intel_miptree_map_gtt(struct brw_context
*brw
,
3038 struct intel_mipmap_tree
*mt
,
3039 struct intel_miptree_map
*map
,
3040 unsigned int level
, unsigned int slice
)
3042 unsigned int bw
, bh
;
3044 unsigned int image_x
, image_y
;
3045 intptr_t x
= map
->x
;
3046 intptr_t y
= map
->y
;
3048 /* For compressed formats, the stride is the number of bytes per
3049 * row of blocks. intel_miptree_get_image_offset() already does
3052 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3053 assert(y
% bh
== 0);
3054 assert(x
% bw
== 0);
3058 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3065 /* Note that in the case of cube maps, the caller must have passed the
3066 * slice number referencing the face.
3068 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3072 map
->stride
= mt
->surf
.row_pitch
;
3073 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3076 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3077 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3078 map
->x
, map
->y
, map
->w
, map
->h
,
3079 mt
, _mesa_get_format_name(mt
->format
),
3080 x
, y
, map
->ptr
, map
->stride
);
3084 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3086 intel_miptree_unmap_raw(mt
);
3090 intel_miptree_map_blit(struct brw_context
*brw
,
3091 struct intel_mipmap_tree
*mt
,
3092 struct intel_miptree_map
*map
,
3093 unsigned int level
, unsigned int slice
)
3095 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3096 /* first_level */ 0,
3100 MIPTREE_LAYOUT_TILING_NONE
);
3102 if (!map
->linear_mt
) {
3103 fprintf(stderr
, "Failed to allocate blit temporary\n");
3106 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3108 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3109 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3110 * invalidate is set, since we'll be writing the whole rectangle from our
3111 * temporary buffer back out.
3113 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3114 if (!intel_miptree_copy(brw
,
3115 mt
, level
, slice
, map
->x
, map
->y
,
3116 map
->linear_mt
, 0, 0, 0, 0,
3118 fprintf(stderr
, "Failed to blit\n");
3123 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3125 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3126 map
->x
, map
->y
, map
->w
, map
->h
,
3127 mt
, _mesa_get_format_name(mt
->format
),
3128 level
, slice
, map
->ptr
, map
->stride
);
3133 intel_miptree_release(&map
->linear_mt
);
3139 intel_miptree_unmap_blit(struct brw_context
*brw
,
3140 struct intel_mipmap_tree
*mt
,
3141 struct intel_miptree_map
*map
,
3145 struct gl_context
*ctx
= &brw
->ctx
;
3147 intel_miptree_unmap_raw(map
->linear_mt
);
3149 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3150 bool ok
= intel_miptree_copy(brw
,
3151 map
->linear_mt
, 0, 0, 0, 0,
3152 mt
, level
, slice
, map
->x
, map
->y
,
3154 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3157 intel_miptree_release(&map
->linear_mt
);
3161 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3163 #if defined(USE_SSE41)
3165 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3166 struct intel_mipmap_tree
*mt
,
3167 struct intel_miptree_map
*map
,
3168 unsigned int level
, unsigned int slice
)
3170 assert(map
->mode
& GL_MAP_READ_BIT
);
3171 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3173 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3174 map
->x
, map
->y
, map
->w
, map
->h
,
3175 mt
, _mesa_get_format_name(mt
->format
),
3176 level
, slice
, map
->ptr
, map
->stride
);
3178 /* Map the original image */
3181 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3185 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3191 src
+= image_y
* mt
->surf
.row_pitch
;
3192 src
+= image_x
* mt
->cpp
;
3194 /* Due to the pixel offsets for the particular image being mapped, our
3195 * src pointer may not be 16-byte aligned. However, if the pitch is
3196 * divisible by 16, then the amount by which it's misaligned will remain
3197 * consistent from row to row.
3199 assert((mt
->surf
.row_pitch
% 16) == 0);
3200 const int misalignment
= ((uintptr_t) src
) & 15;
3202 /* Create an untiled temporary buffer for the mapping. */
3203 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3205 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3207 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3208 /* Offset the destination so it has the same misalignment as src. */
3209 map
->ptr
= map
->buffer
+ misalignment
;
3211 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3213 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3214 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3215 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3217 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3220 intel_miptree_unmap_raw(mt
);
3224 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3225 struct intel_mipmap_tree
*mt
,
3226 struct intel_miptree_map
*map
,
3230 _mesa_align_free(map
->buffer
);
3237 intel_miptree_map_s8(struct brw_context
*brw
,
3238 struct intel_mipmap_tree
*mt
,
3239 struct intel_miptree_map
*map
,
3240 unsigned int level
, unsigned int slice
)
3242 map
->stride
= map
->w
;
3243 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3247 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3248 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3249 * invalidate is set, since we'll be writing the whole rectangle from our
3250 * temporary buffer back out.
3252 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3253 uint8_t *untiled_s8_map
= map
->ptr
;
3254 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3255 unsigned int image_x
, image_y
;
3257 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3259 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3260 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3261 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3262 x
+ image_x
+ map
->x
,
3263 y
+ image_y
+ map
->y
,
3264 brw
->has_swizzling
);
3265 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3269 intel_miptree_unmap_raw(mt
);
3271 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3272 map
->x
, map
->y
, map
->w
, map
->h
,
3273 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3275 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3276 map
->x
, map
->y
, map
->w
, map
->h
,
3277 mt
, map
->ptr
, map
->stride
);
3282 intel_miptree_unmap_s8(struct brw_context
*brw
,
3283 struct intel_mipmap_tree
*mt
,
3284 struct intel_miptree_map
*map
,
3288 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3289 unsigned int image_x
, image_y
;
3290 uint8_t *untiled_s8_map
= map
->ptr
;
3291 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3293 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3295 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3296 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3297 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3298 image_x
+ x
+ map
->x
,
3299 image_y
+ y
+ map
->y
,
3300 brw
->has_swizzling
);
3301 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3305 intel_miptree_unmap_raw(mt
);
3312 intel_miptree_map_etc(struct brw_context
*brw
,
3313 struct intel_mipmap_tree
*mt
,
3314 struct intel_miptree_map
*map
,
3318 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3319 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3320 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3323 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3324 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3326 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3327 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3328 map
->w
, map
->h
, 1));
3329 map
->ptr
= map
->buffer
;
3333 intel_miptree_unmap_etc(struct brw_context
*brw
,
3334 struct intel_mipmap_tree
*mt
,
3335 struct intel_miptree_map
*map
,
3341 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3346 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3347 + image_y
* mt
->surf
.row_pitch
3348 + image_x
* mt
->cpp
;
3350 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3351 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3352 map
->ptr
, map
->stride
,
3355 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3356 map
->ptr
, map
->stride
,
3357 map
->w
, map
->h
, mt
->etc_format
);
3359 intel_miptree_unmap_raw(mt
);
3364 * Mapping function for packed depth/stencil miptrees backed by real separate
3365 * miptrees for depth and stencil.
3367 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3368 * separate from the depth buffer. Yet at the GL API level, we have to expose
3369 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3370 * be able to map that memory for texture storage and glReadPixels-type
3371 * operations. We give Mesa core that access by mallocing a temporary and
3372 * copying the data between the actual backing store and the temporary.
3375 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3376 struct intel_mipmap_tree
*mt
,
3377 struct intel_miptree_map
*map
,
3378 unsigned int level
, unsigned int slice
)
3380 struct intel_mipmap_tree
*z_mt
= mt
;
3381 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3382 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3383 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3385 map
->stride
= map
->w
* packed_bpp
;
3386 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3390 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3391 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3392 * invalidate is set, since we'll be writing the whole rectangle from our
3393 * temporary buffer back out.
3395 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3396 uint32_t *packed_map
= map
->ptr
;
3397 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3398 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3399 unsigned int s_image_x
, s_image_y
;
3400 unsigned int z_image_x
, z_image_y
;
3402 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3403 &s_image_x
, &s_image_y
);
3404 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3405 &z_image_x
, &z_image_y
);
3407 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3408 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3409 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3410 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3413 brw
->has_swizzling
);
3414 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3415 (z_mt
->surf
.row_pitch
/ 4) +
3416 (map_x
+ z_image_x
));
3417 uint8_t s
= s_map
[s_offset
];
3418 uint32_t z
= z_map
[z_offset
];
3420 if (map_z32f_x24s8
) {
3421 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3422 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3424 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3429 intel_miptree_unmap_raw(s_mt
);
3430 intel_miptree_unmap_raw(z_mt
);
3432 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3434 map
->x
, map
->y
, map
->w
, map
->h
,
3435 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3436 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3437 map
->ptr
, map
->stride
);
3439 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3440 map
->x
, map
->y
, map
->w
, map
->h
,
3441 mt
, map
->ptr
, map
->stride
);
3446 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3447 struct intel_mipmap_tree
*mt
,
3448 struct intel_miptree_map
*map
,
3452 struct intel_mipmap_tree
*z_mt
= mt
;
3453 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3454 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3456 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3457 uint32_t *packed_map
= map
->ptr
;
3458 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3459 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3460 unsigned int s_image_x
, s_image_y
;
3461 unsigned int z_image_x
, z_image_y
;
3463 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3464 &s_image_x
, &s_image_y
);
3465 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3466 &z_image_x
, &z_image_y
);
3468 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3469 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3470 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3471 x
+ s_image_x
+ map
->x
,
3472 y
+ s_image_y
+ map
->y
,
3473 brw
->has_swizzling
);
3474 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3475 (z_mt
->surf
.row_pitch
/ 4) +
3476 (x
+ z_image_x
+ map
->x
));
3478 if (map_z32f_x24s8
) {
3479 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3480 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3482 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3483 s_map
[s_offset
] = packed
>> 24;
3484 z_map
[z_offset
] = packed
;
3489 intel_miptree_unmap_raw(s_mt
);
3490 intel_miptree_unmap_raw(z_mt
);
3492 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3494 map
->x
, map
->y
, map
->w
, map
->h
,
3495 z_mt
, _mesa_get_format_name(z_mt
->format
),
3496 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3497 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3498 map
->ptr
, map
->stride
);
3505 * Create and attach a map to the miptree at (level, slice). Return the
3508 static struct intel_miptree_map
*
3509 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3518 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3523 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3524 mt
->level
[level
].slice
[slice
].map
= map
;
3536 * Release the map at (level, slice).
3539 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3543 struct intel_miptree_map
**map
;
3545 map
= &mt
->level
[level
].slice
[slice
].map
;
3551 can_blit_slice(struct intel_mipmap_tree
*mt
,
3552 unsigned int level
, unsigned int slice
)
3554 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3555 if (mt
->surf
.row_pitch
>= 32768)
3562 use_intel_mipree_map_blit(struct brw_context
*brw
,
3563 struct intel_mipmap_tree
*mt
,
3569 /* It's probably not worth swapping to the blit ring because of
3570 * all the overhead involved.
3572 !(mode
& GL_MAP_WRITE_BIT
) &&
3574 (mt
->surf
.tiling
== ISL_TILING_X
||
3575 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3576 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3577 /* Fast copy blit on skl+ supports all tiling formats. */
3579 can_blit_slice(mt
, level
, slice
))
3582 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3583 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3584 assert(can_blit_slice(mt
, level
, slice
));
3592 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3593 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3594 * arithmetic overflow.
3596 * If you call this function and use \a out_stride, then you're doing pointer
3597 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3598 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3599 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3600 * which usually have type uint32_t or GLuint.
3603 intel_miptree_map(struct brw_context
*brw
,
3604 struct intel_mipmap_tree
*mt
,
3613 ptrdiff_t *out_stride
)
3615 struct intel_miptree_map
*map
;
3617 assert(mt
->surf
.samples
== 1);
3619 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3626 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3627 map
->mode
& GL_MAP_WRITE_BIT
);
3629 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3630 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3631 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3632 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3633 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3634 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3635 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3636 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3637 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3638 #if defined(USE_SSE41)
3639 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3640 !mt
->compressed
&& cpu_has_sse4_1
&&
3641 (mt
->surf
.row_pitch
% 16 == 0)) {
3642 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3645 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3648 *out_ptr
= map
->ptr
;
3649 *out_stride
= map
->stride
;
3651 if (map
->ptr
== NULL
)
3652 intel_miptree_release_map(mt
, level
, slice
);
3656 intel_miptree_unmap(struct brw_context
*brw
,
3657 struct intel_mipmap_tree
*mt
,
3661 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3663 assert(mt
->surf
.samples
== 1);
3668 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3669 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3671 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3672 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3673 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3674 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3675 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3676 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3677 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3678 } else if (map
->linear_mt
) {
3679 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3680 #if defined(USE_SSE41)
3681 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3682 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3685 intel_miptree_unmap_gtt(mt
);
3688 intel_miptree_release_map(mt
, level
, slice
);
3692 get_isl_surf_dim(GLenum target
)
3696 case GL_TEXTURE_1D_ARRAY
:
3697 return ISL_SURF_DIM_1D
;
3700 case GL_TEXTURE_2D_ARRAY
:
3701 case GL_TEXTURE_RECTANGLE
:
3702 case GL_TEXTURE_CUBE_MAP
:
3703 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3704 case GL_TEXTURE_2D_MULTISAMPLE
:
3705 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3706 case GL_TEXTURE_EXTERNAL_OES
:
3707 return ISL_SURF_DIM_2D
;
3710 return ISL_SURF_DIM_3D
;
3713 unreachable("Invalid texture target");
3717 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3718 enum isl_tiling tiling
, GLenum target
,
3719 enum miptree_array_layout array_layout
)
3721 if (array_layout
== GEN6_HIZ_STENCIL
)
3722 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3726 case GL_TEXTURE_1D_ARRAY
:
3727 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3728 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3731 case GL_TEXTURE_2D_ARRAY
:
3732 case GL_TEXTURE_RECTANGLE
:
3733 case GL_TEXTURE_2D_MULTISAMPLE
:
3734 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3735 case GL_TEXTURE_EXTERNAL_OES
:
3736 return ISL_DIM_LAYOUT_GEN4_2D
;
3738 case GL_TEXTURE_CUBE_MAP
:
3739 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3740 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3741 ISL_DIM_LAYOUT_GEN4_2D
);
3744 return (devinfo
->gen
>= 9 ?
3745 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3748 unreachable("Invalid texture target");
3752 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3754 if (mt
->format
== MESA_FORMAT_S_UINT8
)
3755 return ISL_TILING_W
;
3756 return mt
->surf
.tiling
;
3760 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3761 const struct intel_mipmap_tree
*mt
,
3762 struct isl_surf
*surf
)
3764 surf
->dim
= get_isl_surf_dim(mt
->target
);
3765 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3766 mt
->surf
.tiling
, mt
->target
,
3768 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3769 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3770 surf
->row_pitch
= mt
->surf
.row_pitch
;
3771 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3773 if (brw
->gen
>= 9) {
3774 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3775 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3776 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3778 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3779 * alignment in terms of surface elements like we want.
3781 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3784 /* On earlier gens it's stored in pixels. */
3786 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3787 surf
->image_alignment_el
=
3788 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3791 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3792 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3793 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3794 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3795 surf
->logical_level0_px
.array_len
= 1;
3797 surf
->logical_level0_px
.depth
= 1;
3798 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3801 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3802 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3803 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3804 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3805 surf
->phys_level0_sa
.array_len
= 1;
3807 surf
->phys_level0_sa
.depth
= 1;
3808 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3811 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3812 surf
->samples
= mt
->surf
.samples
;
3814 surf
->size
= 0; /* TODO */
3815 surf
->alignment
= 0; /* TODO */
3817 switch (surf
->dim_layout
) {
3818 case ISL_DIM_LAYOUT_GEN4_2D
:
3819 case ISL_DIM_LAYOUT_GEN4_3D
:
3820 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3821 if (brw
->gen
>= 9) {
3822 surf
->array_pitch_el_rows
= mt
->qpitch
;
3825 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3826 assert(mt
->qpitch
% bh
== 0);
3827 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3830 case ISL_DIM_LAYOUT_GEN9_1D
:
3831 surf
->array_pitch_el_rows
= 1;
3835 switch (mt
->array_layout
) {
3836 case ALL_LOD_IN_EACH_SLICE
:
3837 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3839 case ALL_SLICES_AT_EACH_LOD
:
3840 case GEN6_HIZ_STENCIL
:
3841 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3844 unreachable("Invalid array layout");
3847 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3848 switch (base_format
) {
3849 case GL_DEPTH_COMPONENT
:
3850 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3852 case GL_STENCIL_INDEX
:
3853 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3855 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3857 case GL_DEPTH_STENCIL
:
3858 /* In this case we only texture from the depth part */
3859 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3860 ISL_SURF_USAGE_TEXTURE_BIT
;
3863 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3864 if (brw
->mesa_format_supports_render
[mt
->format
])
3865 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3869 if (_mesa_is_cube_map_texture(mt
->target
))
3870 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3874 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3875 const struct intel_mipmap_tree
*mt
)
3878 return ISL_AUX_USAGE_HIZ
;
3881 return ISL_AUX_USAGE_NONE
;
3883 return mt
->aux_usage
;