2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return brw_losslessly_compressible_format(brw
, brw_format
);
270 /* On Gen9 support for color buffer compression was extended to single
271 * sampled surfaces. This is a helper considering both auxiliary buffer
272 * type and number of samples telling if the given miptree represents
273 * the new single sampled case - also called lossless compression.
276 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
277 const struct intel_mipmap_tree
*mt
)
279 /* Only available from Gen9 onwards. */
283 /* Compression always requires auxiliary buffer. */
287 /* Single sample compression is represented re-using msaa compression
288 * layout type: "Compressed Multisampled Surfaces".
290 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
293 /* And finally distinguish between msaa and single sample case. */
294 return mt
->num_samples
<= 1;
298 * Determine depth format corresponding to a depth+stencil format,
299 * for separate stencil.
302 intel_depth_format_for_depthstencil_format(mesa_format format
) {
304 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
305 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
306 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
307 return MESA_FORMAT_Z_FLOAT32
;
315 * @param for_bo Indicates that the caller is
316 * intel_miptree_create_for_bo(). If true, then do not create
319 static struct intel_mipmap_tree
*
320 intel_miptree_create_layout(struct brw_context
*brw
,
329 uint32_t layout_flags
)
331 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
335 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
336 _mesa_enum_to_string(target
),
337 _mesa_get_format_name(format
),
338 first_level
, last_level
, depth0
, mt
);
340 if (target
== GL_TEXTURE_1D_ARRAY
) {
341 /* For a 1D Array texture the OpenGL API will treat the height0
342 * parameter as the number of array slices. For Intel hardware, we treat
343 * the 1D array as a 2D Array with a height of 1.
345 * So, when we first come through this path to create a 1D Array
346 * texture, height0 stores the number of slices, and depth0 is 1. In
347 * this case, we want to swap height0 and depth0.
349 * Since some miptrees will be created based on the base miptree, we may
350 * come through this path and see height0 as 1 and depth0 being the
351 * number of slices. In this case we don't need to do the swap.
353 assert(height0
== 1 || depth0
== 1);
362 mt
->first_level
= first_level
;
363 mt
->last_level
= last_level
;
364 mt
->logical_width0
= width0
;
365 mt
->logical_height0
= height0
;
366 mt
->logical_depth0
= depth0
;
367 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
368 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
369 exec_list_make_empty(&mt
->hiz_map
);
370 mt
->cpp
= _mesa_get_format_bytes(format
);
371 mt
->num_samples
= num_samples
;
372 mt
->compressed
= _mesa_is_format_compressed(format
);
373 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
376 if (num_samples
> 1) {
377 /* Adjust width/height/depth for MSAA */
378 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
379 mt
->disable_aux_buffers
);
380 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
381 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
382 * "If the surface is multisampled and it is a depth or stencil
383 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
384 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
387 * +----------------------------------------------------------------+
388 * | Num Multisamples | W_l = | H_l = |
389 * +----------------------------------------------------------------+
390 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
391 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
392 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
393 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
394 * +----------------------------------------------------------------+
397 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
398 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
399 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
401 * Another more complicated explanation for these adjustments comes
402 * from the Sandybridge PRM, volume 4, part 1, page 31:
404 * "Any of the other messages (sample*, LOD, load4) used with a
405 * (4x) multisampled surface will in-effect sample a surface with
406 * double the height and width as that indicated in the surface
407 * state. Each pixel position on the original-sized surface is
408 * replaced with a 2x2 of samples with the following arrangement:
413 * Thus, when sampling from a multisampled texture, it behaves as
414 * though the layout in memory for (x,y,sample) is:
416 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
417 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
419 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
420 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
422 * However, the actual layout of multisampled data in memory is:
424 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
425 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
427 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
428 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
430 * This pattern repeats for each 2x2 pixel block.
432 * As a result, when calculating the size of our 4-sample buffer for
433 * an odd width or height, we have to align before scaling up because
434 * sample 3 is in that bottom right 2x2 block.
436 switch (num_samples
) {
438 assert(brw
->gen
>= 8);
439 width0
= ALIGN(width0
, 2) * 2;
440 height0
= ALIGN(height0
, 2);
443 width0
= ALIGN(width0
, 2) * 2;
444 height0
= ALIGN(height0
, 2) * 2;
447 width0
= ALIGN(width0
, 2) * 4;
448 height0
= ALIGN(height0
, 2) * 2;
451 width0
= ALIGN(width0
, 2) * 4;
452 height0
= ALIGN(height0
, 2) * 4;
455 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
458 unreachable("not reached");
461 /* Non-interleaved */
462 depth0
*= num_samples
;
466 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
467 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
468 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
469 * used on Gen8 to make it pick a qpitch value which doesn't include space
470 * for the mipmaps. On Gen9 this is not necessary because it will
471 * automatically pick a packed qpitch value whenever mt->first_level ==
473 * TODO: can we use it elsewhere?
474 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
477 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
479 switch (mt
->msaa_layout
) {
480 case INTEL_MSAA_LAYOUT_NONE
:
481 case INTEL_MSAA_LAYOUT_IMS
:
482 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
484 case INTEL_MSAA_LAYOUT_UMS
:
485 case INTEL_MSAA_LAYOUT_CMS
:
486 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
491 if (target
== GL_TEXTURE_CUBE_MAP
) {
496 mt
->physical_width0
= width0
;
497 mt
->physical_height0
= height0
;
498 mt
->physical_depth0
= depth0
;
500 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
501 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
502 (brw
->must_use_separate_stencil
||
503 (brw
->has_separate_stencil
&&
504 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
505 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
507 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
508 MIPTREE_LAYOUT_TILING_ANY
;
511 mt
->stencil_mt
= intel_miptree_create(brw
,
522 if (!mt
->stencil_mt
) {
523 intel_miptree_release(&mt
);
527 /* Fix up the Z miptree format for how we're splitting out separate
528 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
530 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
533 if (format
== mt
->format
) {
534 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
535 _mesa_get_format_name(mt
->format
));
539 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
540 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
543 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
544 * multisampled or have an AUX buffer attached to it.
546 * GEN | MSRT | AUX_CCS_* or AUX_MCS
547 * -------------------------------------------
548 * 9 | HALIGN_16 | HALIGN_16
549 * 8 | HALIGN_ANY | HALIGN_16
553 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
554 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
555 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
556 } else if (brw
->gen
>= 9 && num_samples
> 1) {
557 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
559 /* For now, nothing else has this requirement */
560 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
563 brw_miptree_layout(brw
, mt
, layout_flags
);
565 if (mt
->disable_aux_buffers
)
566 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
573 * Choose an appropriate uncompressed format for a requested
574 * compressed format, if unsupported.
577 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
579 /* No need to lower ETC formats on these platforms,
580 * they are supported natively.
582 if (brw
->gen
>= 8 || brw
->is_baytrail
)
586 case MESA_FORMAT_ETC1_RGB8
:
587 return MESA_FORMAT_R8G8B8X8_UNORM
;
588 case MESA_FORMAT_ETC2_RGB8
:
589 return MESA_FORMAT_R8G8B8X8_UNORM
;
590 case MESA_FORMAT_ETC2_SRGB8
:
591 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
592 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
593 return MESA_FORMAT_B8G8R8A8_SRGB
;
594 case MESA_FORMAT_ETC2_RGBA8_EAC
:
595 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
596 return MESA_FORMAT_R8G8B8A8_UNORM
;
597 case MESA_FORMAT_ETC2_R11_EAC
:
598 return MESA_FORMAT_R_UNORM16
;
599 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
600 return MESA_FORMAT_R_SNORM16
;
601 case MESA_FORMAT_ETC2_RG11_EAC
:
602 return MESA_FORMAT_R16G16_UNORM
;
603 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
604 return MESA_FORMAT_R16G16_SNORM
;
606 /* Non ETC1 / ETC2 format */
611 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
613 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
614 unsigned long *pitch
)
616 uint32_t tile_width
, tile_height
;
617 unsigned long stride
, size
, aligned_y
;
619 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
620 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
621 &tile_width
, &tile_height
);
623 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
624 stride
= mt
->total_width
* mt
->cpp
;
625 stride
= ALIGN(stride
, tile_width
);
626 size
= stride
* aligned_y
;
628 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
629 assert(size
% 4096 == 0);
632 assert(size
% (64 * 1024) == 0);
633 *alignment
= 64 * 1024;
639 static struct intel_mipmap_tree
*
640 miptree_create(struct brw_context
*brw
,
649 uint32_t layout_flags
)
651 struct intel_mipmap_tree
*mt
;
652 mesa_format tex_format
= format
;
653 mesa_format etc_format
= MESA_FORMAT_NONE
;
654 uint32_t alloc_flags
= 0;
656 format
= intel_lower_compressed_format(brw
, format
);
658 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
660 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
661 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
662 mt
= intel_miptree_create_layout(brw
, target
, format
,
663 first_level
, last_level
, width0
,
664 height0
, depth0
, num_samples
,
667 * pitch == 0 || height == 0 indicates the null texture
669 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
670 intel_miptree_release(&mt
);
674 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
675 mt
->tiling
= I915_TILING_Y
;
677 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
678 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
681 mt
->etc_format
= etc_format
;
683 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
684 unsigned alignment
= 0;
686 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
688 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
691 if (format
== MESA_FORMAT_S_UINT8
) {
692 /* Align to size of W tile, 64x64. */
693 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
694 ALIGN(mt
->total_width
, 64),
695 ALIGN(mt
->total_height
, 64),
696 mt
->cpp
, &mt
->tiling
, &pitch
,
699 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
700 mt
->total_width
, mt
->total_height
,
701 mt
->cpp
, &mt
->tiling
, &pitch
,
711 struct intel_mipmap_tree
*
712 intel_miptree_create(struct brw_context
*brw
,
721 uint32_t layout_flags
)
723 struct intel_mipmap_tree
*mt
= miptree_create(
725 first_level
, last_level
,
726 width0
, height0
, depth0
, num_samples
,
729 /* If the BO is too large to fit in the aperture, we need to use the
730 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
731 * handle Y-tiling, so we need to fall back to X.
733 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
734 mt
->tiling
== I915_TILING_Y
) {
735 unsigned long pitch
= mt
->pitch
;
736 const uint32_t alloc_flags
=
737 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
738 BO_ALLOC_FOR_RENDER
: 0;
739 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
740 mt
->total_width
, mt
->total_height
);
742 mt
->tiling
= I915_TILING_X
;
743 drm_intel_bo_unreference(mt
->bo
);
744 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
745 mt
->total_width
, mt
->total_height
, mt
->cpp
,
746 &mt
->tiling
, &pitch
, alloc_flags
);
753 intel_miptree_release(&mt
);
758 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
759 assert(mt
->num_samples
> 1);
760 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
761 intel_miptree_release(&mt
);
766 /* If this miptree is capable of supporting fast color clears, set
767 * fast_clear_state appropriately to ensure that fast clears will occur.
768 * Allocation of the MCS miptree will be deferred until the first fast
769 * clear actually occurs.
771 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
772 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
773 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
774 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
780 struct intel_mipmap_tree
*
781 intel_miptree_create_for_bo(struct brw_context
*brw
,
789 uint32_t layout_flags
)
791 struct intel_mipmap_tree
*mt
;
792 uint32_t tiling
, swizzle
;
795 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
797 /* Nothing will be able to use this miptree with the BO if the offset isn't
800 if (tiling
!= I915_TILING_NONE
)
801 assert(offset
% 4096 == 0);
803 /* miptrees can't handle negative pitch. If you need flipping of images,
804 * that's outside of the scope of the mt.
808 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
810 /* The BO already has a tiling format and we shouldn't confuse the lower
811 * layers by making it try to find a tiling format again.
813 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
814 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
816 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
817 mt
= intel_miptree_create_layout(brw
, target
, format
,
819 width
, height
, depth
, 0,
824 drm_intel_bo_reference(bo
);
834 * For a singlesample renderbuffer, this simply wraps the given BO with a
837 * For a multisample renderbuffer, this wraps the window system's
838 * (singlesample) BO with a singlesample miptree attached to the
839 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
840 * that will contain the actual rendering (which is lazily resolved to
841 * irb->singlesample_mt).
844 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
845 struct intel_renderbuffer
*irb
,
847 uint32_t width
, uint32_t height
,
850 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
851 struct intel_mipmap_tree
*multisample_mt
= NULL
;
852 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
853 mesa_format format
= rb
->Format
;
854 int num_samples
= rb
->NumSamples
;
856 /* Only the front and back buffers, which are color buffers, are allocated
857 * through the image loader.
859 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
860 _mesa_get_format_base_format(format
) == GL_RGBA
);
862 singlesample_mt
= intel_miptree_create_for_bo(intel
,
871 if (!singlesample_mt
)
874 /* If this miptree is capable of supporting fast color clears, set
875 * mcs_state appropriately to ensure that fast clears will occur.
876 * Allocation of the MCS miptree will be deferred until the first fast
877 * clear actually occurs.
879 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
880 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
881 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
884 if (num_samples
== 0) {
885 intel_miptree_release(&irb
->mt
);
886 irb
->mt
= singlesample_mt
;
888 assert(!irb
->singlesample_mt
);
890 intel_miptree_release(&irb
->singlesample_mt
);
891 irb
->singlesample_mt
= singlesample_mt
;
894 irb
->mt
->logical_width0
!= width
||
895 irb
->mt
->logical_height0
!= height
) {
896 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
904 irb
->need_downsample
= false;
905 intel_miptree_release(&irb
->mt
);
906 irb
->mt
= multisample_mt
;
912 intel_miptree_release(&irb
->singlesample_mt
);
913 intel_miptree_release(&irb
->mt
);
917 struct intel_mipmap_tree
*
918 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
922 uint32_t num_samples
)
924 struct intel_mipmap_tree
*mt
;
927 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
928 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
929 MIPTREE_LAYOUT_TILING_ANY
;
932 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
933 width
, height
, depth
, num_samples
,
938 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
939 ok
= intel_miptree_alloc_hiz(brw
, mt
);
947 intel_miptree_release(&mt
);
952 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
953 struct intel_mipmap_tree
*src
)
958 intel_miptree_release(dst
);
962 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
970 intel_miptree_release(struct intel_mipmap_tree
**mt
)
975 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
976 if (--(*mt
)->refcount
<= 0) {
979 DBG("%s deleting %p\n", __func__
, *mt
);
981 drm_intel_bo_unreference((*mt
)->bo
);
982 intel_miptree_release(&(*mt
)->stencil_mt
);
983 if ((*mt
)->hiz_buf
) {
984 if ((*mt
)->hiz_buf
->mt
)
985 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
987 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
988 free((*mt
)->hiz_buf
);
990 intel_miptree_release(&(*mt
)->mcs_mt
);
991 intel_resolve_map_clear(&(*mt
)->hiz_map
);
993 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
994 free((*mt
)->level
[i
].slice
);
1004 intel_get_image_dims(struct gl_texture_image
*image
,
1005 int *width
, int *height
, int *depth
)
1007 switch (image
->TexObject
->Target
) {
1008 case GL_TEXTURE_1D_ARRAY
:
1009 /* For a 1D Array texture the OpenGL API will treat the image height as
1010 * the number of array slices. For Intel hardware, we treat the 1D array
1011 * as a 2D Array with a height of 1. So, here we want to swap image
1014 *width
= image
->Width
;
1016 *depth
= image
->Height
;
1019 *width
= image
->Width
;
1020 *height
= image
->Height
;
1021 *depth
= image
->Depth
;
1027 * Can the image be pulled into a unified mipmap tree? This mirrors
1028 * the completeness test in a lot of ways.
1030 * Not sure whether I want to pass gl_texture_image here.
1033 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1034 struct gl_texture_image
*image
)
1036 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1037 GLuint level
= intelImage
->base
.Base
.Level
;
1038 int width
, height
, depth
;
1040 /* glTexImage* choose the texture object based on the target passed in, and
1041 * objects can't change targets over their lifetimes, so this should be
1044 assert(image
->TexObject
->Target
== mt
->target
);
1046 mesa_format mt_format
= mt
->format
;
1047 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1048 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1049 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1050 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1051 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1052 mt_format
= mt
->etc_format
;
1054 if (image
->TexFormat
!= mt_format
)
1057 intel_get_image_dims(image
, &width
, &height
, &depth
);
1059 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1062 int level_depth
= mt
->level
[level
].depth
;
1063 if (mt
->num_samples
> 1) {
1064 switch (mt
->msaa_layout
) {
1065 case INTEL_MSAA_LAYOUT_NONE
:
1066 case INTEL_MSAA_LAYOUT_IMS
:
1068 case INTEL_MSAA_LAYOUT_UMS
:
1069 case INTEL_MSAA_LAYOUT_CMS
:
1070 level_depth
/= mt
->num_samples
;
1075 /* Test image dimensions against the base level image adjusted for
1076 * minification. This will also catch images not present in the
1077 * tree, changed targets, etc.
1079 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1080 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1081 depth
!= level_depth
) {
1085 if (image
->NumSamples
!= mt
->num_samples
)
1093 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1095 GLuint x
, GLuint y
, GLuint d
)
1097 mt
->level
[level
].depth
= d
;
1098 mt
->level
[level
].level_x
= x
;
1099 mt
->level
[level
].level_y
= y
;
1101 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1104 assert(mt
->level
[level
].slice
== NULL
);
1106 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1107 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1108 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1113 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1114 GLuint level
, GLuint img
,
1117 if (img
== 0 && level
== 0)
1118 assert(x
== 0 && y
== 0);
1120 assert(img
< mt
->level
[level
].depth
);
1122 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1123 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1125 DBG("%s level %d img %d pos %d,%d\n",
1126 __func__
, level
, img
,
1127 mt
->level
[level
].slice
[img
].x_offset
,
1128 mt
->level
[level
].slice
[img
].y_offset
);
1132 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1133 GLuint level
, GLuint slice
,
1134 GLuint
*x
, GLuint
*y
)
1136 assert(slice
< mt
->level
[level
].depth
);
1138 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1139 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1144 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1145 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1146 * and tile_h is set to 1.
1149 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1150 uint32_t *tile_w
, uint32_t *tile_h
)
1152 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1162 case I915_TILING_NONE
:
1167 unreachable("not reached");
1170 uint32_t aspect_ratio
= 1;
1171 assert(_mesa_is_pow_two(cpp
));
1186 unreachable("not reached");
1189 if (cpp
== 2 || cpp
== 8)
1192 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1195 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1201 * This function computes masks that may be used to select the bits of the X
1202 * and Y coordinates that indicate the offset within a tile. If the BO is
1203 * untiled, the masks are set to 0.
1206 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1207 bool map_stencil_as_y_tiled
,
1208 uint32_t *mask_x
, uint32_t *mask_y
)
1210 uint32_t tile_w_bytes
, tile_h
;
1211 if (map_stencil_as_y_tiled
)
1212 tiling
= I915_TILING_Y
;
1214 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1216 *mask_x
= tile_w_bytes
/ cpp
- 1;
1217 *mask_y
= tile_h
- 1;
1221 * Compute the offset (in bytes) from the start of the BO to the given x
1222 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1223 * multiples of the tile size.
1226 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1227 uint32_t x
, uint32_t y
,
1228 bool map_stencil_as_y_tiled
)
1231 uint32_t pitch
= mt
->pitch
;
1232 uint32_t tiling
= mt
->tiling
;
1234 if (map_stencil_as_y_tiled
) {
1235 tiling
= I915_TILING_Y
;
1237 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1238 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1239 * the resulting surface is twice the pitch of the original miptree,
1240 * since each row in the Y-tiled view corresponds to two rows in the
1241 * actual W-tiled surface. So we need to correct the pitch before
1242 * computing the offsets.
1249 unreachable("not reached");
1250 case I915_TILING_NONE
:
1251 return y
* pitch
+ x
* cpp
;
1253 assert((x
% (512 / cpp
)) == 0);
1254 assert((y
% 8) == 0);
1255 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1257 assert((x
% (128 / cpp
)) == 0);
1258 assert((y
% 32) == 0);
1259 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1264 * Rendering with tiled buffers requires that the base address of the buffer
1265 * be aligned to a page boundary. For renderbuffers, and sometimes with
1266 * textures, we may want the surface to point at a texture image level that
1267 * isn't at a page boundary.
1269 * This function returns an appropriately-aligned base offset
1270 * according to the tiling restrictions, plus any required x/y offset
1274 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1275 GLuint level
, GLuint slice
,
1280 uint32_t mask_x
, mask_y
;
1282 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1283 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1285 *tile_x
= x
& mask_x
;
1286 *tile_y
= y
& mask_y
;
1288 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1292 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1293 struct intel_mipmap_tree
*dst_mt
,
1294 struct intel_mipmap_tree
*src_mt
,
1301 ptrdiff_t src_stride
, dst_stride
;
1302 int cpp
= dst_mt
->cpp
;
1304 intel_miptree_map(brw
, src_mt
,
1308 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1311 intel_miptree_map(brw
, dst_mt
,
1315 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1319 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1320 _mesa_get_format_name(src_mt
->format
),
1321 src_mt
, src
, src_stride
,
1322 _mesa_get_format_name(dst_mt
->format
),
1323 dst_mt
, dst
, dst_stride
,
1326 int row_size
= cpp
* width
;
1327 if (src_stride
== row_size
&&
1328 dst_stride
== row_size
) {
1329 memcpy(dst
, src
, row_size
* height
);
1331 for (int i
= 0; i
< height
; i
++) {
1332 memcpy(dst
, src
, row_size
);
1338 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1339 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1341 /* Don't forget to copy the stencil data over, too. We could have skipped
1342 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1343 * shuffling the two data sources in/out of temporary storage instead of
1344 * the direct mapping we get this way.
1346 if (dst_mt
->stencil_mt
) {
1347 assert(src_mt
->stencil_mt
);
1348 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1349 level
, slice
, width
, height
);
1354 intel_miptree_copy_slice(struct brw_context
*brw
,
1355 struct intel_mipmap_tree
*dst_mt
,
1356 struct intel_mipmap_tree
*src_mt
,
1362 mesa_format format
= src_mt
->format
;
1363 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1364 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1372 assert(depth
< src_mt
->level
[level
].depth
);
1373 assert(src_mt
->format
== dst_mt
->format
);
1375 if (dst_mt
->compressed
) {
1377 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1378 height
= ALIGN_NPOT(height
, j
) / j
;
1379 width
= ALIGN_NPOT(width
, i
) / i
;
1382 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1383 * below won't apply since we can't do the depth's Y tiling or the
1384 * stencil's W tiling in the blitter.
1386 if (src_mt
->stencil_mt
) {
1387 intel_miptree_copy_slice_sw(brw
,
1394 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1395 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1396 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1398 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1399 _mesa_get_format_name(src_mt
->format
),
1400 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1401 _mesa_get_format_name(dst_mt
->format
),
1402 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1405 if (!intel_miptree_blit(brw
,
1406 src_mt
, level
, slice
, 0, 0, false,
1407 dst_mt
, level
, slice
, 0, 0, false,
1408 width
, height
, GL_COPY
)) {
1409 perf_debug("miptree validate blit for %s failed\n",
1410 _mesa_get_format_name(format
));
1412 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1418 * Copies the image's current data to the given miptree, and associates that
1419 * miptree with the image.
1421 * If \c invalidate is true, then the actual image data does not need to be
1422 * copied, but the image still needs to be associated to the new miptree (this
1423 * is set to true if we're about to clear the image).
1426 intel_miptree_copy_teximage(struct brw_context
*brw
,
1427 struct intel_texture_image
*intelImage
,
1428 struct intel_mipmap_tree
*dst_mt
,
1431 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1432 struct intel_texture_object
*intel_obj
=
1433 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1434 int level
= intelImage
->base
.Base
.Level
;
1435 int face
= intelImage
->base
.Base
.Face
;
1438 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1439 depth
= intelImage
->base
.Base
.Height
;
1441 depth
= intelImage
->base
.Base
.Depth
;
1444 for (int slice
= 0; slice
< depth
; slice
++) {
1445 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1449 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1450 intel_obj
->needs_validate
= true;
1454 intel_miptree_init_mcs(struct brw_context
*brw
,
1455 struct intel_mipmap_tree
*mt
,
1458 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1460 * When MCS buffer is enabled and bound to MSRT, it is required that it
1461 * is cleared prior to any rendering.
1463 * Since we don't use the MCS buffer for any purpose other than rendering,
1464 * it makes sense to just clear it immediately upon allocation.
1466 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1468 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1469 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1470 intel_miptree_unmap_raw(mt
->mcs_mt
);
1471 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1475 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1476 struct intel_mipmap_tree
*mt
,
1479 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1480 assert(mt
->mcs_mt
== NULL
);
1481 assert(!mt
->disable_aux_buffers
);
1483 /* Choose the correct format for the MCS buffer. All that really matters
1484 * is that we allocate the right buffer size, since we'll always be
1485 * accessing this miptree using MCS-specific hardware mechanisms, which
1486 * infer the correct format based on num_samples.
1489 switch (num_samples
) {
1492 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1495 format
= MESA_FORMAT_R_UNORM8
;
1498 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1499 * for each sample, plus 8 padding bits).
1501 format
= MESA_FORMAT_R_UINT32
;
1504 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1507 format
= MESA_FORMAT_RG_UINT32
;
1510 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1513 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1515 * "The MCS surface must be stored as Tile Y."
1517 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1518 MIPTREE_LAYOUT_TILING_Y
;
1519 mt
->mcs_mt
= miptree_create(brw
,
1525 mt
->logical_height0
,
1527 0 /* num_samples */,
1530 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1537 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1538 struct intel_mipmap_tree
*mt
)
1540 assert(mt
->mcs_mt
== NULL
);
1541 assert(!mt
->disable_aux_buffers
);
1543 /* The format of the MCS buffer is opaque to the driver; all that matters
1544 * is that we get its size and pitch right. We'll pretend that the format
1545 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1546 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1547 * the block width and then a further factor of 4. Since an MCS tile
1548 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1549 * we'll need to scale the height down by the block height and then a
1550 * further factor of 8.
1552 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1553 unsigned block_width_px
;
1554 unsigned block_height
;
1555 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1556 unsigned width_divisor
= block_width_px
* 4;
1557 unsigned height_divisor
= block_height
* 8;
1559 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1561 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1562 * in the main surface. In Skylake, it's two bits. The extra bit
1563 * doubles the MCS height, not width, because in Skylake the MCS is always
1567 height_divisor
/= 2;
1569 unsigned mcs_width
=
1570 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1571 unsigned mcs_height
=
1572 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1573 assert(mt
->logical_depth0
== 1);
1574 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1575 MIPTREE_LAYOUT_TILING_Y
;
1576 if (brw
->gen
>= 8) {
1577 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1579 mt
->mcs_mt
= miptree_create(brw
,
1587 0 /* num_samples */,
1595 * Helper for intel_miptree_alloc_hiz() that sets
1596 * \c mt->level[level].has_hiz. Return true if and only if
1597 * \c has_hiz was set.
1600 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1601 struct intel_mipmap_tree
*mt
,
1604 assert(mt
->hiz_buf
);
1606 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1607 uint32_t width
= minify(mt
->physical_width0
, level
);
1608 uint32_t height
= minify(mt
->physical_height0
, level
);
1610 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1611 * and the height is 4 aligned. This allows our HiZ support
1612 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1613 * we can grow the width & height to allow the HiZ op to
1614 * force the proper size alignments.
1616 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1617 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1622 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1623 mt
->level
[level
].has_hiz
= true;
1629 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1630 * buffer dimensions and allocates a bo for the hiz buffer.
1632 static struct intel_miptree_aux_buffer
*
1633 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1634 struct intel_mipmap_tree
*mt
)
1636 unsigned z_width
= mt
->logical_width0
;
1637 unsigned z_height
= mt
->logical_height0
;
1638 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1639 unsigned hz_width
, hz_height
;
1640 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1645 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1646 * adjustments required for Z_Height and Z_Width based on multisampling.
1648 switch (mt
->num_samples
) {
1662 unreachable("unsupported sample count");
1665 const unsigned vertical_align
= 8; /* 'j' in the docs */
1666 const unsigned H0
= z_height
;
1667 const unsigned h0
= ALIGN(H0
, vertical_align
);
1668 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1669 const unsigned Z0
= z_depth
;
1671 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1672 hz_width
= ALIGN(z_width
, 16);
1674 if (mt
->target
== GL_TEXTURE_3D
) {
1678 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1679 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1680 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1681 hz_height
+= h_i
* Z_i
;
1682 H_i
= minify(H_i
, 1);
1683 Z_i
= minify(Z_i
, 1);
1686 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1688 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1690 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1691 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1692 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1693 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1694 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1696 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1697 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1701 unsigned long pitch
;
1702 uint32_t tiling
= I915_TILING_Y
;
1703 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1704 hz_width
, hz_height
, 1,
1706 BO_ALLOC_FOR_RENDER
);
1710 } else if (tiling
!= I915_TILING_Y
) {
1711 drm_intel_bo_unreference(buf
->bo
);
1723 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1724 * buffer dimensions and allocates a bo for the hiz buffer.
1726 static struct intel_miptree_aux_buffer
*
1727 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1728 struct intel_mipmap_tree
*mt
)
1730 unsigned z_width
= mt
->logical_width0
;
1731 unsigned z_height
= mt
->logical_height0
;
1732 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1733 unsigned hz_width
, hz_height
;
1734 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1739 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1740 * adjustments required for Z_Height and Z_Width based on multisampling.
1743 switch (mt
->num_samples
) {
1757 unreachable("unsupported sample count");
1761 const unsigned vertical_align
= 8; /* 'j' in the docs */
1762 const unsigned H0
= z_height
;
1763 const unsigned h0
= ALIGN(H0
, vertical_align
);
1764 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1765 const unsigned Z0
= z_depth
;
1767 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1768 hz_width
= ALIGN(z_width
, 16);
1772 unsigned sum_h_i
= 0;
1773 unsigned hz_height_3d_sum
= 0;
1774 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1775 unsigned i
= level
- mt
->first_level
;
1776 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1777 /* sum(i=2 to m; h_i) */
1781 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1782 hz_height_3d_sum
+= h_i
* Z_i
;
1783 H_i
= minify(H_i
, 1);
1784 Z_i
= minify(Z_i
, 1);
1786 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1787 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1789 if (mt
->target
== GL_TEXTURE_3D
) {
1790 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1791 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1793 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1794 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1795 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1796 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1797 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1799 * We can can just take our hz_height calculation from above, and
1800 * multiply by 6 for the cube map and cube map array types.
1806 unsigned long pitch
;
1807 uint32_t tiling
= I915_TILING_Y
;
1808 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1809 hz_width
, hz_height
, 1,
1811 BO_ALLOC_FOR_RENDER
);
1815 } else if (tiling
!= I915_TILING_Y
) {
1816 drm_intel_bo_unreference(buf
->bo
);
1827 static struct intel_miptree_aux_buffer
*
1828 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1829 struct intel_mipmap_tree
*mt
)
1831 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1832 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1835 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1840 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1841 buf
->mt
= intel_miptree_create(brw
,
1847 mt
->logical_height0
,
1856 buf
->bo
= buf
->mt
->bo
;
1857 buf
->pitch
= buf
->mt
->pitch
;
1858 buf
->qpitch
= buf
->mt
->qpitch
;
1864 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1865 struct intel_mipmap_tree
*mt
)
1870 if (mt
->hiz_buf
!= NULL
)
1873 if (mt
->disable_aux_buffers
)
1876 switch (mt
->format
) {
1877 case MESA_FORMAT_Z_FLOAT32
:
1878 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1879 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1880 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1881 case MESA_FORMAT_Z_UNORM16
:
1889 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1890 struct intel_mipmap_tree
*mt
)
1892 assert(mt
->hiz_buf
== NULL
);
1893 assert(!mt
->disable_aux_buffers
);
1895 if (brw
->gen
== 7) {
1896 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1897 } else if (brw
->gen
>= 8) {
1898 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1900 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1906 /* Mark that all slices need a HiZ resolve. */
1907 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1908 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1911 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1912 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1913 exec_node_init(&m
->link
);
1916 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1918 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1926 * Does the miptree slice have hiz enabled?
1929 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1931 intel_miptree_check_level_layer(mt
, level
, 0);
1932 return mt
->level
[level
].has_hiz
;
1936 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1940 if (!intel_miptree_level_has_hiz(mt
, level
))
1943 intel_resolve_map_set(&mt
->hiz_map
,
1944 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1949 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1953 if (!intel_miptree_level_has_hiz(mt
, level
))
1956 intel_resolve_map_set(&mt
->hiz_map
,
1957 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1961 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1965 uint32_t end_layer
= mt
->level
[level
].depth
;
1967 for (layer
= 0; layer
< end_layer
; layer
++) {
1968 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1973 intel_miptree_slice_resolve(struct brw_context
*brw
,
1974 struct intel_mipmap_tree
*mt
,
1977 enum gen6_hiz_op need
)
1979 intel_miptree_check_level_layer(mt
, level
, layer
);
1981 struct intel_resolve_map
*item
=
1982 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1984 if (!item
|| item
->need
!= need
)
1987 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1988 intel_resolve_map_remove(item
);
1993 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1994 struct intel_mipmap_tree
*mt
,
1998 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1999 GEN6_HIZ_OP_HIZ_RESOLVE
);
2003 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2004 struct intel_mipmap_tree
*mt
,
2008 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2009 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2013 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2014 struct intel_mipmap_tree
*mt
,
2015 enum gen6_hiz_op need
)
2017 bool did_resolve
= false;
2019 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2020 if (map
->need
!= need
)
2023 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2024 intel_resolve_map_remove(map
);
2032 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2033 struct intel_mipmap_tree
*mt
)
2035 return intel_miptree_all_slices_resolve(brw
, mt
,
2036 GEN6_HIZ_OP_HIZ_RESOLVE
);
2040 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2041 struct intel_mipmap_tree
*mt
)
2043 return intel_miptree_all_slices_resolve(brw
, mt
,
2044 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2049 intel_miptree_resolve_color(struct brw_context
*brw
,
2050 struct intel_mipmap_tree
*mt
,
2053 /* From gen9 onwards there is new compression scheme for single sampled
2054 * surfaces called "lossless compressed". These don't need to be always
2057 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2058 intel_miptree_is_lossless_compressed(brw
, mt
))
2061 switch (mt
->fast_clear_state
) {
2062 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2063 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2064 /* No resolve needed */
2066 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2067 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2068 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2069 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2070 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2071 brw_meta_resolve_color(brw
, mt
);
2079 * Make it possible to share the BO backing the given miptree with another
2080 * process or another miptree.
2082 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2083 * then discard the MCS buffer, if present. We also set the fast_clear_state
2084 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2085 * allocated in the future.
2088 intel_miptree_make_shareable(struct brw_context
*brw
,
2089 struct intel_mipmap_tree
*mt
)
2091 /* MCS buffers are also used for multisample buffers, but we can't resolve
2092 * away a multisample MCS buffer because it's an integral part of how the
2093 * pixel data is stored. Fortunately this code path should never be
2094 * reached for multisample buffers.
2096 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2099 intel_miptree_resolve_color(brw
, mt
, 0);
2100 intel_miptree_release(&mt
->mcs_mt
);
2101 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2107 * \brief Get pointer offset into stencil buffer.
2109 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2110 * must decode the tile's layout in software.
2113 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2115 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2117 * Even though the returned offset is always positive, the return type is
2119 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2120 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2123 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2125 uint32_t tile_size
= 4096;
2126 uint32_t tile_width
= 64;
2127 uint32_t tile_height
= 64;
2128 uint32_t row_size
= 64 * stride
;
2130 uint32_t tile_x
= x
/ tile_width
;
2131 uint32_t tile_y
= y
/ tile_height
;
2133 /* The byte's address relative to the tile's base addres. */
2134 uint32_t byte_x
= x
% tile_width
;
2135 uint32_t byte_y
= y
% tile_height
;
2137 uintptr_t u
= tile_y
* row_size
2138 + tile_x
* tile_size
2139 + 512 * (byte_x
/ 8)
2141 + 32 * ((byte_y
/ 4) % 2)
2142 + 16 * ((byte_x
/ 4) % 2)
2143 + 8 * ((byte_y
/ 2) % 2)
2144 + 4 * ((byte_x
/ 2) % 2)
2149 /* adjust for bit6 swizzling */
2150 if (((byte_x
/ 8) % 2) == 1) {
2151 if (((byte_y
/ 8) % 2) == 0) {
2163 intel_miptree_updownsample(struct brw_context
*brw
,
2164 struct intel_mipmap_tree
*src
,
2165 struct intel_mipmap_tree
*dst
)
2167 /* There is support only for four and eight samples. */
2168 const bool use_blorp
= src
->num_samples
!= 2 && dst
->num_samples
!= 2 &&
2169 src
->num_samples
<= 8 && dst
->num_samples
<= 8;
2172 brw_blorp_blit_miptrees(brw
,
2173 src
, 0 /* level */, 0 /* layer */,
2174 src
->format
, SWIZZLE_XYZW
,
2175 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2177 src
->logical_width0
, src
->logical_height0
,
2179 dst
->logical_width0
, dst
->logical_height0
,
2180 GL_NEAREST
, false, false /*mirror x, y*/,
2182 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2183 brw_meta_stencil_updownsample(brw
, src
, dst
);
2185 brw_meta_updownsample(brw
, src
, dst
);
2188 if (src
->stencil_mt
) {
2190 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2194 brw_blorp_blit_miptrees(brw
,
2195 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2196 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2197 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2198 dst
->stencil_mt
->format
,
2200 src
->logical_width0
, src
->logical_height0
,
2202 dst
->logical_width0
, dst
->logical_height0
,
2203 GL_NEAREST
, false, false /*mirror x, y*/,
2204 false, false /* decode/encode srgb */);
2209 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2211 /* CPU accesses to color buffers don't understand fast color clears, so
2212 * resolve any pending fast color clears before we map.
2214 intel_miptree_resolve_color(brw
, mt
, 0);
2216 drm_intel_bo
*bo
= mt
->bo
;
2218 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2219 intel_batchbuffer_flush(brw
);
2221 if (mt
->tiling
!= I915_TILING_NONE
)
2222 brw_bo_map_gtt(brw
, bo
, "miptree");
2224 brw_bo_map(brw
, bo
, true, "miptree");
2230 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2232 drm_intel_bo_unmap(mt
->bo
);
2236 intel_miptree_map_gtt(struct brw_context
*brw
,
2237 struct intel_mipmap_tree
*mt
,
2238 struct intel_miptree_map
*map
,
2239 unsigned int level
, unsigned int slice
)
2241 unsigned int bw
, bh
;
2243 unsigned int image_x
, image_y
;
2244 intptr_t x
= map
->x
;
2245 intptr_t y
= map
->y
;
2247 /* For compressed formats, the stride is the number of bytes per
2248 * row of blocks. intel_miptree_get_image_offset() already does
2251 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2252 assert(y
% bh
== 0);
2253 assert(x
% bw
== 0);
2257 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2262 /* Note that in the case of cube maps, the caller must have passed the
2263 * slice number referencing the face.
2265 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2269 map
->stride
= mt
->pitch
;
2270 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2273 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2274 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2275 map
->x
, map
->y
, map
->w
, map
->h
,
2276 mt
, _mesa_get_format_name(mt
->format
),
2277 x
, y
, map
->ptr
, map
->stride
);
2281 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2283 intel_miptree_unmap_raw(mt
);
2287 intel_miptree_map_blit(struct brw_context
*brw
,
2288 struct intel_mipmap_tree
*mt
,
2289 struct intel_miptree_map
*map
,
2290 unsigned int level
, unsigned int slice
)
2292 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2293 /* first_level */ 0,
2297 MIPTREE_LAYOUT_TILING_NONE
);
2299 if (!map
->linear_mt
) {
2300 fprintf(stderr
, "Failed to allocate blit temporary\n");
2303 map
->stride
= map
->linear_mt
->pitch
;
2305 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2306 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2307 * invalidate is set, since we'll be writing the whole rectangle from our
2308 * temporary buffer back out.
2310 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2311 if (!intel_miptree_blit(brw
,
2313 map
->x
, map
->y
, false,
2314 map
->linear_mt
, 0, 0,
2316 map
->w
, map
->h
, GL_COPY
)) {
2317 fprintf(stderr
, "Failed to blit\n");
2322 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2324 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2325 map
->x
, map
->y
, map
->w
, map
->h
,
2326 mt
, _mesa_get_format_name(mt
->format
),
2327 level
, slice
, map
->ptr
, map
->stride
);
2332 intel_miptree_release(&map
->linear_mt
);
2338 intel_miptree_unmap_blit(struct brw_context
*brw
,
2339 struct intel_mipmap_tree
*mt
,
2340 struct intel_miptree_map
*map
,
2344 struct gl_context
*ctx
= &brw
->ctx
;
2346 intel_miptree_unmap_raw(map
->linear_mt
);
2348 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2349 bool ok
= intel_miptree_blit(brw
,
2350 map
->linear_mt
, 0, 0,
2353 map
->x
, map
->y
, false,
2354 map
->w
, map
->h
, GL_COPY
);
2355 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2358 intel_miptree_release(&map
->linear_mt
);
2362 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2364 #if defined(USE_SSE41)
2366 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2367 struct intel_mipmap_tree
*mt
,
2368 struct intel_miptree_map
*map
,
2369 unsigned int level
, unsigned int slice
)
2371 assert(map
->mode
& GL_MAP_READ_BIT
);
2372 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2374 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2375 map
->x
, map
->y
, map
->w
, map
->h
,
2376 mt
, _mesa_get_format_name(mt
->format
),
2377 level
, slice
, map
->ptr
, map
->stride
);
2379 /* Map the original image */
2382 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2386 void *src
= intel_miptree_map_raw(brw
, mt
);
2389 src
+= image_y
* mt
->pitch
;
2390 src
+= image_x
* mt
->cpp
;
2392 /* Due to the pixel offsets for the particular image being mapped, our
2393 * src pointer may not be 16-byte aligned. However, if the pitch is
2394 * divisible by 16, then the amount by which it's misaligned will remain
2395 * consistent from row to row.
2397 assert((mt
->pitch
% 16) == 0);
2398 const int misalignment
= ((uintptr_t) src
) & 15;
2400 /* Create an untiled temporary buffer for the mapping. */
2401 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2403 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2405 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2406 /* Offset the destination so it has the same misalignment as src. */
2407 map
->ptr
= map
->buffer
+ misalignment
;
2409 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2411 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2412 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2413 void *src_ptr
= src
+ y
* mt
->pitch
;
2415 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2418 intel_miptree_unmap_raw(mt
);
2422 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2423 struct intel_mipmap_tree
*mt
,
2424 struct intel_miptree_map
*map
,
2428 _mesa_align_free(map
->buffer
);
2435 intel_miptree_map_s8(struct brw_context
*brw
,
2436 struct intel_mipmap_tree
*mt
,
2437 struct intel_miptree_map
*map
,
2438 unsigned int level
, unsigned int slice
)
2440 map
->stride
= map
->w
;
2441 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2445 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2446 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2447 * invalidate is set, since we'll be writing the whole rectangle from our
2448 * temporary buffer back out.
2450 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2451 uint8_t *untiled_s8_map
= map
->ptr
;
2452 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2453 unsigned int image_x
, image_y
;
2455 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2457 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2458 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2459 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2460 x
+ image_x
+ map
->x
,
2461 y
+ image_y
+ map
->y
,
2462 brw
->has_swizzling
);
2463 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2467 intel_miptree_unmap_raw(mt
);
2469 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2470 map
->x
, map
->y
, map
->w
, map
->h
,
2471 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2473 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2474 map
->x
, map
->y
, map
->w
, map
->h
,
2475 mt
, map
->ptr
, map
->stride
);
2480 intel_miptree_unmap_s8(struct brw_context
*brw
,
2481 struct intel_mipmap_tree
*mt
,
2482 struct intel_miptree_map
*map
,
2486 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2487 unsigned int image_x
, image_y
;
2488 uint8_t *untiled_s8_map
= map
->ptr
;
2489 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2491 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2493 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2494 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2495 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2498 brw
->has_swizzling
);
2499 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2503 intel_miptree_unmap_raw(mt
);
2510 intel_miptree_map_etc(struct brw_context
*brw
,
2511 struct intel_mipmap_tree
*mt
,
2512 struct intel_miptree_map
*map
,
2516 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2517 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2518 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2521 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2522 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2524 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2525 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2526 map
->w
, map
->h
, 1));
2527 map
->ptr
= map
->buffer
;
2531 intel_miptree_unmap_etc(struct brw_context
*brw
,
2532 struct intel_mipmap_tree
*mt
,
2533 struct intel_miptree_map
*map
,
2539 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2544 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2545 + image_y
* mt
->pitch
2546 + image_x
* mt
->cpp
;
2548 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2549 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2550 map
->ptr
, map
->stride
,
2553 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2554 map
->ptr
, map
->stride
,
2555 map
->w
, map
->h
, mt
->etc_format
);
2557 intel_miptree_unmap_raw(mt
);
2562 * Mapping function for packed depth/stencil miptrees backed by real separate
2563 * miptrees for depth and stencil.
2565 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2566 * separate from the depth buffer. Yet at the GL API level, we have to expose
2567 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2568 * be able to map that memory for texture storage and glReadPixels-type
2569 * operations. We give Mesa core that access by mallocing a temporary and
2570 * copying the data between the actual backing store and the temporary.
2573 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2574 struct intel_mipmap_tree
*mt
,
2575 struct intel_miptree_map
*map
,
2576 unsigned int level
, unsigned int slice
)
2578 struct intel_mipmap_tree
*z_mt
= mt
;
2579 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2580 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2581 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2583 map
->stride
= map
->w
* packed_bpp
;
2584 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2588 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2589 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2590 * invalidate is set, since we'll be writing the whole rectangle from our
2591 * temporary buffer back out.
2593 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2594 uint32_t *packed_map
= map
->ptr
;
2595 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2596 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2597 unsigned int s_image_x
, s_image_y
;
2598 unsigned int z_image_x
, z_image_y
;
2600 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2601 &s_image_x
, &s_image_y
);
2602 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2603 &z_image_x
, &z_image_y
);
2605 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2606 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2607 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2608 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2611 brw
->has_swizzling
);
2612 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2614 (map_x
+ z_image_x
));
2615 uint8_t s
= s_map
[s_offset
];
2616 uint32_t z
= z_map
[z_offset
];
2618 if (map_z32f_x24s8
) {
2619 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2620 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2622 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2627 intel_miptree_unmap_raw(s_mt
);
2628 intel_miptree_unmap_raw(z_mt
);
2630 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2632 map
->x
, map
->y
, map
->w
, map
->h
,
2633 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2634 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2635 map
->ptr
, map
->stride
);
2637 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2638 map
->x
, map
->y
, map
->w
, map
->h
,
2639 mt
, map
->ptr
, map
->stride
);
2644 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2645 struct intel_mipmap_tree
*mt
,
2646 struct intel_miptree_map
*map
,
2650 struct intel_mipmap_tree
*z_mt
= mt
;
2651 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2652 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2654 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2655 uint32_t *packed_map
= map
->ptr
;
2656 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2657 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2658 unsigned int s_image_x
, s_image_y
;
2659 unsigned int z_image_x
, z_image_y
;
2661 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2662 &s_image_x
, &s_image_y
);
2663 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2664 &z_image_x
, &z_image_y
);
2666 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2667 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2668 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2669 x
+ s_image_x
+ map
->x
,
2670 y
+ s_image_y
+ map
->y
,
2671 brw
->has_swizzling
);
2672 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2674 (x
+ z_image_x
+ map
->x
));
2676 if (map_z32f_x24s8
) {
2677 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2678 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2680 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2681 s_map
[s_offset
] = packed
>> 24;
2682 z_map
[z_offset
] = packed
;
2687 intel_miptree_unmap_raw(s_mt
);
2688 intel_miptree_unmap_raw(z_mt
);
2690 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2692 map
->x
, map
->y
, map
->w
, map
->h
,
2693 z_mt
, _mesa_get_format_name(z_mt
->format
),
2694 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2695 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2696 map
->ptr
, map
->stride
);
2703 * Create and attach a map to the miptree at (level, slice). Return the
2706 static struct intel_miptree_map
*
2707 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2716 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2721 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2722 mt
->level
[level
].slice
[slice
].map
= map
;
2734 * Release the map at (level, slice).
2737 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2741 struct intel_miptree_map
**map
;
2743 map
= &mt
->level
[level
].slice
[slice
].map
;
2749 can_blit_slice(struct intel_mipmap_tree
*mt
,
2750 unsigned int level
, unsigned int slice
)
2754 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2755 if (image_x
>= 32768 || image_y
>= 32768)
2758 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2759 if (mt
->pitch
>= 32768)
2766 use_intel_mipree_map_blit(struct brw_context
*brw
,
2767 struct intel_mipmap_tree
*mt
,
2773 /* It's probably not worth swapping to the blit ring because of
2774 * all the overhead involved. But, we must use blitter for the
2775 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2777 (!(mode
& GL_MAP_WRITE_BIT
) ||
2778 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2780 (mt
->tiling
== I915_TILING_X
||
2781 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2782 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2783 /* Fast copy blit on skl+ supports all tiling formats. */
2785 can_blit_slice(mt
, level
, slice
))
2788 if (mt
->tiling
!= I915_TILING_NONE
&&
2789 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2790 assert(can_blit_slice(mt
, level
, slice
));
2798 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2799 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2800 * arithmetic overflow.
2802 * If you call this function and use \a out_stride, then you're doing pointer
2803 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2804 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2805 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2806 * which usually have type uint32_t or GLuint.
2809 intel_miptree_map(struct brw_context
*brw
,
2810 struct intel_mipmap_tree
*mt
,
2819 ptrdiff_t *out_stride
)
2821 struct intel_miptree_map
*map
;
2823 assert(mt
->num_samples
<= 1);
2825 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2832 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2833 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2834 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2837 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2838 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2839 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2840 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2841 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2842 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2843 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2844 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2845 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2846 #if defined(USE_SSE41)
2847 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2848 !mt
->compressed
&& cpu_has_sse4_1
&&
2849 (mt
->pitch
% 16 == 0)) {
2850 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2853 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2854 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2855 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2858 *out_ptr
= map
->ptr
;
2859 *out_stride
= map
->stride
;
2861 if (map
->ptr
== NULL
)
2862 intel_miptree_release_map(mt
, level
, slice
);
2866 intel_miptree_unmap(struct brw_context
*brw
,
2867 struct intel_mipmap_tree
*mt
,
2871 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2873 assert(mt
->num_samples
<= 1);
2878 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2879 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2881 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2882 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2883 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2884 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2885 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2886 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2887 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2888 } else if (map
->linear_mt
) {
2889 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2890 #if defined(USE_SSE41)
2891 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2892 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2895 intel_miptree_unmap_gtt(mt
);
2898 intel_miptree_release_map(mt
, level
, slice
);