2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
,
125 enum isl_tiling tiling
)
127 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
128 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
130 * - Support is limited to tiled render targets.
132 * Gen9 changes the restriction to Y-tile only.
135 return tiling
== ISL_TILING_Y0
;
136 else if (brw
->gen
>= 7)
137 return tiling
!= ISL_TILING_LINEAR
;
143 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
144 * can be used. This doesn't (and should not) inspect any of the properties of
147 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
148 * beneath the "Fast Color Clear" bullet (p326):
150 * - Support is for non-mip-mapped and non-array surface types only.
152 * And then later, on p327:
154 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
157 * From the Skylake documentation, it is made clear that X-tiling is no longer
160 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
164 intel_miptree_supports_ccs(struct brw_context
*brw
,
165 const struct intel_mipmap_tree
*mt
)
167 /* MCS support does not exist prior to Gen7 */
171 /* This function applies only to non-multisampled render targets. */
172 if (mt
->surf
.samples
> 1)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
186 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
187 const bool arrayed
= mt
->physical_depth0
!= 1;
190 /* Multisample surfaces with the CMS layout are not layered surfaces,
191 * yet still have physical_depth0 > 1. Assert that we don't
192 * accidentally reject a multisampled surface here. We should have
193 * rejected it earlier by explicitly checking the sample count.
195 assert(mt
->surf
.samples
== 1);
198 /* Handle the hardware restrictions...
200 * All GENs have the following restriction: "MCS buffer for non-MSRT is
201 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
203 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
204 * Non-MultiSampler Render Target Restrictions) Support is for
205 * non-mip-mapped and non-array surface types only.
207 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
208 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
209 * surfaces are supported with MCS buffer layout with these alignments in
210 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
212 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
213 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
214 * surfaces are supported with MCS buffer layout with these alignments in
215 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
217 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
220 /* There's no point in using an MCS buffer if the surface isn't in a
223 if (!brw
->mesa_format_supports_render
[mt
->format
])
227 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
228 const enum isl_format isl_format
=
229 brw_isl_format_for_mesa_format(linear_format
);
230 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
236 intel_tiling_supports_hiz(const struct brw_context
*brw
,
237 enum isl_tiling tiling
)
242 return tiling
== ISL_TILING_Y0
;
246 intel_miptree_supports_hiz(const struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
252 switch (mt
->format
) {
253 case MESA_FORMAT_Z_FLOAT32
:
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
256 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
257 case MESA_FORMAT_Z_UNORM16
:
265 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
266 const struct intel_mipmap_tree
*mt
)
268 /* For now compression is only enabled for integer formats even though
269 * there exist supported floating point formats also. This is a heuristic
270 * decision based on current public benchmarks. In none of the cases these
271 * formats provided any improvement but a few cases were seen to regress.
272 * Hence these are left to to be enabled in the future when they are known
275 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
278 if (!intel_miptree_supports_ccs(brw
, mt
))
281 /* Fast clear can be also used to clear srgb surfaces by using equivalent
282 * linear format. This trick, however, can't be extended to be used with
283 * lossless compression and therefore a check is needed to see if the format
286 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
290 * Determine depth format corresponding to a depth+stencil format,
291 * for separate stencil.
294 intel_depth_format_for_depthstencil_format(mesa_format format
) {
296 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
297 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
298 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
299 return MESA_FORMAT_Z_FLOAT32
;
306 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
307 unsigned depth0
, struct intel_mipmap_level
*table
)
309 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
311 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
313 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
314 if (!table
[level
].slice
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++)
322 free(table
[level
].slice
);
328 needs_separate_stencil(const struct brw_context
*brw
,
329 struct intel_mipmap_tree
*mt
,
330 mesa_format format
, uint32_t layout_flags
)
333 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
336 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
339 if (brw
->must_use_separate_stencil
)
342 return brw
->has_separate_stencil
&&
343 intel_miptree_supports_hiz(brw
, mt
);
347 * @param for_bo Indicates that the caller is
348 * intel_miptree_create_for_bo(). If true, then do not create
351 static struct intel_mipmap_tree
*
352 intel_miptree_create_layout(struct brw_context
*brw
,
361 uint32_t layout_flags
)
363 assert(num_samples
> 0);
365 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
369 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
370 _mesa_enum_to_string(target
),
371 _mesa_get_format_name(format
),
372 first_level
, last_level
, depth0
, mt
);
374 if (target
== GL_TEXTURE_1D_ARRAY
)
375 assert(height0
== 1);
379 mt
->first_level
= first_level
;
380 mt
->last_level
= last_level
;
381 mt
->logical_width0
= width0
;
382 mt
->logical_height0
= height0
;
383 mt
->logical_depth0
= depth0
;
384 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
385 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
386 mt
->supports_fast_clear
= false;
387 mt
->aux_state
= NULL
;
388 mt
->cpp
= _mesa_get_format_bytes(format
);
389 mt
->surf
.samples
= num_samples
;
390 mt
->compressed
= _mesa_is_format_compressed(format
);
391 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
394 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
395 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
397 int depth_multiply
= 1;
398 if (num_samples
> 1) {
399 /* Adjust width/height/depth for MSAA */
400 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
401 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
402 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
403 * "If the surface is multisampled and it is a depth or stencil
404 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
405 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
408 * +----------------------------------------------------------------+
409 * | Num Multisamples | W_l = | H_l = |
410 * +----------------------------------------------------------------+
411 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
412 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
413 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
414 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
415 * +----------------------------------------------------------------+
418 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
419 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
420 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
422 * Another more complicated explanation for these adjustments comes
423 * from the Sandybridge PRM, volume 4, part 1, page 31:
425 * "Any of the other messages (sample*, LOD, load4) used with a
426 * (4x) multisampled surface will in-effect sample a surface with
427 * double the height and width as that indicated in the surface
428 * state. Each pixel position on the original-sized surface is
429 * replaced with a 2x2 of samples with the following arrangement:
434 * Thus, when sampling from a multisampled texture, it behaves as
435 * though the layout in memory for (x,y,sample) is:
437 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
438 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
440 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
441 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
443 * However, the actual layout of multisampled data in memory is:
445 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
446 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
448 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
449 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
451 * This pattern repeats for each 2x2 pixel block.
453 * As a result, when calculating the size of our 4-sample buffer for
454 * an odd width or height, we have to align before scaling up because
455 * sample 3 is in that bottom right 2x2 block.
457 switch (num_samples
) {
459 assert(brw
->gen
>= 8);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2);
464 width0
= ALIGN(width0
, 2) * 2;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 2;
472 width0
= ALIGN(width0
, 2) * 4;
473 height0
= ALIGN(height0
, 2) * 4;
476 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
479 unreachable("not reached");
482 /* Non-interleaved */
483 depth_multiply
= num_samples
;
484 depth0
*= depth_multiply
;
488 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->surf
.msaa_layout
) {
508 case ISL_MSAA_LAYOUT_NONE
:
509 case ISL_MSAA_LAYOUT_INTERLEAVED
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case ISL_MSAA_LAYOUT_ARRAY
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
519 assert(depth0
== 6 * depth_multiply
);
521 mt
->physical_width0
= width0
;
522 mt
->physical_height0
= height0
;
523 mt
->physical_depth0
= depth0
;
525 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
)) {
526 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
528 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
531 mt
->stencil_mt
= intel_miptree_create(brw
,
542 if (!mt
->stencil_mt
) {
543 intel_miptree_release(&mt
);
546 mt
->stencil_mt
->r8stencil_needs_update
= true;
548 /* Fix up the Z miptree format for how we're splitting out separate
549 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
551 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
554 if (format
== mt
->format
) {
555 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
556 _mesa_get_format_name(mt
->format
));
560 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
561 mt
->array_layout
= GEN6_HIZ_STENCIL
;
564 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
565 * multisampled or have an AUX buffer attached to it.
567 * GEN | MSRT | AUX_CCS_* or AUX_MCS
568 * -------------------------------------------
569 * 9 | HALIGN_16 | HALIGN_16
570 * 8 | HALIGN_ANY | HALIGN_16
574 if (intel_miptree_supports_ccs(brw
, mt
)) {
575 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
576 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
577 } else if (brw
->gen
>= 9 && num_samples
> 1) {
578 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
580 const UNUSED
bool is_lossless_compressed_aux
=
581 brw
->gen
>= 9 && num_samples
== 1 &&
582 mt
->format
== MESA_FORMAT_R_UINT32
;
584 /* For now, nothing else has this requirement */
585 assert(is_lossless_compressed_aux
||
586 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
589 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
590 intel_miptree_release(&mt
);
599 * Choose the aux usage for this miptree. This function must be called fairly
600 * late in the miptree create process after we have a tiling.
603 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
604 struct intel_mipmap_tree
*mt
)
606 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
608 const unsigned no_flags
= 0;
609 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
610 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
611 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
612 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
613 intel_miptree_supports_ccs(brw
, mt
)) {
614 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
615 brw
->gen
>= 9 && !mt
->is_scanout
&&
616 intel_miptree_supports_ccs_e(brw
, mt
)) {
617 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
619 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
621 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
622 intel_miptree_supports_hiz(brw
, mt
)) {
623 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
626 /* We can do fast-clear on all auxiliary surface types that are
627 * allocated through the normal texture creation paths.
629 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
630 mt
->supports_fast_clear
= true;
635 * Choose an appropriate uncompressed format for a requested
636 * compressed format, if unsupported.
639 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
641 /* No need to lower ETC formats on these platforms,
642 * they are supported natively.
644 if (brw
->gen
>= 8 || brw
->is_baytrail
)
648 case MESA_FORMAT_ETC1_RGB8
:
649 return MESA_FORMAT_R8G8B8X8_UNORM
;
650 case MESA_FORMAT_ETC2_RGB8
:
651 return MESA_FORMAT_R8G8B8X8_UNORM
;
652 case MESA_FORMAT_ETC2_SRGB8
:
653 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
654 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
655 return MESA_FORMAT_B8G8R8A8_SRGB
;
656 case MESA_FORMAT_ETC2_RGBA8_EAC
:
657 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
658 return MESA_FORMAT_R8G8B8A8_UNORM
;
659 case MESA_FORMAT_ETC2_R11_EAC
:
660 return MESA_FORMAT_R_UNORM16
;
661 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
662 return MESA_FORMAT_R_SNORM16
;
663 case MESA_FORMAT_ETC2_RG11_EAC
:
664 return MESA_FORMAT_R16G16_UNORM
;
665 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
666 return MESA_FORMAT_R16G16_SNORM
;
668 /* Non ETC1 / ETC2 format */
673 /** \brief Assert that the level and layer are valid for the miptree. */
675 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
683 assert(level
>= mt
->first_level
);
684 assert(level
<= mt
->last_level
);
686 if (mt
->surf
.size
> 0)
687 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
688 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
689 mt
->surf
.phys_level0_sa
.array_len
));
691 assert(layer
< mt
->level
[level
].depth
);
694 static enum isl_aux_state
**
695 create_aux_state_map(struct intel_mipmap_tree
*mt
,
696 enum isl_aux_state initial
)
698 const uint32_t levels
= mt
->last_level
+ 1;
700 uint32_t total_slices
= 0;
701 for (uint32_t level
= 0; level
< levels
; level
++)
702 total_slices
+= mt
->level
[level
].depth
;
704 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
706 /* We're going to allocate a single chunk of data for both the per-level
707 * reference array and the arrays of aux_state. This makes cleanup
708 * significantly easier.
710 const size_t total_size
= per_level_array_size
+
711 total_slices
* sizeof(enum isl_aux_state
);
712 void *data
= malloc(total_size
);
716 enum isl_aux_state
**per_level_arr
= data
;
717 enum isl_aux_state
*s
= data
+ per_level_array_size
;
718 for (uint32_t level
= 0; level
< levels
; level
++) {
719 per_level_arr
[level
] = s
;
720 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
723 assert((void *)s
== data
+ total_size
);
725 return per_level_arr
;
729 free_aux_state_map(enum isl_aux_state
**state
)
734 static struct intel_mipmap_tree
*
735 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
736 unsigned first_level
, unsigned last_level
,
737 unsigned width0
, unsigned height0
, unsigned depth0
,
738 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
739 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
740 unsigned row_pitch
, struct brw_bo
*bo
)
742 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
746 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
754 if (target
== GL_TEXTURE_CUBE_MAP
||
755 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
756 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
758 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
760 _mesa_enum_to_string(target
),
761 _mesa_get_format_name(format
),
762 num_samples
, width0
, height0
, depth0
,
763 first_level
, last_level
, mt
);
765 struct isl_surf_init_info init_info
= {
766 .dim
= get_isl_surf_dim(target
),
767 .format
= translate_tex_format(brw
, format
, false),
770 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
771 .levels
= last_level
- first_level
+ 1,
772 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
773 .samples
= num_samples
,
774 .row_pitch
= row_pitch
,
775 .usage
= isl_usage_flags
,
776 .tiling_flags
= tiling_flags
,
779 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
782 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
785 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
787 isl_tiling_to_i915_tiling(
789 mt
->surf
.row_pitch
, alloc_flags
);
796 mt
->first_level
= first_level
;
797 mt
->last_level
= last_level
;
800 mt
->aux_state
= NULL
;
805 intel_miptree_release(&mt
);
809 static struct intel_mipmap_tree
*
810 miptree_create(struct brw_context
*brw
,
819 uint32_t layout_flags
)
821 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
822 return make_surface(brw
, target
, format
, first_level
, last_level
,
823 width0
, height0
, depth0
, num_samples
,
825 ISL_SURF_USAGE_STENCIL_BIT
|
826 ISL_SURF_USAGE_TEXTURE_BIT
,
827 BO_ALLOC_FOR_RENDER
, 0, NULL
);
829 struct intel_mipmap_tree
*mt
;
830 mesa_format tex_format
= format
;
831 mesa_format etc_format
= MESA_FORMAT_NONE
;
832 uint32_t alloc_flags
= 0;
834 format
= intel_lower_compressed_format(brw
, format
);
836 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
838 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
839 mt
= intel_miptree_create_layout(brw
, target
, format
,
840 first_level
, last_level
, width0
,
841 height0
, depth0
, num_samples
,
846 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
847 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
849 mt
->etc_format
= etc_format
;
851 if (format
== MESA_FORMAT_S_UINT8
) {
852 /* Align to size of W tile, 64x64. */
853 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
854 ALIGN(mt
->total_width
, 64),
855 ALIGN(mt
->total_height
, 64),
857 isl_tiling_to_i915_tiling(
862 /* The stencil buffer has quirky pitch requirements. From the
863 * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
864 * dword 1 bits 16:0 - Surface Pitch):
866 * The pitch must be set to 2x the value computed based on width, as
867 * the stencil buffer is stored with two rows interleaved.
869 * While the Ivybridge PRM lacks this comment, the BSpec contains the
870 * same text, and experiments indicate that this is necessary.
872 mt
->surf
.row_pitch
*= 2;
874 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
875 mt
->total_width
, mt
->total_height
,
877 isl_tiling_to_i915_tiling(
883 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
884 mt
->bo
->cache_coherent
= false;
886 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
887 intel_miptree_choose_aux_usage(brw
, mt
);
892 struct intel_mipmap_tree
*
893 intel_miptree_create(struct brw_context
*brw
,
902 uint32_t layout_flags
)
904 assert(num_samples
> 0);
906 struct intel_mipmap_tree
*mt
= miptree_create(
908 first_level
, last_level
,
909 width0
, height0
, depth0
, num_samples
,
914 /* If the BO is too large to fit in the aperture, we need to use the
915 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
916 * handle Y-tiling, so we need to fall back to X.
918 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
919 mt
->surf
.tiling
== ISL_TILING_Y0
) {
920 const uint32_t alloc_flags
=
921 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
922 BO_ALLOC_FOR_RENDER
: 0;
923 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
924 mt
->total_width
, mt
->total_height
);
926 mt
->surf
.tiling
= ISL_TILING_X
;
927 brw_bo_unreference(mt
->bo
);
928 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
929 mt
->total_width
, mt
->total_height
, mt
->cpp
,
930 isl_tiling_to_i915_tiling(
932 &mt
->surf
.row_pitch
, alloc_flags
);
938 intel_miptree_release(&mt
);
942 if (!intel_miptree_alloc_aux(brw
, mt
)) {
943 intel_miptree_release(&mt
);
950 struct intel_mipmap_tree
*
951 intel_miptree_create_for_bo(struct brw_context
*brw
,
959 uint32_t layout_flags
)
961 struct intel_mipmap_tree
*mt
;
962 uint32_t tiling
, swizzle
;
963 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
965 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
966 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
967 0, 0, width
, height
, depth
, 1,
969 ISL_SURF_USAGE_STENCIL_BIT
|
970 ISL_SURF_USAGE_TEXTURE_BIT
,
971 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
975 assert(bo
->size
>= mt
->surf
.size
);
977 brw_bo_reference(bo
);
981 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
983 /* Nothing will be able to use this miptree with the BO if the offset isn't
986 if (tiling
!= I915_TILING_NONE
)
987 assert(offset
% 4096 == 0);
989 /* miptrees can't handle negative pitch. If you need flipping of images,
990 * that's outside of the scope of the mt.
994 /* The BO already has a tiling format and we shouldn't confuse the lower
995 * layers by making it try to find a tiling format again.
997 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
998 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
1000 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
1001 mt
= intel_miptree_create_layout(brw
, target
, format
,
1003 width
, height
, depth
,
1004 1 /* num_samples */,
1009 brw_bo_reference(bo
);
1011 mt
->surf
.row_pitch
= pitch
;
1012 mt
->offset
= offset
;
1013 mt
->surf
.tiling
= isl_tiling_from_i915_tiling(tiling
);
1015 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1016 intel_miptree_choose_aux_usage(brw
, mt
);
1021 static struct intel_mipmap_tree
*
1022 miptree_create_for_planar_image(struct brw_context
*brw
,
1023 __DRIimage
*image
, GLenum target
)
1025 struct intel_image_format
*f
= image
->planar_format
;
1026 struct intel_mipmap_tree
*planar_mt
= NULL
;
1028 for (int i
= 0; i
< f
->nplanes
; i
++) {
1029 const int index
= f
->planes
[i
].buffer_index
;
1030 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1031 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1032 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1033 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1035 /* Disable creation of the texture's aux buffers because the driver
1036 * exposes no EGL API to manage them. That is, there is no API for
1037 * resolving the aux buffer's content to the main buffer nor for
1038 * invalidating the aux buffer's content.
1040 struct intel_mipmap_tree
*mt
=
1041 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1042 image
->offsets
[index
],
1044 image
->strides
[index
],
1045 MIPTREE_LAYOUT_DISABLE_AUX
);
1049 mt
->target
= target
;
1054 planar_mt
->plane
[i
- 1] = mt
;
1060 struct intel_mipmap_tree
*
1061 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1062 __DRIimage
*image
, GLenum target
,
1063 enum isl_colorspace colorspace
,
1064 bool is_winsys_image
)
1066 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1067 assert(colorspace
== ISL_COLORSPACE_NONE
||
1068 colorspace
== ISL_COLORSPACE_YUV
);
1069 return miptree_create_for_planar_image(brw
, image
, target
);
1072 mesa_format format
= image
->format
;
1073 switch (colorspace
) {
1074 case ISL_COLORSPACE_NONE
:
1075 /* Keep the image format unmodified */
1078 case ISL_COLORSPACE_LINEAR
:
1079 format
=_mesa_get_srgb_format_linear(format
);
1082 case ISL_COLORSPACE_SRGB
:
1083 format
=_mesa_get_linear_format_srgb(format
);
1087 unreachable("Inalid colorspace for non-planar image");
1090 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1091 /* The texture storage paths in core Mesa detect if the driver does not
1092 * support the user-requested format, and then searches for a
1093 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1094 * do the fallbacks here for important formats.
1096 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1097 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1098 * the Chrome OS compositor consumes as dma_buf EGLImages.
1100 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1103 if (!brw
->ctx
.TextureFormatSupported
[format
])
1106 /* If this image comes in from a window system, we have different
1107 * requirements than if it comes in via an EGL import operation. Window
1108 * system images can use any form of auxiliary compression we wish because
1109 * they get "flushed" before being handed off to the window system and we
1110 * have the opportunity to do resolves. Window system buffers also may be
1111 * used for scanout so we need to flag that appropriately.
1113 const uint32_t mt_layout_flags
=
1114 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1116 /* Disable creation of the texture's aux buffers because the driver exposes
1117 * no EGL API to manage them. That is, there is no API for resolving the aux
1118 * buffer's content to the main buffer nor for invalidating the aux buffer's
1121 struct intel_mipmap_tree
*mt
=
1122 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1123 image
->offset
, image
->width
, image
->height
, 1,
1124 image
->pitch
, mt_layout_flags
);
1128 mt
->target
= target
;
1129 mt
->level
[0].level_x
= image
->tile_x
;
1130 mt
->level
[0].level_y
= image
->tile_y
;
1131 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1132 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1134 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1135 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1136 * trouble resolving back to destination image due to alignment issues.
1138 if (!brw
->has_surface_tile_offset
) {
1139 uint32_t draw_x
, draw_y
;
1140 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1142 if (draw_x
!= 0 || draw_y
!= 0) {
1143 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1144 intel_miptree_release(&mt
);
1149 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1150 intel_miptree_release(&mt
);
1158 * For a singlesample renderbuffer, this simply wraps the given BO with a
1161 * For a multisample renderbuffer, this wraps the window system's
1162 * (singlesample) BO with a singlesample miptree attached to the
1163 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1164 * that will contain the actual rendering (which is lazily resolved to
1165 * irb->singlesample_mt).
1168 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1169 struct intel_renderbuffer
*irb
,
1170 struct intel_mipmap_tree
*singlesample_mt
,
1171 uint32_t width
, uint32_t height
,
1174 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1175 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1176 mesa_format format
= rb
->Format
;
1177 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1179 /* Only the front and back buffers, which are color buffers, are allocated
1180 * through the image loader.
1182 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1183 _mesa_get_format_base_format(format
) == GL_RGBA
);
1185 assert(singlesample_mt
);
1187 if (num_samples
== 1) {
1188 intel_miptree_release(&irb
->mt
);
1189 irb
->mt
= singlesample_mt
;
1191 assert(!irb
->singlesample_mt
);
1193 intel_miptree_release(&irb
->singlesample_mt
);
1194 irb
->singlesample_mt
= singlesample_mt
;
1197 irb
->mt
->logical_width0
!= width
||
1198 irb
->mt
->logical_height0
!= height
) {
1199 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1204 if (!multisample_mt
)
1207 irb
->need_downsample
= false;
1208 intel_miptree_release(&irb
->mt
);
1209 irb
->mt
= multisample_mt
;
1215 intel_miptree_release(&irb
->mt
);
1219 struct intel_mipmap_tree
*
1220 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1224 uint32_t num_samples
)
1226 struct intel_mipmap_tree
*mt
;
1228 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1229 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1230 MIPTREE_LAYOUT_TILING_ANY
|
1231 MIPTREE_LAYOUT_FOR_SCANOUT
;
1233 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1234 width
, height
, depth
, num_samples
,
1242 intel_miptree_release(&mt
);
1247 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1248 struct intel_mipmap_tree
*src
)
1253 intel_miptree_release(dst
);
1257 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1264 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1266 if (aux_buf
== NULL
)
1269 brw_bo_unreference(aux_buf
->bo
);
1275 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1280 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1281 if (--(*mt
)->refcount
<= 0) {
1284 DBG("%s deleting %p\n", __func__
, *mt
);
1286 brw_bo_unreference((*mt
)->bo
);
1287 intel_miptree_release(&(*mt
)->stencil_mt
);
1288 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1289 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1290 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1291 free_aux_state_map((*mt
)->aux_state
);
1293 intel_miptree_release(&(*mt
)->plane
[0]);
1294 intel_miptree_release(&(*mt
)->plane
[1]);
1296 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1297 free((*mt
)->level
[i
].slice
);
1307 intel_get_image_dims(struct gl_texture_image
*image
,
1308 int *width
, int *height
, int *depth
)
1310 switch (image
->TexObject
->Target
) {
1311 case GL_TEXTURE_1D_ARRAY
:
1312 /* For a 1D Array texture the OpenGL API will treat the image height as
1313 * the number of array slices. For Intel hardware, we treat the 1D array
1314 * as a 2D Array with a height of 1. So, here we want to swap image
1317 assert(image
->Depth
== 1);
1318 *width
= image
->Width
;
1320 *depth
= image
->Height
;
1322 case GL_TEXTURE_CUBE_MAP
:
1323 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1324 * though we really have 6 slices.
1326 assert(image
->Depth
== 1);
1327 *width
= image
->Width
;
1328 *height
= image
->Height
;
1332 *width
= image
->Width
;
1333 *height
= image
->Height
;
1334 *depth
= image
->Depth
;
1340 * Can the image be pulled into a unified mipmap tree? This mirrors
1341 * the completeness test in a lot of ways.
1343 * Not sure whether I want to pass gl_texture_image here.
1346 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1347 struct gl_texture_image
*image
)
1349 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1350 GLuint level
= intelImage
->base
.Base
.Level
;
1351 int width
, height
, depth
;
1353 /* glTexImage* choose the texture object based on the target passed in, and
1354 * objects can't change targets over their lifetimes, so this should be
1357 assert(image
->TexObject
->Target
== mt
->target
);
1359 mesa_format mt_format
= mt
->format
;
1360 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1361 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1362 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1363 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1364 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1365 mt_format
= mt
->etc_format
;
1367 if (image
->TexFormat
!= mt_format
)
1370 intel_get_image_dims(image
, &width
, &height
, &depth
);
1372 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1375 if (mt
->surf
.size
> 0) {
1376 if (level
>= mt
->surf
.levels
)
1379 const unsigned level_depth
=
1380 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1381 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1382 mt
->surf
.logical_level0_px
.array_len
;
1384 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1385 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1386 depth
== level_depth
&&
1387 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1390 int level_depth
= mt
->level
[level
].depth
;
1391 if (mt
->surf
.samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1392 level_depth
/= mt
->surf
.samples
;
1394 /* Test image dimensions against the base level image adjusted for
1395 * minification. This will also catch images not present in the
1396 * tree, changed targets, etc.
1398 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1399 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1400 depth
!= level_depth
) {
1404 /* Core uses sample number of zero to indicate single-sampled. */
1405 if (MAX2(image
->NumSamples
, 1) != mt
->surf
.samples
)
1413 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1415 GLuint x
, GLuint y
, GLuint d
)
1417 mt
->level
[level
].depth
= d
;
1418 mt
->level
[level
].level_x
= x
;
1419 mt
->level
[level
].level_y
= y
;
1421 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1424 assert(mt
->level
[level
].slice
);
1426 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1427 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1432 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1433 GLuint level
, GLuint img
,
1436 if (img
== 0 && level
== 0)
1437 assert(x
== 0 && y
== 0);
1439 assert(img
< mt
->level
[level
].depth
);
1441 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1442 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1444 DBG("%s level %d img %d pos %d,%d\n",
1445 __func__
, level
, img
,
1446 mt
->level
[level
].slice
[img
].x_offset
,
1447 mt
->level
[level
].slice
[img
].y_offset
);
1451 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1452 GLuint level
, GLuint slice
,
1453 GLuint
*x
, GLuint
*y
)
1455 if (mt
->surf
.size
> 0) {
1456 uint32_t x_offset_sa
, y_offset_sa
;
1458 /* Given level is relative to level zero while the miptree may be
1459 * represent just a subset of all levels starting from 'first_level'.
1461 assert(level
>= mt
->first_level
);
1462 level
-= mt
->first_level
;
1464 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1465 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1466 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1467 &x_offset_sa
, &y_offset_sa
);
1474 assert(slice
< mt
->level
[level
].depth
);
1476 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1477 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1482 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1483 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1484 * and tile_h is set to 1.
1487 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1488 uint32_t *tile_w
, uint32_t *tile_h
)
1499 case ISL_TILING_LINEAR
:
1504 unreachable("not reached");
1510 * This function computes masks that may be used to select the bits of the X
1511 * and Y coordinates that indicate the offset within a tile. If the BO is
1512 * untiled, the masks are set to 0.
1515 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1516 uint32_t *mask_x
, uint32_t *mask_y
)
1518 uint32_t tile_w_bytes
, tile_h
;
1520 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1522 *mask_x
= tile_w_bytes
/ cpp
- 1;
1523 *mask_y
= tile_h
- 1;
1527 * Compute the offset (in bytes) from the start of the BO to the given x
1528 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1529 * multiples of the tile size.
1532 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1533 uint32_t x
, uint32_t y
)
1536 uint32_t pitch
= mt
->surf
.row_pitch
;
1538 switch (mt
->surf
.tiling
) {
1540 unreachable("not reached");
1541 case ISL_TILING_LINEAR
:
1542 return y
* pitch
+ x
* cpp
;
1544 assert((x
% (512 / cpp
)) == 0);
1545 assert((y
% 8) == 0);
1546 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1548 assert((x
% (128 / cpp
)) == 0);
1549 assert((y
% 32) == 0);
1550 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1555 * Rendering with tiled buffers requires that the base address of the buffer
1556 * be aligned to a page boundary. For renderbuffers, and sometimes with
1557 * textures, we may want the surface to point at a texture image level that
1558 * isn't at a page boundary.
1560 * This function returns an appropriately-aligned base offset
1561 * according to the tiling restrictions, plus any required x/y offset
1565 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1566 GLuint level
, GLuint slice
,
1571 uint32_t mask_x
, mask_y
;
1573 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1574 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1576 *tile_x
= x
& mask_x
;
1577 *tile_y
= y
& mask_y
;
1579 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1583 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1584 struct intel_mipmap_tree
*src_mt
,
1585 unsigned src_level
, unsigned src_layer
,
1586 struct intel_mipmap_tree
*dst_mt
,
1587 unsigned dst_level
, unsigned dst_layer
,
1588 unsigned width
, unsigned height
)
1591 ptrdiff_t src_stride
, dst_stride
;
1592 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1593 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1595 intel_miptree_map(brw
, src_mt
,
1596 src_level
, src_layer
,
1599 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1602 intel_miptree_map(brw
, dst_mt
,
1603 dst_level
, dst_layer
,
1606 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1610 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1611 _mesa_get_format_name(src_mt
->format
),
1612 src_mt
, src
, src_stride
,
1613 _mesa_get_format_name(dst_mt
->format
),
1614 dst_mt
, dst
, dst_stride
,
1617 int row_size
= cpp
* width
;
1618 if (src_stride
== row_size
&&
1619 dst_stride
== row_size
) {
1620 memcpy(dst
, src
, row_size
* height
);
1622 for (int i
= 0; i
< height
; i
++) {
1623 memcpy(dst
, src
, row_size
);
1629 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1630 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1632 /* Don't forget to copy the stencil data over, too. We could have skipped
1633 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1634 * shuffling the two data sources in/out of temporary storage instead of
1635 * the direct mapping we get this way.
1637 if (dst_mt
->stencil_mt
) {
1638 assert(src_mt
->stencil_mt
);
1639 intel_miptree_copy_slice_sw(brw
,
1640 src_mt
->stencil_mt
, src_level
, src_layer
,
1641 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1647 intel_miptree_copy_slice(struct brw_context
*brw
,
1648 struct intel_mipmap_tree
*src_mt
,
1649 unsigned src_level
, unsigned src_layer
,
1650 struct intel_mipmap_tree
*dst_mt
,
1651 unsigned dst_level
, unsigned dst_layer
)
1654 mesa_format format
= src_mt
->format
;
1655 uint32_t width
, height
;
1657 if (src_mt
->surf
.size
> 0) {
1658 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1659 src_level
- src_mt
->first_level
);
1660 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1661 src_level
- src_mt
->first_level
);
1663 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1664 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1665 src_level
- src_mt
->first_level
));
1667 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1669 width
= minify(src_mt
->physical_width0
,
1670 src_level
- src_mt
->first_level
);
1671 height
= minify(src_mt
->physical_height0
,
1672 src_level
- src_mt
->first_level
);
1673 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1676 assert(src_mt
->format
== dst_mt
->format
);
1678 if (dst_mt
->compressed
) {
1680 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1681 height
= ALIGN_NPOT(height
, j
) / j
;
1682 width
= ALIGN_NPOT(width
, i
) / i
;
1685 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1686 * below won't apply since we can't do the depth's Y tiling or the
1687 * stencil's W tiling in the blitter.
1689 if (src_mt
->stencil_mt
) {
1690 intel_miptree_copy_slice_sw(brw
,
1691 src_mt
, src_level
, src_layer
,
1692 dst_mt
, dst_level
, dst_layer
,
1697 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1698 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1700 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1703 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1704 _mesa_get_format_name(src_mt
->format
),
1705 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1706 _mesa_get_format_name(dst_mt
->format
),
1707 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1710 if (!intel_miptree_blit(brw
,
1711 src_mt
, src_level
, src_layer
, 0, 0, false,
1712 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1713 width
, height
, GL_COPY
)) {
1714 perf_debug("miptree validate blit for %s failed\n",
1715 _mesa_get_format_name(format
));
1717 intel_miptree_copy_slice_sw(brw
,
1718 src_mt
, src_level
, src_layer
,
1719 dst_mt
, dst_level
, dst_layer
,
1725 * Copies the image's current data to the given miptree, and associates that
1726 * miptree with the image.
1728 * If \c invalidate is true, then the actual image data does not need to be
1729 * copied, but the image still needs to be associated to the new miptree (this
1730 * is set to true if we're about to clear the image).
1733 intel_miptree_copy_teximage(struct brw_context
*brw
,
1734 struct intel_texture_image
*intelImage
,
1735 struct intel_mipmap_tree
*dst_mt
,
1738 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1739 struct intel_texture_object
*intel_obj
=
1740 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1741 int level
= intelImage
->base
.Base
.Level
;
1742 const unsigned face
= intelImage
->base
.Base
.Face
;
1743 unsigned start_layer
, end_layer
;
1745 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1747 assert(intelImage
->base
.Base
.Height
);
1749 end_layer
= intelImage
->base
.Base
.Height
- 1;
1750 } else if (face
> 0) {
1754 assert(intelImage
->base
.Base
.Depth
);
1756 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1760 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1761 intel_miptree_copy_slice(brw
,
1767 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1768 intel_obj
->needs_validate
= true;
1772 intel_miptree_init_mcs(struct brw_context
*brw
,
1773 struct intel_mipmap_tree
*mt
,
1776 assert(mt
->mcs_buf
!= NULL
);
1778 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1780 * When MCS buffer is enabled and bound to MSRT, it is required that it
1781 * is cleared prior to any rendering.
1783 * Since we don't use the MCS buffer for any purpose other than rendering,
1784 * it makes sense to just clear it immediately upon allocation.
1786 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1788 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1789 if (unlikely(map
== NULL
)) {
1790 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1791 brw_bo_unreference(mt
->mcs_buf
->bo
);
1796 memset(data
, init_value
, mt
->mcs_buf
->size
);
1797 brw_bo_unmap(mt
->mcs_buf
->bo
);
1800 static struct intel_miptree_aux_buffer
*
1801 intel_alloc_aux_buffer(struct brw_context
*brw
,
1803 const struct isl_surf
*aux_surf
,
1804 uint32_t alloc_flags
,
1805 struct intel_mipmap_tree
*mt
)
1807 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1811 buf
->size
= aux_surf
->size
;
1812 buf
->pitch
= aux_surf
->row_pitch
;
1813 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1815 /* ISL has stricter set of alignment rules then the drm allocator.
1816 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1817 * trying to recalculate based on different format block sizes.
1819 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1820 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1826 buf
->surf
= *aux_surf
;
1832 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1833 struct intel_mipmap_tree
*mt
,
1836 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1837 assert(mt
->mcs_buf
== NULL
);
1838 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1840 /* Multisampled miptrees are only supported for single level. */
1841 assert(mt
->first_level
== 0);
1842 enum isl_aux_state
**aux_state
=
1843 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1847 struct isl_surf temp_main_surf
;
1848 struct isl_surf temp_mcs_surf
;
1850 /* Create first an ISL presentation for the main color surface and let ISL
1851 * calculate equivalent MCS surface against it.
1853 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1854 MAYBE_UNUSED
bool ok
=
1855 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1858 /* Buffer needs to be initialised requiring the buffer to be immediately
1859 * mapped to cpu space for writing. Therefore do not use the gpu access
1860 * flag which can cause an unnecessary delay if the backing pages happened
1861 * to be just used by the GPU.
1863 const uint32_t alloc_flags
= 0;
1864 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1865 &temp_mcs_surf
, alloc_flags
, mt
);
1871 mt
->aux_state
= aux_state
;
1873 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1879 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1880 struct intel_mipmap_tree
*mt
)
1882 assert(mt
->mcs_buf
== NULL
);
1883 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1884 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1886 struct isl_surf temp_main_surf
;
1887 struct isl_surf temp_ccs_surf
;
1889 /* Create first an ISL presentation for the main color surface and let ISL
1890 * calculate equivalent CCS surface against it.
1892 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1893 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1897 assert(temp_ccs_surf
.size
&&
1898 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1900 enum isl_aux_state
**aux_state
=
1901 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1905 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1906 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1908 * "If Software wants to enable Color Compression without Fast clear,
1909 * Software needs to initialize MCS with zeros."
1911 * A CCS value of 0 indicates that the corresponding block is in the
1912 * pass-through state which is what we want.
1914 * For CCS_D, on the other hand, we don't care as we're about to perform a
1915 * fast-clear operation. In that case, being hot in caches more useful.
1917 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1918 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1919 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1920 &temp_ccs_surf
, alloc_flags
, mt
);
1926 mt
->aux_state
= aux_state
;
1932 * Helper for intel_miptree_alloc_hiz() that sets
1933 * \c mt->level[level].has_hiz. Return true if and only if
1934 * \c has_hiz was set.
1937 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1938 struct intel_mipmap_tree
*mt
,
1941 assert(mt
->hiz_buf
);
1943 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1944 uint32_t width
= minify(mt
->physical_width0
, level
);
1945 uint32_t height
= minify(mt
->physical_height0
, level
);
1947 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1948 * and the height is 4 aligned. This allows our HiZ support
1949 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1950 * we can grow the width & height to allow the HiZ op to
1951 * force the proper size alignments.
1953 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1954 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1959 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1960 mt
->level
[level
].has_hiz
= true;
1965 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1966 struct intel_mipmap_tree
*mt
)
1968 assert(mt
->hiz_buf
== NULL
);
1969 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1971 enum isl_aux_state
**aux_state
=
1972 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1976 struct isl_surf temp_main_surf
;
1977 struct isl_surf temp_hiz_surf
;
1979 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1980 MAYBE_UNUSED
bool ok
=
1981 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1984 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1985 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1986 &temp_hiz_surf
, alloc_flags
, mt
);
1993 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1994 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1996 mt
->aux_state
= aux_state
;
2003 * Allocate the initial aux surface for a miptree based on mt->aux_usage
2005 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
2006 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
2007 * compress clear color so we wait until an actual fast-clear to allocate it.
2010 intel_miptree_alloc_aux(struct brw_context
*brw
,
2011 struct intel_mipmap_tree
*mt
)
2013 switch (mt
->aux_usage
) {
2014 case ISL_AUX_USAGE_NONE
:
2017 case ISL_AUX_USAGE_HIZ
:
2018 assert(!_mesa_is_format_color_format(mt
->format
));
2019 if (!intel_miptree_alloc_hiz(brw
, mt
))
2023 case ISL_AUX_USAGE_MCS
:
2024 assert(_mesa_is_format_color_format(mt
->format
));
2025 assert(mt
->surf
.samples
> 1);
2026 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
2030 case ISL_AUX_USAGE_CCS_D
:
2031 /* Since CCS_D can only compress clear color so we wait until an actual
2032 * fast-clear to allocate it.
2036 case ISL_AUX_USAGE_CCS_E
:
2037 assert(_mesa_is_format_color_format(mt
->format
));
2038 assert(mt
->surf
.samples
== 1);
2039 if (!intel_miptree_alloc_ccs(brw
, mt
))
2044 unreachable("Invalid aux usage");
2049 * Can the miptree sample using the hiz buffer?
2052 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2053 struct intel_mipmap_tree
*mt
)
2055 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2056 * so keep things conservative for now and never enable it unless we're SKL+.
2066 /* It seems the hardware won't fallback to the depth buffer if some of the
2067 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2068 * of the texture to be HiZ enabled.
2070 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2071 if (!intel_miptree_level_has_hiz(mt
, level
))
2075 /* If compressed multisampling is enabled, then we use it for the auxiliary
2078 * From the BDW PRM (Volume 2d: Command Reference: Structures
2079 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2081 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2082 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2084 * There is no such blurb for 1D textures, but there is sufficient evidence
2085 * that this is broken on SKL+.
2087 return (mt
->surf
.samples
== 1 &&
2088 mt
->target
!= GL_TEXTURE_3D
&&
2089 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2093 * Does the miptree slice have hiz enabled?
2096 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2098 intel_miptree_check_level_layer(mt
, level
, 0);
2099 return mt
->level
[level
].has_hiz
;
2103 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2104 unsigned start_level
, unsigned num_levels
,
2105 unsigned start_layer
, unsigned num_layers
)
2107 assert(_mesa_is_format_color_format(mt
->format
));
2112 /* Clamp the level range to fit the miptree */
2113 assert(start_level
+ num_levels
>= start_level
);
2114 const uint32_t last_level
=
2115 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2116 start_level
= MAX2(mt
->first_level
, start_level
);
2117 num_levels
= last_level
- start_level
+ 1;
2119 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2120 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2121 for (unsigned a
= 0; a
< level_layers
; a
++) {
2122 enum isl_aux_state aux_state
=
2123 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2124 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2125 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2134 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2135 const struct intel_mipmap_tree
*mt
,
2136 unsigned level
, unsigned layer
)
2142 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2143 assert(brw
->gen
>= 8 ||
2144 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2146 /* Compression of arrayed msaa surfaces is supported. */
2147 if (mt
->surf
.samples
> 1)
2150 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2151 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2157 static enum blorp_fast_clear_op
2158 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2159 bool ccs_supported
, bool fast_clear_supported
)
2161 assert(ccs_supported
== fast_clear_supported
);
2163 switch (aux_state
) {
2164 case ISL_AUX_STATE_CLEAR
:
2165 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2167 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2169 return BLORP_FAST_CLEAR_OP_NONE
;
2171 case ISL_AUX_STATE_PASS_THROUGH
:
2172 return BLORP_FAST_CLEAR_OP_NONE
;
2174 case ISL_AUX_STATE_RESOLVED
:
2175 case ISL_AUX_STATE_AUX_INVALID
:
2176 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2180 unreachable("Invalid aux state for CCS_D");
2183 static enum blorp_fast_clear_op
2184 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2185 bool ccs_supported
, bool fast_clear_supported
)
2187 switch (aux_state
) {
2188 case ISL_AUX_STATE_CLEAR
:
2189 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2191 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2192 else if (!fast_clear_supported
)
2193 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2195 return BLORP_FAST_CLEAR_OP_NONE
;
2197 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2199 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2201 return BLORP_FAST_CLEAR_OP_NONE
;
2203 case ISL_AUX_STATE_PASS_THROUGH
:
2204 return BLORP_FAST_CLEAR_OP_NONE
;
2206 case ISL_AUX_STATE_RESOLVED
:
2207 case ISL_AUX_STATE_AUX_INVALID
:
2211 unreachable("Invalid aux state for CCS_E");
2215 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2216 struct intel_mipmap_tree
*mt
,
2217 uint32_t level
, uint32_t layer
,
2219 bool fast_clear_supported
)
2221 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2223 enum blorp_fast_clear_op resolve_op
;
2224 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2225 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2226 fast_clear_supported
);
2228 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2229 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2230 fast_clear_supported
);
2233 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2234 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2235 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2237 switch (resolve_op
) {
2238 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2239 /* The CCS full resolve operation destroys the CCS and sets it to the
2240 * pass-through state. (You can also think of this as being both a
2241 * resolve and an ambiguate in one operation.)
2243 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2244 ISL_AUX_STATE_PASS_THROUGH
);
2247 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2248 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2249 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2253 unreachable("Invalid resolve op");
2259 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2260 struct intel_mipmap_tree
*mt
,
2261 uint32_t level
, uint32_t layer
,
2262 bool written_with_ccs
)
2264 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2266 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2267 switch (aux_state
) {
2268 case ISL_AUX_STATE_CLEAR
:
2269 assert(written_with_ccs
);
2270 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2271 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2274 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2275 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2276 assert(written_with_ccs
);
2277 break; /* Nothing to do */
2279 case ISL_AUX_STATE_PASS_THROUGH
:
2280 if (written_with_ccs
) {
2281 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2282 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2288 case ISL_AUX_STATE_RESOLVED
:
2289 case ISL_AUX_STATE_AUX_INVALID
:
2290 unreachable("Invalid aux state for CCS_E");
2293 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2294 /* CCS_D is a bit simpler */
2295 switch (aux_state
) {
2296 case ISL_AUX_STATE_CLEAR
:
2297 assert(written_with_ccs
);
2298 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2299 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2302 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2303 assert(written_with_ccs
);
2304 break; /* Nothing to do */
2306 case ISL_AUX_STATE_PASS_THROUGH
:
2310 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2311 case ISL_AUX_STATE_RESOLVED
:
2312 case ISL_AUX_STATE_AUX_INVALID
:
2313 unreachable("Invalid aux state for CCS_D");
2319 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2320 struct intel_mipmap_tree
*mt
,
2321 uint32_t level
, uint32_t layer
,
2322 bool written_with_aux
)
2324 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2325 case ISL_AUX_STATE_CLEAR
:
2326 assert(written_with_aux
);
2327 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2328 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2331 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2332 assert(written_with_aux
);
2333 break; /* Nothing to do */
2335 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2336 case ISL_AUX_STATE_RESOLVED
:
2337 case ISL_AUX_STATE_PASS_THROUGH
:
2338 case ISL_AUX_STATE_AUX_INVALID
:
2339 unreachable("Invalid aux state for MCS");
2344 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2345 struct intel_mipmap_tree
*mt
,
2346 uint32_t level
, uint32_t layer
,
2347 bool hiz_supported
, bool fast_clear_supported
)
2349 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2350 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2351 case ISL_AUX_STATE_CLEAR
:
2352 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2353 if (!hiz_supported
|| !fast_clear_supported
)
2354 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2357 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2359 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2362 case ISL_AUX_STATE_PASS_THROUGH
:
2363 case ISL_AUX_STATE_RESOLVED
:
2366 case ISL_AUX_STATE_AUX_INVALID
:
2368 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2372 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2373 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2376 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2377 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2378 ISL_AUX_STATE_RESOLVED
);
2381 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2382 /* The HiZ resolve operation is actually an ambiguate */
2383 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2384 ISL_AUX_STATE_PASS_THROUGH
);
2388 unreachable("Invalid HiZ op");
2394 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2395 struct intel_mipmap_tree
*mt
,
2396 uint32_t level
, uint32_t layer
,
2397 bool written_with_hiz
)
2399 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2400 case ISL_AUX_STATE_CLEAR
:
2401 assert(written_with_hiz
);
2402 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2403 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2406 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2407 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2408 assert(written_with_hiz
);
2409 break; /* Nothing to do */
2411 case ISL_AUX_STATE_RESOLVED
:
2412 if (written_with_hiz
) {
2413 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2414 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2416 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2417 ISL_AUX_STATE_AUX_INVALID
);
2421 case ISL_AUX_STATE_PASS_THROUGH
:
2422 if (written_with_hiz
) {
2423 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2424 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2428 case ISL_AUX_STATE_AUX_INVALID
:
2429 assert(!written_with_hiz
);
2434 static inline uint32_t
2435 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2436 uint32_t start_level
, uint32_t num_levels
)
2438 assert(start_level
>= mt
->first_level
);
2439 assert(start_level
<= mt
->last_level
);
2441 if (num_levels
== INTEL_REMAINING_LAYERS
)
2442 num_levels
= mt
->last_level
- start_level
+ 1;
2443 /* Check for overflow */
2444 assert(start_level
+ num_levels
>= start_level
);
2445 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2450 static inline uint32_t
2451 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2452 uint32_t start_layer
, uint32_t num_layers
)
2454 assert(level
<= mt
->last_level
);
2455 uint32_t total_num_layers
;
2457 if (mt
->surf
.size
> 0)
2458 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2459 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2460 mt
->surf
.phys_level0_sa
.array_len
;
2462 total_num_layers
= mt
->level
[level
].depth
;
2464 assert(start_layer
< total_num_layers
);
2465 if (num_layers
== INTEL_REMAINING_LAYERS
)
2466 num_layers
= total_num_layers
- start_layer
;
2467 /* Check for overflow */
2468 assert(start_layer
+ num_layers
>= start_layer
);
2469 assert(start_layer
+ num_layers
<= total_num_layers
);
2475 intel_miptree_prepare_access(struct brw_context
*brw
,
2476 struct intel_mipmap_tree
*mt
,
2477 uint32_t start_level
, uint32_t num_levels
,
2478 uint32_t start_layer
, uint32_t num_layers
,
2479 bool aux_supported
, bool fast_clear_supported
)
2481 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2483 if (_mesa_is_format_color_format(mt
->format
)) {
2487 if (mt
->surf
.samples
> 1) {
2488 /* Nothing to do for MSAA */
2489 assert(aux_supported
&& fast_clear_supported
);
2491 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2492 const uint32_t level
= start_level
+ l
;
2493 const uint32_t level_layers
=
2494 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2495 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2496 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2497 start_layer
+ a
, aux_supported
,
2498 fast_clear_supported
);
2502 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2503 /* Nothing to do for stencil */
2508 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2509 const uint32_t level
= start_level
+ l
;
2510 if (!intel_miptree_level_has_hiz(mt
, level
))
2513 const uint32_t level_layers
=
2514 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2515 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2516 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2518 fast_clear_supported
);
2525 intel_miptree_finish_write(struct brw_context
*brw
,
2526 struct intel_mipmap_tree
*mt
, uint32_t level
,
2527 uint32_t start_layer
, uint32_t num_layers
,
2528 bool written_with_aux
)
2530 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2532 if (_mesa_is_format_color_format(mt
->format
)) {
2536 if (mt
->surf
.samples
> 1) {
2537 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2538 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2542 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2543 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2547 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2548 /* Nothing to do for stencil */
2550 if (!intel_miptree_level_has_hiz(mt
, level
))
2553 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2554 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2561 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2562 uint32_t level
, uint32_t layer
)
2564 intel_miptree_check_level_layer(mt
, level
, layer
);
2566 if (_mesa_is_format_color_format(mt
->format
)) {
2567 assert(mt
->mcs_buf
!= NULL
);
2568 assert(mt
->surf
.samples
== 1 ||
2569 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2570 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2571 unreachable("Cannot get aux state for stencil");
2573 assert(intel_miptree_level_has_hiz(mt
, level
));
2576 return mt
->aux_state
[level
][layer
];
2580 intel_miptree_set_aux_state(struct brw_context
*brw
,
2581 struct intel_mipmap_tree
*mt
, uint32_t level
,
2582 uint32_t start_layer
, uint32_t num_layers
,
2583 enum isl_aux_state aux_state
)
2585 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2587 if (_mesa_is_format_color_format(mt
->format
)) {
2588 assert(mt
->mcs_buf
!= NULL
);
2589 assert(mt
->surf
.samples
== 1 ||
2590 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2591 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2592 unreachable("Cannot get aux state for stencil");
2594 assert(intel_miptree_level_has_hiz(mt
, level
));
2597 for (unsigned a
= 0; a
< num_layers
; a
++)
2598 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2601 /* On Gen9 color buffers may be compressed by the hardware (lossless
2602 * compression). There are, however, format restrictions and care needs to be
2603 * taken that the sampler engine is capable for re-interpreting a buffer with
2604 * format different the buffer was originally written with.
2606 * For example, SRGB formats are not compressible and the sampler engine isn't
2607 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2608 * color buffer needs to be resolved so that the sampling surface can be
2609 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2613 can_texture_with_ccs(struct brw_context
*brw
,
2614 struct intel_mipmap_tree
*mt
,
2615 mesa_format view_format
)
2617 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2620 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2621 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2623 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2624 isl_mt_format
, isl_view_format
)) {
2625 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2626 _mesa_get_format_name(view_format
),
2627 _mesa_get_format_name(mt
->format
));
2635 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2636 struct intel_mipmap_tree
*mt
,
2637 mesa_format view_format
,
2638 uint32_t start_level
, uint32_t num_levels
,
2639 uint32_t start_layer
, uint32_t num_layers
,
2640 bool *aux_supported_out
)
2642 bool aux_supported
, clear_supported
;
2643 if (_mesa_is_format_color_format(mt
->format
)) {
2644 if (mt
->surf
.samples
> 1) {
2645 aux_supported
= clear_supported
= true;
2647 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2649 /* Clear color is specified as ints or floats and the conversion is
2650 * done by the sampler. If we have a texture view, we would have to
2651 * perform the clear color conversion manually. Just disable clear
2654 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2656 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2657 aux_supported
= clear_supported
= false;
2659 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2662 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2663 start_layer
, num_layers
,
2664 aux_supported
, clear_supported
);
2665 if (aux_supported_out
)
2666 *aux_supported_out
= aux_supported
;
2670 intel_miptree_prepare_texture(struct brw_context
*brw
,
2671 struct intel_mipmap_tree
*mt
,
2672 mesa_format view_format
,
2673 bool *aux_supported_out
)
2675 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2676 0, INTEL_REMAINING_LEVELS
,
2677 0, INTEL_REMAINING_LAYERS
,
2682 intel_miptree_prepare_image(struct brw_context
*brw
,
2683 struct intel_mipmap_tree
*mt
)
2685 /* The data port doesn't understand any compression */
2686 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2687 0, INTEL_REMAINING_LAYERS
, false, false);
2691 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2692 struct intel_mipmap_tree
*mt
, uint32_t level
,
2693 uint32_t start_layer
, uint32_t num_layers
)
2695 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2696 start_layer
, num_layers
, NULL
);
2700 intel_miptree_prepare_render(struct brw_context
*brw
,
2701 struct intel_mipmap_tree
*mt
, uint32_t level
,
2702 uint32_t start_layer
, uint32_t layer_count
,
2705 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2706 * the single-sampled color renderbuffers because the CCS buffer isn't
2707 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2708 * enabled because otherwise the surface state will be programmed with
2709 * the linear equivalent format anyway.
2711 if (brw
->gen
== 9 && srgb_enabled
&& mt
->surf
.samples
== 1 &&
2712 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2714 /* Lossless compression is not supported for SRGB formats, it
2715 * should be impossible to get here with such surfaces.
2717 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2718 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2724 intel_miptree_finish_render(struct brw_context
*brw
,
2725 struct intel_mipmap_tree
*mt
, uint32_t level
,
2726 uint32_t start_layer
, uint32_t layer_count
)
2728 assert(_mesa_is_format_color_format(mt
->format
));
2729 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2730 mt
->mcs_buf
!= NULL
);
2734 intel_miptree_prepare_depth(struct brw_context
*brw
,
2735 struct intel_mipmap_tree
*mt
, uint32_t level
,
2736 uint32_t start_layer
, uint32_t layer_count
)
2738 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2739 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2743 intel_miptree_finish_depth(struct brw_context
*brw
,
2744 struct intel_mipmap_tree
*mt
, uint32_t level
,
2745 uint32_t start_layer
, uint32_t layer_count
,
2748 if (depth_written
) {
2749 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2750 mt
->hiz_buf
!= NULL
);
2755 * Make it possible to share the BO backing the given miptree with another
2756 * process or another miptree.
2758 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2759 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2760 * ensure that no MCS buffer gets allocated in the future.
2762 * HiZ is similarly unsafe with shared buffers.
2765 intel_miptree_make_shareable(struct brw_context
*brw
,
2766 struct intel_mipmap_tree
*mt
)
2768 /* MCS buffers are also used for multisample buffers, but we can't resolve
2769 * away a multisample MCS buffer because it's an integral part of how the
2770 * pixel data is stored. Fortunately this code path should never be
2771 * reached for multisample buffers.
2773 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2774 mt
->surf
.samples
== 1);
2776 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2777 0, INTEL_REMAINING_LAYERS
, false, false);
2780 brw_bo_unreference(mt
->mcs_buf
->bo
);
2784 /* Any pending MCS/CCS operations are no longer needed. Trying to
2785 * execute any will likely crash due to the missing aux buffer. So let's
2786 * delete all pending ops.
2788 free(mt
->aux_state
);
2789 mt
->aux_state
= NULL
;
2793 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2796 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2797 mt
->level
[l
].has_hiz
= false;
2800 /* Any pending HiZ operations are no longer needed. Trying to execute
2801 * any will likely crash due to the missing aux buffer. So let's delete
2804 free(mt
->aux_state
);
2805 mt
->aux_state
= NULL
;
2808 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2813 * \brief Get pointer offset into stencil buffer.
2815 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2816 * must decode the tile's layout in software.
2819 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2821 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2823 * Even though the returned offset is always positive, the return type is
2825 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2826 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2829 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2831 uint32_t tile_size
= 4096;
2832 uint32_t tile_width
= 64;
2833 uint32_t tile_height
= 64;
2834 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2836 uint32_t tile_x
= x
/ tile_width
;
2837 uint32_t tile_y
= y
/ tile_height
;
2839 /* The byte's address relative to the tile's base addres. */
2840 uint32_t byte_x
= x
% tile_width
;
2841 uint32_t byte_y
= y
% tile_height
;
2843 uintptr_t u
= tile_y
* row_size
2844 + tile_x
* tile_size
2845 + 512 * (byte_x
/ 8)
2847 + 32 * ((byte_y
/ 4) % 2)
2848 + 16 * ((byte_x
/ 4) % 2)
2849 + 8 * ((byte_y
/ 2) % 2)
2850 + 4 * ((byte_x
/ 2) % 2)
2855 /* adjust for bit6 swizzling */
2856 if (((byte_x
/ 8) % 2) == 1) {
2857 if (((byte_y
/ 8) % 2) == 0) {
2869 intel_miptree_updownsample(struct brw_context
*brw
,
2870 struct intel_mipmap_tree
*src
,
2871 struct intel_mipmap_tree
*dst
)
2873 unsigned src_w
, src_h
, dst_w
, dst_h
;
2875 if (src
->surf
.size
> 0) {
2876 src_w
= src
->surf
.logical_level0_px
.width
;
2877 src_h
= src
->surf
.logical_level0_px
.height
;
2879 src_w
= src
->logical_width0
;
2880 src_h
= src
->logical_height0
;
2883 if (dst
->surf
.size
> 0) {
2884 dst_w
= dst
->surf
.logical_level0_px
.width
;
2885 dst_h
= dst
->surf
.logical_level0_px
.height
;
2887 dst_w
= dst
->logical_width0
;
2888 dst_h
= dst
->logical_height0
;
2891 brw_blorp_blit_miptrees(brw
,
2892 src
, 0 /* level */, 0 /* layer */,
2893 src
->format
, SWIZZLE_XYZW
,
2894 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2897 GL_NEAREST
, false, false /*mirror x, y*/,
2900 if (src
->stencil_mt
) {
2901 if (src
->stencil_mt
->surf
.size
> 0) {
2902 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2903 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2905 src_w
= src
->stencil_mt
->logical_width0
;
2906 src_h
= src
->stencil_mt
->logical_height0
;
2909 if (dst
->stencil_mt
->surf
.size
> 0) {
2910 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2911 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2913 dst_w
= dst
->stencil_mt
->logical_width0
;
2914 dst_h
= dst
->stencil_mt
->logical_height0
;
2917 brw_blorp_blit_miptrees(brw
,
2918 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2919 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2920 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2921 dst
->stencil_mt
->format
,
2924 GL_NEAREST
, false, false /*mirror x, y*/,
2925 false, false /* decode/encode srgb */);
2930 intel_update_r8stencil(struct brw_context
*brw
,
2931 struct intel_mipmap_tree
*mt
)
2933 assert(brw
->gen
>= 7);
2934 struct intel_mipmap_tree
*src
=
2935 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2936 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2939 if (!mt
->r8stencil_mt
) {
2940 const uint32_t r8stencil_flags
=
2941 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2942 MIPTREE_LAYOUT_DISABLE_AUX
;
2943 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2944 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2946 MESA_FORMAT_R_UINT8
,
2949 src
->logical_width0
,
2950 src
->logical_height0
,
2951 src
->logical_depth0
,
2954 assert(mt
->r8stencil_mt
);
2957 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2959 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2960 const unsigned depth
= src
->level
[level
].depth
;
2962 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2963 brw_blorp_copy_miptrees(brw
,
2967 minify(src
->logical_width0
, level
),
2968 minify(src
->logical_height0
, level
));
2972 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2973 src
->r8stencil_needs_update
= false;
2977 intel_miptree_map_raw(struct brw_context
*brw
,
2978 struct intel_mipmap_tree
*mt
,
2981 struct brw_bo
*bo
= mt
->bo
;
2983 if (brw_batch_references(&brw
->batch
, bo
))
2984 intel_batchbuffer_flush(brw
);
2986 return brw_bo_map(brw
, bo
, mode
);
2990 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2992 brw_bo_unmap(mt
->bo
);
2996 intel_miptree_map_gtt(struct brw_context
*brw
,
2997 struct intel_mipmap_tree
*mt
,
2998 struct intel_miptree_map
*map
,
2999 unsigned int level
, unsigned int slice
)
3001 unsigned int bw
, bh
;
3003 unsigned int image_x
, image_y
;
3004 intptr_t x
= map
->x
;
3005 intptr_t y
= map
->y
;
3007 /* For compressed formats, the stride is the number of bytes per
3008 * row of blocks. intel_miptree_get_image_offset() already does
3011 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3012 assert(y
% bh
== 0);
3013 assert(x
% bw
== 0);
3017 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3024 /* Note that in the case of cube maps, the caller must have passed the
3025 * slice number referencing the face.
3027 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3031 map
->stride
= mt
->surf
.row_pitch
;
3032 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3035 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3036 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3037 map
->x
, map
->y
, map
->w
, map
->h
,
3038 mt
, _mesa_get_format_name(mt
->format
),
3039 x
, y
, map
->ptr
, map
->stride
);
3043 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3045 intel_miptree_unmap_raw(mt
);
3049 intel_miptree_map_blit(struct brw_context
*brw
,
3050 struct intel_mipmap_tree
*mt
,
3051 struct intel_miptree_map
*map
,
3052 unsigned int level
, unsigned int slice
)
3054 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3055 /* first_level */ 0,
3059 MIPTREE_LAYOUT_TILING_NONE
);
3061 if (!map
->linear_mt
) {
3062 fprintf(stderr
, "Failed to allocate blit temporary\n");
3065 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3067 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3068 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3069 * invalidate is set, since we'll be writing the whole rectangle from our
3070 * temporary buffer back out.
3072 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3073 if (!intel_miptree_copy(brw
,
3074 mt
, level
, slice
, map
->x
, map
->y
,
3075 map
->linear_mt
, 0, 0, 0, 0,
3077 fprintf(stderr
, "Failed to blit\n");
3082 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3084 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3085 map
->x
, map
->y
, map
->w
, map
->h
,
3086 mt
, _mesa_get_format_name(mt
->format
),
3087 level
, slice
, map
->ptr
, map
->stride
);
3092 intel_miptree_release(&map
->linear_mt
);
3098 intel_miptree_unmap_blit(struct brw_context
*brw
,
3099 struct intel_mipmap_tree
*mt
,
3100 struct intel_miptree_map
*map
,
3104 struct gl_context
*ctx
= &brw
->ctx
;
3106 intel_miptree_unmap_raw(map
->linear_mt
);
3108 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3109 bool ok
= intel_miptree_copy(brw
,
3110 map
->linear_mt
, 0, 0, 0, 0,
3111 mt
, level
, slice
, map
->x
, map
->y
,
3113 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3116 intel_miptree_release(&map
->linear_mt
);
3120 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3122 #if defined(USE_SSE41)
3124 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3125 struct intel_mipmap_tree
*mt
,
3126 struct intel_miptree_map
*map
,
3127 unsigned int level
, unsigned int slice
)
3129 assert(map
->mode
& GL_MAP_READ_BIT
);
3130 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3132 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3133 map
->x
, map
->y
, map
->w
, map
->h
,
3134 mt
, _mesa_get_format_name(mt
->format
),
3135 level
, slice
, map
->ptr
, map
->stride
);
3137 /* Map the original image */
3140 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3144 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3150 src
+= image_y
* mt
->surf
.row_pitch
;
3151 src
+= image_x
* mt
->cpp
;
3153 /* Due to the pixel offsets for the particular image being mapped, our
3154 * src pointer may not be 16-byte aligned. However, if the pitch is
3155 * divisible by 16, then the amount by which it's misaligned will remain
3156 * consistent from row to row.
3158 assert((mt
->surf
.row_pitch
% 16) == 0);
3159 const int misalignment
= ((uintptr_t) src
) & 15;
3161 /* Create an untiled temporary buffer for the mapping. */
3162 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3164 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3166 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3167 /* Offset the destination so it has the same misalignment as src. */
3168 map
->ptr
= map
->buffer
+ misalignment
;
3170 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3172 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3173 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3174 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3176 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3179 intel_miptree_unmap_raw(mt
);
3183 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3184 struct intel_mipmap_tree
*mt
,
3185 struct intel_miptree_map
*map
,
3189 _mesa_align_free(map
->buffer
);
3196 intel_miptree_map_s8(struct brw_context
*brw
,
3197 struct intel_mipmap_tree
*mt
,
3198 struct intel_miptree_map
*map
,
3199 unsigned int level
, unsigned int slice
)
3201 map
->stride
= map
->w
;
3202 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3206 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3207 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3208 * invalidate is set, since we'll be writing the whole rectangle from our
3209 * temporary buffer back out.
3211 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3212 uint8_t *untiled_s8_map
= map
->ptr
;
3213 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3214 unsigned int image_x
, image_y
;
3216 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3218 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3219 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3220 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3221 x
+ image_x
+ map
->x
,
3222 y
+ image_y
+ map
->y
,
3223 brw
->has_swizzling
);
3224 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3228 intel_miptree_unmap_raw(mt
);
3230 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3231 map
->x
, map
->y
, map
->w
, map
->h
,
3232 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3234 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3235 map
->x
, map
->y
, map
->w
, map
->h
,
3236 mt
, map
->ptr
, map
->stride
);
3241 intel_miptree_unmap_s8(struct brw_context
*brw
,
3242 struct intel_mipmap_tree
*mt
,
3243 struct intel_miptree_map
*map
,
3247 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3248 unsigned int image_x
, image_y
;
3249 uint8_t *untiled_s8_map
= map
->ptr
;
3250 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3252 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3254 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3255 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3256 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3257 image_x
+ x
+ map
->x
,
3258 image_y
+ y
+ map
->y
,
3259 brw
->has_swizzling
);
3260 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3264 intel_miptree_unmap_raw(mt
);
3271 intel_miptree_map_etc(struct brw_context
*brw
,
3272 struct intel_mipmap_tree
*mt
,
3273 struct intel_miptree_map
*map
,
3277 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3278 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3279 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3282 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3283 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3285 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3286 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3287 map
->w
, map
->h
, 1));
3288 map
->ptr
= map
->buffer
;
3292 intel_miptree_unmap_etc(struct brw_context
*brw
,
3293 struct intel_mipmap_tree
*mt
,
3294 struct intel_miptree_map
*map
,
3300 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3305 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3306 + image_y
* mt
->surf
.row_pitch
3307 + image_x
* mt
->cpp
;
3309 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3310 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3311 map
->ptr
, map
->stride
,
3314 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3315 map
->ptr
, map
->stride
,
3316 map
->w
, map
->h
, mt
->etc_format
);
3318 intel_miptree_unmap_raw(mt
);
3323 * Mapping function for packed depth/stencil miptrees backed by real separate
3324 * miptrees for depth and stencil.
3326 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3327 * separate from the depth buffer. Yet at the GL API level, we have to expose
3328 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3329 * be able to map that memory for texture storage and glReadPixels-type
3330 * operations. We give Mesa core that access by mallocing a temporary and
3331 * copying the data between the actual backing store and the temporary.
3334 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3335 struct intel_mipmap_tree
*mt
,
3336 struct intel_miptree_map
*map
,
3337 unsigned int level
, unsigned int slice
)
3339 struct intel_mipmap_tree
*z_mt
= mt
;
3340 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3341 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3342 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3344 map
->stride
= map
->w
* packed_bpp
;
3345 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3349 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3350 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3351 * invalidate is set, since we'll be writing the whole rectangle from our
3352 * temporary buffer back out.
3354 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3355 uint32_t *packed_map
= map
->ptr
;
3356 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3357 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3358 unsigned int s_image_x
, s_image_y
;
3359 unsigned int z_image_x
, z_image_y
;
3361 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3362 &s_image_x
, &s_image_y
);
3363 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3364 &z_image_x
, &z_image_y
);
3366 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3367 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3368 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3369 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3372 brw
->has_swizzling
);
3373 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3374 (z_mt
->surf
.row_pitch
/ 4) +
3375 (map_x
+ z_image_x
));
3376 uint8_t s
= s_map
[s_offset
];
3377 uint32_t z
= z_map
[z_offset
];
3379 if (map_z32f_x24s8
) {
3380 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3381 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3383 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3388 intel_miptree_unmap_raw(s_mt
);
3389 intel_miptree_unmap_raw(z_mt
);
3391 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3393 map
->x
, map
->y
, map
->w
, map
->h
,
3394 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3395 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3396 map
->ptr
, map
->stride
);
3398 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3399 map
->x
, map
->y
, map
->w
, map
->h
,
3400 mt
, map
->ptr
, map
->stride
);
3405 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3406 struct intel_mipmap_tree
*mt
,
3407 struct intel_miptree_map
*map
,
3411 struct intel_mipmap_tree
*z_mt
= mt
;
3412 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3413 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3415 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3416 uint32_t *packed_map
= map
->ptr
;
3417 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3418 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3419 unsigned int s_image_x
, s_image_y
;
3420 unsigned int z_image_x
, z_image_y
;
3422 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3423 &s_image_x
, &s_image_y
);
3424 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3425 &z_image_x
, &z_image_y
);
3427 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3428 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3429 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3430 x
+ s_image_x
+ map
->x
,
3431 y
+ s_image_y
+ map
->y
,
3432 brw
->has_swizzling
);
3433 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3434 (z_mt
->surf
.row_pitch
/ 4) +
3435 (x
+ z_image_x
+ map
->x
));
3437 if (map_z32f_x24s8
) {
3438 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3439 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3441 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3442 s_map
[s_offset
] = packed
>> 24;
3443 z_map
[z_offset
] = packed
;
3448 intel_miptree_unmap_raw(s_mt
);
3449 intel_miptree_unmap_raw(z_mt
);
3451 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3453 map
->x
, map
->y
, map
->w
, map
->h
,
3454 z_mt
, _mesa_get_format_name(z_mt
->format
),
3455 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3456 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3457 map
->ptr
, map
->stride
);
3464 * Create and attach a map to the miptree at (level, slice). Return the
3467 static struct intel_miptree_map
*
3468 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3477 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3482 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3483 mt
->level
[level
].slice
[slice
].map
= map
;
3495 * Release the map at (level, slice).
3498 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3502 struct intel_miptree_map
**map
;
3504 map
= &mt
->level
[level
].slice
[slice
].map
;
3510 can_blit_slice(struct intel_mipmap_tree
*mt
,
3511 unsigned int level
, unsigned int slice
)
3513 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3514 if (mt
->surf
.row_pitch
>= 32768)
3521 use_intel_mipree_map_blit(struct brw_context
*brw
,
3522 struct intel_mipmap_tree
*mt
,
3528 /* It's probably not worth swapping to the blit ring because of
3529 * all the overhead involved.
3531 !(mode
& GL_MAP_WRITE_BIT
) &&
3533 (mt
->surf
.tiling
== ISL_TILING_X
||
3534 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3535 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3536 /* Fast copy blit on skl+ supports all tiling formats. */
3538 can_blit_slice(mt
, level
, slice
))
3541 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3542 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3543 assert(can_blit_slice(mt
, level
, slice
));
3551 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3552 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3553 * arithmetic overflow.
3555 * If you call this function and use \a out_stride, then you're doing pointer
3556 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3557 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3558 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3559 * which usually have type uint32_t or GLuint.
3562 intel_miptree_map(struct brw_context
*brw
,
3563 struct intel_mipmap_tree
*mt
,
3572 ptrdiff_t *out_stride
)
3574 struct intel_miptree_map
*map
;
3576 assert(mt
->surf
.samples
== 1);
3578 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3585 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3586 map
->mode
& GL_MAP_WRITE_BIT
);
3588 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3589 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3590 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3591 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3592 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3593 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3594 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3595 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3596 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3597 #if defined(USE_SSE41)
3598 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3599 !mt
->compressed
&& cpu_has_sse4_1
&&
3600 (mt
->surf
.row_pitch
% 16 == 0)) {
3601 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3604 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3607 *out_ptr
= map
->ptr
;
3608 *out_stride
= map
->stride
;
3610 if (map
->ptr
== NULL
)
3611 intel_miptree_release_map(mt
, level
, slice
);
3615 intel_miptree_unmap(struct brw_context
*brw
,
3616 struct intel_mipmap_tree
*mt
,
3620 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3622 assert(mt
->surf
.samples
== 1);
3627 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3628 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3630 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3631 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3632 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3633 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3634 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3635 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3636 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3637 } else if (map
->linear_mt
) {
3638 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3639 #if defined(USE_SSE41)
3640 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3641 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3644 intel_miptree_unmap_gtt(mt
);
3647 intel_miptree_release_map(mt
, level
, slice
);
3651 get_isl_surf_dim(GLenum target
)
3655 case GL_TEXTURE_1D_ARRAY
:
3656 return ISL_SURF_DIM_1D
;
3659 case GL_TEXTURE_2D_ARRAY
:
3660 case GL_TEXTURE_RECTANGLE
:
3661 case GL_TEXTURE_CUBE_MAP
:
3662 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3663 case GL_TEXTURE_2D_MULTISAMPLE
:
3664 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3665 case GL_TEXTURE_EXTERNAL_OES
:
3666 return ISL_SURF_DIM_2D
;
3669 return ISL_SURF_DIM_3D
;
3672 unreachable("Invalid texture target");
3676 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3677 enum isl_tiling tiling
, GLenum target
,
3678 enum miptree_array_layout array_layout
)
3680 if (array_layout
== GEN6_HIZ_STENCIL
)
3681 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3685 case GL_TEXTURE_1D_ARRAY
:
3686 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3687 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3690 case GL_TEXTURE_2D_ARRAY
:
3691 case GL_TEXTURE_RECTANGLE
:
3692 case GL_TEXTURE_2D_MULTISAMPLE
:
3693 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3694 case GL_TEXTURE_EXTERNAL_OES
:
3695 return ISL_DIM_LAYOUT_GEN4_2D
;
3697 case GL_TEXTURE_CUBE_MAP
:
3698 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3699 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3700 ISL_DIM_LAYOUT_GEN4_2D
);
3703 return (devinfo
->gen
>= 9 ?
3704 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3707 unreachable("Invalid texture target");
3711 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3713 if (mt
->format
== MESA_FORMAT_S_UINT8
)
3714 return ISL_TILING_W
;
3715 return mt
->surf
.tiling
;
3719 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3720 const struct intel_mipmap_tree
*mt
,
3721 struct isl_surf
*surf
)
3723 surf
->dim
= get_isl_surf_dim(mt
->target
);
3724 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3725 mt
->surf
.tiling
, mt
->target
,
3727 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3728 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3729 surf
->row_pitch
= mt
->surf
.row_pitch
;
3730 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3732 if (brw
->gen
>= 9) {
3733 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3734 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3735 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3737 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3738 * alignment in terms of surface elements like we want.
3740 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3743 /* On earlier gens it's stored in pixels. */
3745 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3746 surf
->image_alignment_el
=
3747 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3750 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3751 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3752 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3753 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3754 surf
->logical_level0_px
.array_len
= 1;
3756 surf
->logical_level0_px
.depth
= 1;
3757 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3760 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3761 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3762 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3763 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3764 surf
->phys_level0_sa
.array_len
= 1;
3766 surf
->phys_level0_sa
.depth
= 1;
3767 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3770 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3771 surf
->samples
= mt
->surf
.samples
;
3773 surf
->size
= 0; /* TODO */
3774 surf
->alignment
= 0; /* TODO */
3776 switch (surf
->dim_layout
) {
3777 case ISL_DIM_LAYOUT_GEN4_2D
:
3778 case ISL_DIM_LAYOUT_GEN4_3D
:
3779 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3780 if (brw
->gen
>= 9) {
3781 surf
->array_pitch_el_rows
= mt
->qpitch
;
3784 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3785 assert(mt
->qpitch
% bh
== 0);
3786 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3789 case ISL_DIM_LAYOUT_GEN9_1D
:
3790 surf
->array_pitch_el_rows
= 1;
3794 switch (mt
->array_layout
) {
3795 case ALL_LOD_IN_EACH_SLICE
:
3796 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3798 case ALL_SLICES_AT_EACH_LOD
:
3799 case GEN6_HIZ_STENCIL
:
3800 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3803 unreachable("Invalid array layout");
3806 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3807 switch (base_format
) {
3808 case GL_DEPTH_COMPONENT
:
3809 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3811 case GL_STENCIL_INDEX
:
3812 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3814 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3816 case GL_DEPTH_STENCIL
:
3817 /* In this case we only texture from the depth part */
3818 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3819 ISL_SURF_USAGE_TEXTURE_BIT
;
3822 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3823 if (brw
->mesa_format_supports_render
[mt
->format
])
3824 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3828 if (_mesa_is_cube_map_texture(mt
->target
))
3829 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3833 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3834 const struct intel_mipmap_tree
*mt
)
3837 return ISL_AUX_USAGE_HIZ
;
3840 return ISL_AUX_USAGE_NONE
;
3842 return mt
->aux_usage
;