2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 uint32_t layout_flags
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
107 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
108 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
110 * - Support is limited to tiled render targets.
112 * Gen9 changes the restriction to Y-tile only.
115 return tiling
== I915_TILING_Y
;
116 else if (brw
->gen
>= 7)
117 return tiling
!= I915_TILING_NONE
;
123 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
124 * can be used. This doesn't (and should not) inspect any of the properties of
127 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
128 * beneath the "Fast Color Clear" bullet (p326):
130 * - Support is for non-mip-mapped and non-array surface types only.
132 * And then later, on p327:
134 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
137 * From the Skylake documentation, it is made clear that X-tiling is no longer
140 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
144 intel_miptree_supports_ccs(struct brw_context
*brw
,
145 const struct intel_mipmap_tree
*mt
)
147 /* MCS support does not exist prior to Gen7 */
151 /* This function applies only to non-multisampled render targets. */
152 if (mt
->num_samples
> 1)
155 /* MCS is only supported for color buffers */
156 switch (_mesa_get_format_base_format(mt
->format
)) {
157 case GL_DEPTH_COMPONENT
:
158 case GL_DEPTH_STENCIL
:
159 case GL_STENCIL_INDEX
:
163 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
166 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
167 const bool arrayed
= mt
->physical_depth0
!= 1;
170 /* Multisample surfaces with the CMS layout are not layered surfaces,
171 * yet still have physical_depth0 > 1. Assert that we don't
172 * accidentally reject a multisampled surface here. We should have
173 * rejected it earlier by explicitly checking the sample count.
175 assert(mt
->num_samples
<= 1);
178 /* Handle the hardware restrictions...
180 * All GENs have the following restriction: "MCS buffer for non-MSRT is
181 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
183 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
184 * Non-MultiSampler Render Target Restrictions) Support is for
185 * non-mip-mapped and non-array surface types only.
187 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
188 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
189 * surfaces are supported with MCS buffer layout with these alignments in
190 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
192 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
193 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
194 * surfaces are supported with MCS buffer layout with these alignments in
195 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
197 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
200 /* There's no point in using an MCS buffer if the surface isn't in a
203 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
208 const enum isl_format isl_format
=
209 brw_isl_format_for_mesa_format(linear_format
);
210 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
216 intel_miptree_supports_hiz(struct brw_context
*brw
,
217 struct intel_mipmap_tree
*mt
)
222 switch (mt
->format
) {
223 case MESA_FORMAT_Z_FLOAT32
:
224 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
225 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
226 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
227 case MESA_FORMAT_Z_UNORM16
:
235 /* On Gen9 support for color buffer compression was extended to single
236 * sampled surfaces. This is a helper considering both auxiliary buffer
237 * type and number of samples telling if the given miptree represents
238 * the new single sampled case - also called lossless compression.
241 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
242 const struct intel_mipmap_tree
*mt
)
244 /* Only available from Gen9 onwards. */
248 /* Compression always requires auxiliary buffer. */
252 /* Single sample compression is represented re-using msaa compression
253 * layout type: "Compressed Multisampled Surfaces".
255 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
258 /* And finally distinguish between msaa and single sample case. */
259 return mt
->num_samples
<= 1;
263 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
264 const struct intel_mipmap_tree
*mt
)
266 /* For now compression is only enabled for integer formats even though
267 * there exist supported floating point formats also. This is a heuristic
268 * decision based on current public benchmarks. In none of the cases these
269 * formats provided any improvement but a few cases were seen to regress.
270 * Hence these are left to to be enabled in the future when they are known
273 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
276 if (!intel_miptree_supports_ccs(brw
, mt
))
279 /* Fast clear can be also used to clear srgb surfaces by using equivalent
280 * linear format. This trick, however, can't be extended to be used with
281 * lossless compression and therefore a check is needed to see if the format
284 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
288 * Determine depth format corresponding to a depth+stencil format,
289 * for separate stencil.
292 intel_depth_format_for_depthstencil_format(mesa_format format
) {
294 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
295 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
296 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
297 return MESA_FORMAT_Z_FLOAT32
;
304 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
305 unsigned depth0
, struct intel_mipmap_level
*table
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
309 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
311 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
312 if (!table
[level
].slice
)
319 for (unsigned level
= first_level
; level
<= last_level
; level
++)
320 free(table
[level
].slice
);
326 * @param for_bo Indicates that the caller is
327 * intel_miptree_create_for_bo(). If true, then do not create
330 static struct intel_mipmap_tree
*
331 intel_miptree_create_layout(struct brw_context
*brw
,
340 uint32_t layout_flags
)
342 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
346 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
347 _mesa_enum_to_string(target
),
348 _mesa_get_format_name(format
),
349 first_level
, last_level
, depth0
, mt
);
351 if (target
== GL_TEXTURE_1D_ARRAY
)
352 assert(height0
== 1);
356 mt
->first_level
= first_level
;
357 mt
->last_level
= last_level
;
358 mt
->logical_width0
= width0
;
359 mt
->logical_height0
= height0
;
360 mt
->logical_depth0
= depth0
;
361 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
362 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
363 mt
->supports_fast_clear
= false;
364 mt
->aux_state
= NULL
;
365 mt
->cpp
= _mesa_get_format_bytes(format
);
366 mt
->num_samples
= num_samples
;
367 mt
->compressed
= _mesa_is_format_compressed(format
);
368 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
371 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
372 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
374 int depth_multiply
= 1;
375 if (num_samples
> 1) {
376 /* Adjust width/height/depth for MSAA */
377 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
378 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
379 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
380 * "If the surface is multisampled and it is a depth or stencil
381 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
382 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
385 * +----------------------------------------------------------------+
386 * | Num Multisamples | W_l = | H_l = |
387 * +----------------------------------------------------------------+
388 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
389 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
390 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
391 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
392 * +----------------------------------------------------------------+
395 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
396 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
397 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
399 * Another more complicated explanation for these adjustments comes
400 * from the Sandybridge PRM, volume 4, part 1, page 31:
402 * "Any of the other messages (sample*, LOD, load4) used with a
403 * (4x) multisampled surface will in-effect sample a surface with
404 * double the height and width as that indicated in the surface
405 * state. Each pixel position on the original-sized surface is
406 * replaced with a 2x2 of samples with the following arrangement:
411 * Thus, when sampling from a multisampled texture, it behaves as
412 * though the layout in memory for (x,y,sample) is:
414 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
415 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
417 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
418 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
420 * However, the actual layout of multisampled data in memory is:
422 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
423 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
425 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
426 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
428 * This pattern repeats for each 2x2 pixel block.
430 * As a result, when calculating the size of our 4-sample buffer for
431 * an odd width or height, we have to align before scaling up because
432 * sample 3 is in that bottom right 2x2 block.
434 switch (num_samples
) {
436 assert(brw
->gen
>= 8);
437 width0
= ALIGN(width0
, 2) * 2;
438 height0
= ALIGN(height0
, 2);
441 width0
= ALIGN(width0
, 2) * 2;
442 height0
= ALIGN(height0
, 2) * 2;
445 width0
= ALIGN(width0
, 2) * 4;
446 height0
= ALIGN(height0
, 2) * 2;
449 width0
= ALIGN(width0
, 2) * 4;
450 height0
= ALIGN(height0
, 2) * 4;
453 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
456 unreachable("not reached");
459 /* Non-interleaved */
460 depth_multiply
= num_samples
;
461 depth0
*= depth_multiply
;
465 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
471 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
472 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
473 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
474 * used on Gen8 to make it pick a qpitch value which doesn't include space
475 * for the mipmaps. On Gen9 this is not necessary because it will
476 * automatically pick a packed qpitch value whenever mt->first_level ==
478 * TODO: can we use it elsewhere?
479 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
482 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
484 switch (mt
->msaa_layout
) {
485 case INTEL_MSAA_LAYOUT_NONE
:
486 case INTEL_MSAA_LAYOUT_IMS
:
487 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
489 case INTEL_MSAA_LAYOUT_UMS
:
490 case INTEL_MSAA_LAYOUT_CMS
:
491 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
496 if (target
== GL_TEXTURE_CUBE_MAP
)
497 assert(depth0
== 6 * depth_multiply
);
499 mt
->physical_width0
= width0
;
500 mt
->physical_height0
= height0
;
501 mt
->physical_depth0
= depth0
;
503 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
504 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
505 (brw
->must_use_separate_stencil
||
506 (brw
->has_separate_stencil
&& intel_miptree_supports_hiz(brw
, mt
)))) {
507 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
509 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
512 mt
->stencil_mt
= intel_miptree_create(brw
,
523 if (!mt
->stencil_mt
) {
524 intel_miptree_release(&mt
);
527 mt
->stencil_mt
->r8stencil_needs_update
= true;
529 /* Fix up the Z miptree format for how we're splitting out separate
530 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
532 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
535 if (format
== mt
->format
) {
536 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
537 _mesa_get_format_name(mt
->format
));
541 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
542 mt
->array_layout
= GEN6_HIZ_STENCIL
;
545 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
546 * multisampled or have an AUX buffer attached to it.
548 * GEN | MSRT | AUX_CCS_* or AUX_MCS
549 * -------------------------------------------
550 * 9 | HALIGN_16 | HALIGN_16
551 * 8 | HALIGN_ANY | HALIGN_16
555 if (intel_miptree_supports_ccs(brw
, mt
)) {
556 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
557 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
558 } else if (brw
->gen
>= 9 && num_samples
> 1) {
559 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
561 const UNUSED
bool is_lossless_compressed_aux
=
562 brw
->gen
>= 9 && num_samples
== 1 &&
563 mt
->format
== MESA_FORMAT_R_UINT32
;
565 /* For now, nothing else has this requirement */
566 assert(is_lossless_compressed_aux
||
567 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
570 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
571 intel_miptree_release(&mt
);
580 * Choose the aux usage for this miptree. This function must be called fairly
581 * late in the miptree create process after we have a tiling.
584 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
585 struct intel_mipmap_tree
*mt
)
587 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
589 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
590 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
591 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
592 intel_miptree_supports_ccs(brw
, mt
)) {
593 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
594 brw
->gen
>= 9 && !mt
->is_scanout
&&
595 intel_miptree_supports_ccs_e(brw
, mt
)) {
596 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
598 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
600 } else if (intel_miptree_supports_hiz(brw
, mt
)) {
601 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
604 /* We can do fast-clear on all auxiliary surface types that are
605 * allocated through the normal texture creation paths.
607 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
608 mt
->supports_fast_clear
= true;
613 * Choose an appropriate uncompressed format for a requested
614 * compressed format, if unsupported.
617 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
619 /* No need to lower ETC formats on these platforms,
620 * they are supported natively.
622 if (brw
->gen
>= 8 || brw
->is_baytrail
)
626 case MESA_FORMAT_ETC1_RGB8
:
627 return MESA_FORMAT_R8G8B8X8_UNORM
;
628 case MESA_FORMAT_ETC2_RGB8
:
629 return MESA_FORMAT_R8G8B8X8_UNORM
;
630 case MESA_FORMAT_ETC2_SRGB8
:
631 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
632 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
633 return MESA_FORMAT_B8G8R8A8_SRGB
;
634 case MESA_FORMAT_ETC2_RGBA8_EAC
:
635 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
636 return MESA_FORMAT_R8G8B8A8_UNORM
;
637 case MESA_FORMAT_ETC2_R11_EAC
:
638 return MESA_FORMAT_R_UNORM16
;
639 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
640 return MESA_FORMAT_R_SNORM16
;
641 case MESA_FORMAT_ETC2_RG11_EAC
:
642 return MESA_FORMAT_R16G16_UNORM
;
643 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
644 return MESA_FORMAT_R16G16_SNORM
;
646 /* Non ETC1 / ETC2 format */
651 /** \brief Assert that the level and layer are valid for the miptree. */
653 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
661 assert(level
>= mt
->first_level
);
662 assert(level
<= mt
->last_level
);
664 if (mt
->surf
.size
> 0)
665 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
666 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
667 mt
->surf
.phys_level0_sa
.array_len
));
669 assert(layer
< mt
->level
[level
].depth
);
672 static enum isl_aux_state
**
673 create_aux_state_map(struct intel_mipmap_tree
*mt
,
674 enum isl_aux_state initial
)
676 const uint32_t levels
= mt
->last_level
+ 1;
678 uint32_t total_slices
= 0;
679 for (uint32_t level
= 0; level
< levels
; level
++)
680 total_slices
+= mt
->level
[level
].depth
;
682 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
684 /* We're going to allocate a single chunk of data for both the per-level
685 * reference array and the arrays of aux_state. This makes cleanup
686 * significantly easier.
688 const size_t total_size
= per_level_array_size
+
689 total_slices
* sizeof(enum isl_aux_state
);
690 void *data
= malloc(total_size
);
694 enum isl_aux_state
**per_level_arr
= data
;
695 enum isl_aux_state
*s
= data
+ per_level_array_size
;
696 for (uint32_t level
= 0; level
< levels
; level
++) {
697 per_level_arr
[level
] = s
;
698 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
701 assert((void *)s
== data
+ total_size
);
703 return per_level_arr
;
707 free_aux_state_map(enum isl_aux_state
**state
)
712 static struct intel_mipmap_tree
*
713 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
714 unsigned first_level
, unsigned last_level
,
715 unsigned width0
, unsigned height0
, unsigned depth0
,
716 unsigned num_samples
, enum isl_tiling isl_tiling
,
717 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
720 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
724 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
730 if (target
== GL_TEXTURE_CUBE_MAP
||
731 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
732 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
734 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
736 _mesa_enum_to_string(target
),
737 _mesa_get_format_name(format
),
738 num_samples
, width0
, height0
, depth0
,
739 first_level
, last_level
, mt
);
741 struct isl_surf_init_info init_info
= {
742 .dim
= get_isl_surf_dim(target
),
743 .format
= translate_tex_format(brw
, format
, false),
746 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
747 .levels
= last_level
- first_level
+ 1,
748 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
749 .samples
= MAX2(num_samples
, 1),
750 .usage
= isl_usage_flags
,
751 .tiling_flags
= 1u << isl_tiling
754 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
757 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
760 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
762 isl_tiling_to_bufmgr_tiling(isl_tiling
),
763 mt
->surf
.row_pitch
, alloc_flags
);
770 mt
->first_level
= first_level
;
771 mt
->last_level
= last_level
;
775 mt
->aux_state
= NULL
;
780 intel_miptree_release(&mt
);
784 static struct intel_mipmap_tree
*
785 miptree_create(struct brw_context
*brw
,
794 uint32_t layout_flags
)
796 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
797 return make_surface(brw
, target
, format
, first_level
, last_level
,
798 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
799 ISL_SURF_USAGE_STENCIL_BIT
|
800 ISL_SURF_USAGE_TEXTURE_BIT
,
801 BO_ALLOC_FOR_RENDER
, NULL
);
803 struct intel_mipmap_tree
*mt
;
804 mesa_format tex_format
= format
;
805 mesa_format etc_format
= MESA_FORMAT_NONE
;
806 uint32_t alloc_flags
= 0;
808 format
= intel_lower_compressed_format(brw
, format
);
810 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
812 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
813 mt
= intel_miptree_create_layout(brw
, target
, format
,
814 first_level
, last_level
, width0
,
815 height0
, depth0
, num_samples
,
820 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
821 mt
->tiling
= I915_TILING_Y
;
823 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
824 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
826 mt
->etc_format
= etc_format
;
828 if (format
== MESA_FORMAT_S_UINT8
) {
829 /* Align to size of W tile, 64x64. */
830 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
831 ALIGN(mt
->total_width
, 64),
832 ALIGN(mt
->total_height
, 64),
833 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
836 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
837 mt
->total_width
, mt
->total_height
,
838 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
842 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
843 mt
->bo
->cache_coherent
= false;
845 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
846 intel_miptree_choose_aux_usage(brw
, mt
);
851 struct intel_mipmap_tree
*
852 intel_miptree_create(struct brw_context
*brw
,
861 uint32_t layout_flags
)
863 struct intel_mipmap_tree
*mt
= miptree_create(
865 first_level
, last_level
,
866 width0
, height0
, depth0
, num_samples
,
869 /* If the BO is too large to fit in the aperture, we need to use the
870 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
871 * handle Y-tiling, so we need to fall back to X.
873 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
874 mt
->tiling
== I915_TILING_Y
) {
875 const uint32_t alloc_flags
=
876 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
877 BO_ALLOC_FOR_RENDER
: 0;
878 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
879 mt
->total_width
, mt
->total_height
);
881 mt
->tiling
= I915_TILING_X
;
882 brw_bo_unreference(mt
->bo
);
883 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
884 mt
->total_width
, mt
->total_height
, mt
->cpp
,
885 mt
->tiling
, &mt
->pitch
, alloc_flags
);
891 intel_miptree_release(&mt
);
896 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
897 assert(mt
->num_samples
> 1);
898 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
899 intel_miptree_release(&mt
);
904 /* Since CCS_E can compress more than just clear color, we create the CCS
905 * for it up-front. For CCS_D which only compresses clears, we create the
906 * CCS on-demand when a clear occurs that wants one.
908 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
909 if (!intel_miptree_alloc_ccs(brw
, mt
)) {
910 intel_miptree_release(&mt
);
918 struct intel_mipmap_tree
*
919 intel_miptree_create_for_bo(struct brw_context
*brw
,
927 uint32_t layout_flags
)
929 struct intel_mipmap_tree
*mt
;
930 uint32_t tiling
, swizzle
;
931 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
933 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
934 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
935 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
936 ISL_SURF_USAGE_STENCIL_BIT
|
937 ISL_SURF_USAGE_TEXTURE_BIT
,
938 BO_ALLOC_FOR_RENDER
, bo
);
942 assert(bo
->size
>= mt
->surf
.size
);
944 brw_bo_reference(bo
);
948 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
950 /* Nothing will be able to use this miptree with the BO if the offset isn't
953 if (tiling
!= I915_TILING_NONE
)
954 assert(offset
% 4096 == 0);
956 /* miptrees can't handle negative pitch. If you need flipping of images,
957 * that's outside of the scope of the mt.
961 /* The BO already has a tiling format and we shouldn't confuse the lower
962 * layers by making it try to find a tiling format again.
964 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
965 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
967 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
968 mt
= intel_miptree_create_layout(brw
, target
, format
,
970 width
, height
, depth
, 0,
975 brw_bo_reference(bo
);
981 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
)) {
982 intel_miptree_choose_aux_usage(brw
, mt
);
984 /* Since CCS_E can compress more than just clear color, we create the
985 * CCS for it up-front. For CCS_D which only compresses clears, we
986 * create the CCS on-demand when a clear occurs that wants one.
988 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
989 if (!intel_miptree_alloc_ccs(brw
, mt
)) {
990 intel_miptree_release(&mt
);
1000 * For a singlesample renderbuffer, this simply wraps the given BO with a
1003 * For a multisample renderbuffer, this wraps the window system's
1004 * (singlesample) BO with a singlesample miptree attached to the
1005 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1006 * that will contain the actual rendering (which is lazily resolved to
1007 * irb->singlesample_mt).
1010 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1011 struct intel_renderbuffer
*irb
,
1013 uint32_t width
, uint32_t height
,
1016 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
1017 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1018 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1019 mesa_format format
= rb
->Format
;
1020 int num_samples
= rb
->NumSamples
;
1022 /* Only the front and back buffers, which are color buffers, are allocated
1023 * through the image loader.
1025 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1026 _mesa_get_format_base_format(format
) == GL_RGBA
);
1028 singlesample_mt
= intel_miptree_create_for_bo(intel
,
1036 MIPTREE_LAYOUT_FOR_SCANOUT
);
1037 if (!singlesample_mt
)
1040 if (num_samples
== 0) {
1041 intel_miptree_release(&irb
->mt
);
1042 irb
->mt
= singlesample_mt
;
1044 assert(!irb
->singlesample_mt
);
1046 intel_miptree_release(&irb
->singlesample_mt
);
1047 irb
->singlesample_mt
= singlesample_mt
;
1050 irb
->mt
->logical_width0
!= width
||
1051 irb
->mt
->logical_height0
!= height
) {
1052 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1057 if (!multisample_mt
)
1060 irb
->need_downsample
= false;
1061 intel_miptree_release(&irb
->mt
);
1062 irb
->mt
= multisample_mt
;
1068 intel_miptree_release(&irb
->singlesample_mt
);
1069 intel_miptree_release(&irb
->mt
);
1073 struct intel_mipmap_tree
*
1074 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1078 uint32_t num_samples
)
1080 struct intel_mipmap_tree
*mt
;
1083 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1084 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1085 MIPTREE_LAYOUT_TILING_ANY
|
1086 MIPTREE_LAYOUT_FOR_SCANOUT
;
1088 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1089 width
, height
, depth
, num_samples
,
1094 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1095 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1103 intel_miptree_release(&mt
);
1108 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1109 struct intel_mipmap_tree
*src
)
1114 intel_miptree_release(dst
);
1118 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1125 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1127 if (aux_buf
== NULL
)
1130 brw_bo_unreference(aux_buf
->bo
);
1136 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1141 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1142 if (--(*mt
)->refcount
<= 0) {
1145 DBG("%s deleting %p\n", __func__
, *mt
);
1147 brw_bo_unreference((*mt
)->bo
);
1148 intel_miptree_release(&(*mt
)->stencil_mt
);
1149 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1150 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1151 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1152 free_aux_state_map((*mt
)->aux_state
);
1154 intel_miptree_release(&(*mt
)->plane
[0]);
1155 intel_miptree_release(&(*mt
)->plane
[1]);
1157 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1158 free((*mt
)->level
[i
].slice
);
1168 intel_get_image_dims(struct gl_texture_image
*image
,
1169 int *width
, int *height
, int *depth
)
1171 switch (image
->TexObject
->Target
) {
1172 case GL_TEXTURE_1D_ARRAY
:
1173 /* For a 1D Array texture the OpenGL API will treat the image height as
1174 * the number of array slices. For Intel hardware, we treat the 1D array
1175 * as a 2D Array with a height of 1. So, here we want to swap image
1178 assert(image
->Depth
== 1);
1179 *width
= image
->Width
;
1181 *depth
= image
->Height
;
1183 case GL_TEXTURE_CUBE_MAP
:
1184 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1185 * though we really have 6 slices.
1187 assert(image
->Depth
== 1);
1188 *width
= image
->Width
;
1189 *height
= image
->Height
;
1193 *width
= image
->Width
;
1194 *height
= image
->Height
;
1195 *depth
= image
->Depth
;
1201 * Can the image be pulled into a unified mipmap tree? This mirrors
1202 * the completeness test in a lot of ways.
1204 * Not sure whether I want to pass gl_texture_image here.
1207 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1208 struct gl_texture_image
*image
)
1210 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1211 GLuint level
= intelImage
->base
.Base
.Level
;
1212 int width
, height
, depth
;
1214 /* glTexImage* choose the texture object based on the target passed in, and
1215 * objects can't change targets over their lifetimes, so this should be
1218 assert(image
->TexObject
->Target
== mt
->target
);
1220 mesa_format mt_format
= mt
->format
;
1221 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1222 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1223 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1224 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1225 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1226 mt_format
= mt
->etc_format
;
1228 if (image
->TexFormat
!= mt_format
)
1231 intel_get_image_dims(image
, &width
, &height
, &depth
);
1233 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1236 if (mt
->surf
.size
> 0) {
1237 if (level
>= mt
->surf
.levels
)
1240 const unsigned level_depth
=
1241 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1242 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1243 mt
->surf
.logical_level0_px
.array_len
;
1245 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1246 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1247 depth
== level_depth
&&
1248 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1251 int level_depth
= mt
->level
[level
].depth
;
1252 if (mt
->num_samples
> 1) {
1253 switch (mt
->msaa_layout
) {
1254 case INTEL_MSAA_LAYOUT_NONE
:
1255 case INTEL_MSAA_LAYOUT_IMS
:
1257 case INTEL_MSAA_LAYOUT_UMS
:
1258 case INTEL_MSAA_LAYOUT_CMS
:
1259 level_depth
/= mt
->num_samples
;
1264 /* Test image dimensions against the base level image adjusted for
1265 * minification. This will also catch images not present in the
1266 * tree, changed targets, etc.
1268 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1269 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1270 depth
!= level_depth
) {
1274 if (image
->NumSamples
!= mt
->num_samples
)
1282 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1284 GLuint x
, GLuint y
, GLuint d
)
1286 mt
->level
[level
].depth
= d
;
1287 mt
->level
[level
].level_x
= x
;
1288 mt
->level
[level
].level_y
= y
;
1290 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1293 assert(mt
->level
[level
].slice
);
1295 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1296 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1301 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1302 GLuint level
, GLuint img
,
1305 if (img
== 0 && level
== 0)
1306 assert(x
== 0 && y
== 0);
1308 assert(img
< mt
->level
[level
].depth
);
1310 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1311 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1313 DBG("%s level %d img %d pos %d,%d\n",
1314 __func__
, level
, img
,
1315 mt
->level
[level
].slice
[img
].x_offset
,
1316 mt
->level
[level
].slice
[img
].y_offset
);
1320 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1321 GLuint level
, GLuint slice
,
1322 GLuint
*x
, GLuint
*y
)
1324 if (mt
->surf
.size
> 0) {
1325 uint32_t x_offset_sa
, y_offset_sa
;
1327 /* Given level is relative to level zero while the miptree may be
1328 * represent just a subset of all levels starting from 'first_level'.
1330 assert(level
>= mt
->first_level
);
1331 level
-= mt
->first_level
;
1333 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1334 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1335 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1336 &x_offset_sa
, &y_offset_sa
);
1343 assert(slice
< mt
->level
[level
].depth
);
1345 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1346 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1351 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1352 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1353 * and tile_h is set to 1.
1356 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1357 uint32_t *tile_w
, uint32_t *tile_h
)
1368 case I915_TILING_NONE
:
1373 unreachable("not reached");
1379 * This function computes masks that may be used to select the bits of the X
1380 * and Y coordinates that indicate the offset within a tile. If the BO is
1381 * untiled, the masks are set to 0.
1384 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1385 uint32_t *mask_x
, uint32_t *mask_y
)
1387 uint32_t tile_w_bytes
, tile_h
;
1389 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1391 *mask_x
= tile_w_bytes
/ cpp
- 1;
1392 *mask_y
= tile_h
- 1;
1396 * Compute the offset (in bytes) from the start of the BO to the given x
1397 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1398 * multiples of the tile size.
1401 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1402 uint32_t x
, uint32_t y
)
1405 uint32_t pitch
= mt
->pitch
;
1406 uint32_t tiling
= mt
->tiling
;
1410 unreachable("not reached");
1411 case I915_TILING_NONE
:
1412 return y
* pitch
+ x
* cpp
;
1414 assert((x
% (512 / cpp
)) == 0);
1415 assert((y
% 8) == 0);
1416 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1418 assert((x
% (128 / cpp
)) == 0);
1419 assert((y
% 32) == 0);
1420 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1425 * Rendering with tiled buffers requires that the base address of the buffer
1426 * be aligned to a page boundary. For renderbuffers, and sometimes with
1427 * textures, we may want the surface to point at a texture image level that
1428 * isn't at a page boundary.
1430 * This function returns an appropriately-aligned base offset
1431 * according to the tiling restrictions, plus any required x/y offset
1435 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1436 GLuint level
, GLuint slice
,
1441 uint32_t mask_x
, mask_y
;
1443 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1444 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1446 *tile_x
= x
& mask_x
;
1447 *tile_y
= y
& mask_y
;
1449 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1453 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1454 struct intel_mipmap_tree
*src_mt
,
1455 unsigned src_level
, unsigned src_layer
,
1456 struct intel_mipmap_tree
*dst_mt
,
1457 unsigned dst_level
, unsigned dst_layer
,
1458 unsigned width
, unsigned height
)
1461 ptrdiff_t src_stride
, dst_stride
;
1462 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1463 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1465 intel_miptree_map(brw
, src_mt
,
1466 src_level
, src_layer
,
1469 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1472 intel_miptree_map(brw
, dst_mt
,
1473 dst_level
, dst_layer
,
1476 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1480 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1481 _mesa_get_format_name(src_mt
->format
),
1482 src_mt
, src
, src_stride
,
1483 _mesa_get_format_name(dst_mt
->format
),
1484 dst_mt
, dst
, dst_stride
,
1487 int row_size
= cpp
* width
;
1488 if (src_stride
== row_size
&&
1489 dst_stride
== row_size
) {
1490 memcpy(dst
, src
, row_size
* height
);
1492 for (int i
= 0; i
< height
; i
++) {
1493 memcpy(dst
, src
, row_size
);
1499 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1500 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1502 /* Don't forget to copy the stencil data over, too. We could have skipped
1503 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1504 * shuffling the two data sources in/out of temporary storage instead of
1505 * the direct mapping we get this way.
1507 if (dst_mt
->stencil_mt
) {
1508 assert(src_mt
->stencil_mt
);
1509 intel_miptree_copy_slice_sw(brw
,
1510 src_mt
->stencil_mt
, src_level
, src_layer
,
1511 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1517 intel_miptree_copy_slice(struct brw_context
*brw
,
1518 struct intel_mipmap_tree
*src_mt
,
1519 unsigned src_level
, unsigned src_layer
,
1520 struct intel_mipmap_tree
*dst_mt
,
1521 unsigned dst_level
, unsigned dst_layer
)
1524 mesa_format format
= src_mt
->format
;
1525 uint32_t width
, height
;
1527 if (src_mt
->surf
.size
> 0) {
1528 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1529 src_level
- src_mt
->first_level
);
1530 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1531 src_level
- src_mt
->first_level
);
1533 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1534 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1535 src_level
- src_mt
->first_level
));
1537 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1539 width
= minify(src_mt
->physical_width0
,
1540 src_level
- src_mt
->first_level
);
1541 height
= minify(src_mt
->physical_height0
,
1542 src_level
- src_mt
->first_level
);
1543 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1546 assert(src_mt
->format
== dst_mt
->format
);
1548 if (dst_mt
->compressed
) {
1550 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1551 height
= ALIGN_NPOT(height
, j
) / j
;
1552 width
= ALIGN_NPOT(width
, i
) / i
;
1555 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1556 * below won't apply since we can't do the depth's Y tiling or the
1557 * stencil's W tiling in the blitter.
1559 if (src_mt
->stencil_mt
) {
1560 intel_miptree_copy_slice_sw(brw
,
1561 src_mt
, src_level
, src_layer
,
1562 dst_mt
, dst_level
, dst_layer
,
1567 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1568 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1570 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1573 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1574 _mesa_get_format_name(src_mt
->format
),
1575 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1576 _mesa_get_format_name(dst_mt
->format
),
1577 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1580 if (!intel_miptree_blit(brw
,
1581 src_mt
, src_level
, src_layer
, 0, 0, false,
1582 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1583 width
, height
, GL_COPY
)) {
1584 perf_debug("miptree validate blit for %s failed\n",
1585 _mesa_get_format_name(format
));
1587 intel_miptree_copy_slice_sw(brw
,
1588 src_mt
, src_level
, src_layer
,
1589 dst_mt
, dst_level
, dst_layer
,
1595 * Copies the image's current data to the given miptree, and associates that
1596 * miptree with the image.
1598 * If \c invalidate is true, then the actual image data does not need to be
1599 * copied, but the image still needs to be associated to the new miptree (this
1600 * is set to true if we're about to clear the image).
1603 intel_miptree_copy_teximage(struct brw_context
*brw
,
1604 struct intel_texture_image
*intelImage
,
1605 struct intel_mipmap_tree
*dst_mt
,
1608 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1609 struct intel_texture_object
*intel_obj
=
1610 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1611 int level
= intelImage
->base
.Base
.Level
;
1612 const unsigned face
= intelImage
->base
.Base
.Face
;
1613 unsigned start_layer
, end_layer
;
1615 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1617 assert(intelImage
->base
.Base
.Height
);
1619 end_layer
= intelImage
->base
.Base
.Height
- 1;
1620 } else if (face
> 0) {
1624 assert(intelImage
->base
.Base
.Depth
);
1626 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1630 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1631 intel_miptree_copy_slice(brw
,
1637 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1638 intel_obj
->needs_validate
= true;
1642 intel_miptree_init_mcs(struct brw_context
*brw
,
1643 struct intel_mipmap_tree
*mt
,
1646 assert(mt
->mcs_buf
!= NULL
);
1648 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1650 * When MCS buffer is enabled and bound to MSRT, it is required that it
1651 * is cleared prior to any rendering.
1653 * Since we don't use the MCS buffer for any purpose other than rendering,
1654 * it makes sense to just clear it immediately upon allocation.
1656 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1658 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1659 if (unlikely(map
== NULL
)) {
1660 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1661 brw_bo_unreference(mt
->mcs_buf
->bo
);
1666 memset(data
, init_value
, mt
->mcs_buf
->size
);
1667 brw_bo_unmap(mt
->mcs_buf
->bo
);
1670 static struct intel_miptree_aux_buffer
*
1671 intel_alloc_aux_buffer(struct brw_context
*brw
,
1673 const struct isl_surf
*aux_surf
,
1674 uint32_t alloc_flags
,
1675 struct intel_mipmap_tree
*mt
)
1677 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1681 buf
->size
= aux_surf
->size
;
1682 buf
->pitch
= aux_surf
->row_pitch
;
1683 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1685 /* ISL has stricter set of alignment rules then the drm allocator.
1686 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1687 * trying to recalculate based on different format block sizes.
1689 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1690 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1696 buf
->surf
= *aux_surf
;
1702 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1703 struct intel_mipmap_tree
*mt
,
1706 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1707 assert(mt
->mcs_buf
== NULL
);
1708 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1710 /* Multisampled miptrees are only supported for single level. */
1711 assert(mt
->first_level
== 0);
1712 enum isl_aux_state
**aux_state
=
1713 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1717 struct isl_surf temp_main_surf
;
1718 struct isl_surf temp_mcs_surf
;
1720 /* Create first an ISL presentation for the main color surface and let ISL
1721 * calculate equivalent MCS surface against it.
1723 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1724 MAYBE_UNUSED
bool ok
=
1725 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1728 /* Buffer needs to be initialised requiring the buffer to be immediately
1729 * mapped to cpu space for writing. Therefore do not use the gpu access
1730 * flag which can cause an unnecessary delay if the backing pages happened
1731 * to be just used by the GPU.
1733 const uint32_t alloc_flags
= 0;
1734 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1735 &temp_mcs_surf
, alloc_flags
, mt
);
1741 mt
->aux_state
= aux_state
;
1743 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1749 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1750 struct intel_mipmap_tree
*mt
)
1752 assert(mt
->mcs_buf
== NULL
);
1753 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1754 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1756 struct isl_surf temp_main_surf
;
1757 struct isl_surf temp_ccs_surf
;
1759 /* Create first an ISL presentation for the main color surface and let ISL
1760 * calculate equivalent CCS surface against it.
1762 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1763 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1766 assert(temp_ccs_surf
.size
&&
1767 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1769 enum isl_aux_state
**aux_state
=
1770 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1774 /* In case of compression mcs buffer needs to be initialised requiring the
1775 * buffer to be immediately mapped to cpu space for writing. Therefore do
1776 * not use the gpu access flag which can cause an unnecessary delay if the
1777 * backing pages happened to be just used by the GPU.
1779 const uint32_t alloc_flags
=
1780 mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
? 0 : BO_ALLOC_FOR_RENDER
;
1781 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1782 &temp_ccs_surf
, alloc_flags
, mt
);
1788 mt
->aux_state
= aux_state
;
1790 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1791 * used for lossless compression which requires similar initialisation
1792 * as multi-sample compression.
1794 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1795 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1796 * resolve. Initialize it accordingly in case the first renderer is
1797 * cpu (or other none compression aware party).
1799 * This is also explicitly stated in the spec (MCS Buffer for Render
1801 * "If Software wants to enable Color Compression without Fast clear,
1802 * Software needs to initialize MCS with zeros."
1804 intel_miptree_init_mcs(brw
, mt
, 0);
1805 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1812 * Helper for intel_miptree_alloc_hiz() that sets
1813 * \c mt->level[level].has_hiz. Return true if and only if
1814 * \c has_hiz was set.
1817 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1818 struct intel_mipmap_tree
*mt
,
1821 assert(mt
->hiz_buf
);
1823 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1824 uint32_t width
= minify(mt
->physical_width0
, level
);
1825 uint32_t height
= minify(mt
->physical_height0
, level
);
1827 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1828 * and the height is 4 aligned. This allows our HiZ support
1829 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1830 * we can grow the width & height to allow the HiZ op to
1831 * force the proper size alignments.
1833 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1834 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1839 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1840 mt
->level
[level
].has_hiz
= true;
1845 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1846 struct intel_mipmap_tree
*mt
)
1848 assert(mt
->hiz_buf
== NULL
);
1849 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1851 enum isl_aux_state
**aux_state
=
1852 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1856 struct isl_surf temp_main_surf
;
1857 struct isl_surf temp_hiz_surf
;
1859 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1860 MAYBE_UNUSED
bool ok
=
1861 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1864 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1865 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1866 &temp_hiz_surf
, alloc_flags
, mt
);
1873 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1874 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1876 mt
->aux_state
= aux_state
;
1882 * Can the miptree sample using the hiz buffer?
1885 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1886 struct intel_mipmap_tree
*mt
)
1888 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1889 * so keep things conservative for now and never enable it unless we're SKL+.
1899 /* It seems the hardware won't fallback to the depth buffer if some of the
1900 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1901 * of the texture to be HiZ enabled.
1903 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1904 if (!intel_miptree_level_has_hiz(mt
, level
))
1908 /* If compressed multisampling is enabled, then we use it for the auxiliary
1911 * From the BDW PRM (Volume 2d: Command Reference: Structures
1912 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1914 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1915 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1917 * There is no such blurb for 1D textures, but there is sufficient evidence
1918 * that this is broken on SKL+.
1920 return (mt
->num_samples
<= 1 &&
1921 mt
->target
!= GL_TEXTURE_3D
&&
1922 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1926 * Does the miptree slice have hiz enabled?
1929 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1931 intel_miptree_check_level_layer(mt
, level
, 0);
1932 return mt
->level
[level
].has_hiz
;
1936 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1937 unsigned start_level
, unsigned num_levels
,
1938 unsigned start_layer
, unsigned num_layers
)
1940 assert(_mesa_is_format_color_format(mt
->format
));
1945 /* Clamp the level range to fit the miptree */
1946 assert(start_level
+ num_levels
>= start_level
);
1947 const uint32_t last_level
=
1948 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
1949 start_level
= MAX2(mt
->first_level
, start_level
);
1950 num_levels
= last_level
- start_level
+ 1;
1952 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
1953 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
1954 for (unsigned a
= 0; a
< level_layers
; a
++) {
1955 enum isl_aux_state aux_state
=
1956 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1957 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1958 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1967 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1968 const struct intel_mipmap_tree
*mt
,
1969 unsigned level
, unsigned layer
)
1975 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1976 assert(brw
->gen
>= 8 ||
1977 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1979 /* Compression of arrayed msaa surfaces is supported. */
1980 if (mt
->num_samples
> 1)
1983 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1984 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
1990 static enum blorp_fast_clear_op
1991 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1992 bool ccs_supported
, bool fast_clear_supported
)
1994 assert(ccs_supported
== fast_clear_supported
);
1996 switch (aux_state
) {
1997 case ISL_AUX_STATE_CLEAR
:
1998 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2000 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2002 return BLORP_FAST_CLEAR_OP_NONE
;
2004 case ISL_AUX_STATE_PASS_THROUGH
:
2005 return BLORP_FAST_CLEAR_OP_NONE
;
2007 case ISL_AUX_STATE_RESOLVED
:
2008 case ISL_AUX_STATE_AUX_INVALID
:
2009 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2013 unreachable("Invalid aux state for CCS_D");
2016 static enum blorp_fast_clear_op
2017 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2018 bool ccs_supported
, bool fast_clear_supported
)
2020 switch (aux_state
) {
2021 case ISL_AUX_STATE_CLEAR
:
2022 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2024 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2025 else if (!fast_clear_supported
)
2026 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2028 return BLORP_FAST_CLEAR_OP_NONE
;
2030 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2032 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2034 return BLORP_FAST_CLEAR_OP_NONE
;
2036 case ISL_AUX_STATE_PASS_THROUGH
:
2037 return BLORP_FAST_CLEAR_OP_NONE
;
2039 case ISL_AUX_STATE_RESOLVED
:
2040 case ISL_AUX_STATE_AUX_INVALID
:
2044 unreachable("Invalid aux state for CCS_E");
2048 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2049 struct intel_mipmap_tree
*mt
,
2050 uint32_t level
, uint32_t layer
,
2052 bool fast_clear_supported
)
2054 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2056 enum blorp_fast_clear_op resolve_op
;
2057 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2058 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2059 fast_clear_supported
);
2061 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2062 fast_clear_supported
);
2065 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2066 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2067 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2069 switch (resolve_op
) {
2070 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2071 /* The CCS full resolve operation destroys the CCS and sets it to the
2072 * pass-through state. (You can also think of this as being both a
2073 * resolve and an ambiguate in one operation.)
2075 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2076 ISL_AUX_STATE_PASS_THROUGH
);
2079 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2080 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2081 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2085 unreachable("Invalid resolve op");
2091 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2092 struct intel_mipmap_tree
*mt
,
2093 uint32_t level
, uint32_t layer
,
2094 bool written_with_ccs
)
2096 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2098 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2099 switch (aux_state
) {
2100 case ISL_AUX_STATE_CLEAR
:
2101 assert(written_with_ccs
);
2102 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2103 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2106 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2107 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2108 assert(written_with_ccs
);
2109 break; /* Nothing to do */
2111 case ISL_AUX_STATE_PASS_THROUGH
:
2112 if (written_with_ccs
) {
2113 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2114 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2120 case ISL_AUX_STATE_RESOLVED
:
2121 case ISL_AUX_STATE_AUX_INVALID
:
2122 unreachable("Invalid aux state for CCS_E");
2125 /* CCS_D is a bit simpler */
2126 switch (aux_state
) {
2127 case ISL_AUX_STATE_CLEAR
:
2128 assert(written_with_ccs
);
2129 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2130 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2133 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2134 assert(written_with_ccs
);
2135 break; /* Nothing to do */
2137 case ISL_AUX_STATE_PASS_THROUGH
:
2141 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2142 case ISL_AUX_STATE_RESOLVED
:
2143 case ISL_AUX_STATE_AUX_INVALID
:
2144 unreachable("Invalid aux state for CCS_D");
2150 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2151 struct intel_mipmap_tree
*mt
,
2152 uint32_t level
, uint32_t layer
,
2153 bool written_with_aux
)
2155 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2156 case ISL_AUX_STATE_CLEAR
:
2157 assert(written_with_aux
);
2158 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2159 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2162 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2163 assert(written_with_aux
);
2164 break; /* Nothing to do */
2166 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2167 case ISL_AUX_STATE_RESOLVED
:
2168 case ISL_AUX_STATE_PASS_THROUGH
:
2169 case ISL_AUX_STATE_AUX_INVALID
:
2170 unreachable("Invalid aux state for MCS");
2175 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2176 struct intel_mipmap_tree
*mt
,
2177 uint32_t level
, uint32_t layer
,
2178 bool hiz_supported
, bool fast_clear_supported
)
2180 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2181 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2182 case ISL_AUX_STATE_CLEAR
:
2183 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2184 if (!hiz_supported
|| !fast_clear_supported
)
2185 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2188 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2190 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2193 case ISL_AUX_STATE_PASS_THROUGH
:
2194 case ISL_AUX_STATE_RESOLVED
:
2197 case ISL_AUX_STATE_AUX_INVALID
:
2199 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2203 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2204 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2207 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2208 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2209 ISL_AUX_STATE_RESOLVED
);
2212 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2213 /* The HiZ resolve operation is actually an ambiguate */
2214 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2215 ISL_AUX_STATE_PASS_THROUGH
);
2219 unreachable("Invalid HiZ op");
2225 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2226 struct intel_mipmap_tree
*mt
,
2227 uint32_t level
, uint32_t layer
,
2228 bool written_with_hiz
)
2230 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2231 case ISL_AUX_STATE_CLEAR
:
2232 assert(written_with_hiz
);
2233 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2234 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2237 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2238 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2239 assert(written_with_hiz
);
2240 break; /* Nothing to do */
2242 case ISL_AUX_STATE_RESOLVED
:
2243 if (written_with_hiz
) {
2244 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2245 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2247 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2248 ISL_AUX_STATE_AUX_INVALID
);
2252 case ISL_AUX_STATE_PASS_THROUGH
:
2253 if (written_with_hiz
) {
2254 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2255 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2259 case ISL_AUX_STATE_AUX_INVALID
:
2260 assert(!written_with_hiz
);
2265 static inline uint32_t
2266 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2267 uint32_t start_level
, uint32_t num_levels
)
2269 assert(start_level
>= mt
->first_level
);
2270 assert(start_level
<= mt
->last_level
);
2272 if (num_levels
== INTEL_REMAINING_LAYERS
)
2273 num_levels
= mt
->last_level
- start_level
+ 1;
2274 /* Check for overflow */
2275 assert(start_level
+ num_levels
>= start_level
);
2276 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2281 static inline uint32_t
2282 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2283 uint32_t start_layer
, uint32_t num_layers
)
2285 assert(level
<= mt
->last_level
);
2286 uint32_t total_num_layers
;
2288 if (mt
->surf
.size
> 0)
2289 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2290 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2291 mt
->surf
.phys_level0_sa
.array_len
;
2293 total_num_layers
= mt
->level
[level
].depth
;
2295 assert(start_layer
< total_num_layers
);
2296 if (num_layers
== INTEL_REMAINING_LAYERS
)
2297 num_layers
= total_num_layers
- start_layer
;
2298 /* Check for overflow */
2299 assert(start_layer
+ num_layers
>= start_layer
);
2300 assert(start_layer
+ num_layers
<= total_num_layers
);
2306 intel_miptree_prepare_access(struct brw_context
*brw
,
2307 struct intel_mipmap_tree
*mt
,
2308 uint32_t start_level
, uint32_t num_levels
,
2309 uint32_t start_layer
, uint32_t num_layers
,
2310 bool aux_supported
, bool fast_clear_supported
)
2312 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2314 if (_mesa_is_format_color_format(mt
->format
)) {
2318 if (mt
->num_samples
> 1) {
2319 /* Nothing to do for MSAA */
2320 assert(aux_supported
&& fast_clear_supported
);
2322 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2323 const uint32_t level
= start_level
+ l
;
2324 const uint32_t level_layers
=
2325 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2326 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2327 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2328 start_layer
+ a
, aux_supported
,
2329 fast_clear_supported
);
2333 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2334 /* Nothing to do for stencil */
2339 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2340 const uint32_t level
= start_level
+ l
;
2341 if (!intel_miptree_level_has_hiz(mt
, level
))
2344 const uint32_t level_layers
=
2345 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2346 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2347 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2349 fast_clear_supported
);
2356 intel_miptree_finish_write(struct brw_context
*brw
,
2357 struct intel_mipmap_tree
*mt
, uint32_t level
,
2358 uint32_t start_layer
, uint32_t num_layers
,
2359 bool written_with_aux
)
2361 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2363 if (_mesa_is_format_color_format(mt
->format
)) {
2367 if (mt
->num_samples
> 1) {
2368 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2369 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2373 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2374 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2378 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2379 /* Nothing to do for stencil */
2381 if (!intel_miptree_level_has_hiz(mt
, level
))
2384 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2385 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2392 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2393 uint32_t level
, uint32_t layer
)
2395 intel_miptree_check_level_layer(mt
, level
, layer
);
2397 if (_mesa_is_format_color_format(mt
->format
)) {
2398 assert(mt
->mcs_buf
!= NULL
);
2399 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2400 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2401 unreachable("Cannot get aux state for stencil");
2403 assert(intel_miptree_level_has_hiz(mt
, level
));
2406 return mt
->aux_state
[level
][layer
];
2410 intel_miptree_set_aux_state(struct brw_context
*brw
,
2411 struct intel_mipmap_tree
*mt
, uint32_t level
,
2412 uint32_t start_layer
, uint32_t num_layers
,
2413 enum isl_aux_state aux_state
)
2415 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2417 if (_mesa_is_format_color_format(mt
->format
)) {
2418 assert(mt
->mcs_buf
!= NULL
);
2419 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2420 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2421 unreachable("Cannot get aux state for stencil");
2423 assert(intel_miptree_level_has_hiz(mt
, level
));
2426 for (unsigned a
= 0; a
< num_layers
; a
++)
2427 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2430 /* On Gen9 color buffers may be compressed by the hardware (lossless
2431 * compression). There are, however, format restrictions and care needs to be
2432 * taken that the sampler engine is capable for re-interpreting a buffer with
2433 * format different the buffer was originally written with.
2435 * For example, SRGB formats are not compressible and the sampler engine isn't
2436 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2437 * color buffer needs to be resolved so that the sampling surface can be
2438 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2442 can_texture_with_ccs(struct brw_context
*brw
,
2443 struct intel_mipmap_tree
*mt
,
2444 mesa_format view_format
)
2446 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2449 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2450 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2452 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2453 isl_mt_format
, isl_view_format
)) {
2454 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2455 _mesa_get_format_name(view_format
),
2456 _mesa_get_format_name(mt
->format
));
2464 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2465 struct intel_mipmap_tree
*mt
,
2466 mesa_format view_format
,
2467 uint32_t start_level
, uint32_t num_levels
,
2468 uint32_t start_layer
, uint32_t num_layers
,
2469 bool *aux_supported_out
)
2471 bool aux_supported
, clear_supported
;
2472 if (_mesa_is_format_color_format(mt
->format
)) {
2473 if (mt
->num_samples
> 1) {
2474 aux_supported
= clear_supported
= true;
2476 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2478 /* Clear color is specified as ints or floats and the conversion is
2479 * done by the sampler. If we have a texture view, we would have to
2480 * perform the clear color conversion manually. Just disable clear
2483 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2485 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2486 aux_supported
= clear_supported
= false;
2488 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2491 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2492 start_layer
, num_layers
,
2493 aux_supported
, clear_supported
);
2494 if (aux_supported_out
)
2495 *aux_supported_out
= aux_supported
;
2499 intel_miptree_prepare_texture(struct brw_context
*brw
,
2500 struct intel_mipmap_tree
*mt
,
2501 mesa_format view_format
,
2502 bool *aux_supported_out
)
2504 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2505 0, INTEL_REMAINING_LEVELS
,
2506 0, INTEL_REMAINING_LAYERS
,
2511 intel_miptree_prepare_image(struct brw_context
*brw
,
2512 struct intel_mipmap_tree
*mt
)
2514 /* The data port doesn't understand any compression */
2515 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2516 0, INTEL_REMAINING_LAYERS
, false, false);
2520 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2521 struct intel_mipmap_tree
*mt
, uint32_t level
,
2522 uint32_t start_layer
, uint32_t num_layers
)
2524 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2525 start_layer
, num_layers
, NULL
);
2529 intel_miptree_prepare_render(struct brw_context
*brw
,
2530 struct intel_mipmap_tree
*mt
, uint32_t level
,
2531 uint32_t start_layer
, uint32_t layer_count
,
2534 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2535 * the single-sampled color renderbuffers because the CCS buffer isn't
2536 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2537 * enabled because otherwise the surface state will be programmed with
2538 * the linear equivalent format anyway.
2540 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2541 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2543 /* Lossless compression is not supported for SRGB formats, it
2544 * should be impossible to get here with such surfaces.
2546 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2547 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2553 intel_miptree_finish_render(struct brw_context
*brw
,
2554 struct intel_mipmap_tree
*mt
, uint32_t level
,
2555 uint32_t start_layer
, uint32_t layer_count
)
2557 assert(_mesa_is_format_color_format(mt
->format
));
2558 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2559 mt
->mcs_buf
!= NULL
);
2563 intel_miptree_prepare_depth(struct brw_context
*brw
,
2564 struct intel_mipmap_tree
*mt
, uint32_t level
,
2565 uint32_t start_layer
, uint32_t layer_count
)
2567 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2568 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2572 intel_miptree_finish_depth(struct brw_context
*brw
,
2573 struct intel_mipmap_tree
*mt
, uint32_t level
,
2574 uint32_t start_layer
, uint32_t layer_count
,
2577 if (depth_written
) {
2578 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2579 mt
->hiz_buf
!= NULL
);
2584 * Make it possible to share the BO backing the given miptree with another
2585 * process or another miptree.
2587 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2588 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2589 * ensure that no MCS buffer gets allocated in the future.
2591 * HiZ is similarly unsafe with shared buffers.
2594 intel_miptree_make_shareable(struct brw_context
*brw
,
2595 struct intel_mipmap_tree
*mt
)
2597 /* MCS buffers are also used for multisample buffers, but we can't resolve
2598 * away a multisample MCS buffer because it's an integral part of how the
2599 * pixel data is stored. Fortunately this code path should never be
2600 * reached for multisample buffers.
2602 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2604 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2605 0, INTEL_REMAINING_LAYERS
, false, false);
2608 brw_bo_unreference(mt
->mcs_buf
->bo
);
2612 /* Any pending MCS/CCS operations are no longer needed. Trying to
2613 * execute any will likely crash due to the missing aux buffer. So let's
2614 * delete all pending ops.
2616 free(mt
->aux_state
);
2617 mt
->aux_state
= NULL
;
2621 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2624 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2625 mt
->level
[l
].has_hiz
= false;
2628 /* Any pending HiZ operations are no longer needed. Trying to execute
2629 * any will likely crash due to the missing aux buffer. So let's delete
2632 free(mt
->aux_state
);
2633 mt
->aux_state
= NULL
;
2636 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2641 * \brief Get pointer offset into stencil buffer.
2643 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2644 * must decode the tile's layout in software.
2647 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2649 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2651 * Even though the returned offset is always positive, the return type is
2653 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2654 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2657 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2659 uint32_t tile_size
= 4096;
2660 uint32_t tile_width
= 64;
2661 uint32_t tile_height
= 64;
2662 uint32_t row_size
= 64 * stride
;
2664 uint32_t tile_x
= x
/ tile_width
;
2665 uint32_t tile_y
= y
/ tile_height
;
2667 /* The byte's address relative to the tile's base addres. */
2668 uint32_t byte_x
= x
% tile_width
;
2669 uint32_t byte_y
= y
% tile_height
;
2671 uintptr_t u
= tile_y
* row_size
2672 + tile_x
* tile_size
2673 + 512 * (byte_x
/ 8)
2675 + 32 * ((byte_y
/ 4) % 2)
2676 + 16 * ((byte_x
/ 4) % 2)
2677 + 8 * ((byte_y
/ 2) % 2)
2678 + 4 * ((byte_x
/ 2) % 2)
2683 /* adjust for bit6 swizzling */
2684 if (((byte_x
/ 8) % 2) == 1) {
2685 if (((byte_y
/ 8) % 2) == 0) {
2697 intel_miptree_updownsample(struct brw_context
*brw
,
2698 struct intel_mipmap_tree
*src
,
2699 struct intel_mipmap_tree
*dst
)
2701 unsigned src_w
, src_h
, dst_w
, dst_h
;
2703 if (src
->surf
.size
> 0) {
2704 src_w
= src
->surf
.logical_level0_px
.width
;
2705 src_h
= src
->surf
.logical_level0_px
.height
;
2707 src_w
= src
->logical_width0
;
2708 src_h
= src
->logical_height0
;
2711 if (dst
->surf
.size
> 0) {
2712 dst_w
= dst
->surf
.logical_level0_px
.width
;
2713 dst_h
= dst
->surf
.logical_level0_px
.height
;
2715 dst_w
= dst
->logical_width0
;
2716 dst_h
= dst
->logical_height0
;
2719 brw_blorp_blit_miptrees(brw
,
2720 src
, 0 /* level */, 0 /* layer */,
2721 src
->format
, SWIZZLE_XYZW
,
2722 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2725 GL_NEAREST
, false, false /*mirror x, y*/,
2728 if (src
->stencil_mt
) {
2729 if (src
->stencil_mt
->surf
.size
> 0) {
2730 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2731 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2733 src_w
= src
->stencil_mt
->logical_width0
;
2734 src_h
= src
->stencil_mt
->logical_height0
;
2737 if (dst
->stencil_mt
->surf
.size
> 0) {
2738 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2739 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2741 dst_w
= dst
->stencil_mt
->logical_width0
;
2742 dst_h
= dst
->stencil_mt
->logical_height0
;
2745 brw_blorp_blit_miptrees(brw
,
2746 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2747 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2748 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2749 dst
->stencil_mt
->format
,
2752 GL_NEAREST
, false, false /*mirror x, y*/,
2753 false, false /* decode/encode srgb */);
2758 intel_update_r8stencil(struct brw_context
*brw
,
2759 struct intel_mipmap_tree
*mt
)
2761 assert(brw
->gen
>= 7);
2762 struct intel_mipmap_tree
*src
=
2763 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2764 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2767 if (!mt
->r8stencil_mt
) {
2768 const uint32_t r8stencil_flags
=
2769 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2770 MIPTREE_LAYOUT_DISABLE_AUX
;
2771 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2772 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2774 MESA_FORMAT_R_UINT8
,
2777 src
->logical_width0
,
2778 src
->logical_height0
,
2779 src
->logical_depth0
,
2782 assert(mt
->r8stencil_mt
);
2785 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2787 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2788 const unsigned depth
= src
->level
[level
].depth
;
2790 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2791 brw_blorp_copy_miptrees(brw
,
2795 minify(src
->logical_width0
, level
),
2796 minify(src
->logical_height0
, level
));
2800 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2801 src
->r8stencil_needs_update
= false;
2805 intel_miptree_map_raw(struct brw_context
*brw
,
2806 struct intel_mipmap_tree
*mt
,
2809 struct brw_bo
*bo
= mt
->bo
;
2811 if (brw_batch_references(&brw
->batch
, bo
))
2812 intel_batchbuffer_flush(brw
);
2814 return brw_bo_map(brw
, bo
, mode
);
2818 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2820 brw_bo_unmap(mt
->bo
);
2824 intel_miptree_map_gtt(struct brw_context
*brw
,
2825 struct intel_mipmap_tree
*mt
,
2826 struct intel_miptree_map
*map
,
2827 unsigned int level
, unsigned int slice
)
2829 unsigned int bw
, bh
;
2831 unsigned int image_x
, image_y
;
2832 intptr_t x
= map
->x
;
2833 intptr_t y
= map
->y
;
2835 /* For compressed formats, the stride is the number of bytes per
2836 * row of blocks. intel_miptree_get_image_offset() already does
2839 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2840 assert(y
% bh
== 0);
2841 assert(x
% bw
== 0);
2845 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2850 /* Note that in the case of cube maps, the caller must have passed the
2851 * slice number referencing the face.
2853 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2857 map
->stride
= mt
->pitch
;
2858 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2861 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2862 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2863 map
->x
, map
->y
, map
->w
, map
->h
,
2864 mt
, _mesa_get_format_name(mt
->format
),
2865 x
, y
, map
->ptr
, map
->stride
);
2869 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2871 intel_miptree_unmap_raw(mt
);
2875 intel_miptree_map_blit(struct brw_context
*brw
,
2876 struct intel_mipmap_tree
*mt
,
2877 struct intel_miptree_map
*map
,
2878 unsigned int level
, unsigned int slice
)
2880 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2881 /* first_level */ 0,
2885 MIPTREE_LAYOUT_TILING_NONE
);
2887 if (!map
->linear_mt
) {
2888 fprintf(stderr
, "Failed to allocate blit temporary\n");
2891 map
->stride
= map
->linear_mt
->pitch
;
2893 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2894 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2895 * invalidate is set, since we'll be writing the whole rectangle from our
2896 * temporary buffer back out.
2898 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2899 if (!intel_miptree_copy(brw
,
2900 mt
, level
, slice
, map
->x
, map
->y
,
2901 map
->linear_mt
, 0, 0, 0, 0,
2903 fprintf(stderr
, "Failed to blit\n");
2908 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2910 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2911 map
->x
, map
->y
, map
->w
, map
->h
,
2912 mt
, _mesa_get_format_name(mt
->format
),
2913 level
, slice
, map
->ptr
, map
->stride
);
2918 intel_miptree_release(&map
->linear_mt
);
2924 intel_miptree_unmap_blit(struct brw_context
*brw
,
2925 struct intel_mipmap_tree
*mt
,
2926 struct intel_miptree_map
*map
,
2930 struct gl_context
*ctx
= &brw
->ctx
;
2932 intel_miptree_unmap_raw(map
->linear_mt
);
2934 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2935 bool ok
= intel_miptree_copy(brw
,
2936 map
->linear_mt
, 0, 0, 0, 0,
2937 mt
, level
, slice
, map
->x
, map
->y
,
2939 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2942 intel_miptree_release(&map
->linear_mt
);
2946 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2948 #if defined(USE_SSE41)
2950 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2951 struct intel_mipmap_tree
*mt
,
2952 struct intel_miptree_map
*map
,
2953 unsigned int level
, unsigned int slice
)
2955 assert(map
->mode
& GL_MAP_READ_BIT
);
2956 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2958 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2959 map
->x
, map
->y
, map
->w
, map
->h
,
2960 mt
, _mesa_get_format_name(mt
->format
),
2961 level
, slice
, map
->ptr
, map
->stride
);
2963 /* Map the original image */
2966 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2970 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2976 src
+= image_y
* mt
->pitch
;
2977 src
+= image_x
* mt
->cpp
;
2979 /* Due to the pixel offsets for the particular image being mapped, our
2980 * src pointer may not be 16-byte aligned. However, if the pitch is
2981 * divisible by 16, then the amount by which it's misaligned will remain
2982 * consistent from row to row.
2984 assert((mt
->pitch
% 16) == 0);
2985 const int misalignment
= ((uintptr_t) src
) & 15;
2987 /* Create an untiled temporary buffer for the mapping. */
2988 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2990 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2992 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2993 /* Offset the destination so it has the same misalignment as src. */
2994 map
->ptr
= map
->buffer
+ misalignment
;
2996 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2998 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2999 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3000 void *src_ptr
= src
+ y
* mt
->pitch
;
3002 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3005 intel_miptree_unmap_raw(mt
);
3009 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3010 struct intel_mipmap_tree
*mt
,
3011 struct intel_miptree_map
*map
,
3015 _mesa_align_free(map
->buffer
);
3022 intel_miptree_map_s8(struct brw_context
*brw
,
3023 struct intel_mipmap_tree
*mt
,
3024 struct intel_miptree_map
*map
,
3025 unsigned int level
, unsigned int slice
)
3027 map
->stride
= map
->w
;
3028 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3032 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3033 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3034 * invalidate is set, since we'll be writing the whole rectangle from our
3035 * temporary buffer back out.
3037 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3038 /* ISL uses a stencil pitch value that is expected by hardware whereas
3039 * traditional miptree uses half of that. Below the value gets supplied
3040 * to intel_offset_S8() which expects the legacy interpretation.
3042 const unsigned pitch
= mt
->surf
.size
> 0 ?
3043 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3044 uint8_t *untiled_s8_map
= map
->ptr
;
3045 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3046 unsigned int image_x
, image_y
;
3048 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3050 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3051 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3052 ptrdiff_t offset
= intel_offset_S8(pitch
,
3053 x
+ image_x
+ map
->x
,
3054 y
+ image_y
+ map
->y
,
3055 brw
->has_swizzling
);
3056 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3060 intel_miptree_unmap_raw(mt
);
3062 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3063 map
->x
, map
->y
, map
->w
, map
->h
,
3064 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3066 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3067 map
->x
, map
->y
, map
->w
, map
->h
,
3068 mt
, map
->ptr
, map
->stride
);
3073 intel_miptree_unmap_s8(struct brw_context
*brw
,
3074 struct intel_mipmap_tree
*mt
,
3075 struct intel_miptree_map
*map
,
3079 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3080 /* ISL uses a stencil pitch value that is expected by hardware whereas
3081 * traditional miptree uses half of that. Below the value gets supplied
3082 * to intel_offset_S8() which expects the legacy interpretation.
3084 const unsigned pitch
= mt
->surf
.size
> 0 ?
3085 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3086 unsigned int image_x
, image_y
;
3087 uint8_t *untiled_s8_map
= map
->ptr
;
3088 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3090 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3092 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3093 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3094 ptrdiff_t offset
= intel_offset_S8(pitch
,
3095 image_x
+ x
+ map
->x
,
3096 image_y
+ y
+ map
->y
,
3097 brw
->has_swizzling
);
3098 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3102 intel_miptree_unmap_raw(mt
);
3109 intel_miptree_map_etc(struct brw_context
*brw
,
3110 struct intel_mipmap_tree
*mt
,
3111 struct intel_miptree_map
*map
,
3115 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3116 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3117 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3120 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3121 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3123 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3124 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3125 map
->w
, map
->h
, 1));
3126 map
->ptr
= map
->buffer
;
3130 intel_miptree_unmap_etc(struct brw_context
*brw
,
3131 struct intel_mipmap_tree
*mt
,
3132 struct intel_miptree_map
*map
,
3138 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3143 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3144 + image_y
* mt
->pitch
3145 + image_x
* mt
->cpp
;
3147 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3148 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3149 map
->ptr
, map
->stride
,
3152 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3153 map
->ptr
, map
->stride
,
3154 map
->w
, map
->h
, mt
->etc_format
);
3156 intel_miptree_unmap_raw(mt
);
3161 * Mapping function for packed depth/stencil miptrees backed by real separate
3162 * miptrees for depth and stencil.
3164 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3165 * separate from the depth buffer. Yet at the GL API level, we have to expose
3166 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3167 * be able to map that memory for texture storage and glReadPixels-type
3168 * operations. We give Mesa core that access by mallocing a temporary and
3169 * copying the data between the actual backing store and the temporary.
3172 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3173 struct intel_mipmap_tree
*mt
,
3174 struct intel_miptree_map
*map
,
3175 unsigned int level
, unsigned int slice
)
3177 struct intel_mipmap_tree
*z_mt
= mt
;
3178 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3179 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3180 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3182 map
->stride
= map
->w
* packed_bpp
;
3183 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3187 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3188 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3189 * invalidate is set, since we'll be writing the whole rectangle from our
3190 * temporary buffer back out.
3192 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3193 /* ISL uses a stencil pitch value that is expected by hardware whereas
3194 * traditional miptree uses half of that. Below the value gets supplied
3195 * to intel_offset_S8() which expects the legacy interpretation.
3197 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3198 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3199 uint32_t *packed_map
= map
->ptr
;
3200 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3201 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3202 unsigned int s_image_x
, s_image_y
;
3203 unsigned int z_image_x
, z_image_y
;
3205 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3206 &s_image_x
, &s_image_y
);
3207 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3208 &z_image_x
, &z_image_y
);
3210 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3211 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3212 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3213 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3216 brw
->has_swizzling
);
3217 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3219 (map_x
+ z_image_x
));
3220 uint8_t s
= s_map
[s_offset
];
3221 uint32_t z
= z_map
[z_offset
];
3223 if (map_z32f_x24s8
) {
3224 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3225 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3227 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3232 intel_miptree_unmap_raw(s_mt
);
3233 intel_miptree_unmap_raw(z_mt
);
3235 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3237 map
->x
, map
->y
, map
->w
, map
->h
,
3238 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3239 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3240 map
->ptr
, map
->stride
);
3242 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3243 map
->x
, map
->y
, map
->w
, map
->h
,
3244 mt
, map
->ptr
, map
->stride
);
3249 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3250 struct intel_mipmap_tree
*mt
,
3251 struct intel_miptree_map
*map
,
3255 struct intel_mipmap_tree
*z_mt
= mt
;
3256 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3257 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3259 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3260 /* ISL uses a stencil pitch value that is expected by hardware whereas
3261 * traditional miptree uses half of that. Below the value gets supplied
3262 * to intel_offset_S8() which expects the legacy interpretation.
3264 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3265 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3266 uint32_t *packed_map
= map
->ptr
;
3267 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3268 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3269 unsigned int s_image_x
, s_image_y
;
3270 unsigned int z_image_x
, z_image_y
;
3272 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3273 &s_image_x
, &s_image_y
);
3274 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3275 &z_image_x
, &z_image_y
);
3277 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3278 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3279 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3280 x
+ s_image_x
+ map
->x
,
3281 y
+ s_image_y
+ map
->y
,
3282 brw
->has_swizzling
);
3283 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3285 (x
+ z_image_x
+ map
->x
));
3287 if (map_z32f_x24s8
) {
3288 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3289 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3291 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3292 s_map
[s_offset
] = packed
>> 24;
3293 z_map
[z_offset
] = packed
;
3298 intel_miptree_unmap_raw(s_mt
);
3299 intel_miptree_unmap_raw(z_mt
);
3301 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3303 map
->x
, map
->y
, map
->w
, map
->h
,
3304 z_mt
, _mesa_get_format_name(z_mt
->format
),
3305 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3306 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3307 map
->ptr
, map
->stride
);
3314 * Create and attach a map to the miptree at (level, slice). Return the
3317 static struct intel_miptree_map
*
3318 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3327 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3332 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3333 mt
->level
[level
].slice
[slice
].map
= map
;
3345 * Release the map at (level, slice).
3348 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3352 struct intel_miptree_map
**map
;
3354 map
= &mt
->level
[level
].slice
[slice
].map
;
3360 can_blit_slice(struct intel_mipmap_tree
*mt
,
3361 unsigned int level
, unsigned int slice
)
3363 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3364 if (mt
->pitch
>= 32768)
3371 use_intel_mipree_map_blit(struct brw_context
*brw
,
3372 struct intel_mipmap_tree
*mt
,
3378 /* It's probably not worth swapping to the blit ring because of
3379 * all the overhead involved.
3381 !(mode
& GL_MAP_WRITE_BIT
) &&
3383 (mt
->tiling
== I915_TILING_X
||
3384 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3385 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3386 /* Fast copy blit on skl+ supports all tiling formats. */
3388 can_blit_slice(mt
, level
, slice
))
3391 if (mt
->tiling
!= I915_TILING_NONE
&&
3392 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3393 assert(can_blit_slice(mt
, level
, slice
));
3401 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3402 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3403 * arithmetic overflow.
3405 * If you call this function and use \a out_stride, then you're doing pointer
3406 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3407 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3408 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3409 * which usually have type uint32_t or GLuint.
3412 intel_miptree_map(struct brw_context
*brw
,
3413 struct intel_mipmap_tree
*mt
,
3422 ptrdiff_t *out_stride
)
3424 struct intel_miptree_map
*map
;
3426 assert(mt
->num_samples
<= 1);
3428 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3435 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3436 map
->mode
& GL_MAP_WRITE_BIT
);
3438 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3439 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3440 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3441 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3442 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3443 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3444 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3445 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3446 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3447 #if defined(USE_SSE41)
3448 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3449 !mt
->compressed
&& cpu_has_sse4_1
&&
3450 (mt
->pitch
% 16 == 0)) {
3451 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3454 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3457 *out_ptr
= map
->ptr
;
3458 *out_stride
= map
->stride
;
3460 if (map
->ptr
== NULL
)
3461 intel_miptree_release_map(mt
, level
, slice
);
3465 intel_miptree_unmap(struct brw_context
*brw
,
3466 struct intel_mipmap_tree
*mt
,
3470 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3472 assert(mt
->num_samples
<= 1);
3477 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3478 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3480 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3481 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3482 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3483 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3484 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3485 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3486 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3487 } else if (map
->linear_mt
) {
3488 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3489 #if defined(USE_SSE41)
3490 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3491 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3494 intel_miptree_unmap_gtt(mt
);
3497 intel_miptree_release_map(mt
, level
, slice
);
3501 get_isl_surf_dim(GLenum target
)
3505 case GL_TEXTURE_1D_ARRAY
:
3506 return ISL_SURF_DIM_1D
;
3509 case GL_TEXTURE_2D_ARRAY
:
3510 case GL_TEXTURE_RECTANGLE
:
3511 case GL_TEXTURE_CUBE_MAP
:
3512 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3513 case GL_TEXTURE_2D_MULTISAMPLE
:
3514 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3515 case GL_TEXTURE_EXTERNAL_OES
:
3516 return ISL_SURF_DIM_2D
;
3519 return ISL_SURF_DIM_3D
;
3522 unreachable("Invalid texture target");
3526 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3527 GLenum target
, enum miptree_array_layout array_layout
)
3529 if (array_layout
== GEN6_HIZ_STENCIL
)
3530 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3534 case GL_TEXTURE_1D_ARRAY
:
3535 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3536 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3539 case GL_TEXTURE_2D_ARRAY
:
3540 case GL_TEXTURE_RECTANGLE
:
3541 case GL_TEXTURE_2D_MULTISAMPLE
:
3542 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3543 case GL_TEXTURE_EXTERNAL_OES
:
3544 return ISL_DIM_LAYOUT_GEN4_2D
;
3546 case GL_TEXTURE_CUBE_MAP
:
3547 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3548 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3549 ISL_DIM_LAYOUT_GEN4_2D
);
3552 return (devinfo
->gen
>= 9 ?
3553 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3556 unreachable("Invalid texture target");
3560 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3562 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3563 return ISL_TILING_W
;
3565 switch (mt
->tiling
) {
3566 case I915_TILING_NONE
:
3567 return ISL_TILING_LINEAR
;
3569 return ISL_TILING_X
;
3571 return ISL_TILING_Y0
;
3573 unreachable("Invalid tiling mode");
3579 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3580 const struct intel_mipmap_tree
*mt
,
3581 struct isl_surf
*surf
)
3583 surf
->dim
= get_isl_surf_dim(mt
->target
);
3584 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3585 mt
->tiling
, mt
->target
,
3588 if (mt
->num_samples
> 1) {
3589 switch (mt
->msaa_layout
) {
3590 case INTEL_MSAA_LAYOUT_IMS
:
3591 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3593 case INTEL_MSAA_LAYOUT_UMS
:
3594 case INTEL_MSAA_LAYOUT_CMS
:
3595 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3598 unreachable("Invalid MSAA layout");
3601 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3604 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3606 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3607 /* The ISL definition of row_pitch matches the surface state pitch field
3608 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3609 * the factor of 2 for W-tiling in row_pitch.
3611 surf
->row_pitch
= 2 * mt
->pitch
;
3613 surf
->row_pitch
= mt
->pitch
;
3616 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3618 if (brw
->gen
>= 9) {
3619 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3620 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3621 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3623 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3624 * alignment in terms of surface elements like we want.
3626 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3629 /* On earlier gens it's stored in pixels. */
3631 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3632 surf
->image_alignment_el
=
3633 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3636 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3637 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3638 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3639 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3640 surf
->logical_level0_px
.array_len
= 1;
3642 surf
->logical_level0_px
.depth
= 1;
3643 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3646 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3647 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3648 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3649 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3650 surf
->phys_level0_sa
.array_len
= 1;
3652 surf
->phys_level0_sa
.depth
= 1;
3653 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3656 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3657 surf
->samples
= MAX2(mt
->num_samples
, 1);
3659 surf
->size
= 0; /* TODO */
3660 surf
->alignment
= 0; /* TODO */
3662 switch (surf
->dim_layout
) {
3663 case ISL_DIM_LAYOUT_GEN4_2D
:
3664 case ISL_DIM_LAYOUT_GEN4_3D
:
3665 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3666 if (brw
->gen
>= 9) {
3667 surf
->array_pitch_el_rows
= mt
->qpitch
;
3670 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3671 assert(mt
->qpitch
% bh
== 0);
3672 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3675 case ISL_DIM_LAYOUT_GEN9_1D
:
3676 surf
->array_pitch_el_rows
= 1;
3680 switch (mt
->array_layout
) {
3681 case ALL_LOD_IN_EACH_SLICE
:
3682 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3684 case ALL_SLICES_AT_EACH_LOD
:
3685 case GEN6_HIZ_STENCIL
:
3686 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3689 unreachable("Invalid array layout");
3692 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3693 switch (base_format
) {
3694 case GL_DEPTH_COMPONENT
:
3695 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3697 case GL_STENCIL_INDEX
:
3698 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3700 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3702 case GL_DEPTH_STENCIL
:
3703 /* In this case we only texture from the depth part */
3704 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3705 ISL_SURF_USAGE_TEXTURE_BIT
;
3708 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3709 if (brw
->mesa_format_supports_render
[mt
->format
])
3710 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3714 if (_mesa_is_cube_map_texture(mt
->target
))
3715 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3719 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3720 const struct intel_mipmap_tree
*mt
)
3723 return ISL_AUX_USAGE_HIZ
;
3726 return ISL_AUX_USAGE_NONE
;
3728 return mt
->aux_usage
;