2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
126 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
127 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
129 * - Support is limited to tiled render targets.
131 * Gen9 changes the restriction to Y-tile only.
134 return tiling
== I915_TILING_Y
;
135 else if (brw
->gen
>= 7)
136 return tiling
!= I915_TILING_NONE
;
142 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
143 * can be used. This doesn't (and should not) inspect any of the properties of
146 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
147 * beneath the "Fast Color Clear" bullet (p326):
149 * - Support is for non-mip-mapped and non-array surface types only.
151 * And then later, on p327:
153 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
156 * From the Skylake documentation, it is made clear that X-tiling is no longer
159 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
163 intel_miptree_supports_ccs(struct brw_context
*brw
,
164 const struct intel_mipmap_tree
*mt
)
166 /* MCS support does not exist prior to Gen7 */
170 /* This function applies only to non-multisampled render targets. */
171 if (mt
->num_samples
> 1)
174 /* MCS is only supported for color buffers */
175 switch (_mesa_get_format_base_format(mt
->format
)) {
176 case GL_DEPTH_COMPONENT
:
177 case GL_DEPTH_STENCIL
:
178 case GL_STENCIL_INDEX
:
182 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
185 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
186 const bool arrayed
= mt
->physical_depth0
!= 1;
189 /* Multisample surfaces with the CMS layout are not layered surfaces,
190 * yet still have physical_depth0 > 1. Assert that we don't
191 * accidentally reject a multisampled surface here. We should have
192 * rejected it earlier by explicitly checking the sample count.
194 assert(mt
->num_samples
<= 1);
197 /* Handle the hardware restrictions...
199 * All GENs have the following restriction: "MCS buffer for non-MSRT is
200 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
202 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
203 * Non-MultiSampler Render Target Restrictions) Support is for
204 * non-mip-mapped and non-array surface types only.
206 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
207 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
208 * surfaces are supported with MCS buffer layout with these alignments in
209 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
211 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
212 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
213 * surfaces are supported with MCS buffer layout with these alignments in
214 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
216 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
219 /* There's no point in using an MCS buffer if the surface isn't in a
222 if (!brw
->mesa_format_supports_render
[mt
->format
])
226 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
227 const enum isl_format isl_format
=
228 brw_isl_format_for_mesa_format(linear_format
);
229 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
235 intel_tiling_supports_hiz(const struct brw_context
*brw
, unsigned tiling
)
240 return tiling
== I915_TILING_Y
;
244 intel_miptree_supports_hiz(const struct brw_context
*brw
,
245 const struct intel_mipmap_tree
*mt
)
250 switch (mt
->format
) {
251 case MESA_FORMAT_Z_FLOAT32
:
252 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
253 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
254 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
255 case MESA_FORMAT_Z_UNORM16
:
263 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
264 const struct intel_mipmap_tree
*mt
)
266 /* For now compression is only enabled for integer formats even though
267 * there exist supported floating point formats also. This is a heuristic
268 * decision based on current public benchmarks. In none of the cases these
269 * formats provided any improvement but a few cases were seen to regress.
270 * Hence these are left to to be enabled in the future when they are known
273 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
276 if (!intel_miptree_supports_ccs(brw
, mt
))
279 /* Fast clear can be also used to clear srgb surfaces by using equivalent
280 * linear format. This trick, however, can't be extended to be used with
281 * lossless compression and therefore a check is needed to see if the format
284 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
288 * Determine depth format corresponding to a depth+stencil format,
289 * for separate stencil.
292 intel_depth_format_for_depthstencil_format(mesa_format format
) {
294 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
295 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
296 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
297 return MESA_FORMAT_Z_FLOAT32
;
304 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
305 unsigned depth0
, struct intel_mipmap_level
*table
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
309 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
311 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
312 if (!table
[level
].slice
)
319 for (unsigned level
= first_level
; level
<= last_level
; level
++)
320 free(table
[level
].slice
);
326 needs_separate_stencil(const struct brw_context
*brw
,
327 struct intel_mipmap_tree
*mt
,
328 mesa_format format
, uint32_t layout_flags
)
331 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
334 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
337 if (brw
->must_use_separate_stencil
)
340 return brw
->has_separate_stencil
&&
341 intel_miptree_supports_hiz(brw
, mt
);
345 * @param for_bo Indicates that the caller is
346 * intel_miptree_create_for_bo(). If true, then do not create
349 static struct intel_mipmap_tree
*
350 intel_miptree_create_layout(struct brw_context
*brw
,
359 uint32_t layout_flags
)
361 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
365 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
366 _mesa_enum_to_string(target
),
367 _mesa_get_format_name(format
),
368 first_level
, last_level
, depth0
, mt
);
370 if (target
== GL_TEXTURE_1D_ARRAY
)
371 assert(height0
== 1);
375 mt
->first_level
= first_level
;
376 mt
->last_level
= last_level
;
377 mt
->logical_width0
= width0
;
378 mt
->logical_height0
= height0
;
379 mt
->logical_depth0
= depth0
;
380 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
381 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
382 mt
->supports_fast_clear
= false;
383 mt
->aux_state
= NULL
;
384 mt
->cpp
= _mesa_get_format_bytes(format
);
385 mt
->num_samples
= num_samples
;
386 mt
->compressed
= _mesa_is_format_compressed(format
);
387 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
390 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
391 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
393 int depth_multiply
= 1;
394 if (num_samples
> 1) {
395 /* Adjust width/height/depth for MSAA */
396 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
397 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
398 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
399 * "If the surface is multisampled and it is a depth or stencil
400 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
401 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
404 * +----------------------------------------------------------------+
405 * | Num Multisamples | W_l = | H_l = |
406 * +----------------------------------------------------------------+
407 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
408 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
409 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
410 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
411 * +----------------------------------------------------------------+
414 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
415 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
416 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
418 * Another more complicated explanation for these adjustments comes
419 * from the Sandybridge PRM, volume 4, part 1, page 31:
421 * "Any of the other messages (sample*, LOD, load4) used with a
422 * (4x) multisampled surface will in-effect sample a surface with
423 * double the height and width as that indicated in the surface
424 * state. Each pixel position on the original-sized surface is
425 * replaced with a 2x2 of samples with the following arrangement:
430 * Thus, when sampling from a multisampled texture, it behaves as
431 * though the layout in memory for (x,y,sample) is:
433 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
434 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
436 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
437 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
439 * However, the actual layout of multisampled data in memory is:
441 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
442 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
444 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
445 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
447 * This pattern repeats for each 2x2 pixel block.
449 * As a result, when calculating the size of our 4-sample buffer for
450 * an odd width or height, we have to align before scaling up because
451 * sample 3 is in that bottom right 2x2 block.
453 switch (num_samples
) {
455 assert(brw
->gen
>= 8);
456 width0
= ALIGN(width0
, 2) * 2;
457 height0
= ALIGN(height0
, 2);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2) * 2;
464 width0
= ALIGN(width0
, 2) * 4;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 4;
472 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
475 unreachable("not reached");
478 /* Non-interleaved */
479 depth_multiply
= num_samples
;
480 depth0
*= depth_multiply
;
484 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
490 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
491 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
492 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
493 * used on Gen8 to make it pick a qpitch value which doesn't include space
494 * for the mipmaps. On Gen9 this is not necessary because it will
495 * automatically pick a packed qpitch value whenever mt->first_level ==
497 * TODO: can we use it elsewhere?
498 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
501 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
503 switch (mt
->surf
.msaa_layout
) {
504 case ISL_MSAA_LAYOUT_NONE
:
505 case ISL_MSAA_LAYOUT_INTERLEAVED
:
506 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
508 case ISL_MSAA_LAYOUT_ARRAY
:
509 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
514 if (target
== GL_TEXTURE_CUBE_MAP
)
515 assert(depth0
== 6 * depth_multiply
);
517 mt
->physical_width0
= width0
;
518 mt
->physical_height0
= height0
;
519 mt
->physical_depth0
= depth0
;
521 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
)) {
522 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
524 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
527 mt
->stencil_mt
= intel_miptree_create(brw
,
538 if (!mt
->stencil_mt
) {
539 intel_miptree_release(&mt
);
542 mt
->stencil_mt
->r8stencil_needs_update
= true;
544 /* Fix up the Z miptree format for how we're splitting out separate
545 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
547 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
550 if (format
== mt
->format
) {
551 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
552 _mesa_get_format_name(mt
->format
));
556 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
557 mt
->array_layout
= GEN6_HIZ_STENCIL
;
560 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
561 * multisampled or have an AUX buffer attached to it.
563 * GEN | MSRT | AUX_CCS_* or AUX_MCS
564 * -------------------------------------------
565 * 9 | HALIGN_16 | HALIGN_16
566 * 8 | HALIGN_ANY | HALIGN_16
570 if (intel_miptree_supports_ccs(brw
, mt
)) {
571 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
572 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
573 } else if (brw
->gen
>= 9 && num_samples
> 1) {
574 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
576 const UNUSED
bool is_lossless_compressed_aux
=
577 brw
->gen
>= 9 && num_samples
== 1 &&
578 mt
->format
== MESA_FORMAT_R_UINT32
;
580 /* For now, nothing else has this requirement */
581 assert(is_lossless_compressed_aux
||
582 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
585 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
586 intel_miptree_release(&mt
);
595 * Choose the aux usage for this miptree. This function must be called fairly
596 * late in the miptree create process after we have a tiling.
599 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
600 struct intel_mipmap_tree
*mt
)
602 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
604 const unsigned no_flags
= 0;
605 if (mt
->num_samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
606 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
607 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
608 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
609 intel_miptree_supports_ccs(brw
, mt
)) {
610 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
611 brw
->gen
>= 9 && !mt
->is_scanout
&&
612 intel_miptree_supports_ccs_e(brw
, mt
)) {
613 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
615 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
617 } else if (intel_tiling_supports_hiz(brw
, mt
->tiling
) &&
618 intel_miptree_supports_hiz(brw
, mt
)) {
619 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
622 /* We can do fast-clear on all auxiliary surface types that are
623 * allocated through the normal texture creation paths.
625 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
626 mt
->supports_fast_clear
= true;
631 * Choose an appropriate uncompressed format for a requested
632 * compressed format, if unsupported.
635 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
637 /* No need to lower ETC formats on these platforms,
638 * they are supported natively.
640 if (brw
->gen
>= 8 || brw
->is_baytrail
)
644 case MESA_FORMAT_ETC1_RGB8
:
645 return MESA_FORMAT_R8G8B8X8_UNORM
;
646 case MESA_FORMAT_ETC2_RGB8
:
647 return MESA_FORMAT_R8G8B8X8_UNORM
;
648 case MESA_FORMAT_ETC2_SRGB8
:
649 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
650 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
651 return MESA_FORMAT_B8G8R8A8_SRGB
;
652 case MESA_FORMAT_ETC2_RGBA8_EAC
:
653 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
654 return MESA_FORMAT_R8G8B8A8_UNORM
;
655 case MESA_FORMAT_ETC2_R11_EAC
:
656 return MESA_FORMAT_R_UNORM16
;
657 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
658 return MESA_FORMAT_R_SNORM16
;
659 case MESA_FORMAT_ETC2_RG11_EAC
:
660 return MESA_FORMAT_R16G16_UNORM
;
661 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
662 return MESA_FORMAT_R16G16_SNORM
;
664 /* Non ETC1 / ETC2 format */
669 /** \brief Assert that the level and layer are valid for the miptree. */
671 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
679 assert(level
>= mt
->first_level
);
680 assert(level
<= mt
->last_level
);
682 if (mt
->surf
.size
> 0)
683 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
684 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
685 mt
->surf
.phys_level0_sa
.array_len
));
687 assert(layer
< mt
->level
[level
].depth
);
690 static enum isl_aux_state
**
691 create_aux_state_map(struct intel_mipmap_tree
*mt
,
692 enum isl_aux_state initial
)
694 const uint32_t levels
= mt
->last_level
+ 1;
696 uint32_t total_slices
= 0;
697 for (uint32_t level
= 0; level
< levels
; level
++)
698 total_slices
+= mt
->level
[level
].depth
;
700 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
702 /* We're going to allocate a single chunk of data for both the per-level
703 * reference array and the arrays of aux_state. This makes cleanup
704 * significantly easier.
706 const size_t total_size
= per_level_array_size
+
707 total_slices
* sizeof(enum isl_aux_state
);
708 void *data
= malloc(total_size
);
712 enum isl_aux_state
**per_level_arr
= data
;
713 enum isl_aux_state
*s
= data
+ per_level_array_size
;
714 for (uint32_t level
= 0; level
< levels
; level
++) {
715 per_level_arr
[level
] = s
;
716 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
719 assert((void *)s
== data
+ total_size
);
721 return per_level_arr
;
725 free_aux_state_map(enum isl_aux_state
**state
)
730 static struct intel_mipmap_tree
*
731 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
732 unsigned first_level
, unsigned last_level
,
733 unsigned width0
, unsigned height0
, unsigned depth0
,
734 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
735 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
736 unsigned row_pitch
, struct brw_bo
*bo
)
738 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
742 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
750 if (target
== GL_TEXTURE_CUBE_MAP
||
751 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
752 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
754 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
756 _mesa_enum_to_string(target
),
757 _mesa_get_format_name(format
),
758 num_samples
, width0
, height0
, depth0
,
759 first_level
, last_level
, mt
);
761 struct isl_surf_init_info init_info
= {
762 .dim
= get_isl_surf_dim(target
),
763 .format
= translate_tex_format(brw
, format
, false),
766 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
767 .levels
= last_level
- first_level
+ 1,
768 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
769 .samples
= MAX2(num_samples
, 1),
770 .row_pitch
= row_pitch
,
771 .usage
= isl_usage_flags
,
772 .tiling_flags
= tiling_flags
,
775 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
778 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
781 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
783 isl_tiling_to_bufmgr_tiling(
785 mt
->surf
.row_pitch
, alloc_flags
);
792 mt
->first_level
= first_level
;
793 mt
->last_level
= last_level
;
796 mt
->aux_state
= NULL
;
801 intel_miptree_release(&mt
);
805 static struct intel_mipmap_tree
*
806 miptree_create(struct brw_context
*brw
,
815 uint32_t layout_flags
)
817 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
818 return make_surface(brw
, target
, format
, first_level
, last_level
,
819 width0
, height0
, depth0
, num_samples
,
821 ISL_SURF_USAGE_STENCIL_BIT
|
822 ISL_SURF_USAGE_TEXTURE_BIT
,
823 BO_ALLOC_FOR_RENDER
, 0, NULL
);
825 struct intel_mipmap_tree
*mt
;
826 mesa_format tex_format
= format
;
827 mesa_format etc_format
= MESA_FORMAT_NONE
;
828 uint32_t alloc_flags
= 0;
830 format
= intel_lower_compressed_format(brw
, format
);
832 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
834 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
835 mt
= intel_miptree_create_layout(brw
, target
, format
,
836 first_level
, last_level
, width0
,
837 height0
, depth0
, num_samples
,
842 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
843 mt
->tiling
= I915_TILING_Y
;
845 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
846 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
848 mt
->etc_format
= etc_format
;
850 if (format
== MESA_FORMAT_S_UINT8
) {
851 /* Align to size of W tile, 64x64. */
852 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
853 ALIGN(mt
->total_width
, 64),
854 ALIGN(mt
->total_height
, 64),
855 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
858 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
859 mt
->total_width
, mt
->total_height
,
860 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
864 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
865 mt
->bo
->cache_coherent
= false;
867 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
868 intel_miptree_choose_aux_usage(brw
, mt
);
873 struct intel_mipmap_tree
*
874 intel_miptree_create(struct brw_context
*brw
,
883 uint32_t layout_flags
)
885 struct intel_mipmap_tree
*mt
= miptree_create(
887 first_level
, last_level
,
888 width0
, height0
, depth0
, num_samples
,
893 /* If the BO is too large to fit in the aperture, we need to use the
894 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
895 * handle Y-tiling, so we need to fall back to X.
897 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
898 mt
->tiling
== I915_TILING_Y
) {
899 const uint32_t alloc_flags
=
900 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
901 BO_ALLOC_FOR_RENDER
: 0;
902 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
903 mt
->total_width
, mt
->total_height
);
905 mt
->tiling
= I915_TILING_X
;
906 brw_bo_unreference(mt
->bo
);
907 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
908 mt
->total_width
, mt
->total_height
, mt
->cpp
,
909 mt
->tiling
, &mt
->pitch
, alloc_flags
);
915 intel_miptree_release(&mt
);
919 if (!intel_miptree_alloc_aux(brw
, mt
)) {
920 intel_miptree_release(&mt
);
927 struct intel_mipmap_tree
*
928 intel_miptree_create_for_bo(struct brw_context
*brw
,
936 uint32_t layout_flags
)
938 struct intel_mipmap_tree
*mt
;
939 uint32_t tiling
, swizzle
;
940 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
942 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
943 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
944 0, 0, width
, height
, depth
, 1,
946 ISL_SURF_USAGE_STENCIL_BIT
|
947 ISL_SURF_USAGE_TEXTURE_BIT
,
948 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
952 assert(bo
->size
>= mt
->surf
.size
);
954 brw_bo_reference(bo
);
958 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
960 /* Nothing will be able to use this miptree with the BO if the offset isn't
963 if (tiling
!= I915_TILING_NONE
)
964 assert(offset
% 4096 == 0);
966 /* miptrees can't handle negative pitch. If you need flipping of images,
967 * that's outside of the scope of the mt.
971 /* The BO already has a tiling format and we shouldn't confuse the lower
972 * layers by making it try to find a tiling format again.
974 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
975 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
977 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
978 mt
= intel_miptree_create_layout(brw
, target
, format
,
980 width
, height
, depth
, 0,
985 brw_bo_reference(bo
);
991 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
992 intel_miptree_choose_aux_usage(brw
, mt
);
997 static struct intel_mipmap_tree
*
998 miptree_create_for_planar_image(struct brw_context
*brw
,
999 __DRIimage
*image
, GLenum target
)
1001 struct intel_image_format
*f
= image
->planar_format
;
1002 struct intel_mipmap_tree
*planar_mt
= NULL
;
1004 for (int i
= 0; i
< f
->nplanes
; i
++) {
1005 const int index
= f
->planes
[i
].buffer_index
;
1006 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1007 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1008 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1009 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1011 /* Disable creation of the texture's aux buffers because the driver
1012 * exposes no EGL API to manage them. That is, there is no API for
1013 * resolving the aux buffer's content to the main buffer nor for
1014 * invalidating the aux buffer's content.
1016 struct intel_mipmap_tree
*mt
=
1017 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1018 image
->offsets
[index
],
1020 image
->strides
[index
],
1021 MIPTREE_LAYOUT_DISABLE_AUX
);
1025 mt
->target
= target
;
1030 planar_mt
->plane
[i
- 1] = mt
;
1036 struct intel_mipmap_tree
*
1037 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1038 __DRIimage
*image
, GLenum target
,
1039 enum isl_colorspace colorspace
,
1040 bool is_winsys_image
)
1042 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1043 assert(colorspace
== ISL_COLORSPACE_NONE
||
1044 colorspace
== ISL_COLORSPACE_YUV
);
1045 return miptree_create_for_planar_image(brw
, image
, target
);
1048 mesa_format format
= image
->format
;
1049 switch (colorspace
) {
1050 case ISL_COLORSPACE_NONE
:
1051 /* Keep the image format unmodified */
1054 case ISL_COLORSPACE_LINEAR
:
1055 format
=_mesa_get_srgb_format_linear(format
);
1058 case ISL_COLORSPACE_SRGB
:
1059 format
=_mesa_get_linear_format_srgb(format
);
1063 unreachable("Inalid colorspace for non-planar image");
1066 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1067 /* The texture storage paths in core Mesa detect if the driver does not
1068 * support the user-requested format, and then searches for a
1069 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1070 * do the fallbacks here for important formats.
1072 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1073 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1074 * the Chrome OS compositor consumes as dma_buf EGLImages.
1076 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1079 if (!brw
->ctx
.TextureFormatSupported
[format
])
1082 /* If this image comes in from a window system, we have different
1083 * requirements than if it comes in via an EGL import operation. Window
1084 * system images can use any form of auxiliary compression we wish because
1085 * they get "flushed" before being handed off to the window system and we
1086 * have the opportunity to do resolves. Window system buffers also may be
1087 * used for scanout so we need to flag that appropriately.
1089 const uint32_t mt_layout_flags
=
1090 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1092 /* Disable creation of the texture's aux buffers because the driver exposes
1093 * no EGL API to manage them. That is, there is no API for resolving the aux
1094 * buffer's content to the main buffer nor for invalidating the aux buffer's
1097 struct intel_mipmap_tree
*mt
=
1098 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1099 image
->offset
, image
->width
, image
->height
, 1,
1100 image
->pitch
, mt_layout_flags
);
1104 mt
->target
= target
;
1105 mt
->level
[0].level_x
= image
->tile_x
;
1106 mt
->level
[0].level_y
= image
->tile_y
;
1107 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1108 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1110 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1111 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1112 * trouble resolving back to destination image due to alignment issues.
1114 if (!brw
->has_surface_tile_offset
) {
1115 uint32_t draw_x
, draw_y
;
1116 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1118 if (draw_x
!= 0 || draw_y
!= 0) {
1119 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1120 intel_miptree_release(&mt
);
1125 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1126 intel_miptree_release(&mt
);
1134 * For a singlesample renderbuffer, this simply wraps the given BO with a
1137 * For a multisample renderbuffer, this wraps the window system's
1138 * (singlesample) BO with a singlesample miptree attached to the
1139 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1140 * that will contain the actual rendering (which is lazily resolved to
1141 * irb->singlesample_mt).
1144 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1145 struct intel_renderbuffer
*irb
,
1146 struct intel_mipmap_tree
*singlesample_mt
,
1147 uint32_t width
, uint32_t height
,
1150 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1151 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1152 mesa_format format
= rb
->Format
;
1153 int num_samples
= rb
->NumSamples
;
1155 /* Only the front and back buffers, which are color buffers, are allocated
1156 * through the image loader.
1158 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1159 _mesa_get_format_base_format(format
) == GL_RGBA
);
1161 assert(singlesample_mt
);
1163 if (num_samples
== 0) {
1164 intel_miptree_release(&irb
->mt
);
1165 irb
->mt
= singlesample_mt
;
1167 assert(!irb
->singlesample_mt
);
1169 intel_miptree_release(&irb
->singlesample_mt
);
1170 irb
->singlesample_mt
= singlesample_mt
;
1173 irb
->mt
->logical_width0
!= width
||
1174 irb
->mt
->logical_height0
!= height
) {
1175 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1180 if (!multisample_mt
)
1183 irb
->need_downsample
= false;
1184 intel_miptree_release(&irb
->mt
);
1185 irb
->mt
= multisample_mt
;
1191 intel_miptree_release(&irb
->mt
);
1195 struct intel_mipmap_tree
*
1196 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1200 uint32_t num_samples
)
1202 struct intel_mipmap_tree
*mt
;
1204 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1205 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1206 MIPTREE_LAYOUT_TILING_ANY
|
1207 MIPTREE_LAYOUT_FOR_SCANOUT
;
1209 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1210 width
, height
, depth
, num_samples
,
1218 intel_miptree_release(&mt
);
1223 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1224 struct intel_mipmap_tree
*src
)
1229 intel_miptree_release(dst
);
1233 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1240 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1242 if (aux_buf
== NULL
)
1245 brw_bo_unreference(aux_buf
->bo
);
1251 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1256 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1257 if (--(*mt
)->refcount
<= 0) {
1260 DBG("%s deleting %p\n", __func__
, *mt
);
1262 brw_bo_unreference((*mt
)->bo
);
1263 intel_miptree_release(&(*mt
)->stencil_mt
);
1264 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1265 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1266 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1267 free_aux_state_map((*mt
)->aux_state
);
1269 intel_miptree_release(&(*mt
)->plane
[0]);
1270 intel_miptree_release(&(*mt
)->plane
[1]);
1272 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1273 free((*mt
)->level
[i
].slice
);
1283 intel_get_image_dims(struct gl_texture_image
*image
,
1284 int *width
, int *height
, int *depth
)
1286 switch (image
->TexObject
->Target
) {
1287 case GL_TEXTURE_1D_ARRAY
:
1288 /* For a 1D Array texture the OpenGL API will treat the image height as
1289 * the number of array slices. For Intel hardware, we treat the 1D array
1290 * as a 2D Array with a height of 1. So, here we want to swap image
1293 assert(image
->Depth
== 1);
1294 *width
= image
->Width
;
1296 *depth
= image
->Height
;
1298 case GL_TEXTURE_CUBE_MAP
:
1299 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1300 * though we really have 6 slices.
1302 assert(image
->Depth
== 1);
1303 *width
= image
->Width
;
1304 *height
= image
->Height
;
1308 *width
= image
->Width
;
1309 *height
= image
->Height
;
1310 *depth
= image
->Depth
;
1316 * Can the image be pulled into a unified mipmap tree? This mirrors
1317 * the completeness test in a lot of ways.
1319 * Not sure whether I want to pass gl_texture_image here.
1322 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1323 struct gl_texture_image
*image
)
1325 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1326 GLuint level
= intelImage
->base
.Base
.Level
;
1327 int width
, height
, depth
;
1329 /* glTexImage* choose the texture object based on the target passed in, and
1330 * objects can't change targets over their lifetimes, so this should be
1333 assert(image
->TexObject
->Target
== mt
->target
);
1335 mesa_format mt_format
= mt
->format
;
1336 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1337 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1338 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1339 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1340 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1341 mt_format
= mt
->etc_format
;
1343 if (image
->TexFormat
!= mt_format
)
1346 intel_get_image_dims(image
, &width
, &height
, &depth
);
1348 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1351 if (mt
->surf
.size
> 0) {
1352 if (level
>= mt
->surf
.levels
)
1355 const unsigned level_depth
=
1356 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1357 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1358 mt
->surf
.logical_level0_px
.array_len
;
1360 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1361 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1362 depth
== level_depth
&&
1363 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1366 int level_depth
= mt
->level
[level
].depth
;
1367 if (mt
->num_samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1368 level_depth
/= mt
->num_samples
;
1370 /* Test image dimensions against the base level image adjusted for
1371 * minification. This will also catch images not present in the
1372 * tree, changed targets, etc.
1374 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1375 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1376 depth
!= level_depth
) {
1380 if (image
->NumSamples
!= mt
->num_samples
)
1388 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1390 GLuint x
, GLuint y
, GLuint d
)
1392 mt
->level
[level
].depth
= d
;
1393 mt
->level
[level
].level_x
= x
;
1394 mt
->level
[level
].level_y
= y
;
1396 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1399 assert(mt
->level
[level
].slice
);
1401 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1402 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1407 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1408 GLuint level
, GLuint img
,
1411 if (img
== 0 && level
== 0)
1412 assert(x
== 0 && y
== 0);
1414 assert(img
< mt
->level
[level
].depth
);
1416 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1417 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1419 DBG("%s level %d img %d pos %d,%d\n",
1420 __func__
, level
, img
,
1421 mt
->level
[level
].slice
[img
].x_offset
,
1422 mt
->level
[level
].slice
[img
].y_offset
);
1426 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1427 GLuint level
, GLuint slice
,
1428 GLuint
*x
, GLuint
*y
)
1430 if (mt
->surf
.size
> 0) {
1431 uint32_t x_offset_sa
, y_offset_sa
;
1433 /* Given level is relative to level zero while the miptree may be
1434 * represent just a subset of all levels starting from 'first_level'.
1436 assert(level
>= mt
->first_level
);
1437 level
-= mt
->first_level
;
1439 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1440 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1441 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1442 &x_offset_sa
, &y_offset_sa
);
1449 assert(slice
< mt
->level
[level
].depth
);
1451 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1452 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1457 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1458 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1459 * and tile_h is set to 1.
1462 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1463 uint32_t *tile_w
, uint32_t *tile_h
)
1474 case I915_TILING_NONE
:
1479 unreachable("not reached");
1485 * This function computes masks that may be used to select the bits of the X
1486 * and Y coordinates that indicate the offset within a tile. If the BO is
1487 * untiled, the masks are set to 0.
1490 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1491 uint32_t *mask_x
, uint32_t *mask_y
)
1493 uint32_t tile_w_bytes
, tile_h
;
1495 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1497 *mask_x
= tile_w_bytes
/ cpp
- 1;
1498 *mask_y
= tile_h
- 1;
1502 * Compute the offset (in bytes) from the start of the BO to the given x
1503 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1504 * multiples of the tile size.
1507 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1508 uint32_t x
, uint32_t y
)
1511 uint32_t pitch
= mt
->pitch
;
1512 uint32_t tiling
= mt
->tiling
;
1516 unreachable("not reached");
1517 case I915_TILING_NONE
:
1518 return y
* pitch
+ x
* cpp
;
1520 assert((x
% (512 / cpp
)) == 0);
1521 assert((y
% 8) == 0);
1522 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1524 assert((x
% (128 / cpp
)) == 0);
1525 assert((y
% 32) == 0);
1526 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1531 * Rendering with tiled buffers requires that the base address of the buffer
1532 * be aligned to a page boundary. For renderbuffers, and sometimes with
1533 * textures, we may want the surface to point at a texture image level that
1534 * isn't at a page boundary.
1536 * This function returns an appropriately-aligned base offset
1537 * according to the tiling restrictions, plus any required x/y offset
1541 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1542 GLuint level
, GLuint slice
,
1547 uint32_t mask_x
, mask_y
;
1549 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1550 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1552 *tile_x
= x
& mask_x
;
1553 *tile_y
= y
& mask_y
;
1555 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1559 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1560 struct intel_mipmap_tree
*src_mt
,
1561 unsigned src_level
, unsigned src_layer
,
1562 struct intel_mipmap_tree
*dst_mt
,
1563 unsigned dst_level
, unsigned dst_layer
,
1564 unsigned width
, unsigned height
)
1567 ptrdiff_t src_stride
, dst_stride
;
1568 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1569 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1571 intel_miptree_map(brw
, src_mt
,
1572 src_level
, src_layer
,
1575 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1578 intel_miptree_map(brw
, dst_mt
,
1579 dst_level
, dst_layer
,
1582 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1586 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1587 _mesa_get_format_name(src_mt
->format
),
1588 src_mt
, src
, src_stride
,
1589 _mesa_get_format_name(dst_mt
->format
),
1590 dst_mt
, dst
, dst_stride
,
1593 int row_size
= cpp
* width
;
1594 if (src_stride
== row_size
&&
1595 dst_stride
== row_size
) {
1596 memcpy(dst
, src
, row_size
* height
);
1598 for (int i
= 0; i
< height
; i
++) {
1599 memcpy(dst
, src
, row_size
);
1605 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1606 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1608 /* Don't forget to copy the stencil data over, too. We could have skipped
1609 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1610 * shuffling the two data sources in/out of temporary storage instead of
1611 * the direct mapping we get this way.
1613 if (dst_mt
->stencil_mt
) {
1614 assert(src_mt
->stencil_mt
);
1615 intel_miptree_copy_slice_sw(brw
,
1616 src_mt
->stencil_mt
, src_level
, src_layer
,
1617 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1623 intel_miptree_copy_slice(struct brw_context
*brw
,
1624 struct intel_mipmap_tree
*src_mt
,
1625 unsigned src_level
, unsigned src_layer
,
1626 struct intel_mipmap_tree
*dst_mt
,
1627 unsigned dst_level
, unsigned dst_layer
)
1630 mesa_format format
= src_mt
->format
;
1631 uint32_t width
, height
;
1633 if (src_mt
->surf
.size
> 0) {
1634 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1635 src_level
- src_mt
->first_level
);
1636 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1637 src_level
- src_mt
->first_level
);
1639 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1640 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1641 src_level
- src_mt
->first_level
));
1643 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1645 width
= minify(src_mt
->physical_width0
,
1646 src_level
- src_mt
->first_level
);
1647 height
= minify(src_mt
->physical_height0
,
1648 src_level
- src_mt
->first_level
);
1649 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1652 assert(src_mt
->format
== dst_mt
->format
);
1654 if (dst_mt
->compressed
) {
1656 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1657 height
= ALIGN_NPOT(height
, j
) / j
;
1658 width
= ALIGN_NPOT(width
, i
) / i
;
1661 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1662 * below won't apply since we can't do the depth's Y tiling or the
1663 * stencil's W tiling in the blitter.
1665 if (src_mt
->stencil_mt
) {
1666 intel_miptree_copy_slice_sw(brw
,
1667 src_mt
, src_level
, src_layer
,
1668 dst_mt
, dst_level
, dst_layer
,
1673 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1674 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1676 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1679 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1680 _mesa_get_format_name(src_mt
->format
),
1681 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1682 _mesa_get_format_name(dst_mt
->format
),
1683 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1686 if (!intel_miptree_blit(brw
,
1687 src_mt
, src_level
, src_layer
, 0, 0, false,
1688 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1689 width
, height
, GL_COPY
)) {
1690 perf_debug("miptree validate blit for %s failed\n",
1691 _mesa_get_format_name(format
));
1693 intel_miptree_copy_slice_sw(brw
,
1694 src_mt
, src_level
, src_layer
,
1695 dst_mt
, dst_level
, dst_layer
,
1701 * Copies the image's current data to the given miptree, and associates that
1702 * miptree with the image.
1704 * If \c invalidate is true, then the actual image data does not need to be
1705 * copied, but the image still needs to be associated to the new miptree (this
1706 * is set to true if we're about to clear the image).
1709 intel_miptree_copy_teximage(struct brw_context
*brw
,
1710 struct intel_texture_image
*intelImage
,
1711 struct intel_mipmap_tree
*dst_mt
,
1714 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1715 struct intel_texture_object
*intel_obj
=
1716 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1717 int level
= intelImage
->base
.Base
.Level
;
1718 const unsigned face
= intelImage
->base
.Base
.Face
;
1719 unsigned start_layer
, end_layer
;
1721 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1723 assert(intelImage
->base
.Base
.Height
);
1725 end_layer
= intelImage
->base
.Base
.Height
- 1;
1726 } else if (face
> 0) {
1730 assert(intelImage
->base
.Base
.Depth
);
1732 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1736 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1737 intel_miptree_copy_slice(brw
,
1743 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1744 intel_obj
->needs_validate
= true;
1748 intel_miptree_init_mcs(struct brw_context
*brw
,
1749 struct intel_mipmap_tree
*mt
,
1752 assert(mt
->mcs_buf
!= NULL
);
1754 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1756 * When MCS buffer is enabled and bound to MSRT, it is required that it
1757 * is cleared prior to any rendering.
1759 * Since we don't use the MCS buffer for any purpose other than rendering,
1760 * it makes sense to just clear it immediately upon allocation.
1762 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1764 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1765 if (unlikely(map
== NULL
)) {
1766 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1767 brw_bo_unreference(mt
->mcs_buf
->bo
);
1772 memset(data
, init_value
, mt
->mcs_buf
->size
);
1773 brw_bo_unmap(mt
->mcs_buf
->bo
);
1776 static struct intel_miptree_aux_buffer
*
1777 intel_alloc_aux_buffer(struct brw_context
*brw
,
1779 const struct isl_surf
*aux_surf
,
1780 uint32_t alloc_flags
,
1781 struct intel_mipmap_tree
*mt
)
1783 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1787 buf
->size
= aux_surf
->size
;
1788 buf
->pitch
= aux_surf
->row_pitch
;
1789 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1791 /* ISL has stricter set of alignment rules then the drm allocator.
1792 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1793 * trying to recalculate based on different format block sizes.
1795 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1796 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1802 buf
->surf
= *aux_surf
;
1808 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1809 struct intel_mipmap_tree
*mt
,
1812 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1813 assert(mt
->mcs_buf
== NULL
);
1814 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1816 /* Multisampled miptrees are only supported for single level. */
1817 assert(mt
->first_level
== 0);
1818 enum isl_aux_state
**aux_state
=
1819 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1823 struct isl_surf temp_main_surf
;
1824 struct isl_surf temp_mcs_surf
;
1826 /* Create first an ISL presentation for the main color surface and let ISL
1827 * calculate equivalent MCS surface against it.
1829 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1830 MAYBE_UNUSED
bool ok
=
1831 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1834 /* Buffer needs to be initialised requiring the buffer to be immediately
1835 * mapped to cpu space for writing. Therefore do not use the gpu access
1836 * flag which can cause an unnecessary delay if the backing pages happened
1837 * to be just used by the GPU.
1839 const uint32_t alloc_flags
= 0;
1840 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1841 &temp_mcs_surf
, alloc_flags
, mt
);
1847 mt
->aux_state
= aux_state
;
1849 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1855 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1856 struct intel_mipmap_tree
*mt
)
1858 assert(mt
->mcs_buf
== NULL
);
1859 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1860 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1862 struct isl_surf temp_main_surf
;
1863 struct isl_surf temp_ccs_surf
;
1865 /* Create first an ISL presentation for the main color surface and let ISL
1866 * calculate equivalent CCS surface against it.
1868 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1869 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1873 assert(temp_ccs_surf
.size
&&
1874 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1876 enum isl_aux_state
**aux_state
=
1877 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1881 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1882 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1884 * "If Software wants to enable Color Compression without Fast clear,
1885 * Software needs to initialize MCS with zeros."
1887 * A CCS value of 0 indicates that the corresponding block is in the
1888 * pass-through state which is what we want.
1890 * For CCS_D, on the other hand, we don't care as we're about to perform a
1891 * fast-clear operation. In that case, being hot in caches more useful.
1893 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1894 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1895 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1896 &temp_ccs_surf
, alloc_flags
, mt
);
1902 mt
->aux_state
= aux_state
;
1908 * Helper for intel_miptree_alloc_hiz() that sets
1909 * \c mt->level[level].has_hiz. Return true if and only if
1910 * \c has_hiz was set.
1913 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1914 struct intel_mipmap_tree
*mt
,
1917 assert(mt
->hiz_buf
);
1919 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1920 uint32_t width
= minify(mt
->physical_width0
, level
);
1921 uint32_t height
= minify(mt
->physical_height0
, level
);
1923 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1924 * and the height is 4 aligned. This allows our HiZ support
1925 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1926 * we can grow the width & height to allow the HiZ op to
1927 * force the proper size alignments.
1929 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1930 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1935 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1936 mt
->level
[level
].has_hiz
= true;
1941 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1942 struct intel_mipmap_tree
*mt
)
1944 assert(mt
->hiz_buf
== NULL
);
1945 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1947 enum isl_aux_state
**aux_state
=
1948 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1952 struct isl_surf temp_main_surf
;
1953 struct isl_surf temp_hiz_surf
;
1955 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1956 MAYBE_UNUSED
bool ok
=
1957 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1960 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1961 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1962 &temp_hiz_surf
, alloc_flags
, mt
);
1969 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1970 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1972 mt
->aux_state
= aux_state
;
1979 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1981 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1982 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1983 * compress clear color so we wait until an actual fast-clear to allocate it.
1986 intel_miptree_alloc_aux(struct brw_context
*brw
,
1987 struct intel_mipmap_tree
*mt
)
1989 switch (mt
->aux_usage
) {
1990 case ISL_AUX_USAGE_NONE
:
1993 case ISL_AUX_USAGE_HIZ
:
1994 assert(!_mesa_is_format_color_format(mt
->format
));
1995 if (!intel_miptree_alloc_hiz(brw
, mt
))
1999 case ISL_AUX_USAGE_MCS
:
2000 assert(_mesa_is_format_color_format(mt
->format
));
2001 assert(mt
->num_samples
> 1);
2002 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->num_samples
))
2006 case ISL_AUX_USAGE_CCS_D
:
2007 /* Since CCS_D can only compress clear color so we wait until an actual
2008 * fast-clear to allocate it.
2012 case ISL_AUX_USAGE_CCS_E
:
2013 assert(_mesa_is_format_color_format(mt
->format
));
2014 assert(mt
->num_samples
<= 1);
2015 if (!intel_miptree_alloc_ccs(brw
, mt
))
2020 unreachable("Invalid aux usage");
2025 * Can the miptree sample using the hiz buffer?
2028 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2029 struct intel_mipmap_tree
*mt
)
2031 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2032 * so keep things conservative for now and never enable it unless we're SKL+.
2042 /* It seems the hardware won't fallback to the depth buffer if some of the
2043 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2044 * of the texture to be HiZ enabled.
2046 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2047 if (!intel_miptree_level_has_hiz(mt
, level
))
2051 /* If compressed multisampling is enabled, then we use it for the auxiliary
2054 * From the BDW PRM (Volume 2d: Command Reference: Structures
2055 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2057 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2058 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2060 * There is no such blurb for 1D textures, but there is sufficient evidence
2061 * that this is broken on SKL+.
2063 return (mt
->num_samples
<= 1 &&
2064 mt
->target
!= GL_TEXTURE_3D
&&
2065 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2069 * Does the miptree slice have hiz enabled?
2072 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2074 intel_miptree_check_level_layer(mt
, level
, 0);
2075 return mt
->level
[level
].has_hiz
;
2079 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2080 unsigned start_level
, unsigned num_levels
,
2081 unsigned start_layer
, unsigned num_layers
)
2083 assert(_mesa_is_format_color_format(mt
->format
));
2088 /* Clamp the level range to fit the miptree */
2089 assert(start_level
+ num_levels
>= start_level
);
2090 const uint32_t last_level
=
2091 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2092 start_level
= MAX2(mt
->first_level
, start_level
);
2093 num_levels
= last_level
- start_level
+ 1;
2095 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2096 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2097 for (unsigned a
= 0; a
< level_layers
; a
++) {
2098 enum isl_aux_state aux_state
=
2099 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2100 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2101 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2110 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2111 const struct intel_mipmap_tree
*mt
,
2112 unsigned level
, unsigned layer
)
2118 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2119 assert(brw
->gen
>= 8 ||
2120 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2122 /* Compression of arrayed msaa surfaces is supported. */
2123 if (mt
->num_samples
> 1)
2126 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2127 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2133 static enum blorp_fast_clear_op
2134 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2135 bool ccs_supported
, bool fast_clear_supported
)
2137 assert(ccs_supported
== fast_clear_supported
);
2139 switch (aux_state
) {
2140 case ISL_AUX_STATE_CLEAR
:
2141 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2143 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2145 return BLORP_FAST_CLEAR_OP_NONE
;
2147 case ISL_AUX_STATE_PASS_THROUGH
:
2148 return BLORP_FAST_CLEAR_OP_NONE
;
2150 case ISL_AUX_STATE_RESOLVED
:
2151 case ISL_AUX_STATE_AUX_INVALID
:
2152 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2156 unreachable("Invalid aux state for CCS_D");
2159 static enum blorp_fast_clear_op
2160 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2161 bool ccs_supported
, bool fast_clear_supported
)
2163 switch (aux_state
) {
2164 case ISL_AUX_STATE_CLEAR
:
2165 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2167 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2168 else if (!fast_clear_supported
)
2169 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2171 return BLORP_FAST_CLEAR_OP_NONE
;
2173 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2175 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2177 return BLORP_FAST_CLEAR_OP_NONE
;
2179 case ISL_AUX_STATE_PASS_THROUGH
:
2180 return BLORP_FAST_CLEAR_OP_NONE
;
2182 case ISL_AUX_STATE_RESOLVED
:
2183 case ISL_AUX_STATE_AUX_INVALID
:
2187 unreachable("Invalid aux state for CCS_E");
2191 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2192 struct intel_mipmap_tree
*mt
,
2193 uint32_t level
, uint32_t layer
,
2195 bool fast_clear_supported
)
2197 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2199 enum blorp_fast_clear_op resolve_op
;
2200 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2201 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2202 fast_clear_supported
);
2204 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2205 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2206 fast_clear_supported
);
2209 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2210 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2211 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2213 switch (resolve_op
) {
2214 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2215 /* The CCS full resolve operation destroys the CCS and sets it to the
2216 * pass-through state. (You can also think of this as being both a
2217 * resolve and an ambiguate in one operation.)
2219 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2220 ISL_AUX_STATE_PASS_THROUGH
);
2223 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2224 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2225 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2229 unreachable("Invalid resolve op");
2235 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2236 struct intel_mipmap_tree
*mt
,
2237 uint32_t level
, uint32_t layer
,
2238 bool written_with_ccs
)
2240 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2242 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2243 switch (aux_state
) {
2244 case ISL_AUX_STATE_CLEAR
:
2245 assert(written_with_ccs
);
2246 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2247 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2250 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2251 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2252 assert(written_with_ccs
);
2253 break; /* Nothing to do */
2255 case ISL_AUX_STATE_PASS_THROUGH
:
2256 if (written_with_ccs
) {
2257 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2258 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2264 case ISL_AUX_STATE_RESOLVED
:
2265 case ISL_AUX_STATE_AUX_INVALID
:
2266 unreachable("Invalid aux state for CCS_E");
2269 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2270 /* CCS_D is a bit simpler */
2271 switch (aux_state
) {
2272 case ISL_AUX_STATE_CLEAR
:
2273 assert(written_with_ccs
);
2274 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2275 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2278 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2279 assert(written_with_ccs
);
2280 break; /* Nothing to do */
2282 case ISL_AUX_STATE_PASS_THROUGH
:
2286 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2287 case ISL_AUX_STATE_RESOLVED
:
2288 case ISL_AUX_STATE_AUX_INVALID
:
2289 unreachable("Invalid aux state for CCS_D");
2295 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2296 struct intel_mipmap_tree
*mt
,
2297 uint32_t level
, uint32_t layer
,
2298 bool written_with_aux
)
2300 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2301 case ISL_AUX_STATE_CLEAR
:
2302 assert(written_with_aux
);
2303 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2304 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2307 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2308 assert(written_with_aux
);
2309 break; /* Nothing to do */
2311 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2312 case ISL_AUX_STATE_RESOLVED
:
2313 case ISL_AUX_STATE_PASS_THROUGH
:
2314 case ISL_AUX_STATE_AUX_INVALID
:
2315 unreachable("Invalid aux state for MCS");
2320 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2321 struct intel_mipmap_tree
*mt
,
2322 uint32_t level
, uint32_t layer
,
2323 bool hiz_supported
, bool fast_clear_supported
)
2325 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2326 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2327 case ISL_AUX_STATE_CLEAR
:
2328 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2329 if (!hiz_supported
|| !fast_clear_supported
)
2330 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2333 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2335 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2338 case ISL_AUX_STATE_PASS_THROUGH
:
2339 case ISL_AUX_STATE_RESOLVED
:
2342 case ISL_AUX_STATE_AUX_INVALID
:
2344 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2348 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2349 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2352 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2353 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2354 ISL_AUX_STATE_RESOLVED
);
2357 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2358 /* The HiZ resolve operation is actually an ambiguate */
2359 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2360 ISL_AUX_STATE_PASS_THROUGH
);
2364 unreachable("Invalid HiZ op");
2370 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2371 struct intel_mipmap_tree
*mt
,
2372 uint32_t level
, uint32_t layer
,
2373 bool written_with_hiz
)
2375 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2376 case ISL_AUX_STATE_CLEAR
:
2377 assert(written_with_hiz
);
2378 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2379 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2382 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2383 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2384 assert(written_with_hiz
);
2385 break; /* Nothing to do */
2387 case ISL_AUX_STATE_RESOLVED
:
2388 if (written_with_hiz
) {
2389 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2390 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2392 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2393 ISL_AUX_STATE_AUX_INVALID
);
2397 case ISL_AUX_STATE_PASS_THROUGH
:
2398 if (written_with_hiz
) {
2399 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2400 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2404 case ISL_AUX_STATE_AUX_INVALID
:
2405 assert(!written_with_hiz
);
2410 static inline uint32_t
2411 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2412 uint32_t start_level
, uint32_t num_levels
)
2414 assert(start_level
>= mt
->first_level
);
2415 assert(start_level
<= mt
->last_level
);
2417 if (num_levels
== INTEL_REMAINING_LAYERS
)
2418 num_levels
= mt
->last_level
- start_level
+ 1;
2419 /* Check for overflow */
2420 assert(start_level
+ num_levels
>= start_level
);
2421 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2426 static inline uint32_t
2427 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2428 uint32_t start_layer
, uint32_t num_layers
)
2430 assert(level
<= mt
->last_level
);
2431 uint32_t total_num_layers
;
2433 if (mt
->surf
.size
> 0)
2434 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2435 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2436 mt
->surf
.phys_level0_sa
.array_len
;
2438 total_num_layers
= mt
->level
[level
].depth
;
2440 assert(start_layer
< total_num_layers
);
2441 if (num_layers
== INTEL_REMAINING_LAYERS
)
2442 num_layers
= total_num_layers
- start_layer
;
2443 /* Check for overflow */
2444 assert(start_layer
+ num_layers
>= start_layer
);
2445 assert(start_layer
+ num_layers
<= total_num_layers
);
2451 intel_miptree_prepare_access(struct brw_context
*brw
,
2452 struct intel_mipmap_tree
*mt
,
2453 uint32_t start_level
, uint32_t num_levels
,
2454 uint32_t start_layer
, uint32_t num_layers
,
2455 bool aux_supported
, bool fast_clear_supported
)
2457 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2459 if (_mesa_is_format_color_format(mt
->format
)) {
2463 if (mt
->num_samples
> 1) {
2464 /* Nothing to do for MSAA */
2465 assert(aux_supported
&& fast_clear_supported
);
2467 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2468 const uint32_t level
= start_level
+ l
;
2469 const uint32_t level_layers
=
2470 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2471 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2472 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2473 start_layer
+ a
, aux_supported
,
2474 fast_clear_supported
);
2478 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2479 /* Nothing to do for stencil */
2484 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2485 const uint32_t level
= start_level
+ l
;
2486 if (!intel_miptree_level_has_hiz(mt
, level
))
2489 const uint32_t level_layers
=
2490 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2491 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2492 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2494 fast_clear_supported
);
2501 intel_miptree_finish_write(struct brw_context
*brw
,
2502 struct intel_mipmap_tree
*mt
, uint32_t level
,
2503 uint32_t start_layer
, uint32_t num_layers
,
2504 bool written_with_aux
)
2506 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2508 if (_mesa_is_format_color_format(mt
->format
)) {
2512 if (mt
->num_samples
> 1) {
2513 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2514 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2518 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2519 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2523 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2524 /* Nothing to do for stencil */
2526 if (!intel_miptree_level_has_hiz(mt
, level
))
2529 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2530 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2537 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2538 uint32_t level
, uint32_t layer
)
2540 intel_miptree_check_level_layer(mt
, level
, layer
);
2542 if (_mesa_is_format_color_format(mt
->format
)) {
2543 assert(mt
->mcs_buf
!= NULL
);
2544 assert(mt
->num_samples
<= 1 ||
2545 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2546 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2547 unreachable("Cannot get aux state for stencil");
2549 assert(intel_miptree_level_has_hiz(mt
, level
));
2552 return mt
->aux_state
[level
][layer
];
2556 intel_miptree_set_aux_state(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
, uint32_t level
,
2558 uint32_t start_layer
, uint32_t num_layers
,
2559 enum isl_aux_state aux_state
)
2561 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2563 if (_mesa_is_format_color_format(mt
->format
)) {
2564 assert(mt
->mcs_buf
!= NULL
);
2565 assert(mt
->num_samples
<= 1 ||
2566 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2567 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2568 unreachable("Cannot get aux state for stencil");
2570 assert(intel_miptree_level_has_hiz(mt
, level
));
2573 for (unsigned a
= 0; a
< num_layers
; a
++)
2574 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2577 /* On Gen9 color buffers may be compressed by the hardware (lossless
2578 * compression). There are, however, format restrictions and care needs to be
2579 * taken that the sampler engine is capable for re-interpreting a buffer with
2580 * format different the buffer was originally written with.
2582 * For example, SRGB formats are not compressible and the sampler engine isn't
2583 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2584 * color buffer needs to be resolved so that the sampling surface can be
2585 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2589 can_texture_with_ccs(struct brw_context
*brw
,
2590 struct intel_mipmap_tree
*mt
,
2591 mesa_format view_format
)
2593 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2596 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2597 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2599 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2600 isl_mt_format
, isl_view_format
)) {
2601 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2602 _mesa_get_format_name(view_format
),
2603 _mesa_get_format_name(mt
->format
));
2611 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2612 struct intel_mipmap_tree
*mt
,
2613 mesa_format view_format
,
2614 uint32_t start_level
, uint32_t num_levels
,
2615 uint32_t start_layer
, uint32_t num_layers
,
2616 bool *aux_supported_out
)
2618 bool aux_supported
, clear_supported
;
2619 if (_mesa_is_format_color_format(mt
->format
)) {
2620 if (mt
->num_samples
> 1) {
2621 aux_supported
= clear_supported
= true;
2623 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2625 /* Clear color is specified as ints or floats and the conversion is
2626 * done by the sampler. If we have a texture view, we would have to
2627 * perform the clear color conversion manually. Just disable clear
2630 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2632 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2633 aux_supported
= clear_supported
= false;
2635 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2638 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2639 start_layer
, num_layers
,
2640 aux_supported
, clear_supported
);
2641 if (aux_supported_out
)
2642 *aux_supported_out
= aux_supported
;
2646 intel_miptree_prepare_texture(struct brw_context
*brw
,
2647 struct intel_mipmap_tree
*mt
,
2648 mesa_format view_format
,
2649 bool *aux_supported_out
)
2651 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2652 0, INTEL_REMAINING_LEVELS
,
2653 0, INTEL_REMAINING_LAYERS
,
2658 intel_miptree_prepare_image(struct brw_context
*brw
,
2659 struct intel_mipmap_tree
*mt
)
2661 /* The data port doesn't understand any compression */
2662 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2663 0, INTEL_REMAINING_LAYERS
, false, false);
2667 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2668 struct intel_mipmap_tree
*mt
, uint32_t level
,
2669 uint32_t start_layer
, uint32_t num_layers
)
2671 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2672 start_layer
, num_layers
, NULL
);
2676 intel_miptree_prepare_render(struct brw_context
*brw
,
2677 struct intel_mipmap_tree
*mt
, uint32_t level
,
2678 uint32_t start_layer
, uint32_t layer_count
,
2681 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2682 * the single-sampled color renderbuffers because the CCS buffer isn't
2683 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2684 * enabled because otherwise the surface state will be programmed with
2685 * the linear equivalent format anyway.
2687 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2688 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2690 /* Lossless compression is not supported for SRGB formats, it
2691 * should be impossible to get here with such surfaces.
2693 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2694 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2700 intel_miptree_finish_render(struct brw_context
*brw
,
2701 struct intel_mipmap_tree
*mt
, uint32_t level
,
2702 uint32_t start_layer
, uint32_t layer_count
)
2704 assert(_mesa_is_format_color_format(mt
->format
));
2705 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2706 mt
->mcs_buf
!= NULL
);
2710 intel_miptree_prepare_depth(struct brw_context
*brw
,
2711 struct intel_mipmap_tree
*mt
, uint32_t level
,
2712 uint32_t start_layer
, uint32_t layer_count
)
2714 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2715 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2719 intel_miptree_finish_depth(struct brw_context
*brw
,
2720 struct intel_mipmap_tree
*mt
, uint32_t level
,
2721 uint32_t start_layer
, uint32_t layer_count
,
2724 if (depth_written
) {
2725 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2726 mt
->hiz_buf
!= NULL
);
2731 * Make it possible to share the BO backing the given miptree with another
2732 * process or another miptree.
2734 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2735 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2736 * ensure that no MCS buffer gets allocated in the future.
2738 * HiZ is similarly unsafe with shared buffers.
2741 intel_miptree_make_shareable(struct brw_context
*brw
,
2742 struct intel_mipmap_tree
*mt
)
2744 /* MCS buffers are also used for multisample buffers, but we can't resolve
2745 * away a multisample MCS buffer because it's an integral part of how the
2746 * pixel data is stored. Fortunately this code path should never be
2747 * reached for multisample buffers.
2749 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2750 mt
->num_samples
<= 1);
2752 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2753 0, INTEL_REMAINING_LAYERS
, false, false);
2756 brw_bo_unreference(mt
->mcs_buf
->bo
);
2760 /* Any pending MCS/CCS operations are no longer needed. Trying to
2761 * execute any will likely crash due to the missing aux buffer. So let's
2762 * delete all pending ops.
2764 free(mt
->aux_state
);
2765 mt
->aux_state
= NULL
;
2769 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2772 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2773 mt
->level
[l
].has_hiz
= false;
2776 /* Any pending HiZ operations are no longer needed. Trying to execute
2777 * any will likely crash due to the missing aux buffer. So let's delete
2780 free(mt
->aux_state
);
2781 mt
->aux_state
= NULL
;
2784 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2789 * \brief Get pointer offset into stencil buffer.
2791 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2792 * must decode the tile's layout in software.
2795 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2797 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2799 * Even though the returned offset is always positive, the return type is
2801 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2802 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2805 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2807 uint32_t tile_size
= 4096;
2808 uint32_t tile_width
= 64;
2809 uint32_t tile_height
= 64;
2810 uint32_t row_size
= 64 * stride
;
2812 uint32_t tile_x
= x
/ tile_width
;
2813 uint32_t tile_y
= y
/ tile_height
;
2815 /* The byte's address relative to the tile's base addres. */
2816 uint32_t byte_x
= x
% tile_width
;
2817 uint32_t byte_y
= y
% tile_height
;
2819 uintptr_t u
= tile_y
* row_size
2820 + tile_x
* tile_size
2821 + 512 * (byte_x
/ 8)
2823 + 32 * ((byte_y
/ 4) % 2)
2824 + 16 * ((byte_x
/ 4) % 2)
2825 + 8 * ((byte_y
/ 2) % 2)
2826 + 4 * ((byte_x
/ 2) % 2)
2831 /* adjust for bit6 swizzling */
2832 if (((byte_x
/ 8) % 2) == 1) {
2833 if (((byte_y
/ 8) % 2) == 0) {
2845 intel_miptree_updownsample(struct brw_context
*brw
,
2846 struct intel_mipmap_tree
*src
,
2847 struct intel_mipmap_tree
*dst
)
2849 unsigned src_w
, src_h
, dst_w
, dst_h
;
2851 if (src
->surf
.size
> 0) {
2852 src_w
= src
->surf
.logical_level0_px
.width
;
2853 src_h
= src
->surf
.logical_level0_px
.height
;
2855 src_w
= src
->logical_width0
;
2856 src_h
= src
->logical_height0
;
2859 if (dst
->surf
.size
> 0) {
2860 dst_w
= dst
->surf
.logical_level0_px
.width
;
2861 dst_h
= dst
->surf
.logical_level0_px
.height
;
2863 dst_w
= dst
->logical_width0
;
2864 dst_h
= dst
->logical_height0
;
2867 brw_blorp_blit_miptrees(brw
,
2868 src
, 0 /* level */, 0 /* layer */,
2869 src
->format
, SWIZZLE_XYZW
,
2870 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2873 GL_NEAREST
, false, false /*mirror x, y*/,
2876 if (src
->stencil_mt
) {
2877 if (src
->stencil_mt
->surf
.size
> 0) {
2878 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2879 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2881 src_w
= src
->stencil_mt
->logical_width0
;
2882 src_h
= src
->stencil_mt
->logical_height0
;
2885 if (dst
->stencil_mt
->surf
.size
> 0) {
2886 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2887 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2889 dst_w
= dst
->stencil_mt
->logical_width0
;
2890 dst_h
= dst
->stencil_mt
->logical_height0
;
2893 brw_blorp_blit_miptrees(brw
,
2894 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2895 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2896 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2897 dst
->stencil_mt
->format
,
2900 GL_NEAREST
, false, false /*mirror x, y*/,
2901 false, false /* decode/encode srgb */);
2906 intel_update_r8stencil(struct brw_context
*brw
,
2907 struct intel_mipmap_tree
*mt
)
2909 assert(brw
->gen
>= 7);
2910 struct intel_mipmap_tree
*src
=
2911 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2912 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2915 if (!mt
->r8stencil_mt
) {
2916 const uint32_t r8stencil_flags
=
2917 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2918 MIPTREE_LAYOUT_DISABLE_AUX
;
2919 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2920 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2922 MESA_FORMAT_R_UINT8
,
2925 src
->logical_width0
,
2926 src
->logical_height0
,
2927 src
->logical_depth0
,
2930 assert(mt
->r8stencil_mt
);
2933 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2935 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2936 const unsigned depth
= src
->level
[level
].depth
;
2938 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2939 brw_blorp_copy_miptrees(brw
,
2943 minify(src
->logical_width0
, level
),
2944 minify(src
->logical_height0
, level
));
2948 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2949 src
->r8stencil_needs_update
= false;
2953 intel_miptree_map_raw(struct brw_context
*brw
,
2954 struct intel_mipmap_tree
*mt
,
2957 struct brw_bo
*bo
= mt
->bo
;
2959 if (brw_batch_references(&brw
->batch
, bo
))
2960 intel_batchbuffer_flush(brw
);
2962 return brw_bo_map(brw
, bo
, mode
);
2966 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2968 brw_bo_unmap(mt
->bo
);
2972 intel_miptree_map_gtt(struct brw_context
*brw
,
2973 struct intel_mipmap_tree
*mt
,
2974 struct intel_miptree_map
*map
,
2975 unsigned int level
, unsigned int slice
)
2977 unsigned int bw
, bh
;
2979 unsigned int image_x
, image_y
;
2980 intptr_t x
= map
->x
;
2981 intptr_t y
= map
->y
;
2983 /* For compressed formats, the stride is the number of bytes per
2984 * row of blocks. intel_miptree_get_image_offset() already does
2987 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2988 assert(y
% bh
== 0);
2989 assert(x
% bw
== 0);
2993 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3000 /* Note that in the case of cube maps, the caller must have passed the
3001 * slice number referencing the face.
3003 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3007 map
->stride
= mt
->pitch
;
3008 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3011 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3012 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3013 map
->x
, map
->y
, map
->w
, map
->h
,
3014 mt
, _mesa_get_format_name(mt
->format
),
3015 x
, y
, map
->ptr
, map
->stride
);
3019 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3021 intel_miptree_unmap_raw(mt
);
3025 intel_miptree_map_blit(struct brw_context
*brw
,
3026 struct intel_mipmap_tree
*mt
,
3027 struct intel_miptree_map
*map
,
3028 unsigned int level
, unsigned int slice
)
3030 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3031 /* first_level */ 0,
3035 MIPTREE_LAYOUT_TILING_NONE
);
3037 if (!map
->linear_mt
) {
3038 fprintf(stderr
, "Failed to allocate blit temporary\n");
3041 map
->stride
= map
->linear_mt
->pitch
;
3043 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3044 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3045 * invalidate is set, since we'll be writing the whole rectangle from our
3046 * temporary buffer back out.
3048 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3049 if (!intel_miptree_copy(brw
,
3050 mt
, level
, slice
, map
->x
, map
->y
,
3051 map
->linear_mt
, 0, 0, 0, 0,
3053 fprintf(stderr
, "Failed to blit\n");
3058 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3060 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3061 map
->x
, map
->y
, map
->w
, map
->h
,
3062 mt
, _mesa_get_format_name(mt
->format
),
3063 level
, slice
, map
->ptr
, map
->stride
);
3068 intel_miptree_release(&map
->linear_mt
);
3074 intel_miptree_unmap_blit(struct brw_context
*brw
,
3075 struct intel_mipmap_tree
*mt
,
3076 struct intel_miptree_map
*map
,
3080 struct gl_context
*ctx
= &brw
->ctx
;
3082 intel_miptree_unmap_raw(map
->linear_mt
);
3084 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3085 bool ok
= intel_miptree_copy(brw
,
3086 map
->linear_mt
, 0, 0, 0, 0,
3087 mt
, level
, slice
, map
->x
, map
->y
,
3089 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3092 intel_miptree_release(&map
->linear_mt
);
3096 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3098 #if defined(USE_SSE41)
3100 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3101 struct intel_mipmap_tree
*mt
,
3102 struct intel_miptree_map
*map
,
3103 unsigned int level
, unsigned int slice
)
3105 assert(map
->mode
& GL_MAP_READ_BIT
);
3106 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3108 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3109 map
->x
, map
->y
, map
->w
, map
->h
,
3110 mt
, _mesa_get_format_name(mt
->format
),
3111 level
, slice
, map
->ptr
, map
->stride
);
3113 /* Map the original image */
3116 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3120 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3126 src
+= image_y
* mt
->pitch
;
3127 src
+= image_x
* mt
->cpp
;
3129 /* Due to the pixel offsets for the particular image being mapped, our
3130 * src pointer may not be 16-byte aligned. However, if the pitch is
3131 * divisible by 16, then the amount by which it's misaligned will remain
3132 * consistent from row to row.
3134 assert((mt
->pitch
% 16) == 0);
3135 const int misalignment
= ((uintptr_t) src
) & 15;
3137 /* Create an untiled temporary buffer for the mapping. */
3138 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3140 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3142 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3143 /* Offset the destination so it has the same misalignment as src. */
3144 map
->ptr
= map
->buffer
+ misalignment
;
3146 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3148 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3149 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3150 void *src_ptr
= src
+ y
* mt
->pitch
;
3152 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3155 intel_miptree_unmap_raw(mt
);
3159 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3160 struct intel_mipmap_tree
*mt
,
3161 struct intel_miptree_map
*map
,
3165 _mesa_align_free(map
->buffer
);
3172 intel_miptree_map_s8(struct brw_context
*brw
,
3173 struct intel_mipmap_tree
*mt
,
3174 struct intel_miptree_map
*map
,
3175 unsigned int level
, unsigned int slice
)
3177 map
->stride
= map
->w
;
3178 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3182 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3183 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3184 * invalidate is set, since we'll be writing the whole rectangle from our
3185 * temporary buffer back out.
3187 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3188 /* ISL uses a stencil pitch value that is expected by hardware whereas
3189 * traditional miptree uses half of that. Below the value gets supplied
3190 * to intel_offset_S8() which expects the legacy interpretation.
3192 const unsigned pitch
= mt
->surf
.size
> 0 ?
3193 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3194 uint8_t *untiled_s8_map
= map
->ptr
;
3195 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3196 unsigned int image_x
, image_y
;
3198 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3200 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3201 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3202 ptrdiff_t offset
= intel_offset_S8(pitch
,
3203 x
+ image_x
+ map
->x
,
3204 y
+ image_y
+ map
->y
,
3205 brw
->has_swizzling
);
3206 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3210 intel_miptree_unmap_raw(mt
);
3212 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3213 map
->x
, map
->y
, map
->w
, map
->h
,
3214 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3216 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3217 map
->x
, map
->y
, map
->w
, map
->h
,
3218 mt
, map
->ptr
, map
->stride
);
3223 intel_miptree_unmap_s8(struct brw_context
*brw
,
3224 struct intel_mipmap_tree
*mt
,
3225 struct intel_miptree_map
*map
,
3229 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3230 /* ISL uses a stencil pitch value that is expected by hardware whereas
3231 * traditional miptree uses half of that. Below the value gets supplied
3232 * to intel_offset_S8() which expects the legacy interpretation.
3234 const unsigned pitch
= mt
->surf
.size
> 0 ?
3235 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3236 unsigned int image_x
, image_y
;
3237 uint8_t *untiled_s8_map
= map
->ptr
;
3238 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3240 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3242 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3243 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3244 ptrdiff_t offset
= intel_offset_S8(pitch
,
3245 image_x
+ x
+ map
->x
,
3246 image_y
+ y
+ map
->y
,
3247 brw
->has_swizzling
);
3248 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3252 intel_miptree_unmap_raw(mt
);
3259 intel_miptree_map_etc(struct brw_context
*brw
,
3260 struct intel_mipmap_tree
*mt
,
3261 struct intel_miptree_map
*map
,
3265 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3266 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3267 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3270 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3271 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3273 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3274 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3275 map
->w
, map
->h
, 1));
3276 map
->ptr
= map
->buffer
;
3280 intel_miptree_unmap_etc(struct brw_context
*brw
,
3281 struct intel_mipmap_tree
*mt
,
3282 struct intel_miptree_map
*map
,
3288 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3293 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3294 + image_y
* mt
->pitch
3295 + image_x
* mt
->cpp
;
3297 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3298 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3299 map
->ptr
, map
->stride
,
3302 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3303 map
->ptr
, map
->stride
,
3304 map
->w
, map
->h
, mt
->etc_format
);
3306 intel_miptree_unmap_raw(mt
);
3311 * Mapping function for packed depth/stencil miptrees backed by real separate
3312 * miptrees for depth and stencil.
3314 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3315 * separate from the depth buffer. Yet at the GL API level, we have to expose
3316 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3317 * be able to map that memory for texture storage and glReadPixels-type
3318 * operations. We give Mesa core that access by mallocing a temporary and
3319 * copying the data between the actual backing store and the temporary.
3322 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3323 struct intel_mipmap_tree
*mt
,
3324 struct intel_miptree_map
*map
,
3325 unsigned int level
, unsigned int slice
)
3327 struct intel_mipmap_tree
*z_mt
= mt
;
3328 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3329 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3330 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3332 map
->stride
= map
->w
* packed_bpp
;
3333 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3337 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3338 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3339 * invalidate is set, since we'll be writing the whole rectangle from our
3340 * temporary buffer back out.
3342 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3343 /* ISL uses a stencil pitch value that is expected by hardware whereas
3344 * traditional miptree uses half of that. Below the value gets supplied
3345 * to intel_offset_S8() which expects the legacy interpretation.
3347 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3348 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3349 uint32_t *packed_map
= map
->ptr
;
3350 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3351 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3352 unsigned int s_image_x
, s_image_y
;
3353 unsigned int z_image_x
, z_image_y
;
3355 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3356 &s_image_x
, &s_image_y
);
3357 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3358 &z_image_x
, &z_image_y
);
3360 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3361 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3362 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3363 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3366 brw
->has_swizzling
);
3367 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3369 (map_x
+ z_image_x
));
3370 uint8_t s
= s_map
[s_offset
];
3371 uint32_t z
= z_map
[z_offset
];
3373 if (map_z32f_x24s8
) {
3374 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3375 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3377 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3382 intel_miptree_unmap_raw(s_mt
);
3383 intel_miptree_unmap_raw(z_mt
);
3385 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3387 map
->x
, map
->y
, map
->w
, map
->h
,
3388 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3389 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3390 map
->ptr
, map
->stride
);
3392 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3393 map
->x
, map
->y
, map
->w
, map
->h
,
3394 mt
, map
->ptr
, map
->stride
);
3399 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3400 struct intel_mipmap_tree
*mt
,
3401 struct intel_miptree_map
*map
,
3405 struct intel_mipmap_tree
*z_mt
= mt
;
3406 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3407 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3409 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3410 /* ISL uses a stencil pitch value that is expected by hardware whereas
3411 * traditional miptree uses half of that. Below the value gets supplied
3412 * to intel_offset_S8() which expects the legacy interpretation.
3414 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3415 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3416 uint32_t *packed_map
= map
->ptr
;
3417 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3418 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3419 unsigned int s_image_x
, s_image_y
;
3420 unsigned int z_image_x
, z_image_y
;
3422 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3423 &s_image_x
, &s_image_y
);
3424 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3425 &z_image_x
, &z_image_y
);
3427 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3428 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3429 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3430 x
+ s_image_x
+ map
->x
,
3431 y
+ s_image_y
+ map
->y
,
3432 brw
->has_swizzling
);
3433 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3435 (x
+ z_image_x
+ map
->x
));
3437 if (map_z32f_x24s8
) {
3438 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3439 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3441 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3442 s_map
[s_offset
] = packed
>> 24;
3443 z_map
[z_offset
] = packed
;
3448 intel_miptree_unmap_raw(s_mt
);
3449 intel_miptree_unmap_raw(z_mt
);
3451 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3453 map
->x
, map
->y
, map
->w
, map
->h
,
3454 z_mt
, _mesa_get_format_name(z_mt
->format
),
3455 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3456 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3457 map
->ptr
, map
->stride
);
3464 * Create and attach a map to the miptree at (level, slice). Return the
3467 static struct intel_miptree_map
*
3468 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3477 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3482 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3483 mt
->level
[level
].slice
[slice
].map
= map
;
3495 * Release the map at (level, slice).
3498 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3502 struct intel_miptree_map
**map
;
3504 map
= &mt
->level
[level
].slice
[slice
].map
;
3510 can_blit_slice(struct intel_mipmap_tree
*mt
,
3511 unsigned int level
, unsigned int slice
)
3513 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3514 if (mt
->pitch
>= 32768)
3521 use_intel_mipree_map_blit(struct brw_context
*brw
,
3522 struct intel_mipmap_tree
*mt
,
3528 /* It's probably not worth swapping to the blit ring because of
3529 * all the overhead involved.
3531 !(mode
& GL_MAP_WRITE_BIT
) &&
3533 (mt
->tiling
== I915_TILING_X
||
3534 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3535 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3536 /* Fast copy blit on skl+ supports all tiling formats. */
3538 can_blit_slice(mt
, level
, slice
))
3541 if (mt
->tiling
!= I915_TILING_NONE
&&
3542 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3543 assert(can_blit_slice(mt
, level
, slice
));
3551 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3552 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3553 * arithmetic overflow.
3555 * If you call this function and use \a out_stride, then you're doing pointer
3556 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3557 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3558 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3559 * which usually have type uint32_t or GLuint.
3562 intel_miptree_map(struct brw_context
*brw
,
3563 struct intel_mipmap_tree
*mt
,
3572 ptrdiff_t *out_stride
)
3574 struct intel_miptree_map
*map
;
3576 assert(mt
->num_samples
<= 1);
3578 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3585 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3586 map
->mode
& GL_MAP_WRITE_BIT
);
3588 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3589 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3590 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3591 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3592 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3593 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3594 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3595 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3596 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3597 #if defined(USE_SSE41)
3598 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3599 !mt
->compressed
&& cpu_has_sse4_1
&&
3600 (mt
->pitch
% 16 == 0)) {
3601 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3604 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3607 *out_ptr
= map
->ptr
;
3608 *out_stride
= map
->stride
;
3610 if (map
->ptr
== NULL
)
3611 intel_miptree_release_map(mt
, level
, slice
);
3615 intel_miptree_unmap(struct brw_context
*brw
,
3616 struct intel_mipmap_tree
*mt
,
3620 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3622 assert(mt
->num_samples
<= 1);
3627 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3628 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3630 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3631 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3632 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3633 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3634 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3635 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3636 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3637 } else if (map
->linear_mt
) {
3638 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3639 #if defined(USE_SSE41)
3640 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3641 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3644 intel_miptree_unmap_gtt(mt
);
3647 intel_miptree_release_map(mt
, level
, slice
);
3651 get_isl_surf_dim(GLenum target
)
3655 case GL_TEXTURE_1D_ARRAY
:
3656 return ISL_SURF_DIM_1D
;
3659 case GL_TEXTURE_2D_ARRAY
:
3660 case GL_TEXTURE_RECTANGLE
:
3661 case GL_TEXTURE_CUBE_MAP
:
3662 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3663 case GL_TEXTURE_2D_MULTISAMPLE
:
3664 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3665 case GL_TEXTURE_EXTERNAL_OES
:
3666 return ISL_SURF_DIM_2D
;
3669 return ISL_SURF_DIM_3D
;
3672 unreachable("Invalid texture target");
3676 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3677 GLenum target
, enum miptree_array_layout array_layout
)
3679 if (array_layout
== GEN6_HIZ_STENCIL
)
3680 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3684 case GL_TEXTURE_1D_ARRAY
:
3685 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3686 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3689 case GL_TEXTURE_2D_ARRAY
:
3690 case GL_TEXTURE_RECTANGLE
:
3691 case GL_TEXTURE_2D_MULTISAMPLE
:
3692 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3693 case GL_TEXTURE_EXTERNAL_OES
:
3694 return ISL_DIM_LAYOUT_GEN4_2D
;
3696 case GL_TEXTURE_CUBE_MAP
:
3697 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3698 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3699 ISL_DIM_LAYOUT_GEN4_2D
);
3702 return (devinfo
->gen
>= 9 ?
3703 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3706 unreachable("Invalid texture target");
3710 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3712 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3713 return ISL_TILING_W
;
3715 switch (mt
->tiling
) {
3716 case I915_TILING_NONE
:
3717 return ISL_TILING_LINEAR
;
3719 return ISL_TILING_X
;
3721 return ISL_TILING_Y0
;
3723 unreachable("Invalid tiling mode");
3729 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3730 const struct intel_mipmap_tree
*mt
,
3731 struct isl_surf
*surf
)
3733 surf
->dim
= get_isl_surf_dim(mt
->target
);
3734 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3735 mt
->tiling
, mt
->target
,
3737 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3738 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3740 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3741 /* The ISL definition of row_pitch matches the surface state pitch field
3742 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3743 * the factor of 2 for W-tiling in row_pitch.
3745 surf
->row_pitch
= 2 * mt
->pitch
;
3747 surf
->row_pitch
= mt
->pitch
;
3750 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3752 if (brw
->gen
>= 9) {
3753 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3754 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3755 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3757 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3758 * alignment in terms of surface elements like we want.
3760 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3763 /* On earlier gens it's stored in pixels. */
3765 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3766 surf
->image_alignment_el
=
3767 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3770 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3771 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3772 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3773 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3774 surf
->logical_level0_px
.array_len
= 1;
3776 surf
->logical_level0_px
.depth
= 1;
3777 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3780 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3781 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3782 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3783 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3784 surf
->phys_level0_sa
.array_len
= 1;
3786 surf
->phys_level0_sa
.depth
= 1;
3787 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3790 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3791 surf
->samples
= MAX2(mt
->num_samples
, 1);
3793 surf
->size
= 0; /* TODO */
3794 surf
->alignment
= 0; /* TODO */
3796 switch (surf
->dim_layout
) {
3797 case ISL_DIM_LAYOUT_GEN4_2D
:
3798 case ISL_DIM_LAYOUT_GEN4_3D
:
3799 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3800 if (brw
->gen
>= 9) {
3801 surf
->array_pitch_el_rows
= mt
->qpitch
;
3804 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3805 assert(mt
->qpitch
% bh
== 0);
3806 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3809 case ISL_DIM_LAYOUT_GEN9_1D
:
3810 surf
->array_pitch_el_rows
= 1;
3814 switch (mt
->array_layout
) {
3815 case ALL_LOD_IN_EACH_SLICE
:
3816 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3818 case ALL_SLICES_AT_EACH_LOD
:
3819 case GEN6_HIZ_STENCIL
:
3820 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3823 unreachable("Invalid array layout");
3826 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3827 switch (base_format
) {
3828 case GL_DEPTH_COMPONENT
:
3829 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3831 case GL_STENCIL_INDEX
:
3832 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3834 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3836 case GL_DEPTH_STENCIL
:
3837 /* In this case we only texture from the depth part */
3838 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3839 ISL_SURF_USAGE_TEXTURE_BIT
;
3842 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3843 if (brw
->mesa_format_supports_render
[mt
->format
])
3844 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3848 if (_mesa_is_cube_map_texture(mt
->target
))
3849 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3853 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3854 const struct intel_mipmap_tree
*mt
)
3857 return ISL_AUX_USAGE_HIZ
;
3860 return ISL_AUX_USAGE_NONE
;
3862 return mt
->aux_usage
;