2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_meta_util.h"
40 #include "brw_state.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 static void *intel_miptree_map_raw(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
57 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
60 intel_miptree_alloc_aux(struct brw_context
*brw
,
61 struct intel_mipmap_tree
*mt
);
64 intel_miptree_supports_mcs(struct brw_context
*brw
,
65 const struct intel_mipmap_tree
*mt
)
67 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
69 /* MCS compression only applies to multisampled miptrees */
70 if (mt
->surf
.samples
<= 1)
73 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
77 /* See isl_surf_get_mcs_surf for details. */
78 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
81 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
82 switch (_mesa_get_format_base_format(mt
->format
)) {
83 case GL_DEPTH_COMPONENT
:
84 case GL_STENCIL_INDEX
:
85 case GL_DEPTH_STENCIL
:
88 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
90 * This field must be set to 0 for all SINT MSRTs when all RT channels
93 * In practice this means that we have to disable MCS for all signed
94 * integer MSAA buffers. The alternative, to disable MCS only when one
95 * of the render target channels is disabled, is impractical because it
96 * would require converting between CMS and UMS MSAA layouts on the fly,
99 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
108 intel_tiling_supports_ccs(const struct brw_context
*brw
,
109 enum isl_tiling tiling
)
111 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
113 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
114 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
116 * - Support is limited to tiled render targets.
118 * Gen9 changes the restriction to Y-tile only.
120 if (devinfo
->gen
>= 9)
121 return tiling
== ISL_TILING_Y0
;
122 else if (devinfo
->gen
>= 7)
123 return tiling
!= ISL_TILING_LINEAR
;
129 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
130 * can be used. This doesn't (and should not) inspect any of the properties of
133 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
134 * beneath the "Fast Color Clear" bullet (p326):
136 * - Support is for non-mip-mapped and non-array surface types only.
138 * And then later, on p327:
140 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
143 * From the Skylake documentation, it is made clear that X-tiling is no longer
146 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
150 intel_miptree_supports_ccs(struct brw_context
*brw
,
151 const struct intel_mipmap_tree
*mt
)
153 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
155 /* MCS support does not exist prior to Gen7 */
156 if (devinfo
->gen
< 7)
159 /* This function applies only to non-multisampled render targets. */
160 if (mt
->surf
.samples
> 1)
163 /* MCS is only supported for color buffers */
164 switch (_mesa_get_format_base_format(mt
->format
)) {
165 case GL_DEPTH_COMPONENT
:
166 case GL_DEPTH_STENCIL
:
167 case GL_STENCIL_INDEX
:
171 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
174 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
175 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
176 mt
->surf
.logical_level0_px
.depth
> 1;
179 /* Multisample surfaces with the CMS layout are not layered surfaces,
180 * yet still have physical_depth0 > 1. Assert that we don't
181 * accidentally reject a multisampled surface here. We should have
182 * rejected it earlier by explicitly checking the sample count.
184 assert(mt
->surf
.samples
== 1);
187 /* Handle the hardware restrictions...
189 * All GENs have the following restriction: "MCS buffer for non-MSRT is
190 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
192 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
193 * Non-MultiSampler Render Target Restrictions) Support is for
194 * non-mip-mapped and non-array surface types only.
196 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
201 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
202 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
203 * surfaces are supported with MCS buffer layout with these alignments in
204 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
206 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
209 /* There's no point in using an MCS buffer if the surface isn't in a
212 if (!brw
->mesa_format_supports_render
[mt
->format
])
219 intel_tiling_supports_hiz(const struct brw_context
*brw
,
220 enum isl_tiling tiling
)
222 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
224 if (devinfo
->gen
< 6)
227 return tiling
== ISL_TILING_Y0
;
231 intel_miptree_supports_hiz(const struct brw_context
*brw
,
232 const struct intel_mipmap_tree
*mt
)
237 switch (mt
->format
) {
238 case MESA_FORMAT_Z_FLOAT32
:
239 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
240 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
241 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
242 case MESA_FORMAT_Z_UNORM16
:
250 * Return true if the format that will be used to access the miptree is
251 * CCS_E-compatible with the miptree's linear/non-sRGB format.
253 * Why use the linear format? Well, although the miptree may be specified with
254 * an sRGB format, the usage of that color space/format can be toggled. Since
255 * our HW tends to support more linear formats than sRGB ones, we use this
256 * format variant for check for CCS_E compatibility.
259 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
260 const struct intel_mipmap_tree
*mt
,
261 enum isl_format access_format
)
263 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
265 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
266 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
267 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
271 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
272 const struct intel_mipmap_tree
*mt
)
274 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
276 if (devinfo
->gen
< 9)
279 /* For now compression is only enabled for integer formats even though
280 * there exist supported floating point formats also. This is a heuristic
281 * decision based on current public benchmarks. In none of the cases these
282 * formats provided any improvement but a few cases were seen to regress.
283 * Hence these are left to to be enabled in the future when they are known
286 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
289 if (!intel_miptree_supports_ccs(brw
, mt
))
292 /* Many window system buffers are sRGB even if they are never rendered as
293 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
294 * surface is used as sRGB, we fall back to CCS_D.
296 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
297 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
298 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
302 * Determine depth format corresponding to a depth+stencil format,
303 * for separate stencil.
306 intel_depth_format_for_depthstencil_format(mesa_format format
) {
308 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
309 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
310 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
311 return MESA_FORMAT_Z_FLOAT32
;
318 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
319 unsigned depth0
, struct intel_mipmap_level
*table
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
323 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
325 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
326 if (!table
[level
].slice
)
333 for (unsigned level
= first_level
; level
<= last_level
; level
++)
334 free(table
[level
].slice
);
340 needs_separate_stencil(const struct brw_context
*brw
,
341 struct intel_mipmap_tree
*mt
,
344 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
346 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
349 if (devinfo
->must_use_separate_stencil
)
352 return brw
->has_separate_stencil
&&
353 intel_miptree_supports_hiz(brw
, mt
);
357 * Choose the aux usage for this miptree. This function must be called fairly
358 * late in the miptree create process after we have a tiling.
361 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
362 struct intel_mipmap_tree
*mt
)
364 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
366 if (intel_miptree_supports_mcs(brw
, mt
)) {
367 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
368 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
369 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
370 intel_miptree_supports_ccs(brw
, mt
)) {
371 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
372 intel_miptree_supports_ccs_e(brw
, mt
)) {
373 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
375 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
377 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
378 intel_miptree_supports_hiz(brw
, mt
)) {
379 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
382 /* We can do fast-clear on all auxiliary surface types that are
383 * allocated through the normal texture creation paths.
385 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
386 mt
->supports_fast_clear
= true;
391 * Choose an appropriate uncompressed format for a requested
392 * compressed format, if unsupported.
395 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
397 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
399 /* No need to lower ETC formats on these platforms,
400 * they are supported natively.
402 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
406 case MESA_FORMAT_ETC1_RGB8
:
407 return MESA_FORMAT_R8G8B8X8_UNORM
;
408 case MESA_FORMAT_ETC2_RGB8
:
409 return MESA_FORMAT_R8G8B8X8_UNORM
;
410 case MESA_FORMAT_ETC2_SRGB8
:
411 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
412 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
413 return MESA_FORMAT_B8G8R8A8_SRGB
;
414 case MESA_FORMAT_ETC2_RGBA8_EAC
:
415 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
416 return MESA_FORMAT_R8G8B8A8_UNORM
;
417 case MESA_FORMAT_ETC2_R11_EAC
:
418 return MESA_FORMAT_R_UNORM16
;
419 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
420 return MESA_FORMAT_R_SNORM16
;
421 case MESA_FORMAT_ETC2_RG11_EAC
:
422 return MESA_FORMAT_R16G16_UNORM
;
423 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
424 return MESA_FORMAT_R16G16_SNORM
;
426 /* Non ETC1 / ETC2 format */
432 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
434 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
435 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
437 return mt
->surf
.logical_level0_px
.array_len
;
440 UNUSED
static unsigned
441 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
443 /* In case of physical dimensions one needs to consider also the layout.
444 * See isl_calc_phys_level0_extent_sa().
446 if (surf
->dim
!= ISL_SURF_DIM_3D
)
447 return surf
->phys_level0_sa
.array_len
;
449 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
450 return minify(surf
->phys_level0_sa
.array_len
, level
);
452 return minify(surf
->phys_level0_sa
.depth
, level
);
455 /** \brief Assert that the level and layer are valid for the miptree. */
457 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
465 assert(level
>= mt
->first_level
);
466 assert(level
<= mt
->last_level
);
467 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
470 static enum isl_aux_state
**
471 create_aux_state_map(struct intel_mipmap_tree
*mt
,
472 enum isl_aux_state initial
)
474 const uint32_t levels
= mt
->last_level
+ 1;
476 uint32_t total_slices
= 0;
477 for (uint32_t level
= 0; level
< levels
; level
++)
478 total_slices
+= brw_get_num_logical_layers(mt
, level
);
480 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
482 /* We're going to allocate a single chunk of data for both the per-level
483 * reference array and the arrays of aux_state. This makes cleanup
484 * significantly easier.
486 const size_t total_size
= per_level_array_size
+
487 total_slices
* sizeof(enum isl_aux_state
);
488 void *data
= malloc(total_size
);
492 enum isl_aux_state
**per_level_arr
= data
;
493 enum isl_aux_state
*s
= data
+ per_level_array_size
;
494 for (uint32_t level
= 0; level
< levels
; level
++) {
495 per_level_arr
[level
] = s
;
496 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
497 for (uint32_t a
= 0; a
< level_layers
; a
++)
500 assert((void *)s
== data
+ total_size
);
502 return per_level_arr
;
506 free_aux_state_map(enum isl_aux_state
**state
)
512 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
513 enum isl_tiling tiling
, unsigned samples
)
518 if (tiling
== ISL_TILING_LINEAR
)
521 /* If the width is much smaller than a tile, don't bother tiling. */
525 if (ALIGN(row_pitch
, 512) >= 32768) {
526 perf_debug("row pitch %u too large to blit, falling back to untiled",
535 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
536 enum isl_tiling tiling
)
538 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
540 /* If the BO is too large to fit in the aperture, we need to use the
541 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
542 * handle Y-tiling, so we need to fall back to X.
544 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
545 tiling
== ISL_TILING_Y0
)
551 static struct intel_mipmap_tree
*
552 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
553 unsigned first_level
, unsigned last_level
,
554 unsigned width0
, unsigned height0
, unsigned depth0
,
555 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
556 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
557 unsigned row_pitch
, struct brw_bo
*bo
)
559 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
563 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
571 if (target
== GL_TEXTURE_CUBE_MAP
||
572 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
573 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
575 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
577 _mesa_enum_to_string(target
),
578 _mesa_get_format_name(format
),
579 num_samples
, width0
, height0
, depth0
,
580 first_level
, last_level
, mt
);
582 struct isl_surf_init_info init_info
= {
583 .dim
= get_isl_surf_dim(target
),
584 .format
= translate_tex_format(brw
, format
, false),
587 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
588 .levels
= last_level
- first_level
+ 1,
589 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
590 .samples
= num_samples
,
591 .row_pitch
= row_pitch
,
592 .usage
= isl_usage_flags
,
593 .tiling_flags
= tiling_flags
,
596 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
599 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
600 * on gen7 platforms we also need to create Y-tiled copies of stencil for
601 * texturing since the hardware can't sample from W-tiled surfaces. For
602 * everything else, check for corner cases needing special treatment.
604 bool is_depth_stencil
=
605 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
606 if (!is_depth_stencil
) {
607 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
608 mt
->surf
.tiling
, mt
->surf
.samples
)) {
609 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
610 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
612 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
613 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
614 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
619 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
620 * the size may not be multiple of row_pitch.
621 * See isl_apply_surface_padding().
623 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
624 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
627 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
629 isl_tiling_to_i915_tiling(
631 mt
->surf
.row_pitch
, alloc_flags
);
638 mt
->first_level
= first_level
;
639 mt
->last_level
= last_level
;
642 mt
->aux_state
= NULL
;
643 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
644 mt
->compressed
= _mesa_is_format_compressed(format
);
645 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
650 intel_miptree_release(&mt
);
655 make_separate_stencil_surface(struct brw_context
*brw
,
656 struct intel_mipmap_tree
*mt
)
658 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
659 0, mt
->surf
.levels
- 1,
660 mt
->surf
.logical_level0_px
.width
,
661 mt
->surf
.logical_level0_px
.height
,
662 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
663 mt
->surf
.logical_level0_px
.depth
:
664 mt
->surf
.logical_level0_px
.array_len
,
665 mt
->surf
.samples
, ISL_TILING_W_BIT
,
666 ISL_SURF_USAGE_STENCIL_BIT
|
667 ISL_SURF_USAGE_TEXTURE_BIT
,
668 BO_ALLOC_BUSY
, 0, NULL
);
673 mt
->stencil_mt
->r8stencil_needs_update
= true;
678 static struct intel_mipmap_tree
*
679 miptree_create(struct brw_context
*brw
,
688 enum intel_miptree_create_flags flags
)
690 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
692 if (format
== MESA_FORMAT_S_UINT8
)
693 return make_surface(brw
, target
, format
, first_level
, last_level
,
694 width0
, height0
, depth0
, num_samples
,
696 ISL_SURF_USAGE_STENCIL_BIT
|
697 ISL_SURF_USAGE_TEXTURE_BIT
,
702 const GLenum base_format
= _mesa_get_format_base_format(format
);
703 if ((base_format
== GL_DEPTH_COMPONENT
||
704 base_format
== GL_DEPTH_STENCIL
) &&
705 !(flags
& MIPTREE_CREATE_LINEAR
)) {
706 /* Fix up the Z miptree format for how we're splitting out separate
707 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
709 const mesa_format depth_only_format
=
710 intel_depth_format_for_depthstencil_format(format
);
711 struct intel_mipmap_tree
*mt
= make_surface(
712 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
713 first_level
, last_level
,
714 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
715 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
716 BO_ALLOC_BUSY
, 0, NULL
);
718 if (needs_separate_stencil(brw
, mt
, format
) &&
719 !make_separate_stencil_surface(brw
, mt
)) {
720 intel_miptree_release(&mt
);
724 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
725 intel_miptree_choose_aux_usage(brw
, mt
);
730 mesa_format tex_format
= format
;
731 mesa_format etc_format
= MESA_FORMAT_NONE
;
732 uint32_t alloc_flags
= 0;
734 format
= intel_lower_compressed_format(brw
, format
);
736 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
738 if (flags
& MIPTREE_CREATE_BUSY
)
739 alloc_flags
|= BO_ALLOC_BUSY
;
741 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
742 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
744 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
745 if (devinfo
->gen
< 6)
746 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
748 struct intel_mipmap_tree
*mt
= make_surface(
750 first_level
, last_level
,
751 width0
, height0
, depth0
,
752 num_samples
, tiling_flags
,
753 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
754 ISL_SURF_USAGE_TEXTURE_BIT
,
755 alloc_flags
, 0, NULL
);
759 mt
->etc_format
= etc_format
;
761 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
762 intel_miptree_choose_aux_usage(brw
, mt
);
767 struct intel_mipmap_tree
*
768 intel_miptree_create(struct brw_context
*brw
,
777 enum intel_miptree_create_flags flags
)
779 assert(num_samples
> 0);
781 struct intel_mipmap_tree
*mt
= miptree_create(
783 first_level
, last_level
,
784 width0
, height0
, depth0
, num_samples
,
791 if (!intel_miptree_alloc_aux(brw
, mt
)) {
792 intel_miptree_release(&mt
);
799 struct intel_mipmap_tree
*
800 intel_miptree_create_for_bo(struct brw_context
*brw
,
808 enum isl_tiling tiling
,
809 enum intel_miptree_create_flags flags
)
811 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
812 struct intel_mipmap_tree
*mt
;
813 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
814 const GLenum base_format
= _mesa_get_format_base_format(format
);
816 if ((base_format
== GL_DEPTH_COMPONENT
||
817 base_format
== GL_DEPTH_STENCIL
)) {
818 const mesa_format depth_only_format
=
819 intel_depth_format_for_depthstencil_format(format
);
820 mt
= make_surface(brw
, target
,
821 devinfo
->gen
>= 6 ? depth_only_format
: format
,
822 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
823 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
828 brw_bo_reference(bo
);
830 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
831 intel_miptree_choose_aux_usage(brw
, mt
);
834 } else if (format
== MESA_FORMAT_S_UINT8
) {
835 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
836 0, 0, width
, height
, depth
, 1,
838 ISL_SURF_USAGE_STENCIL_BIT
|
839 ISL_SURF_USAGE_TEXTURE_BIT
,
844 assert(bo
->size
>= mt
->surf
.size
);
846 brw_bo_reference(bo
);
850 /* Nothing will be able to use this miptree with the BO if the offset isn't
853 if (tiling
!= ISL_TILING_LINEAR
)
854 assert(offset
% 4096 == 0);
856 /* miptrees can't handle negative pitch. If you need flipping of images,
857 * that's outside of the scope of the mt.
861 /* The BO already has a tiling format and we shouldn't confuse the lower
862 * layers by making it try to find a tiling format again.
864 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
866 mt
= make_surface(brw
, target
, format
,
867 0, 0, width
, height
, depth
, 1,
869 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
870 ISL_SURF_USAGE_TEXTURE_BIT
,
875 brw_bo_reference(bo
);
879 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
880 intel_miptree_choose_aux_usage(brw
, mt
);
882 if (!intel_miptree_alloc_aux(brw
, mt
)) {
883 intel_miptree_release(&mt
);
891 static struct intel_mipmap_tree
*
892 miptree_create_for_planar_image(struct brw_context
*brw
,
893 __DRIimage
*image
, GLenum target
,
894 enum isl_tiling tiling
)
896 const struct intel_image_format
*f
= image
->planar_format
;
897 struct intel_mipmap_tree
*planar_mt
= NULL
;
899 for (int i
= 0; i
< f
->nplanes
; i
++) {
900 const int index
= f
->planes
[i
].buffer_index
;
901 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
902 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
903 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
904 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
906 /* Disable creation of the texture's aux buffers because the driver
907 * exposes no EGL API to manage them. That is, there is no API for
908 * resolving the aux buffer's content to the main buffer nor for
909 * invalidating the aux buffer's content.
911 struct intel_mipmap_tree
*mt
=
912 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
913 image
->offsets
[index
],
915 image
->strides
[index
],
917 MIPTREE_CREATE_NO_AUX
);
926 planar_mt
->plane
[i
- 1] = mt
;
929 planar_mt
->drm_modifier
= image
->modifier
;
935 create_ccs_buf_for_image(struct brw_context
*brw
,
937 struct intel_mipmap_tree
*mt
,
938 enum isl_aux_state initial_state
)
940 struct isl_surf temp_ccs_surf
;
942 /* CCS is only supported for very simple miptrees */
943 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
944 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
945 assert(mt
->surf
.samples
== 1);
946 assert(mt
->surf
.levels
== 1);
947 assert(mt
->surf
.logical_level0_px
.depth
== 1);
948 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
949 assert(mt
->first_level
== 0);
950 assert(mt
->last_level
== 0);
952 /* We shouldn't already have a CCS */
953 assert(!mt
->mcs_buf
);
955 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
959 assert(image
->aux_offset
< image
->bo
->size
);
960 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
962 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
963 if (mt
->mcs_buf
== NULL
)
966 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
967 if (!mt
->aux_state
) {
973 /* On gen10+ we start using an extra space in the aux buffer to store the
974 * indirect clear color. However, if we imported an image from the window
975 * system with CCS, we don't have the extra space at the end of the aux
976 * buffer. So create a new bo here that will store that clear color.
978 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
979 if (devinfo
->gen
>= 10) {
980 mt
->mcs_buf
->clear_color_bo
=
981 brw_bo_alloc(brw
->bufmgr
, "clear_color_bo",
982 brw
->isl_dev
.ss
.clear_color_state_size
);
983 if (!mt
->mcs_buf
->clear_color_bo
) {
990 mt
->mcs_buf
->bo
= image
->bo
;
991 brw_bo_reference(image
->bo
);
993 mt
->mcs_buf
->offset
= image
->aux_offset
;
994 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
995 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
996 mt
->mcs_buf
->qpitch
= 0;
997 mt
->mcs_buf
->surf
= temp_ccs_surf
;
1002 struct intel_mipmap_tree
*
1003 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1004 __DRIimage
*image
, GLenum target
,
1006 bool is_winsys_image
)
1008 uint32_t bo_tiling
, bo_swizzle
;
1009 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1011 const struct isl_drm_modifier_info
*mod_info
=
1012 isl_drm_modifier_get_info(image
->modifier
);
1014 const enum isl_tiling tiling
=
1015 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1017 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1018 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1020 if (image
->planar_format
)
1021 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1023 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1024 /* The texture storage paths in core Mesa detect if the driver does not
1025 * support the user-requested format, and then searches for a
1026 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1027 * do the fallbacks here for important formats.
1029 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1030 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1031 * the Chrome OS compositor consumes as dma_buf EGLImages.
1033 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1036 if (!brw
->ctx
.TextureFormatSupported
[format
])
1039 enum intel_miptree_create_flags mt_create_flags
= 0;
1041 /* If this image comes in from a window system, we have different
1042 * requirements than if it comes in via an EGL import operation. Window
1043 * system images can use any form of auxiliary compression we wish because
1044 * they get "flushed" before being handed off to the window system and we
1045 * have the opportunity to do resolves. Non window-system images, on the
1046 * other hand, have no resolve point so we can't have aux without a
1049 if (!is_winsys_image
)
1050 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1052 /* If we have a modifier which specifies aux, don't create one yet */
1053 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1054 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1056 /* Disable creation of the texture's aux buffers because the driver exposes
1057 * no EGL API to manage them. That is, there is no API for resolving the aux
1058 * buffer's content to the main buffer nor for invalidating the aux buffer's
1061 struct intel_mipmap_tree
*mt
=
1062 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1063 image
->offset
, image
->width
, image
->height
, 1,
1064 image
->pitch
, tiling
, mt_create_flags
);
1068 mt
->target
= target
;
1069 mt
->level
[0].level_x
= image
->tile_x
;
1070 mt
->level
[0].level_y
= image
->tile_y
;
1071 mt
->drm_modifier
= image
->modifier
;
1073 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1074 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1075 * trouble resolving back to destination image due to alignment issues.
1077 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1078 if (!devinfo
->has_surface_tile_offset
) {
1079 uint32_t draw_x
, draw_y
;
1080 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1082 if (draw_x
!= 0 || draw_y
!= 0) {
1083 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1084 intel_miptree_release(&mt
);
1089 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1090 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1092 mt
->aux_usage
= mod_info
->aux_usage
;
1093 /* If we are a window system buffer, then we can support fast-clears
1094 * even if the modifier doesn't support them by doing a partial resolve
1095 * as part of the flush operation.
1097 mt
->supports_fast_clear
=
1098 is_winsys_image
|| mod_info
->supports_clear_color
;
1100 /* We don't know the actual state of the surface when we get it but we
1101 * can make a pretty good guess based on the modifier. What we do know
1102 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1103 * a worst case of compression.
1105 enum isl_aux_state initial_state
=
1106 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1108 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1109 intel_miptree_release(&mt
);
1114 /* Don't assume coherency for imported EGLimages. We don't know what
1115 * external clients are going to do with it. They may scan it out.
1117 image
->bo
->cache_coherent
= false;
1123 * For a singlesample renderbuffer, this simply wraps the given BO with a
1126 * For a multisample renderbuffer, this wraps the window system's
1127 * (singlesample) BO with a singlesample miptree attached to the
1128 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1129 * that will contain the actual rendering (which is lazily resolved to
1130 * irb->singlesample_mt).
1133 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1134 struct intel_renderbuffer
*irb
,
1135 struct intel_mipmap_tree
*singlesample_mt
,
1136 uint32_t width
, uint32_t height
,
1139 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1140 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1141 mesa_format format
= rb
->Format
;
1142 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1144 /* Only the front and back buffers, which are color buffers, are allocated
1145 * through the image loader.
1147 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1148 _mesa_get_format_base_format(format
) == GL_RGBA
);
1150 assert(singlesample_mt
);
1152 if (num_samples
== 1) {
1153 intel_miptree_release(&irb
->mt
);
1154 irb
->mt
= singlesample_mt
;
1156 assert(!irb
->singlesample_mt
);
1158 intel_miptree_release(&irb
->singlesample_mt
);
1159 irb
->singlesample_mt
= singlesample_mt
;
1162 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1163 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1164 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1169 if (!multisample_mt
)
1172 irb
->need_downsample
= false;
1173 intel_miptree_release(&irb
->mt
);
1174 irb
->mt
= multisample_mt
;
1180 intel_miptree_release(&irb
->mt
);
1184 struct intel_mipmap_tree
*
1185 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1189 uint32_t num_samples
)
1191 struct intel_mipmap_tree
*mt
;
1193 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1195 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1196 width
, height
, depth
, num_samples
,
1197 MIPTREE_CREATE_BUSY
);
1204 intel_miptree_release(&mt
);
1209 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1210 struct intel_mipmap_tree
*src
)
1215 intel_miptree_release(dst
);
1219 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1226 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1228 if (aux_buf
== NULL
)
1231 brw_bo_unreference(aux_buf
->bo
);
1232 brw_bo_unreference(aux_buf
->clear_color_bo
);
1238 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1243 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1244 if (--(*mt
)->refcount
<= 0) {
1247 DBG("%s deleting %p\n", __func__
, *mt
);
1249 brw_bo_unreference((*mt
)->bo
);
1250 intel_miptree_release(&(*mt
)->stencil_mt
);
1251 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1252 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1253 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1254 free_aux_state_map((*mt
)->aux_state
);
1256 intel_miptree_release(&(*mt
)->plane
[0]);
1257 intel_miptree_release(&(*mt
)->plane
[1]);
1259 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1260 free((*mt
)->level
[i
].slice
);
1270 intel_get_image_dims(struct gl_texture_image
*image
,
1271 int *width
, int *height
, int *depth
)
1273 switch (image
->TexObject
->Target
) {
1274 case GL_TEXTURE_1D_ARRAY
:
1275 /* For a 1D Array texture the OpenGL API will treat the image height as
1276 * the number of array slices. For Intel hardware, we treat the 1D array
1277 * as a 2D Array with a height of 1. So, here we want to swap image
1280 assert(image
->Depth
== 1);
1281 *width
= image
->Width
;
1283 *depth
= image
->Height
;
1285 case GL_TEXTURE_CUBE_MAP
:
1286 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1287 * though we really have 6 slices.
1289 assert(image
->Depth
== 1);
1290 *width
= image
->Width
;
1291 *height
= image
->Height
;
1295 *width
= image
->Width
;
1296 *height
= image
->Height
;
1297 *depth
= image
->Depth
;
1303 * Can the image be pulled into a unified mipmap tree? This mirrors
1304 * the completeness test in a lot of ways.
1306 * Not sure whether I want to pass gl_texture_image here.
1309 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1310 struct gl_texture_image
*image
)
1312 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1313 GLuint level
= intelImage
->base
.Base
.Level
;
1314 int width
, height
, depth
;
1316 /* glTexImage* choose the texture object based on the target passed in, and
1317 * objects can't change targets over their lifetimes, so this should be
1320 assert(image
->TexObject
->Target
== mt
->target
);
1322 mesa_format mt_format
= mt
->format
;
1323 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1324 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1325 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1326 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1327 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1328 mt_format
= mt
->etc_format
;
1330 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1331 _mesa_get_srgb_format_linear(mt_format
))
1334 intel_get_image_dims(image
, &width
, &height
, &depth
);
1336 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1339 if (level
>= mt
->surf
.levels
)
1342 const unsigned level_depth
=
1343 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1344 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1345 mt
->surf
.logical_level0_px
.array_len
;
1347 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1348 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1349 depth
== level_depth
&&
1350 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1354 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1355 GLuint level
, GLuint slice
,
1356 GLuint
*x
, GLuint
*y
)
1358 if (level
== 0 && slice
== 0) {
1359 *x
= mt
->level
[0].level_x
;
1360 *y
= mt
->level
[0].level_y
;
1364 uint32_t x_offset_sa
, y_offset_sa
;
1366 /* Miptree itself can have an offset only if it represents a single
1367 * slice in an imported buffer object.
1368 * See intel_miptree_create_for_dri_image().
1370 assert(mt
->level
[0].level_x
== 0);
1371 assert(mt
->level
[0].level_y
== 0);
1373 /* Given level is relative to level zero while the miptree may be
1374 * represent just a subset of all levels starting from 'first_level'.
1376 assert(level
>= mt
->first_level
);
1377 level
-= mt
->first_level
;
1379 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1380 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1381 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1382 &x_offset_sa
, &y_offset_sa
);
1390 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1391 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1392 * and tile_h is set to 1.
1395 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1396 uint32_t *tile_w
, uint32_t *tile_h
)
1407 case ISL_TILING_LINEAR
:
1412 unreachable("not reached");
1418 * This function computes masks that may be used to select the bits of the X
1419 * and Y coordinates that indicate the offset within a tile. If the BO is
1420 * untiled, the masks are set to 0.
1423 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1424 uint32_t *mask_x
, uint32_t *mask_y
)
1426 uint32_t tile_w_bytes
, tile_h
;
1428 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1430 *mask_x
= tile_w_bytes
/ cpp
- 1;
1431 *mask_y
= tile_h
- 1;
1435 * Compute the offset (in bytes) from the start of the BO to the given x
1436 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1437 * multiples of the tile size.
1440 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1441 uint32_t x
, uint32_t y
)
1444 uint32_t pitch
= mt
->surf
.row_pitch
;
1446 switch (mt
->surf
.tiling
) {
1448 unreachable("not reached");
1449 case ISL_TILING_LINEAR
:
1450 return y
* pitch
+ x
* cpp
;
1452 assert((x
% (512 / cpp
)) == 0);
1453 assert((y
% 8) == 0);
1454 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1456 assert((x
% (128 / cpp
)) == 0);
1457 assert((y
% 32) == 0);
1458 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1463 * Rendering with tiled buffers requires that the base address of the buffer
1464 * be aligned to a page boundary. For renderbuffers, and sometimes with
1465 * textures, we may want the surface to point at a texture image level that
1466 * isn't at a page boundary.
1468 * This function returns an appropriately-aligned base offset
1469 * according to the tiling restrictions, plus any required x/y offset
1473 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1474 GLuint level
, GLuint slice
,
1479 uint32_t mask_x
, mask_y
;
1481 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1482 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1484 *tile_x
= x
& mask_x
;
1485 *tile_y
= y
& mask_y
;
1487 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1491 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1492 struct intel_mipmap_tree
*src_mt
,
1493 unsigned src_level
, unsigned src_layer
,
1494 struct intel_mipmap_tree
*dst_mt
,
1495 unsigned dst_level
, unsigned dst_layer
,
1496 unsigned width
, unsigned height
)
1499 ptrdiff_t src_stride
, dst_stride
;
1500 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1502 intel_miptree_map(brw
, src_mt
,
1503 src_level
, src_layer
,
1506 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1509 intel_miptree_map(brw
, dst_mt
,
1510 dst_level
, dst_layer
,
1513 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1517 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1518 _mesa_get_format_name(src_mt
->format
),
1519 src_mt
, src
, src_stride
,
1520 _mesa_get_format_name(dst_mt
->format
),
1521 dst_mt
, dst
, dst_stride
,
1524 int row_size
= cpp
* width
;
1525 if (src_stride
== row_size
&&
1526 dst_stride
== row_size
) {
1527 memcpy(dst
, src
, row_size
* height
);
1529 for (int i
= 0; i
< height
; i
++) {
1530 memcpy(dst
, src
, row_size
);
1536 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1537 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1539 /* Don't forget to copy the stencil data over, too. We could have skipped
1540 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1541 * shuffling the two data sources in/out of temporary storage instead of
1542 * the direct mapping we get this way.
1544 if (dst_mt
->stencil_mt
) {
1545 assert(src_mt
->stencil_mt
);
1546 intel_miptree_copy_slice_sw(brw
,
1547 src_mt
->stencil_mt
, src_level
, src_layer
,
1548 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1554 intel_miptree_copy_slice(struct brw_context
*brw
,
1555 struct intel_mipmap_tree
*src_mt
,
1556 unsigned src_level
, unsigned src_layer
,
1557 struct intel_mipmap_tree
*dst_mt
,
1558 unsigned dst_level
, unsigned dst_layer
)
1561 mesa_format format
= src_mt
->format
;
1562 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1563 src_level
- src_mt
->first_level
);
1564 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1565 src_level
- src_mt
->first_level
);
1567 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1568 src_level
- src_mt
->first_level
));
1570 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1571 _mesa_get_srgb_format_linear(dst_mt
->format
));
1573 if (dst_mt
->compressed
) {
1575 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1576 height
= ALIGN_NPOT(height
, j
) / j
;
1577 width
= ALIGN_NPOT(width
, i
) / i
;
1580 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1581 * below won't apply since we can't do the depth's Y tiling or the
1582 * stencil's W tiling in the blitter.
1584 if (src_mt
->stencil_mt
) {
1585 intel_miptree_copy_slice_sw(brw
,
1586 src_mt
, src_level
, src_layer
,
1587 dst_mt
, dst_level
, dst_layer
,
1592 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1593 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1595 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1598 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1599 _mesa_get_format_name(src_mt
->format
),
1600 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1601 _mesa_get_format_name(dst_mt
->format
),
1602 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1605 if (!intel_miptree_blit(brw
,
1606 src_mt
, src_level
, src_layer
, 0, 0, false,
1607 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1608 width
, height
, COLOR_LOGICOP_COPY
)) {
1609 perf_debug("miptree validate blit for %s failed\n",
1610 _mesa_get_format_name(format
));
1612 intel_miptree_copy_slice_sw(brw
,
1613 src_mt
, src_level
, src_layer
,
1614 dst_mt
, dst_level
, dst_layer
,
1620 * Copies the image's current data to the given miptree, and associates that
1621 * miptree with the image.
1624 intel_miptree_copy_teximage(struct brw_context
*brw
,
1625 struct intel_texture_image
*intelImage
,
1626 struct intel_mipmap_tree
*dst_mt
)
1628 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1629 struct intel_texture_object
*intel_obj
=
1630 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1631 int level
= intelImage
->base
.Base
.Level
;
1632 const unsigned face
= intelImage
->base
.Base
.Face
;
1633 unsigned start_layer
, end_layer
;
1635 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1637 assert(intelImage
->base
.Base
.Height
);
1639 end_layer
= intelImage
->base
.Base
.Height
- 1;
1640 } else if (face
> 0) {
1644 assert(intelImage
->base
.Base
.Depth
);
1646 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1649 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1650 intel_miptree_copy_slice(brw
,
1655 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1656 intel_obj
->needs_validate
= true;
1660 intel_miptree_init_mcs(struct brw_context
*brw
,
1661 struct intel_mipmap_tree
*mt
,
1664 assert(mt
->mcs_buf
!= NULL
);
1666 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1668 * When MCS buffer is enabled and bound to MSRT, it is required that it
1669 * is cleared prior to any rendering.
1671 * Since we don't use the MCS buffer for any purpose other than rendering,
1672 * it makes sense to just clear it immediately upon allocation.
1674 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1676 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
| MAP_RAW
);
1677 if (unlikely(map
== NULL
)) {
1678 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1679 brw_bo_unreference(mt
->mcs_buf
->bo
);
1684 memset(data
, init_value
, mt
->mcs_buf
->size
);
1685 brw_bo_unmap(mt
->mcs_buf
->bo
);
1688 static struct intel_miptree_aux_buffer
*
1689 intel_alloc_aux_buffer(struct brw_context
*brw
,
1691 const struct isl_surf
*aux_surf
,
1692 uint32_t alloc_flags
,
1693 struct intel_mipmap_tree
*mt
)
1695 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1699 buf
->size
= aux_surf
->size
;
1701 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1702 if (devinfo
->gen
>= 10) {
1703 /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
1704 * will set a pointer to a dword somewhere that contains the color. So,
1705 * allocate the space for the clear color value here on the aux buffer.
1707 buf
->clear_color_offset
= buf
->size
;
1708 buf
->size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1711 buf
->pitch
= aux_surf
->row_pitch
;
1712 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1714 /* ISL has stricter set of alignment rules then the drm allocator.
1715 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1716 * trying to recalculate based on different format block sizes.
1718 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1719 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1725 if (devinfo
->gen
>= 10) {
1726 buf
->clear_color_bo
= buf
->bo
;
1727 brw_bo_reference(buf
->clear_color_bo
);
1730 buf
->surf
= *aux_surf
;
1736 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1737 struct intel_mipmap_tree
*mt
,
1740 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1741 assert(mt
->mcs_buf
== NULL
);
1742 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1744 /* Multisampled miptrees are only supported for single level. */
1745 assert(mt
->first_level
== 0);
1746 enum isl_aux_state
**aux_state
=
1747 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1751 struct isl_surf temp_mcs_surf
;
1753 MAYBE_UNUSED
bool ok
=
1754 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1757 /* Buffer needs to be initialised requiring the buffer to be immediately
1758 * mapped to cpu space for writing. Therefore do not use the gpu access
1759 * flag which can cause an unnecessary delay if the backing pages happened
1760 * to be just used by the GPU.
1762 const uint32_t alloc_flags
= 0;
1763 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1764 &temp_mcs_surf
, alloc_flags
, mt
);
1770 mt
->aux_state
= aux_state
;
1772 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1778 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1779 struct intel_mipmap_tree
*mt
)
1781 assert(mt
->mcs_buf
== NULL
);
1782 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1783 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1785 struct isl_surf temp_ccs_surf
;
1787 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1790 assert(temp_ccs_surf
.size
&&
1791 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1793 enum isl_aux_state
**aux_state
=
1794 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1798 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1799 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1801 * "If Software wants to enable Color Compression without Fast clear,
1802 * Software needs to initialize MCS with zeros."
1804 * A CCS value of 0 indicates that the corresponding block is in the
1805 * pass-through state which is what we want.
1807 * For CCS_D, on the other hand, we don't care as we're about to perform a
1808 * fast-clear operation. In that case, being hot in caches more useful.
1810 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1811 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1812 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1813 &temp_ccs_surf
, alloc_flags
, mt
);
1819 mt
->aux_state
= aux_state
;
1825 * Helper for intel_miptree_alloc_hiz() that sets
1826 * \c mt->level[level].has_hiz. Return true if and only if
1827 * \c has_hiz was set.
1830 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1831 struct intel_mipmap_tree
*mt
,
1834 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1836 assert(mt
->hiz_buf
);
1837 assert(mt
->surf
.size
> 0);
1839 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1840 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1841 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1843 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1844 * and the height is 4 aligned. This allows our HiZ support
1845 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1846 * we can grow the width & height to allow the HiZ op to
1847 * force the proper size alignments.
1849 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1850 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1855 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1856 mt
->level
[level
].has_hiz
= true;
1861 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1862 struct intel_mipmap_tree
*mt
)
1864 assert(mt
->hiz_buf
== NULL
);
1865 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1867 enum isl_aux_state
**aux_state
=
1868 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1872 struct isl_surf temp_hiz_surf
;
1874 MAYBE_UNUSED
bool ok
=
1875 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1878 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1879 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1880 &temp_hiz_surf
, alloc_flags
, mt
);
1887 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1888 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1890 mt
->aux_state
= aux_state
;
1897 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1899 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1900 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1901 * compress clear color so we wait until an actual fast-clear to allocate it.
1904 intel_miptree_alloc_aux(struct brw_context
*brw
,
1905 struct intel_mipmap_tree
*mt
)
1907 switch (mt
->aux_usage
) {
1908 case ISL_AUX_USAGE_NONE
:
1911 case ISL_AUX_USAGE_HIZ
:
1912 assert(!_mesa_is_format_color_format(mt
->format
));
1913 if (!intel_miptree_alloc_hiz(brw
, mt
))
1917 case ISL_AUX_USAGE_MCS
:
1918 assert(_mesa_is_format_color_format(mt
->format
));
1919 assert(mt
->surf
.samples
> 1);
1920 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1924 case ISL_AUX_USAGE_CCS_D
:
1925 /* Since CCS_D can only compress clear color so we wait until an actual
1926 * fast-clear to allocate it.
1930 case ISL_AUX_USAGE_CCS_E
:
1931 assert(_mesa_is_format_color_format(mt
->format
));
1932 assert(mt
->surf
.samples
== 1);
1933 if (!intel_miptree_alloc_ccs(brw
, mt
))
1938 unreachable("Invalid aux usage");
1943 * Can the miptree sample using the hiz buffer?
1946 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1947 struct intel_mipmap_tree
*mt
)
1949 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1951 if (!devinfo
->has_sample_with_hiz
) {
1959 /* It seems the hardware won't fallback to the depth buffer if some of the
1960 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1961 * of the texture to be HiZ enabled.
1963 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1964 if (!intel_miptree_level_has_hiz(mt
, level
))
1968 /* If compressed multisampling is enabled, then we use it for the auxiliary
1971 * From the BDW PRM (Volume 2d: Command Reference: Structures
1972 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1974 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1975 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1977 * There is no such blurb for 1D textures, but there is sufficient evidence
1978 * that this is broken on SKL+.
1980 return (mt
->surf
.samples
== 1 &&
1981 mt
->target
!= GL_TEXTURE_3D
&&
1982 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1986 * Does the miptree slice have hiz enabled?
1989 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1991 intel_miptree_check_level_layer(mt
, level
, 0);
1992 return mt
->level
[level
].has_hiz
;
1995 static inline uint32_t
1996 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1997 uint32_t start_level
, uint32_t num_levels
)
1999 assert(start_level
>= mt
->first_level
);
2000 assert(start_level
<= mt
->last_level
);
2002 if (num_levels
== INTEL_REMAINING_LAYERS
)
2003 num_levels
= mt
->last_level
- start_level
+ 1;
2004 /* Check for overflow */
2005 assert(start_level
+ num_levels
>= start_level
);
2006 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2011 static inline uint32_t
2012 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2013 uint32_t start_layer
, uint32_t num_layers
)
2015 assert(level
<= mt
->last_level
);
2017 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
2018 assert(start_layer
< total_num_layers
);
2019 if (num_layers
== INTEL_REMAINING_LAYERS
)
2020 num_layers
= total_num_layers
- start_layer
;
2021 /* Check for overflow */
2022 assert(start_layer
+ num_layers
>= start_layer
);
2023 assert(start_layer
+ num_layers
<= total_num_layers
);
2029 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2030 unsigned start_level
, unsigned num_levels
,
2031 unsigned start_layer
, unsigned num_layers
)
2033 assert(_mesa_is_format_color_format(mt
->format
));
2038 /* Clamp the level range to fit the miptree */
2039 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2041 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2042 const uint32_t level
= start_level
+ l
;
2043 const uint32_t level_layers
=
2044 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2045 for (unsigned a
= 0; a
< level_layers
; a
++) {
2046 enum isl_aux_state aux_state
=
2047 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2048 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2049 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2058 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2059 const struct intel_mipmap_tree
*mt
,
2060 unsigned level
, unsigned layer
)
2065 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2066 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2067 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2069 /* Compression of arrayed msaa surfaces is supported. */
2070 if (mt
->surf
.samples
> 1)
2073 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2074 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2076 mt
->surf
.logical_level0_px
.depth
== 1 &&
2077 mt
->surf
.logical_level0_px
.array_len
== 1));
2083 static enum isl_aux_op
2084 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2085 enum isl_aux_usage aux_usage
,
2086 bool fast_clear_supported
)
2088 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2090 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2092 assert(ccs_supported
== fast_clear_supported
);
2094 switch (aux_state
) {
2095 case ISL_AUX_STATE_CLEAR
:
2096 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2098 return ISL_AUX_OP_FULL_RESOLVE
;
2100 return ISL_AUX_OP_NONE
;
2102 case ISL_AUX_STATE_PASS_THROUGH
:
2103 return ISL_AUX_OP_NONE
;
2105 case ISL_AUX_STATE_RESOLVED
:
2106 case ISL_AUX_STATE_AUX_INVALID
:
2107 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2108 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2112 unreachable("Invalid aux state for CCS_D");
2115 static enum isl_aux_op
2116 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2117 enum isl_aux_usage aux_usage
,
2118 bool fast_clear_supported
)
2120 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2121 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2122 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2123 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2125 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2126 assert(fast_clear_supported
);
2128 switch (aux_state
) {
2129 case ISL_AUX_STATE_CLEAR
:
2130 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2131 if (fast_clear_supported
)
2132 return ISL_AUX_OP_NONE
;
2133 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2134 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2136 return ISL_AUX_OP_FULL_RESOLVE
;
2138 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2139 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2140 return ISL_AUX_OP_FULL_RESOLVE
;
2141 else if (!fast_clear_supported
)
2142 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2144 return ISL_AUX_OP_NONE
;
2146 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2147 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2148 return ISL_AUX_OP_FULL_RESOLVE
;
2150 return ISL_AUX_OP_NONE
;
2152 case ISL_AUX_STATE_PASS_THROUGH
:
2153 return ISL_AUX_OP_NONE
;
2155 case ISL_AUX_STATE_RESOLVED
:
2156 case ISL_AUX_STATE_AUX_INVALID
:
2160 unreachable("Invalid aux state for CCS_E");
2164 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2165 struct intel_mipmap_tree
*mt
,
2166 uint32_t level
, uint32_t layer
,
2167 enum isl_aux_usage aux_usage
,
2168 bool fast_clear_supported
)
2170 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2172 enum isl_aux_op resolve_op
;
2173 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2174 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2175 fast_clear_supported
);
2177 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2178 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2179 fast_clear_supported
);
2182 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2183 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2184 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2186 switch (resolve_op
) {
2187 case ISL_AUX_OP_FULL_RESOLVE
:
2188 /* The CCS full resolve operation destroys the CCS and sets it to the
2189 * pass-through state. (You can also think of this as being both a
2190 * resolve and an ambiguate in one operation.)
2192 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2193 ISL_AUX_STATE_PASS_THROUGH
);
2196 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2197 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2198 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2202 unreachable("Invalid resolve op");
2208 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2209 struct intel_mipmap_tree
*mt
,
2210 uint32_t level
, uint32_t layer
,
2211 enum isl_aux_usage aux_usage
)
2213 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2214 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2215 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2217 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2219 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2220 switch (aux_state
) {
2221 case ISL_AUX_STATE_CLEAR
:
2222 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2223 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2224 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2226 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2227 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2228 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2229 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2230 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2231 ISL_AUX_STATE_PARTIAL_CLEAR
);
2235 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2236 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2237 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2238 break; /* Nothing to do */
2240 case ISL_AUX_STATE_PASS_THROUGH
:
2241 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2242 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2243 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2249 case ISL_AUX_STATE_RESOLVED
:
2250 case ISL_AUX_STATE_AUX_INVALID
:
2251 unreachable("Invalid aux state for CCS_E");
2254 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2255 /* CCS_D is a bit simpler */
2256 switch (aux_state
) {
2257 case ISL_AUX_STATE_CLEAR
:
2258 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2259 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2260 ISL_AUX_STATE_PARTIAL_CLEAR
);
2263 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2264 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2265 break; /* Nothing to do */
2267 case ISL_AUX_STATE_PASS_THROUGH
:
2271 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2272 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2273 case ISL_AUX_STATE_RESOLVED
:
2274 case ISL_AUX_STATE_AUX_INVALID
:
2275 unreachable("Invalid aux state for CCS_D");
2281 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2282 struct intel_mipmap_tree
*mt
,
2284 enum isl_aux_usage aux_usage
,
2285 bool fast_clear_supported
)
2287 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2289 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2290 case ISL_AUX_STATE_CLEAR
:
2291 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2292 if (!fast_clear_supported
) {
2293 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2294 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2295 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2299 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2300 break; /* Nothing to do */
2302 case ISL_AUX_STATE_RESOLVED
:
2303 case ISL_AUX_STATE_PASS_THROUGH
:
2304 case ISL_AUX_STATE_AUX_INVALID
:
2305 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2306 unreachable("Invalid aux state for MCS");
2311 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2312 struct intel_mipmap_tree
*mt
,
2314 enum isl_aux_usage aux_usage
)
2316 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2318 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2319 case ISL_AUX_STATE_CLEAR
:
2320 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2321 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2324 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2325 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2326 break; /* Nothing to do */
2328 case ISL_AUX_STATE_RESOLVED
:
2329 case ISL_AUX_STATE_PASS_THROUGH
:
2330 case ISL_AUX_STATE_AUX_INVALID
:
2331 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2332 unreachable("Invalid aux state for MCS");
2337 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2338 struct intel_mipmap_tree
*mt
,
2339 uint32_t level
, uint32_t layer
,
2340 enum isl_aux_usage aux_usage
,
2341 bool fast_clear_supported
)
2343 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2345 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2346 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2347 case ISL_AUX_STATE_CLEAR
:
2348 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2349 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2350 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2353 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2354 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2355 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2358 case ISL_AUX_STATE_PASS_THROUGH
:
2359 case ISL_AUX_STATE_RESOLVED
:
2362 case ISL_AUX_STATE_AUX_INVALID
:
2363 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2364 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2367 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2368 unreachable("Invalid HiZ state");
2371 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2372 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2375 case ISL_AUX_OP_FULL_RESOLVE
:
2376 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2377 ISL_AUX_STATE_RESOLVED
);
2380 case ISL_AUX_OP_AMBIGUATE
:
2381 /* The HiZ resolve operation is actually an ambiguate */
2382 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2383 ISL_AUX_STATE_PASS_THROUGH
);
2387 unreachable("Invalid HiZ op");
2393 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2394 struct intel_mipmap_tree
*mt
,
2395 uint32_t level
, uint32_t layer
,
2396 enum isl_aux_usage aux_usage
)
2398 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2400 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2401 case ISL_AUX_STATE_CLEAR
:
2402 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2403 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2404 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2407 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2408 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2409 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2410 break; /* Nothing to do */
2412 case ISL_AUX_STATE_RESOLVED
:
2413 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2414 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2415 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2417 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2418 ISL_AUX_STATE_AUX_INVALID
);
2422 case ISL_AUX_STATE_PASS_THROUGH
:
2423 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2424 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2425 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2429 case ISL_AUX_STATE_AUX_INVALID
:
2430 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2433 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2434 unreachable("Invalid HiZ state");
2439 intel_miptree_prepare_access(struct brw_context
*brw
,
2440 struct intel_mipmap_tree
*mt
,
2441 uint32_t start_level
, uint32_t num_levels
,
2442 uint32_t start_layer
, uint32_t num_layers
,
2443 enum isl_aux_usage aux_usage
,
2444 bool fast_clear_supported
)
2446 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2448 switch (mt
->aux_usage
) {
2449 case ISL_AUX_USAGE_NONE
:
2453 case ISL_AUX_USAGE_MCS
:
2454 assert(mt
->mcs_buf
);
2455 assert(start_level
== 0 && num_levels
== 1);
2456 const uint32_t level_layers
=
2457 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2458 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2459 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2460 aux_usage
, fast_clear_supported
);
2464 case ISL_AUX_USAGE_CCS_D
:
2465 case ISL_AUX_USAGE_CCS_E
:
2469 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2470 const uint32_t level
= start_level
+ l
;
2471 const uint32_t level_layers
=
2472 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2473 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2474 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2476 aux_usage
, fast_clear_supported
);
2481 case ISL_AUX_USAGE_HIZ
:
2482 assert(mt
->hiz_buf
);
2483 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2484 const uint32_t level
= start_level
+ l
;
2485 if (!intel_miptree_level_has_hiz(mt
, level
))
2488 const uint32_t level_layers
=
2489 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2490 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2491 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2492 aux_usage
, fast_clear_supported
);
2498 unreachable("Invalid aux usage");
2503 intel_miptree_finish_write(struct brw_context
*brw
,
2504 struct intel_mipmap_tree
*mt
, uint32_t level
,
2505 uint32_t start_layer
, uint32_t num_layers
,
2506 enum isl_aux_usage aux_usage
)
2508 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2510 switch (mt
->aux_usage
) {
2511 case ISL_AUX_USAGE_NONE
:
2515 case ISL_AUX_USAGE_MCS
:
2516 assert(mt
->mcs_buf
);
2517 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2518 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2523 case ISL_AUX_USAGE_CCS_D
:
2524 case ISL_AUX_USAGE_CCS_E
:
2528 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2529 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2534 case ISL_AUX_USAGE_HIZ
:
2535 if (!intel_miptree_level_has_hiz(mt
, level
))
2538 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2539 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2545 unreachable("Invavlid aux usage");
2550 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2551 uint32_t level
, uint32_t layer
)
2553 intel_miptree_check_level_layer(mt
, level
, layer
);
2555 if (_mesa_is_format_color_format(mt
->format
)) {
2556 assert(mt
->mcs_buf
!= NULL
);
2557 assert(mt
->surf
.samples
== 1 ||
2558 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2559 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2560 unreachable("Cannot get aux state for stencil");
2562 assert(intel_miptree_level_has_hiz(mt
, level
));
2565 return mt
->aux_state
[level
][layer
];
2569 intel_miptree_set_aux_state(struct brw_context
*brw
,
2570 struct intel_mipmap_tree
*mt
, uint32_t level
,
2571 uint32_t start_layer
, uint32_t num_layers
,
2572 enum isl_aux_state aux_state
)
2574 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2576 if (_mesa_is_format_color_format(mt
->format
)) {
2577 assert(mt
->mcs_buf
!= NULL
);
2578 assert(mt
->surf
.samples
== 1 ||
2579 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2580 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2581 unreachable("Cannot get aux state for stencil");
2583 assert(intel_miptree_level_has_hiz(mt
, level
));
2586 for (unsigned a
= 0; a
< num_layers
; a
++) {
2587 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2588 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2589 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2594 /* On Gen9 color buffers may be compressed by the hardware (lossless
2595 * compression). There are, however, format restrictions and care needs to be
2596 * taken that the sampler engine is capable for re-interpreting a buffer with
2597 * format different the buffer was originally written with.
2599 * For example, SRGB formats are not compressible and the sampler engine isn't
2600 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2601 * color buffer needs to be resolved so that the sampling surface can be
2602 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2606 can_texture_with_ccs(struct brw_context
*brw
,
2607 struct intel_mipmap_tree
*mt
,
2608 enum isl_format view_format
)
2610 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2613 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2615 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2616 isl_format_get_layout(view_format
)->name
,
2617 _mesa_get_format_name(mt
->format
));
2625 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2626 struct intel_mipmap_tree
*mt
,
2627 enum isl_format view_format
)
2629 switch (mt
->aux_usage
) {
2630 case ISL_AUX_USAGE_HIZ
:
2631 if (intel_miptree_sample_with_hiz(brw
, mt
))
2632 return ISL_AUX_USAGE_HIZ
;
2635 case ISL_AUX_USAGE_MCS
:
2636 return ISL_AUX_USAGE_MCS
;
2638 case ISL_AUX_USAGE_CCS_D
:
2639 case ISL_AUX_USAGE_CCS_E
:
2641 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2642 return ISL_AUX_USAGE_NONE
;
2645 /* If we don't have any unresolved color, report an aux usage of
2646 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2647 * aux surface and we can save some bandwidth.
2649 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2650 0, INTEL_REMAINING_LAYERS
))
2651 return ISL_AUX_USAGE_NONE
;
2653 if (can_texture_with_ccs(brw
, mt
, view_format
))
2654 return ISL_AUX_USAGE_CCS_E
;
2661 return ISL_AUX_USAGE_NONE
;
2665 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2667 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2668 * values so sRGB curve application was a no-op for all fast-clearable
2671 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2672 * values, the hardware interprets the floats, not as what would be
2673 * returned from the sampler (or written by the shader), but as being
2674 * between format conversion and sRGB curve application. This means that
2675 * we can switch between sRGB and UNORM without having to whack the clear
2678 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2682 intel_miptree_prepare_texture(struct brw_context
*brw
,
2683 struct intel_mipmap_tree
*mt
,
2684 enum isl_format view_format
,
2685 uint32_t start_level
, uint32_t num_levels
,
2686 uint32_t start_layer
, uint32_t num_layers
)
2688 enum isl_aux_usage aux_usage
=
2689 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2690 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2692 /* Clear color is specified as ints or floats and the conversion is done by
2693 * the sampler. If we have a texture view, we would have to perform the
2694 * clear color conversion manually. Just disable clear color.
2696 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2697 clear_supported
= false;
2699 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2700 start_layer
, num_layers
,
2701 aux_usage
, clear_supported
);
2705 intel_miptree_prepare_image(struct brw_context
*brw
,
2706 struct intel_mipmap_tree
*mt
)
2708 /* The data port doesn't understand any compression */
2709 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2710 0, INTEL_REMAINING_LAYERS
,
2711 ISL_AUX_USAGE_NONE
, false);
2715 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2716 struct intel_mipmap_tree
*mt
,
2717 enum isl_format render_format
,
2719 bool draw_aux_disabled
)
2721 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2723 if (draw_aux_disabled
)
2724 return ISL_AUX_USAGE_NONE
;
2726 switch (mt
->aux_usage
) {
2727 case ISL_AUX_USAGE_MCS
:
2728 assert(mt
->mcs_buf
);
2729 return ISL_AUX_USAGE_MCS
;
2731 case ISL_AUX_USAGE_CCS_D
:
2732 case ISL_AUX_USAGE_CCS_E
:
2734 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2735 return ISL_AUX_USAGE_NONE
;
2738 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2739 * formats. However, there are issues with blending where it doesn't
2740 * properly apply the sRGB curve to the clear color when blending.
2742 if (devinfo
->gen
== 9 && blend_enabled
&&
2743 isl_format_is_srgb(render_format
) &&
2744 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2745 return ISL_AUX_USAGE_NONE
;
2747 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2748 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2750 return ISL_AUX_USAGE_CCS_E
;
2752 /* Otherwise, we have to fall back to CCS_D */
2753 return ISL_AUX_USAGE_CCS_D
;
2756 return ISL_AUX_USAGE_NONE
;
2761 intel_miptree_prepare_render(struct brw_context
*brw
,
2762 struct intel_mipmap_tree
*mt
, uint32_t level
,
2763 uint32_t start_layer
, uint32_t layer_count
,
2764 enum isl_aux_usage aux_usage
)
2766 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2767 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2771 intel_miptree_finish_render(struct brw_context
*brw
,
2772 struct intel_mipmap_tree
*mt
, uint32_t level
,
2773 uint32_t start_layer
, uint32_t layer_count
,
2774 enum isl_aux_usage aux_usage
)
2776 assert(_mesa_is_format_color_format(mt
->format
));
2778 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2783 intel_miptree_prepare_depth(struct brw_context
*brw
,
2784 struct intel_mipmap_tree
*mt
, uint32_t level
,
2785 uint32_t start_layer
, uint32_t layer_count
)
2787 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2788 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2792 intel_miptree_finish_depth(struct brw_context
*brw
,
2793 struct intel_mipmap_tree
*mt
, uint32_t level
,
2794 uint32_t start_layer
, uint32_t layer_count
,
2797 if (depth_written
) {
2798 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2799 mt
->hiz_buf
!= NULL
);
2804 intel_miptree_prepare_external(struct brw_context
*brw
,
2805 struct intel_mipmap_tree
*mt
)
2807 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2808 bool supports_fast_clear
= false;
2810 const struct isl_drm_modifier_info
*mod_info
=
2811 isl_drm_modifier_get_info(mt
->drm_modifier
);
2813 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2814 /* CCS_E is the only supported aux for external images and it's only
2815 * supported on very simple images.
2817 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2818 assert(_mesa_is_format_color_format(mt
->format
));
2819 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2820 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2821 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2822 assert(mt
->surf
.samples
== 1);
2823 assert(mt
->mcs_buf
!= NULL
);
2825 aux_usage
= mod_info
->aux_usage
;
2826 supports_fast_clear
= mod_info
->supports_clear_color
;
2829 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2830 0, INTEL_REMAINING_LAYERS
,
2831 aux_usage
, supports_fast_clear
);
2835 intel_miptree_finish_external(struct brw_context
*brw
,
2836 struct intel_mipmap_tree
*mt
)
2841 /* We don't know the actual aux state of the aux surface. The previous
2842 * owner could have given it to us in a number of different states.
2843 * Because we don't know the aux state, we reset the aux state to the
2844 * least common denominator of possible valid states.
2846 enum isl_aux_state default_aux_state
=
2847 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2848 assert(mt
->last_level
== mt
->first_level
);
2849 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2854 * Make it possible to share the BO backing the given miptree with another
2855 * process or another miptree.
2857 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2858 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2859 * ensure that no MCS buffer gets allocated in the future.
2861 * HiZ is similarly unsafe with shared buffers.
2864 intel_miptree_make_shareable(struct brw_context
*brw
,
2865 struct intel_mipmap_tree
*mt
)
2867 /* MCS buffers are also used for multisample buffers, but we can't resolve
2868 * away a multisample MCS buffer because it's an integral part of how the
2869 * pixel data is stored. Fortunately this code path should never be
2870 * reached for multisample buffers.
2872 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2873 mt
->surf
.samples
== 1);
2875 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2876 0, INTEL_REMAINING_LAYERS
,
2877 ISL_AUX_USAGE_NONE
, false);
2880 brw_bo_unreference(mt
->mcs_buf
->bo
);
2884 /* Any pending MCS/CCS operations are no longer needed. Trying to
2885 * execute any will likely crash due to the missing aux buffer. So let's
2886 * delete all pending ops.
2888 free(mt
->aux_state
);
2889 mt
->aux_state
= NULL
;
2890 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2894 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2897 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2898 mt
->level
[l
].has_hiz
= false;
2901 /* Any pending HiZ operations are no longer needed. Trying to execute
2902 * any will likely crash due to the missing aux buffer. So let's delete
2905 free(mt
->aux_state
);
2906 mt
->aux_state
= NULL
;
2907 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2910 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2911 mt
->supports_fast_clear
= false;
2916 * \brief Get pointer offset into stencil buffer.
2918 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2919 * must decode the tile's layout in software.
2922 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2924 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2926 * Even though the returned offset is always positive, the return type is
2928 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2929 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2932 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2934 uint32_t tile_size
= 4096;
2935 uint32_t tile_width
= 64;
2936 uint32_t tile_height
= 64;
2937 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2939 uint32_t tile_x
= x
/ tile_width
;
2940 uint32_t tile_y
= y
/ tile_height
;
2942 /* The byte's address relative to the tile's base addres. */
2943 uint32_t byte_x
= x
% tile_width
;
2944 uint32_t byte_y
= y
% tile_height
;
2946 uintptr_t u
= tile_y
* row_size
2947 + tile_x
* tile_size
2948 + 512 * (byte_x
/ 8)
2950 + 32 * ((byte_y
/ 4) % 2)
2951 + 16 * ((byte_x
/ 4) % 2)
2952 + 8 * ((byte_y
/ 2) % 2)
2953 + 4 * ((byte_x
/ 2) % 2)
2958 /* adjust for bit6 swizzling */
2959 if (((byte_x
/ 8) % 2) == 1) {
2960 if (((byte_y
/ 8) % 2) == 0) {
2972 intel_miptree_updownsample(struct brw_context
*brw
,
2973 struct intel_mipmap_tree
*src
,
2974 struct intel_mipmap_tree
*dst
)
2976 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2977 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2978 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2979 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2981 brw_blorp_blit_miptrees(brw
,
2982 src
, 0 /* level */, 0 /* layer */,
2983 src
->format
, SWIZZLE_XYZW
,
2984 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2987 GL_NEAREST
, false, false /*mirror x, y*/,
2990 if (src
->stencil_mt
) {
2991 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2992 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2993 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2994 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2996 brw_blorp_blit_miptrees(brw
,
2997 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2998 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2999 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
3000 dst
->stencil_mt
->format
,
3003 GL_NEAREST
, false, false /*mirror x, y*/,
3004 false, false /* decode/encode srgb */);
3009 intel_update_r8stencil(struct brw_context
*brw
,
3010 struct intel_mipmap_tree
*mt
)
3012 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3014 assert(devinfo
->gen
>= 7);
3015 struct intel_mipmap_tree
*src
=
3016 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3017 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
3020 assert(src
->surf
.size
> 0);
3022 if (!mt
->r8stencil_mt
) {
3023 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3024 mt
->r8stencil_mt
= make_surface(
3027 MESA_FORMAT_R_UINT8
,
3028 src
->first_level
, src
->last_level
,
3029 src
->surf
.logical_level0_px
.width
,
3030 src
->surf
.logical_level0_px
.height
,
3031 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3032 src
->surf
.logical_level0_px
.depth
:
3033 src
->surf
.logical_level0_px
.array_len
,
3036 ISL_SURF_USAGE_TEXTURE_BIT
,
3037 BO_ALLOC_BUSY
, 0, NULL
);
3038 assert(mt
->r8stencil_mt
);
3041 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3043 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3044 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3045 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3046 src
->surf
.phys_level0_sa
.array_len
;
3048 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3049 brw_blorp_copy_miptrees(brw
,
3053 minify(src
->surf
.logical_level0_px
.width
,
3055 minify(src
->surf
.logical_level0_px
.height
,
3060 brw_cache_flush_for_read(brw
, dst
->bo
);
3061 src
->r8stencil_needs_update
= false;
3065 intel_miptree_map_raw(struct brw_context
*brw
,
3066 struct intel_mipmap_tree
*mt
,
3069 struct brw_bo
*bo
= mt
->bo
;
3071 if (brw_batch_references(&brw
->batch
, bo
))
3072 intel_batchbuffer_flush(brw
);
3074 return brw_bo_map(brw
, bo
, mode
);
3078 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3080 brw_bo_unmap(mt
->bo
);
3084 intel_miptree_map_gtt(struct brw_context
*brw
,
3085 struct intel_mipmap_tree
*mt
,
3086 struct intel_miptree_map
*map
,
3087 unsigned int level
, unsigned int slice
)
3089 unsigned int bw
, bh
;
3091 unsigned int image_x
, image_y
;
3092 intptr_t x
= map
->x
;
3093 intptr_t y
= map
->y
;
3095 /* For compressed formats, the stride is the number of bytes per
3096 * row of blocks. intel_miptree_get_image_offset() already does
3099 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3100 assert(y
% bh
== 0);
3101 assert(x
% bw
== 0);
3105 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3112 /* Note that in the case of cube maps, the caller must have passed the
3113 * slice number referencing the face.
3115 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3119 map
->stride
= mt
->surf
.row_pitch
;
3120 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3123 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3124 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3125 map
->x
, map
->y
, map
->w
, map
->h
,
3126 mt
, _mesa_get_format_name(mt
->format
),
3127 x
, y
, map
->ptr
, map
->stride
);
3131 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3133 intel_miptree_unmap_raw(mt
);
3137 intel_miptree_map_blit(struct brw_context
*brw
,
3138 struct intel_mipmap_tree
*mt
,
3139 struct intel_miptree_map
*map
,
3140 unsigned int level
, unsigned int slice
)
3142 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3143 /* first_level */ 0,
3147 MIPTREE_CREATE_LINEAR
);
3149 if (!map
->linear_mt
) {
3150 fprintf(stderr
, "Failed to allocate blit temporary\n");
3153 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3155 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3156 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3157 * invalidate is set, since we'll be writing the whole rectangle from our
3158 * temporary buffer back out.
3160 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3161 if (!intel_miptree_copy(brw
,
3162 mt
, level
, slice
, map
->x
, map
->y
,
3163 map
->linear_mt
, 0, 0, 0, 0,
3165 fprintf(stderr
, "Failed to blit\n");
3170 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3172 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3173 map
->x
, map
->y
, map
->w
, map
->h
,
3174 mt
, _mesa_get_format_name(mt
->format
),
3175 level
, slice
, map
->ptr
, map
->stride
);
3180 intel_miptree_release(&map
->linear_mt
);
3186 intel_miptree_unmap_blit(struct brw_context
*brw
,
3187 struct intel_mipmap_tree
*mt
,
3188 struct intel_miptree_map
*map
,
3192 struct gl_context
*ctx
= &brw
->ctx
;
3194 intel_miptree_unmap_raw(map
->linear_mt
);
3196 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3197 bool ok
= intel_miptree_copy(brw
,
3198 map
->linear_mt
, 0, 0, 0, 0,
3199 mt
, level
, slice
, map
->x
, map
->y
,
3201 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3204 intel_miptree_release(&map
->linear_mt
);
3208 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3210 #if defined(USE_SSE41)
3212 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3213 struct intel_mipmap_tree
*mt
,
3214 struct intel_miptree_map
*map
,
3215 unsigned int level
, unsigned int slice
)
3217 assert(map
->mode
& GL_MAP_READ_BIT
);
3218 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3220 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3221 map
->x
, map
->y
, map
->w
, map
->h
,
3222 mt
, _mesa_get_format_name(mt
->format
),
3223 level
, slice
, map
->ptr
, map
->stride
);
3225 /* Map the original image */
3228 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3232 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3238 src
+= image_y
* mt
->surf
.row_pitch
;
3239 src
+= image_x
* mt
->cpp
;
3241 /* Due to the pixel offsets for the particular image being mapped, our
3242 * src pointer may not be 16-byte aligned. However, if the pitch is
3243 * divisible by 16, then the amount by which it's misaligned will remain
3244 * consistent from row to row.
3246 assert((mt
->surf
.row_pitch
% 16) == 0);
3247 const int misalignment
= ((uintptr_t) src
) & 15;
3249 /* Create an untiled temporary buffer for the mapping. */
3250 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3252 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3254 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3255 /* Offset the destination so it has the same misalignment as src. */
3256 map
->ptr
= map
->buffer
+ misalignment
;
3258 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3260 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3261 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3262 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3264 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3267 intel_miptree_unmap_raw(mt
);
3271 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3272 struct intel_mipmap_tree
*mt
,
3273 struct intel_miptree_map
*map
,
3277 _mesa_align_free(map
->buffer
);
3284 intel_miptree_map_s8(struct brw_context
*brw
,
3285 struct intel_mipmap_tree
*mt
,
3286 struct intel_miptree_map
*map
,
3287 unsigned int level
, unsigned int slice
)
3289 map
->stride
= map
->w
;
3290 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3294 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3295 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3296 * invalidate is set, since we'll be writing the whole rectangle from our
3297 * temporary buffer back out.
3299 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3300 uint8_t *untiled_s8_map
= map
->ptr
;
3301 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3302 unsigned int image_x
, image_y
;
3304 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3306 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3307 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3308 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3309 x
+ image_x
+ map
->x
,
3310 y
+ image_y
+ map
->y
,
3311 brw
->has_swizzling
);
3312 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3316 intel_miptree_unmap_raw(mt
);
3318 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3319 map
->x
, map
->y
, map
->w
, map
->h
,
3320 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3322 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3323 map
->x
, map
->y
, map
->w
, map
->h
,
3324 mt
, map
->ptr
, map
->stride
);
3329 intel_miptree_unmap_s8(struct brw_context
*brw
,
3330 struct intel_mipmap_tree
*mt
,
3331 struct intel_miptree_map
*map
,
3335 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3336 unsigned int image_x
, image_y
;
3337 uint8_t *untiled_s8_map
= map
->ptr
;
3338 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3340 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3342 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3343 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3344 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3345 image_x
+ x
+ map
->x
,
3346 image_y
+ y
+ map
->y
,
3347 brw
->has_swizzling
);
3348 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3352 intel_miptree_unmap_raw(mt
);
3359 intel_miptree_map_etc(struct brw_context
*brw
,
3360 struct intel_mipmap_tree
*mt
,
3361 struct intel_miptree_map
*map
,
3365 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3366 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3367 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3370 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3371 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3373 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3374 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3375 map
->w
, map
->h
, 1));
3376 map
->ptr
= map
->buffer
;
3380 intel_miptree_unmap_etc(struct brw_context
*brw
,
3381 struct intel_mipmap_tree
*mt
,
3382 struct intel_miptree_map
*map
,
3388 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3393 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3394 + image_y
* mt
->surf
.row_pitch
3395 + image_x
* mt
->cpp
;
3397 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3398 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3399 map
->ptr
, map
->stride
,
3402 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3403 map
->ptr
, map
->stride
,
3404 map
->w
, map
->h
, mt
->etc_format
);
3406 intel_miptree_unmap_raw(mt
);
3411 * Mapping function for packed depth/stencil miptrees backed by real separate
3412 * miptrees for depth and stencil.
3414 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3415 * separate from the depth buffer. Yet at the GL API level, we have to expose
3416 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3417 * be able to map that memory for texture storage and glReadPixels-type
3418 * operations. We give Mesa core that access by mallocing a temporary and
3419 * copying the data between the actual backing store and the temporary.
3422 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3423 struct intel_mipmap_tree
*mt
,
3424 struct intel_miptree_map
*map
,
3425 unsigned int level
, unsigned int slice
)
3427 struct intel_mipmap_tree
*z_mt
= mt
;
3428 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3429 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3430 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3432 map
->stride
= map
->w
* packed_bpp
;
3433 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3437 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3438 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3439 * invalidate is set, since we'll be writing the whole rectangle from our
3440 * temporary buffer back out.
3442 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3443 uint32_t *packed_map
= map
->ptr
;
3444 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3445 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3446 unsigned int s_image_x
, s_image_y
;
3447 unsigned int z_image_x
, z_image_y
;
3449 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3450 &s_image_x
, &s_image_y
);
3451 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3452 &z_image_x
, &z_image_y
);
3454 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3455 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3456 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3457 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3460 brw
->has_swizzling
);
3461 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3462 (z_mt
->surf
.row_pitch
/ 4) +
3463 (map_x
+ z_image_x
));
3464 uint8_t s
= s_map
[s_offset
];
3465 uint32_t z
= z_map
[z_offset
];
3467 if (map_z32f_x24s8
) {
3468 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3469 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3471 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3476 intel_miptree_unmap_raw(s_mt
);
3477 intel_miptree_unmap_raw(z_mt
);
3479 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3481 map
->x
, map
->y
, map
->w
, map
->h
,
3482 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3483 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3484 map
->ptr
, map
->stride
);
3486 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3487 map
->x
, map
->y
, map
->w
, map
->h
,
3488 mt
, map
->ptr
, map
->stride
);
3493 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3494 struct intel_mipmap_tree
*mt
,
3495 struct intel_miptree_map
*map
,
3499 struct intel_mipmap_tree
*z_mt
= mt
;
3500 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3501 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3503 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3504 uint32_t *packed_map
= map
->ptr
;
3505 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3506 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3507 unsigned int s_image_x
, s_image_y
;
3508 unsigned int z_image_x
, z_image_y
;
3510 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3511 &s_image_x
, &s_image_y
);
3512 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3513 &z_image_x
, &z_image_y
);
3515 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3516 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3517 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3518 x
+ s_image_x
+ map
->x
,
3519 y
+ s_image_y
+ map
->y
,
3520 brw
->has_swizzling
);
3521 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3522 (z_mt
->surf
.row_pitch
/ 4) +
3523 (x
+ z_image_x
+ map
->x
));
3525 if (map_z32f_x24s8
) {
3526 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3527 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3529 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3530 s_map
[s_offset
] = packed
>> 24;
3531 z_map
[z_offset
] = packed
;
3536 intel_miptree_unmap_raw(s_mt
);
3537 intel_miptree_unmap_raw(z_mt
);
3539 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3541 map
->x
, map
->y
, map
->w
, map
->h
,
3542 z_mt
, _mesa_get_format_name(z_mt
->format
),
3543 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3544 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3545 map
->ptr
, map
->stride
);
3552 * Create and attach a map to the miptree at (level, slice). Return the
3555 static struct intel_miptree_map
*
3556 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3565 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3570 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3571 mt
->level
[level
].slice
[slice
].map
= map
;
3583 * Release the map at (level, slice).
3586 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3590 struct intel_miptree_map
**map
;
3592 map
= &mt
->level
[level
].slice
[slice
].map
;
3598 can_blit_slice(struct intel_mipmap_tree
*mt
,
3599 unsigned int level
, unsigned int slice
)
3601 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3602 if (mt
->surf
.row_pitch
>= 32768)
3609 use_intel_mipree_map_blit(struct brw_context
*brw
,
3610 struct intel_mipmap_tree
*mt
,
3615 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3617 if (devinfo
->has_llc
&&
3618 /* It's probably not worth swapping to the blit ring because of
3619 * all the overhead involved.
3621 !(mode
& GL_MAP_WRITE_BIT
) &&
3623 (mt
->surf
.tiling
== ISL_TILING_X
||
3624 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3625 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3626 /* Fast copy blit on skl+ supports all tiling formats. */
3627 devinfo
->gen
>= 9) &&
3628 can_blit_slice(mt
, level
, slice
))
3631 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3632 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3633 assert(can_blit_slice(mt
, level
, slice
));
3641 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3642 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3643 * arithmetic overflow.
3645 * If you call this function and use \a out_stride, then you're doing pointer
3646 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3647 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3648 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3649 * which usually have type uint32_t or GLuint.
3652 intel_miptree_map(struct brw_context
*brw
,
3653 struct intel_mipmap_tree
*mt
,
3662 ptrdiff_t *out_stride
)
3664 struct intel_miptree_map
*map
;
3666 assert(mt
->surf
.samples
== 1);
3668 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3675 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3676 map
->mode
& GL_MAP_WRITE_BIT
);
3678 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3679 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3680 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3681 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3682 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3683 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3684 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3685 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3686 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3687 #if defined(USE_SSE41)
3688 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3689 !mt
->compressed
&& cpu_has_sse4_1
&&
3690 (mt
->surf
.row_pitch
% 16 == 0)) {
3691 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3694 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3697 *out_ptr
= map
->ptr
;
3698 *out_stride
= map
->stride
;
3700 if (map
->ptr
== NULL
)
3701 intel_miptree_release_map(mt
, level
, slice
);
3705 intel_miptree_unmap(struct brw_context
*brw
,
3706 struct intel_mipmap_tree
*mt
,
3710 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3712 assert(mt
->surf
.samples
== 1);
3717 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3718 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3720 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3721 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3722 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3723 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3724 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3725 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3726 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3727 } else if (map
->linear_mt
) {
3728 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3729 #if defined(USE_SSE41)
3730 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3731 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3734 intel_miptree_unmap_gtt(mt
);
3737 intel_miptree_release_map(mt
, level
, slice
);
3741 get_isl_surf_dim(GLenum target
)
3745 case GL_TEXTURE_1D_ARRAY
:
3746 return ISL_SURF_DIM_1D
;
3749 case GL_TEXTURE_2D_ARRAY
:
3750 case GL_TEXTURE_RECTANGLE
:
3751 case GL_TEXTURE_CUBE_MAP
:
3752 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3753 case GL_TEXTURE_2D_MULTISAMPLE
:
3754 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3755 case GL_TEXTURE_EXTERNAL_OES
:
3756 return ISL_SURF_DIM_2D
;
3759 return ISL_SURF_DIM_3D
;
3762 unreachable("Invalid texture target");
3766 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3767 enum isl_tiling tiling
, GLenum target
)
3771 case GL_TEXTURE_1D_ARRAY
:
3772 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3773 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3776 case GL_TEXTURE_2D_ARRAY
:
3777 case GL_TEXTURE_RECTANGLE
:
3778 case GL_TEXTURE_2D_MULTISAMPLE
:
3779 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3780 case GL_TEXTURE_EXTERNAL_OES
:
3781 return ISL_DIM_LAYOUT_GEN4_2D
;
3783 case GL_TEXTURE_CUBE_MAP
:
3784 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3785 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3786 ISL_DIM_LAYOUT_GEN4_2D
);
3789 return (devinfo
->gen
>= 9 ?
3790 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3793 unreachable("Invalid texture target");
3797 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3798 const struct intel_mipmap_tree
*mt
)
3801 return ISL_AUX_USAGE_HIZ
;
3804 return ISL_AUX_USAGE_NONE
;
3806 return mt
->aux_usage
;
3810 intel_miptree_set_clear_color(struct brw_context
*brw
,
3811 struct intel_mipmap_tree
*mt
,
3812 const union gl_color_union
*color
)
3814 const union isl_color_value clear_color
=
3815 brw_meta_convert_fast_clear_color(brw
, mt
, color
);
3817 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3818 mt
->fast_clear_color
= clear_color
;
3819 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3826 intel_miptree_set_depth_clear_value(struct brw_context
*brw
,
3827 struct intel_mipmap_tree
*mt
,
3830 if (mt
->fast_clear_color
.f32
[0] != clear_value
) {
3831 mt
->fast_clear_color
.f32
[0] = clear_value
;
3832 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;