1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
38 #include "intel_fbo.h"
40 #include "brw_blorp.h"
41 #include "brw_context.h"
43 #include "main/enums.h"
44 #include "main/fbobject.h"
45 #include "main/formats.h"
46 #include "main/glformats.h"
47 #include "main/texcompress_etc.h"
48 #include "main/teximage.h"
49 #include "main/streaming-load-memcpy.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* Disable MCS on Broadwell for now. We can enable it once things
72 * are working without it.
75 perf_debug("Missing CMS support on Broadwell.\n");
76 return INTEL_MSAA_LAYOUT_UMS
;
79 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
81 * This field must be set to 0 for all SINT MSRTs when all RT channels
84 * In practice this means that we have to disable MCS for all signed
85 * integer MSAA buffers. The alternative, to disable MCS only when one
86 * of the render target channels is disabled, is impractical because it
87 * would require converting between CMS and UMS MSAA layouts on the fly,
90 if (_mesa_get_format_datatype(format
) == GL_INT
) {
91 /* TODO: is this workaround needed for future chipsets? */
92 assert(brw
->gen
== 7);
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->region
->tiling
) {
149 assert(!"Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
163 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
170 * - Support is for non-mip-mapped and non-array surface types only.
172 * And then later, on p327:
174 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
178 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
179 struct intel_mipmap_tree
*mt
)
181 /* MCS support does not exist prior to Gen7 */
182 if (brw
->gen
< 7 || brw
->gen
>= 8)
185 /* MCS is only supported for color buffers */
186 switch (_mesa_get_format_base_format(mt
->format
)) {
187 case GL_DEPTH_COMPONENT
:
188 case GL_DEPTH_STENCIL
:
189 case GL_STENCIL_INDEX
:
193 if (mt
->region
->tiling
!= I915_TILING_X
&&
194 mt
->region
->tiling
!= I915_TILING_Y
)
196 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
198 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
200 if (mt
->physical_depth0
!= 1)
203 /* There's no point in using an MCS buffer if the surface isn't in a
206 if (!brw
->format_supported_as_render_target
[mt
->format
])
214 * @param for_bo Indicates that the caller is
215 * intel_miptree_create_for_bo(). If true, then do not create
218 struct intel_mipmap_tree
*
219 intel_miptree_create_layout(struct brw_context
*brw
,
230 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
234 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
235 _mesa_lookup_enum_by_nr(target
),
236 _mesa_get_format_name(format
),
237 first_level
, last_level
, depth0
, mt
);
241 mt
->first_level
= first_level
;
242 mt
->last_level
= last_level
;
243 mt
->logical_width0
= width0
;
244 mt
->logical_height0
= height0
;
245 mt
->logical_depth0
= depth0
;
246 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
248 /* The cpp is bytes per (1, blockheight)-sized block for compressed
249 * textures. This is why you'll see divides by blockheight all over
252 _mesa_get_format_block_size(format
, &bw
, &bh
);
253 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
254 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
256 mt
->num_samples
= num_samples
;
257 mt
->compressed
= _mesa_is_format_compressed(format
);
258 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
261 if (num_samples
> 1) {
262 /* Adjust width/height/depth for MSAA */
263 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
264 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
265 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
267 * "Any of the other messages (sample*, LOD, load4) used with a
268 * (4x) multisampled surface will in-effect sample a surface with
269 * double the height and width as that indicated in the surface
270 * state. Each pixel position on the original-sized surface is
271 * replaced with a 2x2 of samples with the following arrangement:
276 * Thus, when sampling from a multisampled texture, it behaves as
277 * though the layout in memory for (x,y,sample) is:
279 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
280 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
282 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
283 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
285 * However, the actual layout of multisampled data in memory is:
287 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
288 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
290 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
291 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
293 * This pattern repeats for each 2x2 pixel block.
295 * As a result, when calculating the size of our 4-sample buffer for
296 * an odd width or height, we have to align before scaling up because
297 * sample 3 is in that bottom right 2x2 block.
299 switch (num_samples
) {
301 assert(brw
->gen
>= 8);
302 width0
= ALIGN(width0
, 2) * 2;
303 height0
= ALIGN(height0
, 2);
306 width0
= ALIGN(width0
, 2) * 2;
307 height0
= ALIGN(height0
, 2) * 2;
310 width0
= ALIGN(width0
, 2) * 4;
311 height0
= ALIGN(height0
, 2) * 2;
314 /* num_samples should already have been quantized to 0, 1, 2, 4, or
320 /* Non-interleaved */
321 depth0
*= num_samples
;
325 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
328 switch (mt
->msaa_layout
) {
329 case INTEL_MSAA_LAYOUT_NONE
:
330 case INTEL_MSAA_LAYOUT_IMS
:
331 mt
->array_spacing_lod0
= false;
333 case INTEL_MSAA_LAYOUT_UMS
:
334 case INTEL_MSAA_LAYOUT_CMS
:
335 mt
->array_spacing_lod0
= true;
339 if (target
== GL_TEXTURE_CUBE_MAP
) {
344 mt
->physical_width0
= width0
;
345 mt
->physical_height0
= height0
;
346 mt
->physical_depth0
= depth0
;
349 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
350 (brw
->must_use_separate_stencil
||
351 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
352 mt
->stencil_mt
= intel_miptree_create(brw
,
362 INTEL_MIPTREE_TILING_ANY
);
363 if (!mt
->stencil_mt
) {
364 intel_miptree_release(&mt
);
368 /* Fix up the Z miptree format for how we're splitting out separate
369 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
371 if (mt
->format
== MESA_FORMAT_Z24_UNORM_S8_UINT
) {
372 mt
->format
= MESA_FORMAT_Z24_UNORM_X8_UINT
;
373 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_S8X24_UINT
) {
374 mt
->format
= MESA_FORMAT_Z_FLOAT32
;
377 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
378 _mesa_get_format_name(mt
->format
));
382 brw_miptree_layout(brw
, mt
);
388 * \brief Helper function for intel_miptree_create().
391 intel_miptree_choose_tiling(struct brw_context
*brw
,
394 uint32_t num_samples
,
395 enum intel_miptree_tiling_mode requested
,
396 struct intel_mipmap_tree
*mt
)
398 if (format
== MESA_FORMAT_S_UINT8
) {
399 /* The stencil buffer is W tiled. However, we request from the kernel a
400 * non-tiled buffer because the GTT is incapable of W fencing.
402 return I915_TILING_NONE
;
405 /* Some usages may want only one type of tiling, like depth miptrees (Y
406 * tiled), or temporary BOs for uploading data once (linear).
409 case INTEL_MIPTREE_TILING_ANY
:
411 case INTEL_MIPTREE_TILING_Y
:
412 return I915_TILING_Y
;
413 case INTEL_MIPTREE_TILING_NONE
:
414 return I915_TILING_NONE
;
417 if (num_samples
> 1) {
418 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
421 * [DevSNB+]: For multi-sample render targets, this field must be
422 * 1. MSRTs can only be tiled.
424 * Our usual reason for preferring X tiling (fast blits using the
425 * blitting engine) doesn't apply to MSAA, since we'll generally be
426 * downsampling or upsampling when blitting between the MSAA buffer
427 * and another buffer, and the blitting engine doesn't support that.
428 * So use Y tiling, since it makes better use of the cache.
430 return I915_TILING_Y
;
433 GLenum base_format
= _mesa_get_format_base_format(format
);
434 if (base_format
== GL_DEPTH_COMPONENT
||
435 base_format
== GL_DEPTH_STENCIL_EXT
)
436 return I915_TILING_Y
;
438 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
440 /* If the width is much smaller than a tile, don't bother tiling. */
441 if (minimum_pitch
< 64)
442 return I915_TILING_NONE
;
444 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
445 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
446 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
447 mt
->total_width
, mt
->total_height
);
448 return I915_TILING_NONE
;
451 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
453 return I915_TILING_X
;
455 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
456 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
458 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
459 * all the way back to 965, but is explicitly permitted on Gen7.
461 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
462 return I915_TILING_X
;
464 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
465 * messages), on p64, under the heading "Surface Vertical Alignment":
467 * This field must be set to VALIGN_4 for all tiled Y Render Target
470 * So if the surface is renderable and uses a vertical alignment of 2,
471 * force it to be X tiled. This is somewhat conservative (it's possible
472 * that the client won't ever render to this surface), but it's difficult
473 * to know that ahead of time. And besides, since we use a vertical
474 * alignment of 4 as often as we can, this shouldn't happen very often.
476 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
477 brw
->format_supported_as_render_target
[format
]) {
478 return I915_TILING_X
;
481 return I915_TILING_Y
| I915_TILING_X
;
484 struct intel_mipmap_tree
*
485 intel_miptree_create(struct brw_context
*brw
,
493 bool expect_accelerated_upload
,
495 enum intel_miptree_tiling_mode requested_tiling
)
497 struct intel_mipmap_tree
*mt
;
498 mesa_format tex_format
= format
;
499 mesa_format etc_format
= MESA_FORMAT_NONE
;
500 GLuint total_width
, total_height
;
502 if (brw
->gen
< 8 && !brw
->is_baytrail
) {
504 case MESA_FORMAT_ETC1_RGB8
:
505 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
507 case MESA_FORMAT_ETC2_RGB8
:
508 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
510 case MESA_FORMAT_ETC2_SRGB8
:
511 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
512 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
513 format
= MESA_FORMAT_B8G8R8A8_SRGB
;
515 case MESA_FORMAT_ETC2_RGBA8_EAC
:
516 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
517 format
= MESA_FORMAT_R8G8B8A8_UNORM
;
519 case MESA_FORMAT_ETC2_R11_EAC
:
520 format
= MESA_FORMAT_R_UNORM16
;
522 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
523 format
= MESA_FORMAT_R_SNORM16
;
525 case MESA_FORMAT_ETC2_RG11_EAC
:
526 format
= MESA_FORMAT_R16G16_UNORM
;
528 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
529 format
= MESA_FORMAT_R16G16_SNORM
;
532 /* Non ETC1 / ETC2 format */
537 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
539 mt
= intel_miptree_create_layout(brw
, target
, format
,
540 first_level
, last_level
, width0
,
544 * pitch == 0 || height == 0 indicates the null texture
546 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
547 intel_miptree_release(&mt
);
551 total_width
= mt
->total_width
;
552 total_height
= mt
->total_height
;
554 if (format
== MESA_FORMAT_S_UINT8
) {
555 /* Align to size of W tile, 64x64. */
556 total_width
= ALIGN(total_width
, 64);
557 total_height
= ALIGN(total_height
, 64);
560 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
561 num_samples
, requested_tiling
,
563 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
565 mt
->etc_format
= etc_format
;
566 mt
->region
= intel_region_alloc(brw
->intelScreen
,
567 y_or_x
? I915_TILING_Y
: tiling
,
571 expect_accelerated_upload
);
573 /* If the region is too large to fit in the aperture, we need to use the
574 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
575 * so we need to fall back to X.
577 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
578 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
579 mt
->total_width
, mt
->total_height
);
580 intel_region_release(&mt
->region
);
582 mt
->region
= intel_region_alloc(brw
->intelScreen
,
587 expect_accelerated_upload
);
593 intel_miptree_release(&mt
);
598 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
599 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
600 intel_miptree_release(&mt
);
605 /* If this miptree is capable of supporting fast color clears, set
606 * fast_clear_state appropriately to ensure that fast clears will occur.
607 * Allocation of the MCS miptree will be deferred until the first fast
608 * clear actually occurs.
610 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
611 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
616 struct intel_mipmap_tree
*
617 intel_miptree_create_for_bo(struct brw_context
*brw
,
626 struct intel_mipmap_tree
*mt
;
628 struct intel_region
*region
= calloc(1, sizeof(*region
));
632 /* Nothing will be able to use this miptree with the BO if the offset isn't
635 if (tiling
!= I915_TILING_NONE
)
636 assert(offset
% 4096 == 0);
638 /* miptrees can't handle negative pitch. If you need flipping of images,
639 * that's outside of the scope of the mt.
643 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
646 true, 0 /* num_samples */);
652 region
->cpp
= mt
->cpp
;
653 region
->width
= width
;
654 region
->height
= height
;
655 region
->pitch
= pitch
;
656 region
->refcount
= 1;
657 drm_intel_bo_reference(bo
);
659 region
->tiling
= tiling
;
668 * For a singlesample image buffer, this simply wraps the given region with a miptree.
670 * For a multisample image buffer, this wraps the given region with
671 * a singlesample miptree, then creates a multisample miptree into which the
672 * singlesample miptree is embedded as a child.
675 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
676 struct intel_renderbuffer
*irb
,
677 struct intel_region
*region
)
679 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
680 struct intel_mipmap_tree
*multisample_mt
= NULL
;
681 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
682 mesa_format format
= rb
->Format
;
683 int num_samples
= rb
->NumSamples
;
685 /* Only the front and back buffers, which are color buffers, are allocated
686 * through the image loader.
688 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
689 _mesa_get_format_base_format(format
) == GL_RGBA
);
691 singlesample_mt
= intel_miptree_create_for_bo(intel
,
699 if (!singlesample_mt
)
702 singlesample_mt
->region
->name
= region
->name
;
704 /* If this miptree is capable of supporting fast color clears, set
705 * mcs_state appropriately to ensure that fast clears will occur.
706 * Allocation of the MCS miptree will be deferred until the first fast
707 * clear actually occurs.
709 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
710 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
712 if (num_samples
== 0) {
713 intel_miptree_release(&irb
->mt
);
714 irb
->mt
= singlesample_mt
;
716 assert(!irb
->singlesample_mt
);
718 intel_miptree_release(&irb
->singlesample_mt
);
719 irb
->singlesample_mt
= singlesample_mt
;
722 irb
->mt
->logical_width0
!= region
->width
||
723 irb
->mt
->logical_height0
!= region
->height
) {
724 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
732 irb
->need_downsample
= false;
733 intel_miptree_release(&irb
->mt
);
734 irb
->mt
= multisample_mt
;
740 intel_miptree_release(&irb
->singlesample_mt
);
741 intel_miptree_release(&irb
->mt
);
745 struct intel_mipmap_tree
*
746 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
750 uint32_t num_samples
)
752 struct intel_mipmap_tree
*mt
;
755 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
757 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
758 width
, height
, depth
, true, num_samples
,
759 INTEL_MIPTREE_TILING_ANY
);
763 if (brw_is_hiz_depth_format(brw
, format
)) {
764 ok
= intel_miptree_alloc_hiz(brw
, mt
);
772 intel_miptree_release(&mt
);
777 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
778 struct intel_mipmap_tree
*src
)
783 intel_miptree_release(dst
);
787 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
795 intel_miptree_release(struct intel_mipmap_tree
**mt
)
800 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
801 if (--(*mt
)->refcount
<= 0) {
804 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
806 intel_region_release(&((*mt
)->region
));
807 intel_miptree_release(&(*mt
)->stencil_mt
);
808 intel_miptree_release(&(*mt
)->hiz_mt
);
809 intel_miptree_release(&(*mt
)->mcs_mt
);
810 intel_resolve_map_clear(&(*mt
)->hiz_map
);
812 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
813 free((*mt
)->level
[i
].slice
);
822 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
823 int *width
, int *height
, int *depth
)
825 switch (image
->TexObject
->Target
) {
826 case GL_TEXTURE_1D_ARRAY
:
827 *width
= image
->Width
;
829 *depth
= image
->Height
;
832 *width
= image
->Width
;
833 *height
= image
->Height
;
834 *depth
= image
->Depth
;
840 * Can the image be pulled into a unified mipmap tree? This mirrors
841 * the completeness test in a lot of ways.
843 * Not sure whether I want to pass gl_texture_image here.
846 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
847 struct gl_texture_image
*image
)
849 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
850 GLuint level
= intelImage
->base
.Base
.Level
;
851 int width
, height
, depth
;
853 /* glTexImage* choose the texture object based on the target passed in, and
854 * objects can't change targets over their lifetimes, so this should be
857 assert(image
->TexObject
->Target
== mt
->target
);
859 mesa_format mt_format
= mt
->format
;
860 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
861 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
862 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
863 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
864 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
865 mt_format
= mt
->etc_format
;
867 if (image
->TexFormat
!= mt_format
)
870 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
872 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
875 int level_depth
= mt
->level
[level
].depth
;
876 if (mt
->num_samples
> 1) {
877 switch (mt
->msaa_layout
) {
878 case INTEL_MSAA_LAYOUT_NONE
:
879 case INTEL_MSAA_LAYOUT_IMS
:
881 case INTEL_MSAA_LAYOUT_UMS
:
882 case INTEL_MSAA_LAYOUT_CMS
:
883 level_depth
/= mt
->num_samples
;
888 /* Test image dimensions against the base level image adjusted for
889 * minification. This will also catch images not present in the
890 * tree, changed targets, etc.
892 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
893 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
894 depth
!= level_depth
) {
898 if (image
->NumSamples
!= mt
->num_samples
)
906 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
908 GLuint x
, GLuint y
, GLuint d
)
910 mt
->level
[level
].depth
= d
;
911 mt
->level
[level
].level_x
= x
;
912 mt
->level
[level
].level_y
= y
;
914 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
917 assert(mt
->level
[level
].slice
== NULL
);
919 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
920 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
921 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
926 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
927 GLuint level
, GLuint img
,
930 if (img
== 0 && level
== 0)
931 assert(x
== 0 && y
== 0);
933 assert(img
< mt
->level
[level
].depth
);
935 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
936 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
938 DBG("%s level %d img %d pos %d,%d\n",
939 __FUNCTION__
, level
, img
,
940 mt
->level
[level
].slice
[img
].x_offset
,
941 mt
->level
[level
].slice
[img
].y_offset
);
945 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
946 GLuint level
, GLuint slice
,
947 GLuint
*x
, GLuint
*y
)
949 assert(slice
< mt
->level
[level
].depth
);
951 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
952 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
956 * Rendering with tiled buffers requires that the base address of the buffer
957 * be aligned to a page boundary. For renderbuffers, and sometimes with
958 * textures, we may want the surface to point at a texture image level that
959 * isn't at a page boundary.
961 * This function returns an appropriately-aligned base offset
962 * according to the tiling restrictions, plus any required x/y offset
966 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
967 GLuint level
, GLuint slice
,
971 const struct intel_region
*region
= mt
->region
;
973 uint32_t mask_x
, mask_y
;
975 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
976 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
978 *tile_x
= x
& mask_x
;
979 *tile_y
= y
& mask_y
;
981 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
986 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
987 struct intel_mipmap_tree
*dst_mt
,
988 struct intel_mipmap_tree
*src_mt
,
995 int src_stride
, dst_stride
;
996 int cpp
= dst_mt
->cpp
;
998 intel_miptree_map(brw
, src_mt
,
1002 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1005 intel_miptree_map(brw
, dst_mt
,
1009 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1013 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1014 _mesa_get_format_name(src_mt
->format
),
1015 src_mt
, src
, src_stride
,
1016 _mesa_get_format_name(dst_mt
->format
),
1017 dst_mt
, dst
, dst_stride
,
1020 int row_size
= cpp
* width
;
1021 if (src_stride
== row_size
&&
1022 dst_stride
== row_size
) {
1023 memcpy(dst
, src
, row_size
* height
);
1025 for (int i
= 0; i
< height
; i
++) {
1026 memcpy(dst
, src
, row_size
);
1032 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1033 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1035 /* Don't forget to copy the stencil data over, too. We could have skipped
1036 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1037 * shuffling the two data sources in/out of temporary storage instead of
1038 * the direct mapping we get this way.
1040 if (dst_mt
->stencil_mt
) {
1041 assert(src_mt
->stencil_mt
);
1042 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1043 level
, slice
, width
, height
);
1048 intel_miptree_copy_slice(struct brw_context
*brw
,
1049 struct intel_mipmap_tree
*dst_mt
,
1050 struct intel_mipmap_tree
*src_mt
,
1056 mesa_format format
= src_mt
->format
;
1057 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1058 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1066 assert(depth
< src_mt
->level
[level
].depth
);
1067 assert(src_mt
->format
== dst_mt
->format
);
1069 if (dst_mt
->compressed
) {
1070 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1071 width
= ALIGN(width
, dst_mt
->align_w
);
1074 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1075 * below won't apply since we can't do the depth's Y tiling or the
1076 * stencil's W tiling in the blitter.
1078 if (src_mt
->stencil_mt
) {
1079 intel_miptree_copy_slice_sw(brw
,
1086 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1087 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1088 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1090 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1091 _mesa_get_format_name(src_mt
->format
),
1092 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1093 _mesa_get_format_name(dst_mt
->format
),
1094 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1097 if (!intel_miptree_blit(brw
,
1098 src_mt
, level
, slice
, 0, 0, false,
1099 dst_mt
, level
, slice
, 0, 0, false,
1100 width
, height
, GL_COPY
)) {
1101 perf_debug("miptree validate blit for %s failed\n",
1102 _mesa_get_format_name(format
));
1104 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1110 * Copies the image's current data to the given miptree, and associates that
1111 * miptree with the image.
1113 * If \c invalidate is true, then the actual image data does not need to be
1114 * copied, but the image still needs to be associated to the new miptree (this
1115 * is set to true if we're about to clear the image).
1118 intel_miptree_copy_teximage(struct brw_context
*brw
,
1119 struct intel_texture_image
*intelImage
,
1120 struct intel_mipmap_tree
*dst_mt
,
1123 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1124 struct intel_texture_object
*intel_obj
=
1125 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1126 int level
= intelImage
->base
.Base
.Level
;
1127 int face
= intelImage
->base
.Base
.Face
;
1128 GLuint depth
= intelImage
->base
.Base
.Depth
;
1131 for (int slice
= 0; slice
< depth
; slice
++) {
1132 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1136 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1137 intel_obj
->needs_validate
= true;
1141 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1142 struct intel_mipmap_tree
*mt
,
1145 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1146 assert(mt
->mcs_mt
== NULL
);
1148 /* Choose the correct format for the MCS buffer. All that really matters
1149 * is that we allocate the right buffer size, since we'll always be
1150 * accessing this miptree using MCS-specific hardware mechanisms, which
1151 * infer the correct format based on num_samples.
1154 switch (num_samples
) {
1156 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1159 format
= MESA_FORMAT_R_UNORM8
;
1162 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1163 * for each sample, plus 8 padding bits).
1165 format
= MESA_FORMAT_R_UINT32
;
1168 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1172 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1174 * "The MCS surface must be stored as Tile Y."
1176 mt
->mcs_mt
= intel_miptree_create(brw
,
1182 mt
->logical_height0
,
1185 0 /* num_samples */,
1186 INTEL_MIPTREE_TILING_Y
);
1188 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1190 * When MCS buffer is enabled and bound to MSRT, it is required that it
1191 * is cleared prior to any rendering.
1193 * Since we don't use the MCS buffer for any purpose other than rendering,
1194 * it makes sense to just clear it immediately upon allocation.
1196 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1198 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1199 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1200 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1201 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1208 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1209 struct intel_mipmap_tree
*mt
)
1211 assert(mt
->mcs_mt
== NULL
);
1213 /* The format of the MCS buffer is opaque to the driver; all that matters
1214 * is that we get its size and pitch right. We'll pretend that the format
1215 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1216 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1217 * the block width and then a further factor of 4. Since an MCS tile
1218 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1219 * we'll need to scale the height down by the block height and then a
1220 * further factor of 8.
1222 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1223 unsigned block_width_px
;
1224 unsigned block_height
;
1225 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1226 unsigned width_divisor
= block_width_px
* 4;
1227 unsigned height_divisor
= block_height
* 8;
1228 unsigned mcs_width
=
1229 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1230 unsigned mcs_height
=
1231 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1232 assert(mt
->logical_depth0
== 1);
1233 mt
->mcs_mt
= intel_miptree_create(brw
,
1242 0 /* num_samples */,
1243 INTEL_MIPTREE_TILING_Y
);
1250 * Helper for intel_miptree_alloc_hiz() that sets
1251 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1252 * \c has_hiz was set.
1255 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1256 struct intel_mipmap_tree
*mt
,
1262 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1263 uint32_t width
= minify(mt
->physical_width0
, level
);
1264 uint32_t height
= minify(mt
->physical_height0
, level
);
1266 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1267 * and the height is 4 aligned. This allows our HiZ support
1268 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1269 * we can grow the width & height to allow the HiZ op to
1270 * force the proper size alignments.
1272 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1277 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1284 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1285 struct intel_mipmap_tree
*mt
)
1287 assert(mt
->hiz_mt
== NULL
);
1288 mt
->hiz_mt
= intel_miptree_create(brw
,
1294 mt
->logical_height0
,
1298 INTEL_MIPTREE_TILING_ANY
);
1303 /* Mark that all slices need a HiZ resolve. */
1304 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1305 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1306 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1307 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1310 head
->next
= malloc(sizeof(*head
->next
));
1311 head
->next
->prev
= head
;
1312 head
->next
->next
= NULL
;
1315 head
->level
= level
;
1316 head
->layer
= layer
;
1317 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1325 * Does the miptree slice have hiz enabled?
1328 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1332 intel_miptree_check_level_layer(mt
, level
, layer
);
1333 return mt
->level
[level
].slice
[layer
].has_hiz
;
1337 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1341 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1344 intel_resolve_map_set(&mt
->hiz_map
,
1345 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1350 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1354 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1357 intel_resolve_map_set(&mt
->hiz_map
,
1358 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1362 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1366 uint32_t end_layer
= mt
->level
[level
].depth
;
1368 for (layer
= 0; layer
< end_layer
; layer
++) {
1369 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1374 intel_miptree_slice_resolve(struct brw_context
*brw
,
1375 struct intel_mipmap_tree
*mt
,
1378 enum gen6_hiz_op need
)
1380 intel_miptree_check_level_layer(mt
, level
, layer
);
1382 struct intel_resolve_map
*item
=
1383 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1385 if (!item
|| item
->need
!= need
)
1388 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1389 intel_resolve_map_remove(item
);
1394 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1395 struct intel_mipmap_tree
*mt
,
1399 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1400 GEN6_HIZ_OP_HIZ_RESOLVE
);
1404 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1405 struct intel_mipmap_tree
*mt
,
1409 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1410 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1414 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1415 struct intel_mipmap_tree
*mt
,
1416 enum gen6_hiz_op need
)
1418 bool did_resolve
= false;
1419 struct intel_resolve_map
*i
, *next
;
1421 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1423 if (i
->need
!= need
)
1426 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1427 intel_resolve_map_remove(i
);
1435 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1436 struct intel_mipmap_tree
*mt
)
1438 return intel_miptree_all_slices_resolve(brw
, mt
,
1439 GEN6_HIZ_OP_HIZ_RESOLVE
);
1443 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1444 struct intel_mipmap_tree
*mt
)
1446 return intel_miptree_all_slices_resolve(brw
, mt
,
1447 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1452 intel_miptree_resolve_color(struct brw_context
*brw
,
1453 struct intel_mipmap_tree
*mt
)
1455 switch (mt
->fast_clear_state
) {
1456 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1457 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1458 /* No resolve needed */
1460 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1461 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1462 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1463 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1464 brw_blorp_resolve_color(brw
, mt
);
1471 * Make it possible to share the region backing the given miptree with another
1472 * process or another miptree.
1474 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1475 * then discard the MCS buffer, if present. We also set the fast_clear_state
1476 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1477 * allocated in the future.
1480 intel_miptree_make_shareable(struct brw_context
*brw
,
1481 struct intel_mipmap_tree
*mt
)
1483 /* MCS buffers are also used for multisample buffers, but we can't resolve
1484 * away a multisample MCS buffer because it's an integral part of how the
1485 * pixel data is stored. Fortunately this code path should never be
1486 * reached for multisample buffers.
1488 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1491 intel_miptree_resolve_color(brw
, mt
);
1492 intel_miptree_release(&mt
->mcs_mt
);
1493 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1499 * \brief Get pointer offset into stencil buffer.
1501 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1502 * must decode the tile's layout in software.
1505 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1507 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1509 * Even though the returned offset is always positive, the return type is
1511 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1512 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1515 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1517 uint32_t tile_size
= 4096;
1518 uint32_t tile_width
= 64;
1519 uint32_t tile_height
= 64;
1520 uint32_t row_size
= 64 * stride
;
1522 uint32_t tile_x
= x
/ tile_width
;
1523 uint32_t tile_y
= y
/ tile_height
;
1525 /* The byte's address relative to the tile's base addres. */
1526 uint32_t byte_x
= x
% tile_width
;
1527 uint32_t byte_y
= y
% tile_height
;
1529 uintptr_t u
= tile_y
* row_size
1530 + tile_x
* tile_size
1531 + 512 * (byte_x
/ 8)
1533 + 32 * ((byte_y
/ 4) % 2)
1534 + 16 * ((byte_x
/ 4) % 2)
1535 + 8 * ((byte_y
/ 2) % 2)
1536 + 4 * ((byte_x
/ 2) % 2)
1541 /* adjust for bit6 swizzling */
1542 if (((byte_x
/ 8) % 2) == 1) {
1543 if (((byte_y
/ 8) % 2) == 0) {
1555 intel_miptree_updownsample(struct brw_context
*brw
,
1556 struct intel_mipmap_tree
*src
,
1557 struct intel_mipmap_tree
*dst
)
1559 if (brw
->gen
< 8 || src
->format
== MESA_FORMAT_S_UINT8
) {
1560 brw_blorp_blit_miptrees(brw
,
1561 src
, 0 /* level */, 0 /* layer */,
1562 dst
, 0 /* level */, 0 /* layer */,
1564 src
->logical_width0
, src
->logical_height0
,
1566 dst
->logical_width0
, dst
->logical_height0
,
1567 GL_NEAREST
, false, false /*mirror x, y*/);
1569 brw_meta_updownsample(brw
, src
, dst
);
1572 if (src
->stencil_mt
) {
1573 brw_blorp_blit_miptrees(brw
,
1574 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1575 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1577 src
->logical_width0
, src
->logical_height0
,
1579 dst
->logical_width0
, dst
->logical_height0
,
1580 GL_NEAREST
, false, false /*mirror x, y*/);
1585 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1587 /* CPU accesses to color buffers don't understand fast color clears, so
1588 * resolve any pending fast color clears before we map.
1590 intel_miptree_resolve_color(brw
, mt
);
1592 drm_intel_bo
*bo
= mt
->region
->bo
;
1594 intel_batchbuffer_flush(brw
);
1596 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1597 brw_bo_map_gtt(brw
, bo
, "miptree");
1599 brw_bo_map(brw
, bo
, true, "miptree");
1605 intel_miptree_unmap_raw(struct brw_context
*brw
,
1606 struct intel_mipmap_tree
*mt
)
1608 drm_intel_bo_unmap(mt
->region
->bo
);
1612 intel_miptree_map_gtt(struct brw_context
*brw
,
1613 struct intel_mipmap_tree
*mt
,
1614 struct intel_miptree_map
*map
,
1615 unsigned int level
, unsigned int slice
)
1617 unsigned int bw
, bh
;
1619 unsigned int image_x
, image_y
;
1623 /* For compressed formats, the stride is the number of bytes per
1624 * row of blocks. intel_miptree_get_image_offset() already does
1627 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1628 assert(y
% bh
== 0);
1631 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1636 /* Note that in the case of cube maps, the caller must have passed the
1637 * slice number referencing the face.
1639 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1643 map
->stride
= mt
->region
->pitch
;
1644 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1647 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1648 map
->x
, map
->y
, map
->w
, map
->h
,
1649 mt
, _mesa_get_format_name(mt
->format
),
1650 x
, y
, map
->ptr
, map
->stride
);
1654 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1655 struct intel_mipmap_tree
*mt
,
1656 struct intel_miptree_map
*map
,
1660 intel_miptree_unmap_raw(brw
, mt
);
1664 intel_miptree_map_blit(struct brw_context
*brw
,
1665 struct intel_mipmap_tree
*mt
,
1666 struct intel_miptree_map
*map
,
1667 unsigned int level
, unsigned int slice
)
1669 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1673 INTEL_MIPTREE_TILING_NONE
);
1675 fprintf(stderr
, "Failed to allocate blit temporary\n");
1678 map
->stride
= map
->mt
->region
->pitch
;
1680 if (!intel_miptree_blit(brw
,
1682 map
->x
, map
->y
, false,
1685 map
->w
, map
->h
, GL_COPY
)) {
1686 fprintf(stderr
, "Failed to blit\n");
1690 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1692 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1693 map
->x
, map
->y
, map
->w
, map
->h
,
1694 mt
, _mesa_get_format_name(mt
->format
),
1695 level
, slice
, map
->ptr
, map
->stride
);
1700 intel_miptree_release(&map
->mt
);
1706 intel_miptree_unmap_blit(struct brw_context
*brw
,
1707 struct intel_mipmap_tree
*mt
,
1708 struct intel_miptree_map
*map
,
1712 struct gl_context
*ctx
= &brw
->ctx
;
1714 intel_miptree_unmap_raw(brw
, map
->mt
);
1716 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1717 bool ok
= intel_miptree_blit(brw
,
1721 map
->x
, map
->y
, false,
1722 map
->w
, map
->h
, GL_COPY
);
1723 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1726 intel_miptree_release(&map
->mt
);
1731 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1734 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1735 struct intel_mipmap_tree
*mt
,
1736 struct intel_miptree_map
*map
,
1737 unsigned int level
, unsigned int slice
)
1739 assert(map
->mode
& GL_MAP_READ_BIT
);
1740 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1742 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1743 map
->x
, map
->y
, map
->w
, map
->h
,
1744 mt
, _mesa_get_format_name(mt
->format
),
1745 level
, slice
, map
->ptr
, map
->stride
);
1747 /* Map the original image */
1750 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1754 void *src
= intel_miptree_map_raw(brw
, mt
);
1757 src
+= image_y
* mt
->region
->pitch
;
1758 src
+= image_x
* mt
->region
->cpp
;
1760 /* Due to the pixel offsets for the particular image being mapped, our
1761 * src pointer may not be 16-byte aligned. However, if the pitch is
1762 * divisible by 16, then the amount by which it's misaligned will remain
1763 * consistent from row to row.
1765 assert((mt
->region
->pitch
% 16) == 0);
1766 const int misalignment
= ((uintptr_t) src
) & 15;
1768 /* Create an untiled temporary buffer for the mapping. */
1769 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1771 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1773 map
->buffer
= malloc(map
->stride
* map
->h
);
1774 /* Offset the destination so it has the same misalignment as src. */
1775 map
->ptr
= map
->buffer
+ misalignment
;
1777 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1779 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1780 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1781 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1783 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1786 intel_miptree_unmap_raw(brw
, mt
);
1790 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1791 struct intel_mipmap_tree
*mt
,
1792 struct intel_miptree_map
*map
,
1803 intel_miptree_map_s8(struct brw_context
*brw
,
1804 struct intel_mipmap_tree
*mt
,
1805 struct intel_miptree_map
*map
,
1806 unsigned int level
, unsigned int slice
)
1808 map
->stride
= map
->w
;
1809 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1813 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1814 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1815 * invalidate is set, since we'll be writing the whole rectangle from our
1816 * temporary buffer back out.
1818 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1819 uint8_t *untiled_s8_map
= map
->ptr
;
1820 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1821 unsigned int image_x
, image_y
;
1823 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1825 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1826 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1827 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1828 x
+ image_x
+ map
->x
,
1829 y
+ image_y
+ map
->y
,
1830 brw
->has_swizzling
);
1831 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1835 intel_miptree_unmap_raw(brw
, mt
);
1837 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1838 map
->x
, map
->y
, map
->w
, map
->h
,
1839 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1841 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1842 map
->x
, map
->y
, map
->w
, map
->h
,
1843 mt
, map
->ptr
, map
->stride
);
1848 intel_miptree_unmap_s8(struct brw_context
*brw
,
1849 struct intel_mipmap_tree
*mt
,
1850 struct intel_miptree_map
*map
,
1854 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1855 unsigned int image_x
, image_y
;
1856 uint8_t *untiled_s8_map
= map
->ptr
;
1857 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1859 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1861 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1862 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1863 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1866 brw
->has_swizzling
);
1867 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1871 intel_miptree_unmap_raw(brw
, mt
);
1878 intel_miptree_map_etc(struct brw_context
*brw
,
1879 struct intel_mipmap_tree
*mt
,
1880 struct intel_miptree_map
*map
,
1884 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1885 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1886 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1889 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1890 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1892 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1893 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1894 map
->w
, map
->h
, 1));
1895 map
->ptr
= map
->buffer
;
1899 intel_miptree_unmap_etc(struct brw_context
*brw
,
1900 struct intel_mipmap_tree
*mt
,
1901 struct intel_miptree_map
*map
,
1907 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1912 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
1913 + image_y
* mt
->region
->pitch
1914 + image_x
* mt
->region
->cpp
;
1916 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1917 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1918 map
->ptr
, map
->stride
,
1921 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1922 map
->ptr
, map
->stride
,
1923 map
->w
, map
->h
, mt
->etc_format
);
1925 intel_miptree_unmap_raw(brw
, mt
);
1930 * Mapping function for packed depth/stencil miptrees backed by real separate
1931 * miptrees for depth and stencil.
1933 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1934 * separate from the depth buffer. Yet at the GL API level, we have to expose
1935 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1936 * be able to map that memory for texture storage and glReadPixels-type
1937 * operations. We give Mesa core that access by mallocing a temporary and
1938 * copying the data between the actual backing store and the temporary.
1941 intel_miptree_map_depthstencil(struct brw_context
*brw
,
1942 struct intel_mipmap_tree
*mt
,
1943 struct intel_miptree_map
*map
,
1944 unsigned int level
, unsigned int slice
)
1946 struct intel_mipmap_tree
*z_mt
= mt
;
1947 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1948 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
1949 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1951 map
->stride
= map
->w
* packed_bpp
;
1952 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1956 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1957 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1958 * invalidate is set, since we'll be writing the whole rectangle from our
1959 * temporary buffer back out.
1961 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1962 uint32_t *packed_map
= map
->ptr
;
1963 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1964 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
1965 unsigned int s_image_x
, s_image_y
;
1966 unsigned int z_image_x
, z_image_y
;
1968 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1969 &s_image_x
, &s_image_y
);
1970 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1971 &z_image_x
, &z_image_y
);
1973 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1974 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1975 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1976 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1979 brw
->has_swizzling
);
1980 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1981 (z_mt
->region
->pitch
/ 4) +
1982 (map_x
+ z_image_x
));
1983 uint8_t s
= s_map
[s_offset
];
1984 uint32_t z
= z_map
[z_offset
];
1986 if (map_z32f_x24s8
) {
1987 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1988 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1990 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1995 intel_miptree_unmap_raw(brw
, s_mt
);
1996 intel_miptree_unmap_raw(brw
, z_mt
);
1998 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2000 map
->x
, map
->y
, map
->w
, map
->h
,
2001 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2002 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2003 map
->ptr
, map
->stride
);
2005 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2006 map
->x
, map
->y
, map
->w
, map
->h
,
2007 mt
, map
->ptr
, map
->stride
);
2012 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2013 struct intel_mipmap_tree
*mt
,
2014 struct intel_miptree_map
*map
,
2018 struct intel_mipmap_tree
*z_mt
= mt
;
2019 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2020 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2022 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2023 uint32_t *packed_map
= map
->ptr
;
2024 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2025 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2026 unsigned int s_image_x
, s_image_y
;
2027 unsigned int z_image_x
, z_image_y
;
2029 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2030 &s_image_x
, &s_image_y
);
2031 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2032 &z_image_x
, &z_image_y
);
2034 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2035 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2036 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2037 x
+ s_image_x
+ map
->x
,
2038 y
+ s_image_y
+ map
->y
,
2039 brw
->has_swizzling
);
2040 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2041 (z_mt
->region
->pitch
/ 4) +
2044 if (map_z32f_x24s8
) {
2045 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2046 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2048 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2049 s_map
[s_offset
] = packed
>> 24;
2050 z_map
[z_offset
] = packed
;
2055 intel_miptree_unmap_raw(brw
, s_mt
);
2056 intel_miptree_unmap_raw(brw
, z_mt
);
2058 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2060 map
->x
, map
->y
, map
->w
, map
->h
,
2061 z_mt
, _mesa_get_format_name(z_mt
->format
),
2062 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2063 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2064 map
->ptr
, map
->stride
);
2071 * Create and attach a map to the miptree at (level, slice). Return the
2074 static struct intel_miptree_map
*
2075 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2084 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2089 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2090 mt
->level
[level
].slice
[slice
].map
= map
;
2102 * Release the map at (level, slice).
2105 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2109 struct intel_miptree_map
**map
;
2111 map
= &mt
->level
[level
].slice
[slice
].map
;
2117 can_blit_slice(struct intel_mipmap_tree
*mt
,
2118 unsigned int level
, unsigned int slice
)
2122 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2123 if (image_x
>= 32768 || image_y
>= 32768)
2126 if (mt
->region
->pitch
>= 32768)
2133 intel_miptree_map(struct brw_context
*brw
,
2134 struct intel_mipmap_tree
*mt
,
2145 struct intel_miptree_map
*map
;
2147 assert(mt
->num_samples
<= 1);
2149 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2156 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2157 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2158 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2161 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2162 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2163 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2164 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2165 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2166 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2167 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2169 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2170 else if (brw
->has_llc
&&
2171 !(mode
& GL_MAP_WRITE_BIT
) &&
2173 (mt
->region
->tiling
== I915_TILING_X
||
2174 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2175 can_blit_slice(mt
, level
, slice
)) {
2176 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2177 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2178 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2179 assert(can_blit_slice(mt
, level
, slice
));
2180 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2182 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2183 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2186 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2189 *out_ptr
= map
->ptr
;
2190 *out_stride
= map
->stride
;
2192 if (map
->ptr
== NULL
)
2193 intel_miptree_release_map(mt
, level
, slice
);
2197 intel_miptree_unmap(struct brw_context
*brw
,
2198 struct intel_mipmap_tree
*mt
,
2202 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2204 assert(mt
->num_samples
<= 1);
2209 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2210 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2212 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2213 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2214 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2215 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2216 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2217 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2218 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2219 } else if (map
->mt
) {
2220 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2222 } else if (map
->buffer
) {
2223 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2226 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2229 intel_miptree_release_map(mt
, level
, slice
);