2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 intel_miptree_alloc_mcs(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
56 * Determine which MSAA layout should be used by the MSAA surface being
57 * created, based on the chip generation and the surface type.
59 static enum intel_msaa_layout
60 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
,
61 bool disable_aux_buffers
)
63 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
65 return INTEL_MSAA_LAYOUT_IMS
;
67 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
68 switch (_mesa_get_format_base_format(format
)) {
69 case GL_DEPTH_COMPONENT
:
70 case GL_STENCIL_INDEX
:
71 case GL_DEPTH_STENCIL
:
72 return INTEL_MSAA_LAYOUT_IMS
;
74 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
76 * This field must be set to 0 for all SINT MSRTs when all RT channels
79 * In practice this means that we have to disable MCS for all signed
80 * integer MSAA buffers. The alternative, to disable MCS only when one
81 * of the render target channels is disabled, is impractical because it
82 * would require converting between CMS and UMS MSAA layouts on the fly,
85 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
86 return INTEL_MSAA_LAYOUT_UMS
;
87 } else if (disable_aux_buffers
) {
88 /* We can't use the CMS layout because it uses an aux buffer, the MCS
89 * buffer. So fallback to UMS, which is identical to CMS without the
91 return INTEL_MSAA_LAYOUT_UMS
;
93 return INTEL_MSAA_LAYOUT_CMS
;
100 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
101 * scaled-down bitfield representation of the color buffer which is capable of
102 * recording when blocks of the color buffer are equal to the clear value.
103 * This function returns the block size that will be used by the MCS buffer
104 * corresponding to a certain color miptree.
106 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
107 * beneath the "Fast Color Clear" bullet (p327):
109 * The following table describes the RT alignment
123 * This alignment has the following uses:
125 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
126 * buffer contains 128 blocks horizontally and 256 blocks vertically.
128 * - For figuring out alignment restrictions for a fast clear operation. Fast
129 * clear operations must always clear aligned multiples of 16 blocks
130 * horizontally and 32 blocks vertically.
132 * - For scaling down the coordinates sent through the render pipeline during
133 * a fast clear. X coordinates must be scaled down by 8 times the block
134 * width, and Y coordinates by 16 times the block height.
136 * - For scaling down the coordinates sent through the render pipeline during
137 * a "Render Target Resolve" operation. X coordinates must be scaled down
138 * by half the block width, and Y coordinates by half the block height.
141 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
142 struct intel_mipmap_tree
*mt
,
143 unsigned *width_px
, unsigned *height
)
145 switch (mt
->tiling
) {
147 unreachable("Non-MSRT MCS requires X or Y tiling");
148 /* In release builds, fall through */
150 *width_px
= 32 / mt
->cpp
;
154 *width_px
= 64 / mt
->cpp
;
160 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
162 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
163 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
165 * - Support is limited to tiled render targets.
167 * Gen9 changes the restriction to Y-tile only.
170 return tiling
== I915_TILING_Y
;
171 else if (brw
->gen
>= 7)
172 return tiling
!= I915_TILING_NONE
;
178 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
179 * can be used. This doesn't (and should not) inspect any of the properties of
182 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
183 * beneath the "Fast Color Clear" bullet (p326):
185 * - Support is for non-mip-mapped and non-array surface types only.
187 * And then later, on p327:
189 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
193 intel_miptree_is_fast_clear_capable(struct brw_context
*brw
,
194 struct intel_mipmap_tree
*mt
)
196 /* MCS support does not exist prior to Gen7 */
200 if (mt
->disable_aux_buffers
)
203 /* MCS is only supported for color buffers */
204 switch (_mesa_get_format_base_format(mt
->format
)) {
205 case GL_DEPTH_COMPONENT
:
206 case GL_DEPTH_STENCIL
:
207 case GL_STENCIL_INDEX
:
211 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
213 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
215 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
216 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
221 if (mt
->physical_depth0
!= 1) {
223 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
224 mt
->logical_width0
, mt
->logical_height0
,
225 mt
->physical_depth0
);
231 /* There's no point in using an MCS buffer if the surface isn't in a
234 if (!brw
->format_supported_as_render_target
[mt
->format
])
242 * Determine depth format corresponding to a depth+stencil format,
243 * for separate stencil.
246 intel_depth_format_for_depthstencil_format(mesa_format format
) {
248 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
249 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
250 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
251 return MESA_FORMAT_Z_FLOAT32
;
259 * @param for_bo Indicates that the caller is
260 * intel_miptree_create_for_bo(). If true, then do not create
263 static struct intel_mipmap_tree
*
264 intel_miptree_create_layout(struct brw_context
*brw
,
273 uint32_t layout_flags
)
275 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
279 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
280 _mesa_enum_to_string(target
),
281 _mesa_get_format_name(format
),
282 first_level
, last_level
, depth0
, mt
);
284 if (target
== GL_TEXTURE_1D_ARRAY
) {
285 /* For a 1D Array texture the OpenGL API will treat the height0
286 * parameter as the number of array slices. For Intel hardware, we treat
287 * the 1D array as a 2D Array with a height of 1.
289 * So, when we first come through this path to create a 1D Array
290 * texture, height0 stores the number of slices, and depth0 is 1. In
291 * this case, we want to swap height0 and depth0.
293 * Since some miptrees will be created based on the base miptree, we may
294 * come through this path and see height0 as 1 and depth0 being the
295 * number of slices. In this case we don't need to do the swap.
297 assert(height0
== 1 || depth0
== 1);
306 mt
->first_level
= first_level
;
307 mt
->last_level
= last_level
;
308 mt
->logical_width0
= width0
;
309 mt
->logical_height0
= height0
;
310 mt
->logical_depth0
= depth0
;
311 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
312 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
313 exec_list_make_empty(&mt
->hiz_map
);
314 mt
->cpp
= _mesa_get_format_bytes(format
);
315 mt
->num_samples
= num_samples
;
316 mt
->compressed
= _mesa_is_format_compressed(format
);
317 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
320 if (num_samples
> 1) {
321 /* Adjust width/height/depth for MSAA */
322 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
323 mt
->target
, mt
->disable_aux_buffers
);
324 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
325 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
326 * "If the surface is multisampled and it is a depth or stencil
327 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
328 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
331 * +----------------------------------------------------------------+
332 * | Num Multisamples | W_l = | H_l = |
333 * +----------------------------------------------------------------+
334 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
335 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
336 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
337 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
338 * +----------------------------------------------------------------+
341 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
342 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
343 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
345 * Another more complicated explanation for these adjustments comes
346 * from the Sandybridge PRM, volume 4, part 1, page 31:
348 * "Any of the other messages (sample*, LOD, load4) used with a
349 * (4x) multisampled surface will in-effect sample a surface with
350 * double the height and width as that indicated in the surface
351 * state. Each pixel position on the original-sized surface is
352 * replaced with a 2x2 of samples with the following arrangement:
357 * Thus, when sampling from a multisampled texture, it behaves as
358 * though the layout in memory for (x,y,sample) is:
360 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
361 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
363 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
364 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
366 * However, the actual layout of multisampled data in memory is:
368 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
369 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
371 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
372 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
374 * This pattern repeats for each 2x2 pixel block.
376 * As a result, when calculating the size of our 4-sample buffer for
377 * an odd width or height, we have to align before scaling up because
378 * sample 3 is in that bottom right 2x2 block.
380 switch (num_samples
) {
382 assert(brw
->gen
>= 8);
383 width0
= ALIGN(width0
, 2) * 2;
384 height0
= ALIGN(height0
, 2);
387 width0
= ALIGN(width0
, 2) * 2;
388 height0
= ALIGN(height0
, 2) * 2;
391 width0
= ALIGN(width0
, 2) * 4;
392 height0
= ALIGN(height0
, 2) * 2;
395 /* num_samples should already have been quantized to 0, 1, 2, 4, or
398 unreachable("not reached");
401 /* Non-interleaved */
402 depth0
*= num_samples
;
406 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
407 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
408 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
409 * used on Gen8 to make it pick a qpitch value which doesn't include space
410 * for the mipmaps. On Gen9 this is not necessary because it will
411 * automatically pick a packed qpitch value whenever mt->first_level ==
413 * TODO: can we use it elsewhere?
414 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
417 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
419 switch (mt
->msaa_layout
) {
420 case INTEL_MSAA_LAYOUT_NONE
:
421 case INTEL_MSAA_LAYOUT_IMS
:
422 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
424 case INTEL_MSAA_LAYOUT_UMS
:
425 case INTEL_MSAA_LAYOUT_CMS
:
426 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
431 if (target
== GL_TEXTURE_CUBE_MAP
) {
436 mt
->physical_width0
= width0
;
437 mt
->physical_height0
= height0
;
438 mt
->physical_depth0
= depth0
;
440 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
441 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
442 (brw
->must_use_separate_stencil
||
443 (brw
->has_separate_stencil
&&
444 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
445 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
447 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
448 MIPTREE_LAYOUT_TILING_ANY
;
451 mt
->stencil_mt
= intel_miptree_create(brw
,
462 if (!mt
->stencil_mt
) {
463 intel_miptree_release(&mt
);
467 /* Fix up the Z miptree format for how we're splitting out separate
468 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
470 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
473 if (format
== mt
->format
) {
474 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
475 _mesa_get_format_name(mt
->format
));
479 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
480 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
483 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
484 * multisampled or have an AUX buffer attached to it.
486 * GEN | MSRT | AUX_CCS_* or AUX_MCS
487 * -------------------------------------------
488 * 9 | HALIGN_16 | HALIGN_16
489 * 8 | HALIGN_ANY | HALIGN_16
493 if (intel_miptree_is_fast_clear_capable(brw
, mt
)) {
494 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
495 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
496 } else if (brw
->gen
>= 9 && num_samples
> 1) {
497 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
499 /* For now, nothing else has this requirement */
500 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
503 brw_miptree_layout(brw
, mt
, layout_flags
);
505 if (mt
->disable_aux_buffers
)
506 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
513 * Choose an appropriate uncompressed format for a requested
514 * compressed format, if unsupported.
517 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
519 /* No need to lower ETC formats on these platforms,
520 * they are supported natively.
522 if (brw
->gen
>= 8 || brw
->is_baytrail
)
526 case MESA_FORMAT_ETC1_RGB8
:
527 return MESA_FORMAT_R8G8B8X8_UNORM
;
528 case MESA_FORMAT_ETC2_RGB8
:
529 return MESA_FORMAT_R8G8B8X8_UNORM
;
530 case MESA_FORMAT_ETC2_SRGB8
:
531 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
532 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
533 return MESA_FORMAT_B8G8R8A8_SRGB
;
534 case MESA_FORMAT_ETC2_RGBA8_EAC
:
535 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
536 return MESA_FORMAT_R8G8B8A8_UNORM
;
537 case MESA_FORMAT_ETC2_R11_EAC
:
538 return MESA_FORMAT_R_UNORM16
;
539 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
540 return MESA_FORMAT_R_SNORM16
;
541 case MESA_FORMAT_ETC2_RG11_EAC
:
542 return MESA_FORMAT_R16G16_UNORM
;
543 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
544 return MESA_FORMAT_R16G16_SNORM
;
546 /* Non ETC1 / ETC2 format */
551 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
553 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
554 unsigned long *pitch
)
556 const uint32_t bpp
= mt
->cpp
* 8;
557 const uint32_t aspect_ratio
= (bpp
== 16 || bpp
== 64) ? 2 : 1;
558 uint32_t tile_width
, tile_height
;
559 unsigned long stride
, size
, aligned_y
;
561 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
576 unreachable("not reached");
579 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
582 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
583 stride
= mt
->total_width
* mt
->cpp
;
584 tile_width
= tile_height
* mt
->cpp
* aspect_ratio
;
585 stride
= ALIGN(stride
, tile_width
);
586 size
= stride
* aligned_y
;
588 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
589 assert(size
% 4096 == 0);
592 assert(size
% (64 * 1024) == 0);
593 *alignment
= 64 * 1024;
599 struct intel_mipmap_tree
*
600 intel_miptree_create(struct brw_context
*brw
,
609 uint32_t layout_flags
)
611 struct intel_mipmap_tree
*mt
;
612 mesa_format tex_format
= format
;
613 mesa_format etc_format
= MESA_FORMAT_NONE
;
614 GLuint total_width
, total_height
;
615 uint32_t alloc_flags
= 0;
617 format
= intel_lower_compressed_format(brw
, format
);
619 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
621 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
622 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
623 mt
= intel_miptree_create_layout(brw
, target
, format
,
624 first_level
, last_level
, width0
,
625 height0
, depth0
, num_samples
,
628 * pitch == 0 || height == 0 indicates the null texture
630 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
631 intel_miptree_release(&mt
);
635 total_width
= mt
->total_width
;
636 total_height
= mt
->total_height
;
638 if (format
== MESA_FORMAT_S_UINT8
) {
639 /* Align to size of W tile, 64x64. */
640 total_width
= ALIGN(total_width
, 64);
641 total_height
= ALIGN(total_height
, 64);
646 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
648 mt
->tiling
= I915_TILING_Y
;
651 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
652 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
655 mt
->etc_format
= etc_format
;
657 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
658 unsigned alignment
= 0;
660 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
662 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
665 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
666 total_width
, total_height
, mt
->cpp
,
673 /* If the BO is too large to fit in the aperture, we need to use the
674 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
675 * handle Y-tiling, so we need to fall back to X.
677 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
678 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
679 mt
->total_width
, mt
->total_height
);
681 mt
->tiling
= I915_TILING_X
;
682 drm_intel_bo_unreference(mt
->bo
);
683 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
684 total_width
, total_height
, mt
->cpp
,
685 &mt
->tiling
, &pitch
, alloc_flags
);
692 intel_miptree_release(&mt
);
697 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
698 assert(mt
->num_samples
> 1);
699 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
700 intel_miptree_release(&mt
);
705 /* If this miptree is capable of supporting fast color clears, set
706 * fast_clear_state appropriately to ensure that fast clears will occur.
707 * Allocation of the MCS miptree will be deferred until the first fast
708 * clear actually occurs.
710 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
711 intel_miptree_is_fast_clear_capable(brw
, mt
)) {
712 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
713 assert(brw
->gen
< 8 || mt
->align_w
== 16 || num_samples
<= 1);
719 struct intel_mipmap_tree
*
720 intel_miptree_create_for_bo(struct brw_context
*brw
,
728 uint32_t layout_flags
)
730 struct intel_mipmap_tree
*mt
;
731 uint32_t tiling
, swizzle
;
734 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
736 /* Nothing will be able to use this miptree with the BO if the offset isn't
739 if (tiling
!= I915_TILING_NONE
)
740 assert(offset
% 4096 == 0);
742 /* miptrees can't handle negative pitch. If you need flipping of images,
743 * that's outside of the scope of the mt.
747 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
749 /* The BO already has a tiling format and we shouldn't confuse the lower
750 * layers by making it try to find a tiling format again.
752 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
753 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
755 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
756 mt
= intel_miptree_create_layout(brw
, target
, format
,
758 width
, height
, depth
, 0,
763 drm_intel_bo_reference(bo
);
773 * For a singlesample renderbuffer, this simply wraps the given BO with a
776 * For a multisample renderbuffer, this wraps the window system's
777 * (singlesample) BO with a singlesample miptree attached to the
778 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
779 * that will contain the actual rendering (which is lazily resolved to
780 * irb->singlesample_mt).
783 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
784 struct intel_renderbuffer
*irb
,
786 uint32_t width
, uint32_t height
,
789 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
790 struct intel_mipmap_tree
*multisample_mt
= NULL
;
791 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
792 mesa_format format
= rb
->Format
;
793 int num_samples
= rb
->NumSamples
;
795 /* Only the front and back buffers, which are color buffers, are allocated
796 * through the image loader.
798 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
799 _mesa_get_format_base_format(format
) == GL_RGBA
);
801 singlesample_mt
= intel_miptree_create_for_bo(intel
,
810 if (!singlesample_mt
)
813 /* If this miptree is capable of supporting fast color clears, set
814 * mcs_state appropriately to ensure that fast clears will occur.
815 * Allocation of the MCS miptree will be deferred until the first fast
816 * clear actually occurs.
818 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
819 intel_miptree_is_fast_clear_capable(intel
, singlesample_mt
))
820 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
822 if (num_samples
== 0) {
823 intel_miptree_release(&irb
->mt
);
824 irb
->mt
= singlesample_mt
;
826 assert(!irb
->singlesample_mt
);
828 intel_miptree_release(&irb
->singlesample_mt
);
829 irb
->singlesample_mt
= singlesample_mt
;
832 irb
->mt
->logical_width0
!= width
||
833 irb
->mt
->logical_height0
!= height
) {
834 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
842 irb
->need_downsample
= false;
843 intel_miptree_release(&irb
->mt
);
844 irb
->mt
= multisample_mt
;
850 intel_miptree_release(&irb
->singlesample_mt
);
851 intel_miptree_release(&irb
->mt
);
855 struct intel_mipmap_tree
*
856 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
860 uint32_t num_samples
)
862 struct intel_mipmap_tree
*mt
;
865 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
866 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
867 MIPTREE_LAYOUT_TILING_ANY
;
870 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
871 width
, height
, depth
, num_samples
,
876 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
877 ok
= intel_miptree_alloc_hiz(brw
, mt
);
885 intel_miptree_release(&mt
);
890 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
891 struct intel_mipmap_tree
*src
)
896 intel_miptree_release(dst
);
900 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
908 intel_miptree_release(struct intel_mipmap_tree
**mt
)
913 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
914 if (--(*mt
)->refcount
<= 0) {
917 DBG("%s deleting %p\n", __func__
, *mt
);
919 drm_intel_bo_unreference((*mt
)->bo
);
920 intel_miptree_release(&(*mt
)->stencil_mt
);
921 if ((*mt
)->hiz_buf
) {
922 if ((*mt
)->hiz_buf
->mt
)
923 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
925 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
926 free((*mt
)->hiz_buf
);
928 intel_miptree_release(&(*mt
)->mcs_mt
);
929 intel_resolve_map_clear(&(*mt
)->hiz_map
);
931 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
932 free((*mt
)->level
[i
].slice
);
941 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
942 int *width
, int *height
, int *depth
)
944 switch (image
->TexObject
->Target
) {
945 case GL_TEXTURE_1D_ARRAY
:
946 *width
= image
->Width
;
948 *depth
= image
->Height
;
951 *width
= image
->Width
;
952 *height
= image
->Height
;
953 *depth
= image
->Depth
;
959 * Can the image be pulled into a unified mipmap tree? This mirrors
960 * the completeness test in a lot of ways.
962 * Not sure whether I want to pass gl_texture_image here.
965 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
966 struct gl_texture_image
*image
)
968 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
969 GLuint level
= intelImage
->base
.Base
.Level
;
970 int width
, height
, depth
;
972 /* glTexImage* choose the texture object based on the target passed in, and
973 * objects can't change targets over their lifetimes, so this should be
976 assert(image
->TexObject
->Target
== mt
->target
);
978 mesa_format mt_format
= mt
->format
;
979 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
980 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
981 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
982 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
983 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
984 mt_format
= mt
->etc_format
;
986 if (image
->TexFormat
!= mt_format
)
989 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
991 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
994 int level_depth
= mt
->level
[level
].depth
;
995 if (mt
->num_samples
> 1) {
996 switch (mt
->msaa_layout
) {
997 case INTEL_MSAA_LAYOUT_NONE
:
998 case INTEL_MSAA_LAYOUT_IMS
:
1000 case INTEL_MSAA_LAYOUT_UMS
:
1001 case INTEL_MSAA_LAYOUT_CMS
:
1002 level_depth
/= mt
->num_samples
;
1007 /* Test image dimensions against the base level image adjusted for
1008 * minification. This will also catch images not present in the
1009 * tree, changed targets, etc.
1011 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1012 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1013 depth
!= level_depth
) {
1017 if (image
->NumSamples
!= mt
->num_samples
)
1025 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1027 GLuint x
, GLuint y
, GLuint d
)
1029 mt
->level
[level
].depth
= d
;
1030 mt
->level
[level
].level_x
= x
;
1031 mt
->level
[level
].level_y
= y
;
1033 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1036 assert(mt
->level
[level
].slice
== NULL
);
1038 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1039 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1040 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1045 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1046 GLuint level
, GLuint img
,
1049 if (img
== 0 && level
== 0)
1050 assert(x
== 0 && y
== 0);
1052 assert(img
< mt
->level
[level
].depth
);
1054 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1055 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1057 DBG("%s level %d img %d pos %d,%d\n",
1058 __func__
, level
, img
,
1059 mt
->level
[level
].slice
[img
].x_offset
,
1060 mt
->level
[level
].slice
[img
].y_offset
);
1064 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1065 GLuint level
, GLuint slice
,
1066 GLuint
*x
, GLuint
*y
)
1068 assert(slice
< mt
->level
[level
].depth
);
1070 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1071 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1075 * This function computes masks that may be used to select the bits of the X
1076 * and Y coordinates that indicate the offset within a tile. If the BO is
1077 * untiled, the masks are set to 0.
1080 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1081 uint32_t *mask_x
, uint32_t *mask_y
,
1082 bool map_stencil_as_y_tiled
)
1085 uint32_t tiling
= mt
->tiling
;
1087 if (map_stencil_as_y_tiled
)
1088 tiling
= I915_TILING_Y
;
1092 unreachable("not reached");
1093 case I915_TILING_NONE
:
1094 *mask_x
= *mask_y
= 0;
1097 *mask_x
= 512 / cpp
- 1;
1101 *mask_x
= 128 / cpp
- 1;
1108 * Compute the offset (in bytes) from the start of the BO to the given x
1109 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1110 * multiples of the tile size.
1113 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1114 uint32_t x
, uint32_t y
,
1115 bool map_stencil_as_y_tiled
)
1118 uint32_t pitch
= mt
->pitch
;
1119 uint32_t tiling
= mt
->tiling
;
1121 if (map_stencil_as_y_tiled
) {
1122 tiling
= I915_TILING_Y
;
1124 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1125 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1126 * the resulting surface is twice the pitch of the original miptree,
1127 * since each row in the Y-tiled view corresponds to two rows in the
1128 * actual W-tiled surface. So we need to correct the pitch before
1129 * computing the offsets.
1136 unreachable("not reached");
1137 case I915_TILING_NONE
:
1138 return y
* pitch
+ x
* cpp
;
1140 assert((x
% (512 / cpp
)) == 0);
1141 assert((y
% 8) == 0);
1142 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1144 assert((x
% (128 / cpp
)) == 0);
1145 assert((y
% 32) == 0);
1146 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1151 * Rendering with tiled buffers requires that the base address of the buffer
1152 * be aligned to a page boundary. For renderbuffers, and sometimes with
1153 * textures, we may want the surface to point at a texture image level that
1154 * isn't at a page boundary.
1156 * This function returns an appropriately-aligned base offset
1157 * according to the tiling restrictions, plus any required x/y offset
1161 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1162 GLuint level
, GLuint slice
,
1167 uint32_t mask_x
, mask_y
;
1169 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1170 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1172 *tile_x
= x
& mask_x
;
1173 *tile_y
= y
& mask_y
;
1175 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1179 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1180 struct intel_mipmap_tree
*dst_mt
,
1181 struct intel_mipmap_tree
*src_mt
,
1188 ptrdiff_t src_stride
, dst_stride
;
1189 int cpp
= dst_mt
->cpp
;
1191 intel_miptree_map(brw
, src_mt
,
1195 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1198 intel_miptree_map(brw
, dst_mt
,
1202 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1206 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1207 _mesa_get_format_name(src_mt
->format
),
1208 src_mt
, src
, src_stride
,
1209 _mesa_get_format_name(dst_mt
->format
),
1210 dst_mt
, dst
, dst_stride
,
1213 int row_size
= cpp
* width
;
1214 if (src_stride
== row_size
&&
1215 dst_stride
== row_size
) {
1216 memcpy(dst
, src
, row_size
* height
);
1218 for (int i
= 0; i
< height
; i
++) {
1219 memcpy(dst
, src
, row_size
);
1225 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1226 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1228 /* Don't forget to copy the stencil data over, too. We could have skipped
1229 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1230 * shuffling the two data sources in/out of temporary storage instead of
1231 * the direct mapping we get this way.
1233 if (dst_mt
->stencil_mt
) {
1234 assert(src_mt
->stencil_mt
);
1235 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1236 level
, slice
, width
, height
);
1241 intel_miptree_copy_slice(struct brw_context
*brw
,
1242 struct intel_mipmap_tree
*dst_mt
,
1243 struct intel_mipmap_tree
*src_mt
,
1249 mesa_format format
= src_mt
->format
;
1250 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1251 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1259 assert(depth
< src_mt
->level
[level
].depth
);
1260 assert(src_mt
->format
== dst_mt
->format
);
1262 if (dst_mt
->compressed
) {
1264 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1265 height
= ALIGN_NPOT(height
, j
) / j
;
1266 width
= ALIGN_NPOT(width
, i
) / i
;
1269 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1270 * below won't apply since we can't do the depth's Y tiling or the
1271 * stencil's W tiling in the blitter.
1273 if (src_mt
->stencil_mt
) {
1274 intel_miptree_copy_slice_sw(brw
,
1281 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1282 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1283 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1285 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1286 _mesa_get_format_name(src_mt
->format
),
1287 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1288 _mesa_get_format_name(dst_mt
->format
),
1289 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1292 if (!intel_miptree_blit(brw
,
1293 src_mt
, level
, slice
, 0, 0, false,
1294 dst_mt
, level
, slice
, 0, 0, false,
1295 width
, height
, GL_COPY
)) {
1296 perf_debug("miptree validate blit for %s failed\n",
1297 _mesa_get_format_name(format
));
1299 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1305 * Copies the image's current data to the given miptree, and associates that
1306 * miptree with the image.
1308 * If \c invalidate is true, then the actual image data does not need to be
1309 * copied, but the image still needs to be associated to the new miptree (this
1310 * is set to true if we're about to clear the image).
1313 intel_miptree_copy_teximage(struct brw_context
*brw
,
1314 struct intel_texture_image
*intelImage
,
1315 struct intel_mipmap_tree
*dst_mt
,
1318 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1319 struct intel_texture_object
*intel_obj
=
1320 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1321 int level
= intelImage
->base
.Base
.Level
;
1322 int face
= intelImage
->base
.Base
.Face
;
1325 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1326 depth
= intelImage
->base
.Base
.Height
;
1328 depth
= intelImage
->base
.Base
.Depth
;
1331 for (int slice
= 0; slice
< depth
; slice
++) {
1332 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1336 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1337 intel_obj
->needs_validate
= true;
1341 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1342 struct intel_mipmap_tree
*mt
,
1345 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1346 assert(mt
->mcs_mt
== NULL
);
1347 assert(!mt
->disable_aux_buffers
);
1349 /* Choose the correct format for the MCS buffer. All that really matters
1350 * is that we allocate the right buffer size, since we'll always be
1351 * accessing this miptree using MCS-specific hardware mechanisms, which
1352 * infer the correct format based on num_samples.
1355 switch (num_samples
) {
1358 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1361 format
= MESA_FORMAT_R_UNORM8
;
1364 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1365 * for each sample, plus 8 padding bits).
1367 format
= MESA_FORMAT_R_UINT32
;
1370 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1373 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1375 * "The MCS surface must be stored as Tile Y."
1377 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1378 MIPTREE_LAYOUT_TILING_Y
;
1379 mt
->mcs_mt
= intel_miptree_create(brw
,
1385 mt
->logical_height0
,
1387 0 /* num_samples */,
1390 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1392 * When MCS buffer is enabled and bound to MSRT, it is required that it
1393 * is cleared prior to any rendering.
1395 * Since we don't use the MCS buffer for any purpose other than rendering,
1396 * it makes sense to just clear it immediately upon allocation.
1398 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1400 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1401 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1402 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1403 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1410 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1411 struct intel_mipmap_tree
*mt
)
1413 assert(mt
->mcs_mt
== NULL
);
1414 assert(!mt
->disable_aux_buffers
);
1416 /* The format of the MCS buffer is opaque to the driver; all that matters
1417 * is that we get its size and pitch right. We'll pretend that the format
1418 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1419 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1420 * the block width and then a further factor of 4. Since an MCS tile
1421 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1422 * we'll need to scale the height down by the block height and then a
1423 * further factor of 8.
1425 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1426 unsigned block_width_px
;
1427 unsigned block_height
;
1428 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1429 unsigned width_divisor
= block_width_px
* 4;
1430 unsigned height_divisor
= block_height
* 8;
1431 unsigned mcs_width
=
1432 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1433 unsigned mcs_height
=
1434 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1435 assert(mt
->logical_depth0
== 1);
1436 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1437 MIPTREE_LAYOUT_TILING_Y
;
1438 if (brw
->gen
>= 8) {
1439 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1441 mt
->mcs_mt
= intel_miptree_create(brw
,
1449 0 /* num_samples */,
1457 * Helper for intel_miptree_alloc_hiz() that sets
1458 * \c mt->level[level].has_hiz. Return true if and only if
1459 * \c has_hiz was set.
1462 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1463 struct intel_mipmap_tree
*mt
,
1466 assert(mt
->hiz_buf
);
1468 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1469 uint32_t width
= minify(mt
->physical_width0
, level
);
1470 uint32_t height
= minify(mt
->physical_height0
, level
);
1472 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1473 * and the height is 4 aligned. This allows our HiZ support
1474 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1475 * we can grow the width & height to allow the HiZ op to
1476 * force the proper size alignments.
1478 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1479 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1484 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1485 mt
->level
[level
].has_hiz
= true;
1491 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1492 * buffer dimensions and allocates a bo for the hiz buffer.
1494 static struct intel_miptree_aux_buffer
*
1495 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1496 struct intel_mipmap_tree
*mt
)
1498 unsigned z_width
= mt
->logical_width0
;
1499 unsigned z_height
= mt
->logical_height0
;
1500 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1501 unsigned hz_width
, hz_height
;
1502 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1507 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1508 * adjustments required for Z_Height and Z_Width based on multisampling.
1510 switch (mt
->num_samples
) {
1524 unreachable("unsupported sample count");
1527 const unsigned vertical_align
= 8; /* 'j' in the docs */
1528 const unsigned H0
= z_height
;
1529 const unsigned h0
= ALIGN(H0
, vertical_align
);
1530 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1531 const unsigned Z0
= z_depth
;
1533 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1534 hz_width
= ALIGN(z_width
, 16);
1536 if (mt
->target
== GL_TEXTURE_3D
) {
1540 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1541 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1542 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1543 hz_height
+= h_i
* Z_i
;
1544 H_i
= minify(H_i
, 1);
1545 Z_i
= minify(Z_i
, 1);
1548 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1550 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1552 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1553 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1554 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1555 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1556 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1558 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1559 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1563 unsigned long pitch
;
1564 uint32_t tiling
= I915_TILING_Y
;
1565 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1566 hz_width
, hz_height
, 1,
1568 BO_ALLOC_FOR_RENDER
);
1572 } else if (tiling
!= I915_TILING_Y
) {
1573 drm_intel_bo_unreference(buf
->bo
);
1585 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1586 * buffer dimensions and allocates a bo for the hiz buffer.
1588 static struct intel_miptree_aux_buffer
*
1589 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1590 struct intel_mipmap_tree
*mt
)
1592 unsigned z_width
= mt
->logical_width0
;
1593 unsigned z_height
= mt
->logical_height0
;
1594 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1595 unsigned hz_width
, hz_height
;
1596 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1601 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1602 * adjustments required for Z_Height and Z_Width based on multisampling.
1605 switch (mt
->num_samples
) {
1619 unreachable("unsupported sample count");
1623 const unsigned vertical_align
= 8; /* 'j' in the docs */
1624 const unsigned H0
= z_height
;
1625 const unsigned h0
= ALIGN(H0
, vertical_align
);
1626 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1627 const unsigned Z0
= z_depth
;
1629 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1630 hz_width
= ALIGN(z_width
, 16);
1634 unsigned sum_h_i
= 0;
1635 unsigned hz_height_3d_sum
= 0;
1636 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1637 unsigned i
= level
- mt
->first_level
;
1638 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1639 /* sum(i=2 to m; h_i) */
1643 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1644 hz_height_3d_sum
+= h_i
* Z_i
;
1645 H_i
= minify(H_i
, 1);
1646 Z_i
= minify(Z_i
, 1);
1648 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1649 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1651 if (mt
->target
== GL_TEXTURE_3D
) {
1652 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1653 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1655 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1656 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1657 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1658 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1659 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1661 * We can can just take our hz_height calculation from above, and
1662 * multiply by 6 for the cube map and cube map array types.
1668 unsigned long pitch
;
1669 uint32_t tiling
= I915_TILING_Y
;
1670 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1671 hz_width
, hz_height
, 1,
1673 BO_ALLOC_FOR_RENDER
);
1677 } else if (tiling
!= I915_TILING_Y
) {
1678 drm_intel_bo_unreference(buf
->bo
);
1689 static struct intel_miptree_aux_buffer
*
1690 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1691 struct intel_mipmap_tree
*mt
)
1693 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1694 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1697 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1702 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1703 buf
->mt
= intel_miptree_create(brw
,
1709 mt
->logical_height0
,
1718 buf
->bo
= buf
->mt
->bo
;
1719 buf
->pitch
= buf
->mt
->pitch
;
1720 buf
->qpitch
= buf
->mt
->qpitch
;
1726 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1727 struct intel_mipmap_tree
*mt
)
1732 if (mt
->hiz_buf
!= NULL
)
1735 if (mt
->disable_aux_buffers
)
1738 switch (mt
->format
) {
1739 case MESA_FORMAT_Z_FLOAT32
:
1740 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1741 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1742 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1743 case MESA_FORMAT_Z_UNORM16
:
1751 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1752 struct intel_mipmap_tree
*mt
)
1754 assert(mt
->hiz_buf
== NULL
);
1755 assert(!mt
->disable_aux_buffers
);
1757 if (brw
->gen
== 7) {
1758 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1759 } else if (brw
->gen
>= 8) {
1760 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1762 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1768 /* Mark that all slices need a HiZ resolve. */
1769 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1770 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1773 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1774 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1775 exec_node_init(&m
->link
);
1778 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1780 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1788 * Does the miptree slice have hiz enabled?
1791 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1793 intel_miptree_check_level_layer(mt
, level
, 0);
1794 return mt
->level
[level
].has_hiz
;
1798 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1802 if (!intel_miptree_level_has_hiz(mt
, level
))
1805 intel_resolve_map_set(&mt
->hiz_map
,
1806 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1811 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1815 if (!intel_miptree_level_has_hiz(mt
, level
))
1818 intel_resolve_map_set(&mt
->hiz_map
,
1819 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1823 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1827 uint32_t end_layer
= mt
->level
[level
].depth
;
1829 for (layer
= 0; layer
< end_layer
; layer
++) {
1830 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1835 intel_miptree_slice_resolve(struct brw_context
*brw
,
1836 struct intel_mipmap_tree
*mt
,
1839 enum gen6_hiz_op need
)
1841 intel_miptree_check_level_layer(mt
, level
, layer
);
1843 struct intel_resolve_map
*item
=
1844 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1846 if (!item
|| item
->need
!= need
)
1849 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1850 intel_resolve_map_remove(item
);
1855 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1856 struct intel_mipmap_tree
*mt
,
1860 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1861 GEN6_HIZ_OP_HIZ_RESOLVE
);
1865 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1866 struct intel_mipmap_tree
*mt
,
1870 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1871 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1875 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1876 struct intel_mipmap_tree
*mt
,
1877 enum gen6_hiz_op need
)
1879 bool did_resolve
= false;
1881 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1882 if (map
->need
!= need
)
1885 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1886 intel_resolve_map_remove(map
);
1894 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1895 struct intel_mipmap_tree
*mt
)
1897 return intel_miptree_all_slices_resolve(brw
, mt
,
1898 GEN6_HIZ_OP_HIZ_RESOLVE
);
1902 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1903 struct intel_mipmap_tree
*mt
)
1905 return intel_miptree_all_slices_resolve(brw
, mt
,
1906 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1911 intel_miptree_resolve_color(struct brw_context
*brw
,
1912 struct intel_mipmap_tree
*mt
)
1914 switch (mt
->fast_clear_state
) {
1915 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1916 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1917 /* No resolve needed */
1919 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1920 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1921 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1922 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1923 brw_meta_resolve_color(brw
, mt
);
1930 * Make it possible to share the BO backing the given miptree with another
1931 * process or another miptree.
1933 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1934 * then discard the MCS buffer, if present. We also set the fast_clear_state
1935 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1936 * allocated in the future.
1939 intel_miptree_make_shareable(struct brw_context
*brw
,
1940 struct intel_mipmap_tree
*mt
)
1942 /* MCS buffers are also used for multisample buffers, but we can't resolve
1943 * away a multisample MCS buffer because it's an integral part of how the
1944 * pixel data is stored. Fortunately this code path should never be
1945 * reached for multisample buffers.
1947 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1950 intel_miptree_resolve_color(brw
, mt
);
1951 intel_miptree_release(&mt
->mcs_mt
);
1952 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1958 * \brief Get pointer offset into stencil buffer.
1960 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1961 * must decode the tile's layout in software.
1964 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1966 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1968 * Even though the returned offset is always positive, the return type is
1970 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1971 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1974 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1976 uint32_t tile_size
= 4096;
1977 uint32_t tile_width
= 64;
1978 uint32_t tile_height
= 64;
1979 uint32_t row_size
= 64 * stride
;
1981 uint32_t tile_x
= x
/ tile_width
;
1982 uint32_t tile_y
= y
/ tile_height
;
1984 /* The byte's address relative to the tile's base addres. */
1985 uint32_t byte_x
= x
% tile_width
;
1986 uint32_t byte_y
= y
% tile_height
;
1988 uintptr_t u
= tile_y
* row_size
1989 + tile_x
* tile_size
1990 + 512 * (byte_x
/ 8)
1992 + 32 * ((byte_y
/ 4) % 2)
1993 + 16 * ((byte_x
/ 4) % 2)
1994 + 8 * ((byte_y
/ 2) % 2)
1995 + 4 * ((byte_x
/ 2) % 2)
2000 /* adjust for bit6 swizzling */
2001 if (((byte_x
/ 8) % 2) == 1) {
2002 if (((byte_y
/ 8) % 2) == 0) {
2014 intel_miptree_updownsample(struct brw_context
*brw
,
2015 struct intel_mipmap_tree
*src
,
2016 struct intel_mipmap_tree
*dst
)
2019 brw_blorp_blit_miptrees(brw
,
2020 src
, 0 /* level */, 0 /* layer */, src
->format
,
2021 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2023 src
->logical_width0
, src
->logical_height0
,
2025 dst
->logical_width0
, dst
->logical_height0
,
2026 GL_NEAREST
, false, false /*mirror x, y*/);
2027 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2028 brw_meta_stencil_updownsample(brw
, src
, dst
);
2030 brw_meta_updownsample(brw
, src
, dst
);
2033 if (src
->stencil_mt
) {
2034 if (brw
->gen
>= 8) {
2035 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2039 brw_blorp_blit_miptrees(brw
,
2040 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2041 src
->stencil_mt
->format
,
2042 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2043 dst
->stencil_mt
->format
,
2045 src
->logical_width0
, src
->logical_height0
,
2047 dst
->logical_width0
, dst
->logical_height0
,
2048 GL_NEAREST
, false, false /*mirror x, y*/);
2053 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2055 /* CPU accesses to color buffers don't understand fast color clears, so
2056 * resolve any pending fast color clears before we map.
2058 intel_miptree_resolve_color(brw
, mt
);
2060 drm_intel_bo
*bo
= mt
->bo
;
2062 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2063 intel_batchbuffer_flush(brw
);
2065 if (mt
->tiling
!= I915_TILING_NONE
)
2066 brw_bo_map_gtt(brw
, bo
, "miptree");
2068 brw_bo_map(brw
, bo
, true, "miptree");
2074 intel_miptree_unmap_raw(struct brw_context
*brw
,
2075 struct intel_mipmap_tree
*mt
)
2077 drm_intel_bo_unmap(mt
->bo
);
2081 intel_miptree_map_gtt(struct brw_context
*brw
,
2082 struct intel_mipmap_tree
*mt
,
2083 struct intel_miptree_map
*map
,
2084 unsigned int level
, unsigned int slice
)
2086 unsigned int bw
, bh
;
2088 unsigned int image_x
, image_y
;
2089 intptr_t x
= map
->x
;
2090 intptr_t y
= map
->y
;
2092 /* For compressed formats, the stride is the number of bytes per
2093 * row of blocks. intel_miptree_get_image_offset() already does
2096 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2097 assert(y
% bh
== 0);
2098 assert(x
% bw
== 0);
2102 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2107 /* Note that in the case of cube maps, the caller must have passed the
2108 * slice number referencing the face.
2110 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2114 map
->stride
= mt
->pitch
;
2115 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2118 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2119 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2120 map
->x
, map
->y
, map
->w
, map
->h
,
2121 mt
, _mesa_get_format_name(mt
->format
),
2122 x
, y
, map
->ptr
, map
->stride
);
2126 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2127 struct intel_mipmap_tree
*mt
,
2128 struct intel_miptree_map
*map
,
2132 intel_miptree_unmap_raw(brw
, mt
);
2136 intel_miptree_map_blit(struct brw_context
*brw
,
2137 struct intel_mipmap_tree
*mt
,
2138 struct intel_miptree_map
*map
,
2139 unsigned int level
, unsigned int slice
)
2141 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2144 0, MIPTREE_LAYOUT_TILING_NONE
);
2147 fprintf(stderr
, "Failed to allocate blit temporary\n");
2150 map
->stride
= map
->mt
->pitch
;
2152 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2153 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2154 * invalidate is set, since we'll be writing the whole rectangle from our
2155 * temporary buffer back out.
2157 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2158 if (!intel_miptree_blit(brw
,
2160 map
->x
, map
->y
, false,
2163 map
->w
, map
->h
, GL_COPY
)) {
2164 fprintf(stderr
, "Failed to blit\n");
2169 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2171 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2172 map
->x
, map
->y
, map
->w
, map
->h
,
2173 mt
, _mesa_get_format_name(mt
->format
),
2174 level
, slice
, map
->ptr
, map
->stride
);
2179 intel_miptree_release(&map
->mt
);
2185 intel_miptree_unmap_blit(struct brw_context
*brw
,
2186 struct intel_mipmap_tree
*mt
,
2187 struct intel_miptree_map
*map
,
2191 struct gl_context
*ctx
= &brw
->ctx
;
2193 intel_miptree_unmap_raw(brw
, map
->mt
);
2195 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2196 bool ok
= intel_miptree_blit(brw
,
2200 map
->x
, map
->y
, false,
2201 map
->w
, map
->h
, GL_COPY
);
2202 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2205 intel_miptree_release(&map
->mt
);
2209 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2211 #if defined(USE_SSE41)
2213 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2214 struct intel_mipmap_tree
*mt
,
2215 struct intel_miptree_map
*map
,
2216 unsigned int level
, unsigned int slice
)
2218 assert(map
->mode
& GL_MAP_READ_BIT
);
2219 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2221 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2222 map
->x
, map
->y
, map
->w
, map
->h
,
2223 mt
, _mesa_get_format_name(mt
->format
),
2224 level
, slice
, map
->ptr
, map
->stride
);
2226 /* Map the original image */
2229 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2233 void *src
= intel_miptree_map_raw(brw
, mt
);
2236 src
+= image_y
* mt
->pitch
;
2237 src
+= image_x
* mt
->cpp
;
2239 /* Due to the pixel offsets for the particular image being mapped, our
2240 * src pointer may not be 16-byte aligned. However, if the pitch is
2241 * divisible by 16, then the amount by which it's misaligned will remain
2242 * consistent from row to row.
2244 assert((mt
->pitch
% 16) == 0);
2245 const int misalignment
= ((uintptr_t) src
) & 15;
2247 /* Create an untiled temporary buffer for the mapping. */
2248 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2250 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2252 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2253 /* Offset the destination so it has the same misalignment as src. */
2254 map
->ptr
= map
->buffer
+ misalignment
;
2256 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2258 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2259 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2260 void *src_ptr
= src
+ y
* mt
->pitch
;
2262 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2265 intel_miptree_unmap_raw(brw
, mt
);
2269 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2270 struct intel_mipmap_tree
*mt
,
2271 struct intel_miptree_map
*map
,
2275 _mesa_align_free(map
->buffer
);
2282 intel_miptree_map_s8(struct brw_context
*brw
,
2283 struct intel_mipmap_tree
*mt
,
2284 struct intel_miptree_map
*map
,
2285 unsigned int level
, unsigned int slice
)
2287 map
->stride
= map
->w
;
2288 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2292 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2293 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2294 * invalidate is set, since we'll be writing the whole rectangle from our
2295 * temporary buffer back out.
2297 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2298 uint8_t *untiled_s8_map
= map
->ptr
;
2299 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2300 unsigned int image_x
, image_y
;
2302 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2304 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2305 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2306 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2307 x
+ image_x
+ map
->x
,
2308 y
+ image_y
+ map
->y
,
2309 brw
->has_swizzling
);
2310 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2314 intel_miptree_unmap_raw(brw
, mt
);
2316 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2317 map
->x
, map
->y
, map
->w
, map
->h
,
2318 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2320 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2321 map
->x
, map
->y
, map
->w
, map
->h
,
2322 mt
, map
->ptr
, map
->stride
);
2327 intel_miptree_unmap_s8(struct brw_context
*brw
,
2328 struct intel_mipmap_tree
*mt
,
2329 struct intel_miptree_map
*map
,
2333 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2334 unsigned int image_x
, image_y
;
2335 uint8_t *untiled_s8_map
= map
->ptr
;
2336 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2338 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2340 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2341 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2342 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2345 brw
->has_swizzling
);
2346 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2350 intel_miptree_unmap_raw(brw
, mt
);
2357 intel_miptree_map_etc(struct brw_context
*brw
,
2358 struct intel_mipmap_tree
*mt
,
2359 struct intel_miptree_map
*map
,
2363 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2364 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2365 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2368 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2369 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2371 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2372 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2373 map
->w
, map
->h
, 1));
2374 map
->ptr
= map
->buffer
;
2378 intel_miptree_unmap_etc(struct brw_context
*brw
,
2379 struct intel_mipmap_tree
*mt
,
2380 struct intel_miptree_map
*map
,
2386 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2391 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2392 + image_y
* mt
->pitch
2393 + image_x
* mt
->cpp
;
2395 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2396 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2397 map
->ptr
, map
->stride
,
2400 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2401 map
->ptr
, map
->stride
,
2402 map
->w
, map
->h
, mt
->etc_format
);
2404 intel_miptree_unmap_raw(brw
, mt
);
2409 * Mapping function for packed depth/stencil miptrees backed by real separate
2410 * miptrees for depth and stencil.
2412 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2413 * separate from the depth buffer. Yet at the GL API level, we have to expose
2414 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2415 * be able to map that memory for texture storage and glReadPixels-type
2416 * operations. We give Mesa core that access by mallocing a temporary and
2417 * copying the data between the actual backing store and the temporary.
2420 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2421 struct intel_mipmap_tree
*mt
,
2422 struct intel_miptree_map
*map
,
2423 unsigned int level
, unsigned int slice
)
2425 struct intel_mipmap_tree
*z_mt
= mt
;
2426 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2427 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2428 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2430 map
->stride
= map
->w
* packed_bpp
;
2431 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2435 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2436 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2437 * invalidate is set, since we'll be writing the whole rectangle from our
2438 * temporary buffer back out.
2440 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2441 uint32_t *packed_map
= map
->ptr
;
2442 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2443 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2444 unsigned int s_image_x
, s_image_y
;
2445 unsigned int z_image_x
, z_image_y
;
2447 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2448 &s_image_x
, &s_image_y
);
2449 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2450 &z_image_x
, &z_image_y
);
2452 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2453 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2454 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2455 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2458 brw
->has_swizzling
);
2459 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2461 (map_x
+ z_image_x
));
2462 uint8_t s
= s_map
[s_offset
];
2463 uint32_t z
= z_map
[z_offset
];
2465 if (map_z32f_x24s8
) {
2466 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2467 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2469 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2474 intel_miptree_unmap_raw(brw
, s_mt
);
2475 intel_miptree_unmap_raw(brw
, z_mt
);
2477 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2479 map
->x
, map
->y
, map
->w
, map
->h
,
2480 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2481 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2482 map
->ptr
, map
->stride
);
2484 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2485 map
->x
, map
->y
, map
->w
, map
->h
,
2486 mt
, map
->ptr
, map
->stride
);
2491 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2492 struct intel_mipmap_tree
*mt
,
2493 struct intel_miptree_map
*map
,
2497 struct intel_mipmap_tree
*z_mt
= mt
;
2498 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2499 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2501 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2502 uint32_t *packed_map
= map
->ptr
;
2503 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2504 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2505 unsigned int s_image_x
, s_image_y
;
2506 unsigned int z_image_x
, z_image_y
;
2508 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2509 &s_image_x
, &s_image_y
);
2510 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2511 &z_image_x
, &z_image_y
);
2513 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2514 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2515 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2516 x
+ s_image_x
+ map
->x
,
2517 y
+ s_image_y
+ map
->y
,
2518 brw
->has_swizzling
);
2519 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2521 (x
+ z_image_x
+ map
->x
));
2523 if (map_z32f_x24s8
) {
2524 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2525 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2527 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2528 s_map
[s_offset
] = packed
>> 24;
2529 z_map
[z_offset
] = packed
;
2534 intel_miptree_unmap_raw(brw
, s_mt
);
2535 intel_miptree_unmap_raw(brw
, z_mt
);
2537 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2539 map
->x
, map
->y
, map
->w
, map
->h
,
2540 z_mt
, _mesa_get_format_name(z_mt
->format
),
2541 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2542 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2543 map
->ptr
, map
->stride
);
2550 * Create and attach a map to the miptree at (level, slice). Return the
2553 static struct intel_miptree_map
*
2554 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2563 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2568 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2569 mt
->level
[level
].slice
[slice
].map
= map
;
2581 * Release the map at (level, slice).
2584 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2588 struct intel_miptree_map
**map
;
2590 map
= &mt
->level
[level
].slice
[slice
].map
;
2596 can_blit_slice(struct intel_mipmap_tree
*mt
,
2597 unsigned int level
, unsigned int slice
)
2601 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2602 if (image_x
>= 32768 || image_y
>= 32768)
2605 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2606 if (mt
->pitch
>= 32768)
2613 use_intel_mipree_map_blit(struct brw_context
*brw
,
2614 struct intel_mipmap_tree
*mt
,
2620 /* It's probably not worth swapping to the blit ring because of
2621 * all the overhead involved.
2623 !(mode
& GL_MAP_WRITE_BIT
) &&
2625 (mt
->tiling
== I915_TILING_X
||
2626 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2627 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2628 can_blit_slice(mt
, level
, slice
))
2631 if (mt
->tiling
!= I915_TILING_NONE
&&
2632 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2633 assert(can_blit_slice(mt
, level
, slice
));
2641 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2642 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2643 * arithmetic overflow.
2645 * If you call this function and use \a out_stride, then you're doing pointer
2646 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2647 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2648 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2649 * which usually have type uint32_t or GLuint.
2652 intel_miptree_map(struct brw_context
*brw
,
2653 struct intel_mipmap_tree
*mt
,
2662 ptrdiff_t *out_stride
)
2664 struct intel_miptree_map
*map
;
2666 assert(mt
->num_samples
<= 1);
2668 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2675 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2676 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2677 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2680 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2681 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2682 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2683 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2684 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2685 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2686 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2687 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2688 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2689 #if defined(USE_SSE41)
2690 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2691 !mt
->compressed
&& cpu_has_sse4_1
&&
2692 (mt
->pitch
% 16 == 0)) {
2693 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2696 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2699 *out_ptr
= map
->ptr
;
2700 *out_stride
= map
->stride
;
2702 if (map
->ptr
== NULL
)
2703 intel_miptree_release_map(mt
, level
, slice
);
2707 intel_miptree_unmap(struct brw_context
*brw
,
2708 struct intel_mipmap_tree
*mt
,
2712 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2714 assert(mt
->num_samples
<= 1);
2719 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2720 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2722 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2723 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2724 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2725 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2726 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2727 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2728 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2729 } else if (map
->mt
) {
2730 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2731 #if defined(USE_SSE41)
2732 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2733 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2736 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2739 intel_miptree_release_map(mt
, level
, slice
);