1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 intel_miptree_alloc_mcs(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
58 * Determine which MSAA layout should be used by the MSAA surface being
59 * created, based on the chip generation and the surface type.
61 static enum intel_msaa_layout
62 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
,
63 bool disable_aux_buffers
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
67 return INTEL_MSAA_LAYOUT_IMS
;
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
74 return INTEL_MSAA_LAYOUT_IMS
;
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
88 return INTEL_MSAA_LAYOUT_UMS
;
89 } else if (disable_aux_buffers
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->tiling
) {
149 unreachable("Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
163 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
170 * - Support is for non-mip-mapped and non-array surface types only.
172 * And then later, on p327:
174 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
178 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
179 struct intel_mipmap_tree
*mt
)
181 /* MCS support does not exist prior to Gen7 */
185 if (mt
->disable_aux_buffers
)
188 /* MCS is only supported for color buffers */
189 switch (_mesa_get_format_base_format(mt
->format
)) {
190 case GL_DEPTH_COMPONENT
:
191 case GL_DEPTH_STENCIL
:
192 case GL_STENCIL_INDEX
:
196 if (mt
->tiling
!= I915_TILING_X
&&
197 mt
->tiling
!= I915_TILING_Y
)
199 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
201 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
203 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
204 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
209 if (mt
->physical_depth0
!= 1) {
211 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
212 mt
->logical_width0
, mt
->logical_height0
,
213 mt
->physical_depth0
);
219 /* There's no point in using an MCS buffer if the surface isn't in a
222 if (!brw
->format_supported_as_render_target
[mt
->format
])
230 * Determine depth format corresponding to a depth+stencil format,
231 * for separate stencil.
234 intel_depth_format_for_depthstencil_format(mesa_format format
) {
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
238 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
239 return MESA_FORMAT_Z_FLOAT32
;
247 * @param for_bo Indicates that the caller is
248 * intel_miptree_create_for_bo(). If true, then do not create
251 static struct intel_mipmap_tree
*
252 intel_miptree_create_layout(struct brw_context
*brw
,
262 enum intel_miptree_tiling_mode requested
,
263 bool force_all_slices_at_each_lod
,
264 bool disable_aux_buffers
)
266 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
270 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
271 _mesa_lookup_enum_by_nr(target
),
272 _mesa_get_format_name(format
),
273 first_level
, last_level
, depth0
, mt
);
275 if (target
== GL_TEXTURE_1D_ARRAY
) {
276 /* For a 1D Array texture the OpenGL API will treat the height0
277 * parameter as the number of array slices. For Intel hardware, we treat
278 * the 1D array as a 2D Array with a height of 1.
280 * So, when we first come through this path to create a 1D Array
281 * texture, height0 stores the number of slices, and depth0 is 1. In
282 * this case, we want to swap height0 and depth0.
284 * Since some miptrees will be created based on the base miptree, we may
285 * come through this path and see height0 as 1 and depth0 being the
286 * number of slices. In this case we don't need to do the swap.
288 assert(height0
== 1 || depth0
== 1);
297 mt
->first_level
= first_level
;
298 mt
->last_level
= last_level
;
299 mt
->logical_width0
= width0
;
300 mt
->logical_height0
= height0
;
301 mt
->logical_depth0
= depth0
;
302 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
303 mt
->disable_aux_buffers
= disable_aux_buffers
;
304 exec_list_make_empty(&mt
->hiz_map
);
306 /* The cpp is bytes per (1, blockheight)-sized block for compressed
307 * textures. This is why you'll see divides by blockheight all over
310 _mesa_get_format_block_size(format
, &bw
, &bh
);
311 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
312 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
314 mt
->num_samples
= num_samples
;
315 mt
->compressed
= _mesa_is_format_compressed(format
);
316 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
319 if (num_samples
> 1) {
320 /* Adjust width/height/depth for MSAA */
321 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
322 mt
->target
, mt
->disable_aux_buffers
);
323 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
324 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
325 * "If the surface is multisampled and it is a depth or stencil
326 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
327 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
330 * +----------------------------------------------------------------+
331 * | Num Multisamples | W_l = | H_l = |
332 * +----------------------------------------------------------------+
333 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
334 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
335 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
336 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
337 * +----------------------------------------------------------------+
340 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
341 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
342 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
344 * Another more complicated explanation for these adjustments comes
345 * from the Sandybridge PRM, volume 4, part 1, page 31:
347 * "Any of the other messages (sample*, LOD, load4) used with a
348 * (4x) multisampled surface will in-effect sample a surface with
349 * double the height and width as that indicated in the surface
350 * state. Each pixel position on the original-sized surface is
351 * replaced with a 2x2 of samples with the following arrangement:
356 * Thus, when sampling from a multisampled texture, it behaves as
357 * though the layout in memory for (x,y,sample) is:
359 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
360 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
362 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
363 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
365 * However, the actual layout of multisampled data in memory is:
367 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
368 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
370 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
371 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
373 * This pattern repeats for each 2x2 pixel block.
375 * As a result, when calculating the size of our 4-sample buffer for
376 * an odd width or height, we have to align before scaling up because
377 * sample 3 is in that bottom right 2x2 block.
379 switch (num_samples
) {
381 assert(brw
->gen
>= 8);
382 width0
= ALIGN(width0
, 2) * 2;
383 height0
= ALIGN(height0
, 2);
386 width0
= ALIGN(width0
, 2) * 2;
387 height0
= ALIGN(height0
, 2) * 2;
390 width0
= ALIGN(width0
, 2) * 4;
391 height0
= ALIGN(height0
, 2) * 2;
394 /* num_samples should already have been quantized to 0, 1, 2, 4, or
397 unreachable("not reached");
400 /* Non-interleaved */
401 depth0
*= num_samples
;
405 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
406 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
407 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
408 * used on Gen8 to make it pick a qpitch value which doesn't include space
409 * for the mipmaps. On Gen9 this is not necessary because it will
410 * automatically pick a packed qpitch value whenever mt->first_level ==
412 * TODO: can we use it elsewhere?
413 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
416 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
418 switch (mt
->msaa_layout
) {
419 case INTEL_MSAA_LAYOUT_NONE
:
420 case INTEL_MSAA_LAYOUT_IMS
:
421 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
423 case INTEL_MSAA_LAYOUT_UMS
:
424 case INTEL_MSAA_LAYOUT_CMS
:
425 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
430 if (target
== GL_TEXTURE_CUBE_MAP
) {
435 mt
->physical_width0
= width0
;
436 mt
->physical_height0
= height0
;
437 mt
->physical_depth0
= depth0
;
440 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
441 (brw
->must_use_separate_stencil
||
442 (brw
->has_separate_stencil
&&
443 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
444 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
445 mt
->stencil_mt
= intel_miptree_create(brw
,
455 INTEL_MIPTREE_TILING_ANY
,
456 force_all_slices_at_each_lod
);
457 if (!mt
->stencil_mt
) {
458 intel_miptree_release(&mt
);
462 /* Fix up the Z miptree format for how we're splitting out separate
463 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
465 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
468 if (format
== mt
->format
) {
469 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
470 _mesa_get_format_name(mt
->format
));
474 if (force_all_slices_at_each_lod
)
475 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
477 brw_miptree_layout(brw
, for_bo
, requested
, mt
);
479 if (mt
->disable_aux_buffers
)
480 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
486 * \brief Helper function for intel_miptree_create().
489 intel_miptree_choose_tiling(struct brw_context
*brw
,
492 uint32_t num_samples
,
493 enum intel_miptree_tiling_mode requested
,
494 struct intel_mipmap_tree
*mt
)
496 if (format
== MESA_FORMAT_S_UINT8
) {
497 /* The stencil buffer is W tiled. However, we request from the kernel a
498 * non-tiled buffer because the GTT is incapable of W fencing.
500 return I915_TILING_NONE
;
503 /* Some usages may want only one type of tiling, like depth miptrees (Y
504 * tiled), or temporary BOs for uploading data once (linear).
507 case INTEL_MIPTREE_TILING_ANY
:
509 case INTEL_MIPTREE_TILING_Y
:
510 return I915_TILING_Y
;
511 case INTEL_MIPTREE_TILING_NONE
:
512 return I915_TILING_NONE
;
515 if (num_samples
> 1) {
516 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
519 * [DevSNB+]: For multi-sample render targets, this field must be
520 * 1. MSRTs can only be tiled.
522 * Our usual reason for preferring X tiling (fast blits using the
523 * blitting engine) doesn't apply to MSAA, since we'll generally be
524 * downsampling or upsampling when blitting between the MSAA buffer
525 * and another buffer, and the blitting engine doesn't support that.
526 * So use Y tiling, since it makes better use of the cache.
528 return I915_TILING_Y
;
531 GLenum base_format
= _mesa_get_format_base_format(format
);
532 if (base_format
== GL_DEPTH_COMPONENT
||
533 base_format
== GL_DEPTH_STENCIL_EXT
)
534 return I915_TILING_Y
;
536 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
537 * in fact it leads to a less efficient use of memory space and bandwidth
538 * due to tile alignment.
540 if (mt
->logical_height0
== 1)
541 return I915_TILING_NONE
;
543 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
545 /* If the width is much smaller than a tile, don't bother tiling. */
546 if (minimum_pitch
< 64)
547 return I915_TILING_NONE
;
549 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
550 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
551 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
552 mt
->total_width
, mt
->total_height
);
553 return I915_TILING_NONE
;
556 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
558 return I915_TILING_X
;
560 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
561 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
563 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
564 * all the way back to 965, but is permitted on Gen7+.
566 if (brw
->gen
< 7 && mt
->cpp
>= 16)
567 return I915_TILING_X
;
569 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
570 * messages), on p64, under the heading "Surface Vertical Alignment":
572 * This field must be set to VALIGN_4 for all tiled Y Render Target
575 * So if the surface is renderable and uses a vertical alignment of 2,
576 * force it to be X tiled. This is somewhat conservative (it's possible
577 * that the client won't ever render to this surface), but it's difficult
578 * to know that ahead of time. And besides, since we use a vertical
579 * alignment of 4 as often as we can, this shouldn't happen very often.
581 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
582 brw
->format_supported_as_render_target
[format
]) {
583 return I915_TILING_X
;
586 return I915_TILING_Y
| I915_TILING_X
;
591 * Choose an appropriate uncompressed format for a requested
592 * compressed format, if unsupported.
595 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
597 /* No need to lower ETC formats on these platforms,
598 * they are supported natively.
600 if (brw
->gen
>= 8 || brw
->is_baytrail
)
604 case MESA_FORMAT_ETC1_RGB8
:
605 return MESA_FORMAT_R8G8B8X8_UNORM
;
606 case MESA_FORMAT_ETC2_RGB8
:
607 return MESA_FORMAT_R8G8B8X8_UNORM
;
608 case MESA_FORMAT_ETC2_SRGB8
:
609 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
610 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
611 return MESA_FORMAT_B8G8R8A8_SRGB
;
612 case MESA_FORMAT_ETC2_RGBA8_EAC
:
613 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
614 return MESA_FORMAT_R8G8B8A8_UNORM
;
615 case MESA_FORMAT_ETC2_R11_EAC
:
616 return MESA_FORMAT_R_UNORM16
;
617 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
618 return MESA_FORMAT_R_SNORM16
;
619 case MESA_FORMAT_ETC2_RG11_EAC
:
620 return MESA_FORMAT_R16G16_UNORM
;
621 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
622 return MESA_FORMAT_R16G16_SNORM
;
624 /* Non ETC1 / ETC2 format */
630 struct intel_mipmap_tree
*
631 intel_miptree_create(struct brw_context
*brw
,
639 bool expect_accelerated_upload
,
641 enum intel_miptree_tiling_mode requested_tiling
,
642 bool force_all_slices_at_each_lod
)
644 struct intel_mipmap_tree
*mt
;
645 mesa_format tex_format
= format
;
646 mesa_format etc_format
= MESA_FORMAT_NONE
;
647 GLuint total_width
, total_height
;
649 format
= intel_lower_compressed_format(brw
, format
);
651 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
653 mt
= intel_miptree_create_layout(brw
, target
, format
,
654 first_level
, last_level
, width0
,
658 force_all_slices_at_each_lod
,
659 false /*disable_aux_buffers*/);
664 total_width
= mt
->total_width
;
665 total_height
= mt
->total_height
;
667 if (format
== MESA_FORMAT_S_UINT8
) {
668 /* Align to size of W tile, 64x64. */
669 total_width
= ALIGN(total_width
, 64);
670 total_height
= ALIGN(total_height
, 64);
675 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
677 mt
->tiling
= I915_TILING_Y
;
681 mt
->etc_format
= etc_format
;
682 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
683 total_width
, total_height
, mt
->cpp
,
685 (expect_accelerated_upload
?
686 BO_ALLOC_FOR_RENDER
: 0));
689 /* If the BO is too large to fit in the aperture, we need to use the
690 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
691 * handle Y-tiling, so we need to fall back to X.
693 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
694 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
695 mt
->total_width
, mt
->total_height
);
697 mt
->tiling
= I915_TILING_X
;
698 drm_intel_bo_unreference(mt
->bo
);
699 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
700 total_width
, total_height
, mt
->cpp
,
702 (expect_accelerated_upload
?
703 BO_ALLOC_FOR_RENDER
: 0));
710 intel_miptree_release(&mt
);
715 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
716 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
717 intel_miptree_release(&mt
);
722 /* If this miptree is capable of supporting fast color clears, set
723 * fast_clear_state appropriately to ensure that fast clears will occur.
724 * Allocation of the MCS miptree will be deferred until the first fast
725 * clear actually occurs.
727 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
728 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
733 struct intel_mipmap_tree
*
734 intel_miptree_create_for_bo(struct brw_context
*brw
,
742 bool disable_aux_buffers
)
744 struct intel_mipmap_tree
*mt
;
745 uint32_t tiling
, swizzle
;
748 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
750 /* Nothing will be able to use this miptree with the BO if the offset isn't
753 if (tiling
!= I915_TILING_NONE
)
754 assert(offset
% 4096 == 0);
756 /* miptrees can't handle negative pitch. If you need flipping of images,
757 * that's outside of the scope of the mt.
761 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
763 /* 'requested' parameter of intel_miptree_create_layout() is relevant
764 * only for non bo miptree. Tiling for bo is already computed above.
765 * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is
766 * just a place holder and will not make any change to the miptree
769 mt
= intel_miptree_create_layout(brw
, target
, format
,
771 width
, height
, depth
,
773 INTEL_MIPTREE_TILING_ANY
,
775 disable_aux_buffers
);
779 drm_intel_bo_reference(bo
);
789 * For a singlesample renderbuffer, this simply wraps the given BO with a
792 * For a multisample renderbuffer, this wraps the window system's
793 * (singlesample) BO with a singlesample miptree attached to the
794 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
795 * that will contain the actual rendering (which is lazily resolved to
796 * irb->singlesample_mt).
799 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
800 struct intel_renderbuffer
*irb
,
802 uint32_t width
, uint32_t height
,
805 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
806 struct intel_mipmap_tree
*multisample_mt
= NULL
;
807 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
808 mesa_format format
= rb
->Format
;
809 int num_samples
= rb
->NumSamples
;
811 /* Only the front and back buffers, which are color buffers, are allocated
812 * through the image loader.
814 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
815 _mesa_get_format_base_format(format
) == GL_RGBA
);
817 singlesample_mt
= intel_miptree_create_for_bo(intel
,
826 if (!singlesample_mt
)
829 /* If this miptree is capable of supporting fast color clears, set
830 * mcs_state appropriately to ensure that fast clears will occur.
831 * Allocation of the MCS miptree will be deferred until the first fast
832 * clear actually occurs.
834 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
835 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
837 if (num_samples
== 0) {
838 intel_miptree_release(&irb
->mt
);
839 irb
->mt
= singlesample_mt
;
841 assert(!irb
->singlesample_mt
);
843 intel_miptree_release(&irb
->singlesample_mt
);
844 irb
->singlesample_mt
= singlesample_mt
;
847 irb
->mt
->logical_width0
!= width
||
848 irb
->mt
->logical_height0
!= height
) {
849 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
857 irb
->need_downsample
= false;
858 intel_miptree_release(&irb
->mt
);
859 irb
->mt
= multisample_mt
;
865 intel_miptree_release(&irb
->singlesample_mt
);
866 intel_miptree_release(&irb
->mt
);
870 struct intel_mipmap_tree
*
871 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
875 uint32_t num_samples
)
877 struct intel_mipmap_tree
*mt
;
880 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
882 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
883 width
, height
, depth
, true, num_samples
,
884 INTEL_MIPTREE_TILING_ANY
, false);
888 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
889 ok
= intel_miptree_alloc_hiz(brw
, mt
);
897 intel_miptree_release(&mt
);
902 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
903 struct intel_mipmap_tree
*src
)
908 intel_miptree_release(dst
);
912 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
920 intel_miptree_release(struct intel_mipmap_tree
**mt
)
925 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
926 if (--(*mt
)->refcount
<= 0) {
929 DBG("%s deleting %p\n", __func__
, *mt
);
931 drm_intel_bo_unreference((*mt
)->bo
);
932 intel_miptree_release(&(*mt
)->stencil_mt
);
933 if ((*mt
)->hiz_buf
) {
934 if ((*mt
)->hiz_buf
->mt
)
935 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
937 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
938 free((*mt
)->hiz_buf
);
940 intel_miptree_release(&(*mt
)->mcs_mt
);
941 intel_resolve_map_clear(&(*mt
)->hiz_map
);
943 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
944 free((*mt
)->level
[i
].slice
);
953 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
954 int *width
, int *height
, int *depth
)
956 switch (image
->TexObject
->Target
) {
957 case GL_TEXTURE_1D_ARRAY
:
958 *width
= image
->Width
;
960 *depth
= image
->Height
;
963 *width
= image
->Width
;
964 *height
= image
->Height
;
965 *depth
= image
->Depth
;
971 * Can the image be pulled into a unified mipmap tree? This mirrors
972 * the completeness test in a lot of ways.
974 * Not sure whether I want to pass gl_texture_image here.
977 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
978 struct gl_texture_image
*image
)
980 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
981 GLuint level
= intelImage
->base
.Base
.Level
;
982 int width
, height
, depth
;
984 /* glTexImage* choose the texture object based on the target passed in, and
985 * objects can't change targets over their lifetimes, so this should be
988 assert(image
->TexObject
->Target
== mt
->target
);
990 mesa_format mt_format
= mt
->format
;
991 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
992 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
993 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
994 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
995 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
996 mt_format
= mt
->etc_format
;
998 if (image
->TexFormat
!= mt_format
)
1001 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
1003 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1006 int level_depth
= mt
->level
[level
].depth
;
1007 if (mt
->num_samples
> 1) {
1008 switch (mt
->msaa_layout
) {
1009 case INTEL_MSAA_LAYOUT_NONE
:
1010 case INTEL_MSAA_LAYOUT_IMS
:
1012 case INTEL_MSAA_LAYOUT_UMS
:
1013 case INTEL_MSAA_LAYOUT_CMS
:
1014 level_depth
/= mt
->num_samples
;
1019 /* Test image dimensions against the base level image adjusted for
1020 * minification. This will also catch images not present in the
1021 * tree, changed targets, etc.
1023 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1024 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1025 depth
!= level_depth
) {
1029 if (image
->NumSamples
!= mt
->num_samples
)
1037 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1039 GLuint x
, GLuint y
, GLuint d
)
1041 mt
->level
[level
].depth
= d
;
1042 mt
->level
[level
].level_x
= x
;
1043 mt
->level
[level
].level_y
= y
;
1045 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1048 assert(mt
->level
[level
].slice
== NULL
);
1050 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1051 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1052 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1057 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1058 GLuint level
, GLuint img
,
1061 if (img
== 0 && level
== 0)
1062 assert(x
== 0 && y
== 0);
1064 assert(img
< mt
->level
[level
].depth
);
1066 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1067 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1069 DBG("%s level %d img %d pos %d,%d\n",
1070 __func__
, level
, img
,
1071 mt
->level
[level
].slice
[img
].x_offset
,
1072 mt
->level
[level
].slice
[img
].y_offset
);
1076 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1077 GLuint level
, GLuint slice
,
1078 GLuint
*x
, GLuint
*y
)
1080 assert(slice
< mt
->level
[level
].depth
);
1082 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1083 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1087 * This function computes masks that may be used to select the bits of the X
1088 * and Y coordinates that indicate the offset within a tile. If the BO is
1089 * untiled, the masks are set to 0.
1092 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1093 uint32_t *mask_x
, uint32_t *mask_y
,
1094 bool map_stencil_as_y_tiled
)
1097 uint32_t tiling
= mt
->tiling
;
1099 if (map_stencil_as_y_tiled
)
1100 tiling
= I915_TILING_Y
;
1104 unreachable("not reached");
1105 case I915_TILING_NONE
:
1106 *mask_x
= *mask_y
= 0;
1109 *mask_x
= 512 / cpp
- 1;
1113 *mask_x
= 128 / cpp
- 1;
1120 * Compute the offset (in bytes) from the start of the BO to the given x
1121 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1122 * multiples of the tile size.
1125 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1126 uint32_t x
, uint32_t y
,
1127 bool map_stencil_as_y_tiled
)
1130 uint32_t pitch
= mt
->pitch
;
1131 uint32_t tiling
= mt
->tiling
;
1133 if (map_stencil_as_y_tiled
) {
1134 tiling
= I915_TILING_Y
;
1136 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1137 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1138 * the resulting surface is twice the pitch of the original miptree,
1139 * since each row in the Y-tiled view corresponds to two rows in the
1140 * actual W-tiled surface. So we need to correct the pitch before
1141 * computing the offsets.
1148 unreachable("not reached");
1149 case I915_TILING_NONE
:
1150 return y
* pitch
+ x
* cpp
;
1152 assert((x
% (512 / cpp
)) == 0);
1153 assert((y
% 8) == 0);
1154 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1156 assert((x
% (128 / cpp
)) == 0);
1157 assert((y
% 32) == 0);
1158 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1163 * Rendering with tiled buffers requires that the base address of the buffer
1164 * be aligned to a page boundary. For renderbuffers, and sometimes with
1165 * textures, we may want the surface to point at a texture image level that
1166 * isn't at a page boundary.
1168 * This function returns an appropriately-aligned base offset
1169 * according to the tiling restrictions, plus any required x/y offset
1173 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1174 GLuint level
, GLuint slice
,
1179 uint32_t mask_x
, mask_y
;
1181 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1182 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1184 *tile_x
= x
& mask_x
;
1185 *tile_y
= y
& mask_y
;
1187 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1191 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1192 struct intel_mipmap_tree
*dst_mt
,
1193 struct intel_mipmap_tree
*src_mt
,
1200 ptrdiff_t src_stride
, dst_stride
;
1201 int cpp
= dst_mt
->cpp
;
1203 intel_miptree_map(brw
, src_mt
,
1207 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1210 intel_miptree_map(brw
, dst_mt
,
1214 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1218 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1219 _mesa_get_format_name(src_mt
->format
),
1220 src_mt
, src
, src_stride
,
1221 _mesa_get_format_name(dst_mt
->format
),
1222 dst_mt
, dst
, dst_stride
,
1225 int row_size
= cpp
* width
;
1226 if (src_stride
== row_size
&&
1227 dst_stride
== row_size
) {
1228 memcpy(dst
, src
, row_size
* height
);
1230 for (int i
= 0; i
< height
; i
++) {
1231 memcpy(dst
, src
, row_size
);
1237 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1238 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1240 /* Don't forget to copy the stencil data over, too. We could have skipped
1241 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1242 * shuffling the two data sources in/out of temporary storage instead of
1243 * the direct mapping we get this way.
1245 if (dst_mt
->stencil_mt
) {
1246 assert(src_mt
->stencil_mt
);
1247 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1248 level
, slice
, width
, height
);
1253 intel_miptree_copy_slice(struct brw_context
*brw
,
1254 struct intel_mipmap_tree
*dst_mt
,
1255 struct intel_mipmap_tree
*src_mt
,
1261 mesa_format format
= src_mt
->format
;
1262 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1263 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1271 assert(depth
< src_mt
->level
[level
].depth
);
1272 assert(src_mt
->format
== dst_mt
->format
);
1274 if (dst_mt
->compressed
) {
1275 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1276 width
= ALIGN(width
, dst_mt
->align_w
);
1279 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1280 * below won't apply since we can't do the depth's Y tiling or the
1281 * stencil's W tiling in the blitter.
1283 if (src_mt
->stencil_mt
) {
1284 intel_miptree_copy_slice_sw(brw
,
1291 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1292 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1293 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1295 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1296 _mesa_get_format_name(src_mt
->format
),
1297 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1298 _mesa_get_format_name(dst_mt
->format
),
1299 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1302 if (!intel_miptree_blit(brw
,
1303 src_mt
, level
, slice
, 0, 0, false,
1304 dst_mt
, level
, slice
, 0, 0, false,
1305 width
, height
, GL_COPY
)) {
1306 perf_debug("miptree validate blit for %s failed\n",
1307 _mesa_get_format_name(format
));
1309 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1315 * Copies the image's current data to the given miptree, and associates that
1316 * miptree with the image.
1318 * If \c invalidate is true, then the actual image data does not need to be
1319 * copied, but the image still needs to be associated to the new miptree (this
1320 * is set to true if we're about to clear the image).
1323 intel_miptree_copy_teximage(struct brw_context
*brw
,
1324 struct intel_texture_image
*intelImage
,
1325 struct intel_mipmap_tree
*dst_mt
,
1328 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1329 struct intel_texture_object
*intel_obj
=
1330 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1331 int level
= intelImage
->base
.Base
.Level
;
1332 int face
= intelImage
->base
.Base
.Face
;
1335 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1336 depth
= intelImage
->base
.Base
.Height
;
1338 depth
= intelImage
->base
.Base
.Depth
;
1341 for (int slice
= 0; slice
< depth
; slice
++) {
1342 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1346 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1347 intel_obj
->needs_validate
= true;
1351 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1352 struct intel_mipmap_tree
*mt
,
1355 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1356 assert(mt
->mcs_mt
== NULL
);
1357 assert(!mt
->disable_aux_buffers
);
1359 /* Choose the correct format for the MCS buffer. All that really matters
1360 * is that we allocate the right buffer size, since we'll always be
1361 * accessing this miptree using MCS-specific hardware mechanisms, which
1362 * infer the correct format based on num_samples.
1365 switch (num_samples
) {
1368 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1371 format
= MESA_FORMAT_R_UNORM8
;
1374 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1375 * for each sample, plus 8 padding bits).
1377 format
= MESA_FORMAT_R_UINT32
;
1380 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1383 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1385 * "The MCS surface must be stored as Tile Y."
1387 mt
->mcs_mt
= intel_miptree_create(brw
,
1393 mt
->logical_height0
,
1396 0 /* num_samples */,
1397 INTEL_MIPTREE_TILING_Y
,
1400 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1402 * When MCS buffer is enabled and bound to MSRT, it is required that it
1403 * is cleared prior to any rendering.
1405 * Since we don't use the MCS buffer for any purpose other than rendering,
1406 * it makes sense to just clear it immediately upon allocation.
1408 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1410 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1411 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1412 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1413 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1420 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1421 struct intel_mipmap_tree
*mt
)
1423 assert(mt
->mcs_mt
== NULL
);
1424 assert(!mt
->disable_aux_buffers
);
1426 /* The format of the MCS buffer is opaque to the driver; all that matters
1427 * is that we get its size and pitch right. We'll pretend that the format
1428 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1429 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1430 * the block width and then a further factor of 4. Since an MCS tile
1431 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1432 * we'll need to scale the height down by the block height and then a
1433 * further factor of 8.
1435 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1436 unsigned block_width_px
;
1437 unsigned block_height
;
1438 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1439 unsigned width_divisor
= block_width_px
* 4;
1440 unsigned height_divisor
= block_height
* 8;
1441 unsigned mcs_width
=
1442 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1443 unsigned mcs_height
=
1444 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1445 assert(mt
->logical_depth0
== 1);
1446 mt
->mcs_mt
= intel_miptree_create(brw
,
1455 0 /* num_samples */,
1456 INTEL_MIPTREE_TILING_Y
,
1464 * Helper for intel_miptree_alloc_hiz() that sets
1465 * \c mt->level[level].has_hiz. Return true if and only if
1466 * \c has_hiz was set.
1469 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1470 struct intel_mipmap_tree
*mt
,
1473 assert(mt
->hiz_buf
);
1475 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1476 uint32_t width
= minify(mt
->physical_width0
, level
);
1477 uint32_t height
= minify(mt
->physical_height0
, level
);
1479 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1480 * and the height is 4 aligned. This allows our HiZ support
1481 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1482 * we can grow the width & height to allow the HiZ op to
1483 * force the proper size alignments.
1485 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1486 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1491 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1492 mt
->level
[level
].has_hiz
= true;
1498 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1499 * buffer dimensions and allocates a bo for the hiz buffer.
1501 static struct intel_miptree_aux_buffer
*
1502 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*mt
)
1505 unsigned z_width
= mt
->logical_width0
;
1506 unsigned z_height
= mt
->logical_height0
;
1507 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1508 unsigned hz_width
, hz_height
;
1509 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1514 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1515 * adjustments required for Z_Height and Z_Width based on multisampling.
1517 switch (mt
->num_samples
) {
1531 unreachable("unsupported sample count");
1534 const unsigned vertical_align
= 8; /* 'j' in the docs */
1535 const unsigned H0
= z_height
;
1536 const unsigned h0
= ALIGN(H0
, vertical_align
);
1537 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1538 const unsigned Z0
= z_depth
;
1540 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1541 hz_width
= ALIGN(z_width
, 16);
1543 if (mt
->target
== GL_TEXTURE_3D
) {
1547 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1548 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1549 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1550 hz_height
+= h_i
* Z_i
;
1551 H_i
= minify(H_i
, 1);
1552 Z_i
= minify(Z_i
, 1);
1555 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1557 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1559 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1560 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1561 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1562 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1563 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1565 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1566 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1570 unsigned long pitch
;
1571 uint32_t tiling
= I915_TILING_Y
;
1572 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1573 hz_width
, hz_height
, 1,
1575 BO_ALLOC_FOR_RENDER
);
1579 } else if (tiling
!= I915_TILING_Y
) {
1580 drm_intel_bo_unreference(buf
->bo
);
1592 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1593 * buffer dimensions and allocates a bo for the hiz buffer.
1595 static struct intel_miptree_aux_buffer
*
1596 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1597 struct intel_mipmap_tree
*mt
)
1599 unsigned z_width
= mt
->logical_width0
;
1600 unsigned z_height
= mt
->logical_height0
;
1601 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1602 unsigned hz_width
, hz_height
;
1603 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1608 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1609 * adjustments required for Z_Height and Z_Width based on multisampling.
1611 switch (mt
->num_samples
) {
1625 unreachable("unsupported sample count");
1628 const unsigned vertical_align
= 8; /* 'j' in the docs */
1629 const unsigned H0
= z_height
;
1630 const unsigned h0
= ALIGN(H0
, vertical_align
);
1631 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1632 const unsigned Z0
= z_depth
;
1634 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1635 hz_width
= ALIGN(z_width
, 16);
1639 unsigned sum_h_i
= 0;
1640 unsigned hz_height_3d_sum
= 0;
1641 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1642 unsigned i
= level
- mt
->first_level
;
1643 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1644 /* sum(i=2 to m; h_i) */
1648 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1649 hz_height_3d_sum
+= h_i
* Z_i
;
1650 H_i
= minify(H_i
, 1);
1651 Z_i
= minify(Z_i
, 1);
1653 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1654 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1656 if (mt
->target
== GL_TEXTURE_3D
) {
1657 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1658 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1660 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1661 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1662 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1663 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1664 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1666 * We can can just take our hz_height calculation from above, and
1667 * multiply by 6 for the cube map and cube map array types.
1673 unsigned long pitch
;
1674 uint32_t tiling
= I915_TILING_Y
;
1675 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1676 hz_width
, hz_height
, 1,
1678 BO_ALLOC_FOR_RENDER
);
1682 } else if (tiling
!= I915_TILING_Y
) {
1683 drm_intel_bo_unreference(buf
->bo
);
1694 static struct intel_miptree_aux_buffer
*
1695 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1696 struct intel_mipmap_tree
*mt
)
1698 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1699 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1704 buf
->mt
= intel_miptree_create(brw
,
1710 mt
->logical_height0
,
1714 INTEL_MIPTREE_TILING_ANY
,
1715 force_all_slices_at_each_lod
);
1721 buf
->bo
= buf
->mt
->bo
;
1722 buf
->pitch
= buf
->mt
->pitch
;
1723 buf
->qpitch
= buf
->mt
->qpitch
;
1729 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1730 struct intel_mipmap_tree
*mt
)
1735 if (mt
->hiz_buf
!= NULL
)
1738 if (mt
->disable_aux_buffers
)
1741 switch (mt
->format
) {
1742 case MESA_FORMAT_Z_FLOAT32
:
1743 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1744 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1745 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1746 case MESA_FORMAT_Z_UNORM16
:
1754 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1755 struct intel_mipmap_tree
*mt
)
1757 assert(mt
->hiz_buf
== NULL
);
1758 assert(!mt
->disable_aux_buffers
);
1760 if (brw
->gen
== 7) {
1761 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1762 } else if (brw
->gen
>= 8) {
1763 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1765 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1771 /* Mark that all slices need a HiZ resolve. */
1772 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1773 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1776 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1777 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1778 exec_node_init(&m
->link
);
1781 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1783 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1791 * Does the miptree slice have hiz enabled?
1794 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1796 intel_miptree_check_level_layer(mt
, level
, 0);
1797 return mt
->level
[level
].has_hiz
;
1801 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1805 if (!intel_miptree_level_has_hiz(mt
, level
))
1808 intel_resolve_map_set(&mt
->hiz_map
,
1809 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1814 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1818 if (!intel_miptree_level_has_hiz(mt
, level
))
1821 intel_resolve_map_set(&mt
->hiz_map
,
1822 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1826 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1830 uint32_t end_layer
= mt
->level
[level
].depth
;
1832 for (layer
= 0; layer
< end_layer
; layer
++) {
1833 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1838 intel_miptree_slice_resolve(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*mt
,
1842 enum gen6_hiz_op need
)
1844 intel_miptree_check_level_layer(mt
, level
, layer
);
1846 struct intel_resolve_map
*item
=
1847 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1849 if (!item
|| item
->need
!= need
)
1852 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1853 intel_resolve_map_remove(item
);
1858 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1859 struct intel_mipmap_tree
*mt
,
1863 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1864 GEN6_HIZ_OP_HIZ_RESOLVE
);
1868 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1869 struct intel_mipmap_tree
*mt
,
1873 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1874 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1878 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1879 struct intel_mipmap_tree
*mt
,
1880 enum gen6_hiz_op need
)
1882 bool did_resolve
= false;
1884 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1885 if (map
->need
!= need
)
1888 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1889 intel_resolve_map_remove(map
);
1897 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1898 struct intel_mipmap_tree
*mt
)
1900 return intel_miptree_all_slices_resolve(brw
, mt
,
1901 GEN6_HIZ_OP_HIZ_RESOLVE
);
1905 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1906 struct intel_mipmap_tree
*mt
)
1908 return intel_miptree_all_slices_resolve(brw
, mt
,
1909 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1914 intel_miptree_resolve_color(struct brw_context
*brw
,
1915 struct intel_mipmap_tree
*mt
)
1917 switch (mt
->fast_clear_state
) {
1918 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1919 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1920 /* No resolve needed */
1922 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1923 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1924 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1925 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1926 brw_meta_resolve_color(brw
, mt
);
1933 * Make it possible to share the BO backing the given miptree with another
1934 * process or another miptree.
1936 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1937 * then discard the MCS buffer, if present. We also set the fast_clear_state
1938 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1939 * allocated in the future.
1942 intel_miptree_make_shareable(struct brw_context
*brw
,
1943 struct intel_mipmap_tree
*mt
)
1945 /* MCS buffers are also used for multisample buffers, but we can't resolve
1946 * away a multisample MCS buffer because it's an integral part of how the
1947 * pixel data is stored. Fortunately this code path should never be
1948 * reached for multisample buffers.
1950 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1953 intel_miptree_resolve_color(brw
, mt
);
1954 intel_miptree_release(&mt
->mcs_mt
);
1955 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1961 * \brief Get pointer offset into stencil buffer.
1963 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1964 * must decode the tile's layout in software.
1967 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1969 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1971 * Even though the returned offset is always positive, the return type is
1973 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1974 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1977 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1979 uint32_t tile_size
= 4096;
1980 uint32_t tile_width
= 64;
1981 uint32_t tile_height
= 64;
1982 uint32_t row_size
= 64 * stride
;
1984 uint32_t tile_x
= x
/ tile_width
;
1985 uint32_t tile_y
= y
/ tile_height
;
1987 /* The byte's address relative to the tile's base addres. */
1988 uint32_t byte_x
= x
% tile_width
;
1989 uint32_t byte_y
= y
% tile_height
;
1991 uintptr_t u
= tile_y
* row_size
1992 + tile_x
* tile_size
1993 + 512 * (byte_x
/ 8)
1995 + 32 * ((byte_y
/ 4) % 2)
1996 + 16 * ((byte_x
/ 4) % 2)
1997 + 8 * ((byte_y
/ 2) % 2)
1998 + 4 * ((byte_x
/ 2) % 2)
2003 /* adjust for bit6 swizzling */
2004 if (((byte_x
/ 8) % 2) == 1) {
2005 if (((byte_y
/ 8) % 2) == 0) {
2017 intel_miptree_updownsample(struct brw_context
*brw
,
2018 struct intel_mipmap_tree
*src
,
2019 struct intel_mipmap_tree
*dst
)
2022 brw_blorp_blit_miptrees(brw
,
2023 src
, 0 /* level */, 0 /* layer */, src
->format
,
2024 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2026 src
->logical_width0
, src
->logical_height0
,
2028 dst
->logical_width0
, dst
->logical_height0
,
2029 GL_NEAREST
, false, false /*mirror x, y*/);
2030 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2031 brw_meta_stencil_updownsample(brw
, src
, dst
);
2033 brw_meta_updownsample(brw
, src
, dst
);
2036 if (src
->stencil_mt
) {
2037 if (brw
->gen
>= 8) {
2038 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2042 brw_blorp_blit_miptrees(brw
,
2043 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2044 src
->stencil_mt
->format
,
2045 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2046 dst
->stencil_mt
->format
,
2048 src
->logical_width0
, src
->logical_height0
,
2050 dst
->logical_width0
, dst
->logical_height0
,
2051 GL_NEAREST
, false, false /*mirror x, y*/);
2056 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2058 /* CPU accesses to color buffers don't understand fast color clears, so
2059 * resolve any pending fast color clears before we map.
2061 intel_miptree_resolve_color(brw
, mt
);
2063 drm_intel_bo
*bo
= mt
->bo
;
2065 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2066 intel_batchbuffer_flush(brw
);
2068 if (mt
->tiling
!= I915_TILING_NONE
)
2069 brw_bo_map_gtt(brw
, bo
, "miptree");
2071 brw_bo_map(brw
, bo
, true, "miptree");
2077 intel_miptree_unmap_raw(struct brw_context
*brw
,
2078 struct intel_mipmap_tree
*mt
)
2080 drm_intel_bo_unmap(mt
->bo
);
2084 intel_miptree_map_gtt(struct brw_context
*brw
,
2085 struct intel_mipmap_tree
*mt
,
2086 struct intel_miptree_map
*map
,
2087 unsigned int level
, unsigned int slice
)
2089 unsigned int bw
, bh
;
2091 unsigned int image_x
, image_y
;
2092 intptr_t x
= map
->x
;
2093 intptr_t y
= map
->y
;
2095 /* For compressed formats, the stride is the number of bytes per
2096 * row of blocks. intel_miptree_get_image_offset() already does
2099 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2100 assert(y
% bh
== 0);
2103 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2108 /* Note that in the case of cube maps, the caller must have passed the
2109 * slice number referencing the face.
2111 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2115 map
->stride
= mt
->pitch
;
2116 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2119 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2120 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2121 map
->x
, map
->y
, map
->w
, map
->h
,
2122 mt
, _mesa_get_format_name(mt
->format
),
2123 x
, y
, map
->ptr
, map
->stride
);
2127 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2128 struct intel_mipmap_tree
*mt
,
2129 struct intel_miptree_map
*map
,
2133 intel_miptree_unmap_raw(brw
, mt
);
2137 intel_miptree_map_blit(struct brw_context
*brw
,
2138 struct intel_mipmap_tree
*mt
,
2139 struct intel_miptree_map
*map
,
2140 unsigned int level
, unsigned int slice
)
2142 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2146 INTEL_MIPTREE_TILING_NONE
,
2149 fprintf(stderr
, "Failed to allocate blit temporary\n");
2152 map
->stride
= map
->mt
->pitch
;
2154 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2155 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2156 * invalidate is set, since we'll be writing the whole rectangle from our
2157 * temporary buffer back out.
2159 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2160 if (!intel_miptree_blit(brw
,
2162 map
->x
, map
->y
, false,
2165 map
->w
, map
->h
, GL_COPY
)) {
2166 fprintf(stderr
, "Failed to blit\n");
2171 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2173 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2174 map
->x
, map
->y
, map
->w
, map
->h
,
2175 mt
, _mesa_get_format_name(mt
->format
),
2176 level
, slice
, map
->ptr
, map
->stride
);
2181 intel_miptree_release(&map
->mt
);
2187 intel_miptree_unmap_blit(struct brw_context
*brw
,
2188 struct intel_mipmap_tree
*mt
,
2189 struct intel_miptree_map
*map
,
2193 struct gl_context
*ctx
= &brw
->ctx
;
2195 intel_miptree_unmap_raw(brw
, map
->mt
);
2197 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2198 bool ok
= intel_miptree_blit(brw
,
2202 map
->x
, map
->y
, false,
2203 map
->w
, map
->h
, GL_COPY
);
2204 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2207 intel_miptree_release(&map
->mt
);
2211 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2213 #if defined(USE_SSE41)
2215 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2216 struct intel_mipmap_tree
*mt
,
2217 struct intel_miptree_map
*map
,
2218 unsigned int level
, unsigned int slice
)
2220 assert(map
->mode
& GL_MAP_READ_BIT
);
2221 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2223 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2224 map
->x
, map
->y
, map
->w
, map
->h
,
2225 mt
, _mesa_get_format_name(mt
->format
),
2226 level
, slice
, map
->ptr
, map
->stride
);
2228 /* Map the original image */
2231 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2235 void *src
= intel_miptree_map_raw(brw
, mt
);
2238 src
+= image_y
* mt
->pitch
;
2239 src
+= image_x
* mt
->cpp
;
2241 /* Due to the pixel offsets for the particular image being mapped, our
2242 * src pointer may not be 16-byte aligned. However, if the pitch is
2243 * divisible by 16, then the amount by which it's misaligned will remain
2244 * consistent from row to row.
2246 assert((mt
->pitch
% 16) == 0);
2247 const int misalignment
= ((uintptr_t) src
) & 15;
2249 /* Create an untiled temporary buffer for the mapping. */
2250 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2252 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2254 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2255 /* Offset the destination so it has the same misalignment as src. */
2256 map
->ptr
= map
->buffer
+ misalignment
;
2258 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2260 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2261 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2262 void *src_ptr
= src
+ y
* mt
->pitch
;
2264 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2267 intel_miptree_unmap_raw(brw
, mt
);
2271 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2272 struct intel_mipmap_tree
*mt
,
2273 struct intel_miptree_map
*map
,
2277 _mesa_align_free(map
->buffer
);
2284 intel_miptree_map_s8(struct brw_context
*brw
,
2285 struct intel_mipmap_tree
*mt
,
2286 struct intel_miptree_map
*map
,
2287 unsigned int level
, unsigned int slice
)
2289 map
->stride
= map
->w
;
2290 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2294 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2295 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2296 * invalidate is set, since we'll be writing the whole rectangle from our
2297 * temporary buffer back out.
2299 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2300 uint8_t *untiled_s8_map
= map
->ptr
;
2301 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2302 unsigned int image_x
, image_y
;
2304 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2306 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2307 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2308 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2309 x
+ image_x
+ map
->x
,
2310 y
+ image_y
+ map
->y
,
2311 brw
->has_swizzling
);
2312 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2316 intel_miptree_unmap_raw(brw
, mt
);
2318 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2319 map
->x
, map
->y
, map
->w
, map
->h
,
2320 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2322 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2323 map
->x
, map
->y
, map
->w
, map
->h
,
2324 mt
, map
->ptr
, map
->stride
);
2329 intel_miptree_unmap_s8(struct brw_context
*brw
,
2330 struct intel_mipmap_tree
*mt
,
2331 struct intel_miptree_map
*map
,
2335 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2336 unsigned int image_x
, image_y
;
2337 uint8_t *untiled_s8_map
= map
->ptr
;
2338 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2340 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2342 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2343 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2344 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2347 brw
->has_swizzling
);
2348 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2352 intel_miptree_unmap_raw(brw
, mt
);
2359 intel_miptree_map_etc(struct brw_context
*brw
,
2360 struct intel_mipmap_tree
*mt
,
2361 struct intel_miptree_map
*map
,
2365 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2366 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2367 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2370 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2371 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2373 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2374 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2375 map
->w
, map
->h
, 1));
2376 map
->ptr
= map
->buffer
;
2380 intel_miptree_unmap_etc(struct brw_context
*brw
,
2381 struct intel_mipmap_tree
*mt
,
2382 struct intel_miptree_map
*map
,
2388 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2393 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2394 + image_y
* mt
->pitch
2395 + image_x
* mt
->cpp
;
2397 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2398 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2399 map
->ptr
, map
->stride
,
2402 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2403 map
->ptr
, map
->stride
,
2404 map
->w
, map
->h
, mt
->etc_format
);
2406 intel_miptree_unmap_raw(brw
, mt
);
2411 * Mapping function for packed depth/stencil miptrees backed by real separate
2412 * miptrees for depth and stencil.
2414 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2415 * separate from the depth buffer. Yet at the GL API level, we have to expose
2416 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2417 * be able to map that memory for texture storage and glReadPixels-type
2418 * operations. We give Mesa core that access by mallocing a temporary and
2419 * copying the data between the actual backing store and the temporary.
2422 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2423 struct intel_mipmap_tree
*mt
,
2424 struct intel_miptree_map
*map
,
2425 unsigned int level
, unsigned int slice
)
2427 struct intel_mipmap_tree
*z_mt
= mt
;
2428 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2429 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2430 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2432 map
->stride
= map
->w
* packed_bpp
;
2433 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2437 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2438 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2439 * invalidate is set, since we'll be writing the whole rectangle from our
2440 * temporary buffer back out.
2442 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2443 uint32_t *packed_map
= map
->ptr
;
2444 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2445 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2446 unsigned int s_image_x
, s_image_y
;
2447 unsigned int z_image_x
, z_image_y
;
2449 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2450 &s_image_x
, &s_image_y
);
2451 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2452 &z_image_x
, &z_image_y
);
2454 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2455 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2456 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2457 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2460 brw
->has_swizzling
);
2461 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2463 (map_x
+ z_image_x
));
2464 uint8_t s
= s_map
[s_offset
];
2465 uint32_t z
= z_map
[z_offset
];
2467 if (map_z32f_x24s8
) {
2468 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2469 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2471 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2476 intel_miptree_unmap_raw(brw
, s_mt
);
2477 intel_miptree_unmap_raw(brw
, z_mt
);
2479 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2481 map
->x
, map
->y
, map
->w
, map
->h
,
2482 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2483 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2484 map
->ptr
, map
->stride
);
2486 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2487 map
->x
, map
->y
, map
->w
, map
->h
,
2488 mt
, map
->ptr
, map
->stride
);
2493 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2494 struct intel_mipmap_tree
*mt
,
2495 struct intel_miptree_map
*map
,
2499 struct intel_mipmap_tree
*z_mt
= mt
;
2500 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2501 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2503 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2504 uint32_t *packed_map
= map
->ptr
;
2505 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2506 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2507 unsigned int s_image_x
, s_image_y
;
2508 unsigned int z_image_x
, z_image_y
;
2510 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2511 &s_image_x
, &s_image_y
);
2512 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2513 &z_image_x
, &z_image_y
);
2515 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2516 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2517 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2518 x
+ s_image_x
+ map
->x
,
2519 y
+ s_image_y
+ map
->y
,
2520 brw
->has_swizzling
);
2521 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2523 (x
+ z_image_x
+ map
->x
));
2525 if (map_z32f_x24s8
) {
2526 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2527 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2529 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2530 s_map
[s_offset
] = packed
>> 24;
2531 z_map
[z_offset
] = packed
;
2536 intel_miptree_unmap_raw(brw
, s_mt
);
2537 intel_miptree_unmap_raw(brw
, z_mt
);
2539 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2541 map
->x
, map
->y
, map
->w
, map
->h
,
2542 z_mt
, _mesa_get_format_name(z_mt
->format
),
2543 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2544 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2545 map
->ptr
, map
->stride
);
2552 * Create and attach a map to the miptree at (level, slice). Return the
2555 static struct intel_miptree_map
*
2556 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2565 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2570 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2571 mt
->level
[level
].slice
[slice
].map
= map
;
2583 * Release the map at (level, slice).
2586 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2590 struct intel_miptree_map
**map
;
2592 map
= &mt
->level
[level
].slice
[slice
].map
;
2598 can_blit_slice(struct intel_mipmap_tree
*mt
,
2599 unsigned int level
, unsigned int slice
)
2603 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2604 if (image_x
>= 32768 || image_y
>= 32768)
2607 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2608 if (mt
->pitch
>= 32768)
2615 use_intel_mipree_map_blit(struct brw_context
*brw
,
2616 struct intel_mipmap_tree
*mt
,
2622 /* It's probably not worth swapping to the blit ring because of
2623 * all the overhead involved.
2625 !(mode
& GL_MAP_WRITE_BIT
) &&
2627 (mt
->tiling
== I915_TILING_X
||
2628 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2629 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2630 can_blit_slice(mt
, level
, slice
))
2633 if (mt
->tiling
!= I915_TILING_NONE
&&
2634 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2635 assert(can_blit_slice(mt
, level
, slice
));
2643 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2644 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2645 * arithmetic overflow.
2647 * If you call this function and use \a out_stride, then you're doing pointer
2648 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2649 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2650 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2651 * which usually have type uint32_t or GLuint.
2654 intel_miptree_map(struct brw_context
*brw
,
2655 struct intel_mipmap_tree
*mt
,
2664 ptrdiff_t *out_stride
)
2666 struct intel_miptree_map
*map
;
2668 assert(mt
->num_samples
<= 1);
2670 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2677 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2678 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2679 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2682 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2683 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2684 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2685 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2686 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2687 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2688 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2689 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2690 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2691 #if defined(USE_SSE41)
2692 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2693 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2696 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2699 *out_ptr
= map
->ptr
;
2700 *out_stride
= map
->stride
;
2702 if (map
->ptr
== NULL
)
2703 intel_miptree_release_map(mt
, level
, slice
);
2707 intel_miptree_unmap(struct brw_context
*brw
,
2708 struct intel_mipmap_tree
*mt
,
2712 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2714 assert(mt
->num_samples
<= 1);
2719 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2720 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2722 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2723 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2724 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2725 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2726 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2727 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2728 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2729 } else if (map
->mt
) {
2730 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2731 #if defined(USE_SSE41)
2732 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2733 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2736 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2739 intel_miptree_release_map(mt
, level
, slice
);