2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 intel_tiling_supports_ccs(const struct brw_context
*brw
,
102 enum isl_tiling tiling
)
104 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
105 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
107 * - Support is limited to tiled render targets.
109 * Gen9 changes the restriction to Y-tile only.
112 return tiling
== ISL_TILING_Y0
;
113 else if (brw
->gen
>= 7)
114 return tiling
!= ISL_TILING_LINEAR
;
120 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
121 * can be used. This doesn't (and should not) inspect any of the properties of
124 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
125 * beneath the "Fast Color Clear" bullet (p326):
127 * - Support is for non-mip-mapped and non-array surface types only.
129 * And then later, on p327:
131 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
134 * From the Skylake documentation, it is made clear that X-tiling is no longer
137 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
141 intel_miptree_supports_ccs(struct brw_context
*brw
,
142 const struct intel_mipmap_tree
*mt
)
144 /* MCS support does not exist prior to Gen7 */
148 /* This function applies only to non-multisampled render targets. */
149 if (mt
->surf
.samples
> 1)
152 /* MCS is only supported for color buffers */
153 switch (_mesa_get_format_base_format(mt
->format
)) {
154 case GL_DEPTH_COMPONENT
:
155 case GL_DEPTH_STENCIL
:
156 case GL_STENCIL_INDEX
:
160 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
163 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
164 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
165 mt
->surf
.logical_level0_px
.depth
> 1;
168 /* Multisample surfaces with the CMS layout are not layered surfaces,
169 * yet still have physical_depth0 > 1. Assert that we don't
170 * accidentally reject a multisampled surface here. We should have
171 * rejected it earlier by explicitly checking the sample count.
173 assert(mt
->surf
.samples
== 1);
176 /* Handle the hardware restrictions...
178 * All GENs have the following restriction: "MCS buffer for non-MSRT is
179 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
181 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
182 * Non-MultiSampler Render Target Restrictions) Support is for
183 * non-mip-mapped and non-array surface types only.
185 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
186 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
187 * surfaces are supported with MCS buffer layout with these alignments in
188 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
190 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
195 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
198 /* There's no point in using an MCS buffer if the surface isn't in a
201 if (!brw
->mesa_format_supports_render
[mt
->format
])
205 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
206 const enum isl_format isl_format
=
207 brw_isl_format_for_mesa_format(linear_format
);
208 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
214 intel_tiling_supports_hiz(const struct brw_context
*brw
,
215 enum isl_tiling tiling
)
220 return tiling
== ISL_TILING_Y0
;
224 intel_miptree_supports_hiz(const struct brw_context
*brw
,
225 const struct intel_mipmap_tree
*mt
)
230 switch (mt
->format
) {
231 case MESA_FORMAT_Z_FLOAT32
:
232 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
233 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
234 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
235 case MESA_FORMAT_Z_UNORM16
:
243 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
244 const struct intel_mipmap_tree
*mt
)
249 /* For now compression is only enabled for integer formats even though
250 * there exist supported floating point formats also. This is a heuristic
251 * decision based on current public benchmarks. In none of the cases these
252 * formats provided any improvement but a few cases were seen to regress.
253 * Hence these are left to to be enabled in the future when they are known
256 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
259 if (!intel_miptree_supports_ccs(brw
, mt
))
262 /* Fast clear can be also used to clear srgb surfaces by using equivalent
263 * linear format. This trick, however, can't be extended to be used with
264 * lossless compression and therefore a check is needed to see if the format
267 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
271 * Determine depth format corresponding to a depth+stencil format,
272 * for separate stencil.
275 intel_depth_format_for_depthstencil_format(mesa_format format
) {
277 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
278 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
279 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
280 return MESA_FORMAT_Z_FLOAT32
;
287 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
288 unsigned depth0
, struct intel_mipmap_level
*table
)
290 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
292 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
294 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
295 if (!table
[level
].slice
)
302 for (unsigned level
= first_level
; level
<= last_level
; level
++)
303 free(table
[level
].slice
);
309 needs_separate_stencil(const struct brw_context
*brw
,
310 struct intel_mipmap_tree
*mt
,
311 mesa_format format
, uint32_t layout_flags
)
314 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
317 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
320 if (brw
->must_use_separate_stencil
)
323 return brw
->has_separate_stencil
&&
324 intel_miptree_supports_hiz(brw
, mt
);
328 * Choose the aux usage for this miptree. This function must be called fairly
329 * late in the miptree create process after we have a tiling.
332 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
333 struct intel_mipmap_tree
*mt
)
335 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
337 const unsigned no_flags
= 0;
338 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
339 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
340 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
341 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
342 intel_miptree_supports_ccs(brw
, mt
)) {
343 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
344 intel_miptree_supports_ccs_e(brw
, mt
)) {
345 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
347 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
349 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
350 intel_miptree_supports_hiz(brw
, mt
)) {
351 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
354 /* We can do fast-clear on all auxiliary surface types that are
355 * allocated through the normal texture creation paths.
357 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
358 mt
->supports_fast_clear
= true;
363 * Choose an appropriate uncompressed format for a requested
364 * compressed format, if unsupported.
367 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
369 /* No need to lower ETC formats on these platforms,
370 * they are supported natively.
372 if (brw
->gen
>= 8 || brw
->is_baytrail
)
376 case MESA_FORMAT_ETC1_RGB8
:
377 return MESA_FORMAT_R8G8B8X8_UNORM
;
378 case MESA_FORMAT_ETC2_RGB8
:
379 return MESA_FORMAT_R8G8B8X8_UNORM
;
380 case MESA_FORMAT_ETC2_SRGB8
:
381 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
382 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
383 return MESA_FORMAT_B8G8R8A8_SRGB
;
384 case MESA_FORMAT_ETC2_RGBA8_EAC
:
385 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
386 return MESA_FORMAT_R8G8B8A8_UNORM
;
387 case MESA_FORMAT_ETC2_R11_EAC
:
388 return MESA_FORMAT_R_UNORM16
;
389 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
390 return MESA_FORMAT_R_SNORM16
;
391 case MESA_FORMAT_ETC2_RG11_EAC
:
392 return MESA_FORMAT_R16G16_UNORM
;
393 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
394 return MESA_FORMAT_R16G16_SNORM
;
396 /* Non ETC1 / ETC2 format */
402 get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
404 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
405 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
407 return mt
->surf
.logical_level0_px
.array_len
;
411 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
413 /* In case of physical dimensions one needs to consider also the layout.
414 * See isl_calc_phys_level0_extent_sa().
416 if (surf
->dim
!= ISL_SURF_DIM_3D
)
417 return surf
->phys_level0_sa
.array_len
;
419 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
420 return minify(surf
->phys_level0_sa
.array_len
, level
);
422 return minify(surf
->phys_level0_sa
.depth
, level
);
425 /** \brief Assert that the level and layer are valid for the miptree. */
427 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
435 assert(level
>= mt
->first_level
);
436 assert(level
<= mt
->last_level
);
437 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
440 static enum isl_aux_state
**
441 create_aux_state_map(struct intel_mipmap_tree
*mt
,
442 enum isl_aux_state initial
)
444 const uint32_t levels
= mt
->last_level
+ 1;
446 uint32_t total_slices
= 0;
447 for (uint32_t level
= 0; level
< levels
; level
++)
448 total_slices
+= get_num_logical_layers(mt
, level
);
450 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
452 /* We're going to allocate a single chunk of data for both the per-level
453 * reference array and the arrays of aux_state. This makes cleanup
454 * significantly easier.
456 const size_t total_size
= per_level_array_size
+
457 total_slices
* sizeof(enum isl_aux_state
);
458 void *data
= malloc(total_size
);
462 enum isl_aux_state
**per_level_arr
= data
;
463 enum isl_aux_state
*s
= data
+ per_level_array_size
;
464 for (uint32_t level
= 0; level
< levels
; level
++) {
465 per_level_arr
[level
] = s
;
466 const unsigned level_layers
= get_num_logical_layers(mt
, level
);
467 for (uint32_t a
= 0; a
< level_layers
; a
++)
470 assert((void *)s
== data
+ total_size
);
472 return per_level_arr
;
476 free_aux_state_map(enum isl_aux_state
**state
)
482 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
483 enum isl_tiling tiling
, unsigned samples
)
488 if (tiling
== ISL_TILING_LINEAR
)
491 /* If the width is much smaller than a tile, don't bother tiling. */
495 if (ALIGN(row_pitch
, 512) >= 32768) {
496 perf_debug("row pitch %u too large to blit, falling back to untiled",
505 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
506 enum isl_tiling tiling
)
508 /* If the BO is too large to fit in the aperture, we need to use the
509 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
510 * handle Y-tiling, so we need to fall back to X.
512 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
513 tiling
== ISL_TILING_Y0
)
519 static struct intel_mipmap_tree
*
520 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
521 unsigned first_level
, unsigned last_level
,
522 unsigned width0
, unsigned height0
, unsigned depth0
,
523 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
524 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
525 unsigned row_pitch
, struct brw_bo
*bo
)
527 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
531 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
539 if (target
== GL_TEXTURE_CUBE_MAP
||
540 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
541 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
543 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
545 _mesa_enum_to_string(target
),
546 _mesa_get_format_name(format
),
547 num_samples
, width0
, height0
, depth0
,
548 first_level
, last_level
, mt
);
550 struct isl_surf_init_info init_info
= {
551 .dim
= get_isl_surf_dim(target
),
552 .format
= translate_tex_format(brw
, format
, false),
555 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
556 .levels
= last_level
- first_level
+ 1,
557 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
558 .samples
= num_samples
,
559 .row_pitch
= row_pitch
,
560 .usage
= isl_usage_flags
,
561 .tiling_flags
= tiling_flags
,
564 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
567 /* In case caller doesn't specifically request Y-tiling (needed
568 * unconditionally for depth), check for corner cases needing special
571 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
572 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
573 mt
->surf
.tiling
, mt
->surf
.samples
)) {
574 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
575 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
577 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
578 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
579 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
584 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
585 * the size may not be multiple of row_pitch.
586 * See isl_apply_surface_padding().
588 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
589 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
592 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
594 isl_tiling_to_i915_tiling(
596 mt
->surf
.row_pitch
, alloc_flags
);
603 mt
->first_level
= first_level
;
604 mt
->last_level
= last_level
;
607 mt
->aux_state
= NULL
;
608 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
609 mt
->compressed
= _mesa_is_format_compressed(format
);
614 intel_miptree_release(&mt
);
619 make_separate_stencil_surface(struct brw_context
*brw
,
620 struct intel_mipmap_tree
*mt
)
622 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
623 0, mt
->surf
.levels
- 1,
624 mt
->surf
.logical_level0_px
.width
,
625 mt
->surf
.logical_level0_px
.height
,
626 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
627 mt
->surf
.logical_level0_px
.depth
:
628 mt
->surf
.logical_level0_px
.array_len
,
629 mt
->surf
.samples
, ISL_TILING_W_BIT
,
630 ISL_SURF_USAGE_STENCIL_BIT
|
631 ISL_SURF_USAGE_TEXTURE_BIT
,
632 BO_ALLOC_FOR_RENDER
, 0, NULL
);
637 mt
->stencil_mt
->r8stencil_needs_update
= true;
643 force_linear_tiling(uint32_t layout_flags
)
645 /* ANY includes NONE and Y bit. */
646 if (layout_flags
& MIPTREE_LAYOUT_TILING_Y
)
649 return layout_flags
& MIPTREE_LAYOUT_TILING_NONE
;
652 static struct intel_mipmap_tree
*
653 miptree_create(struct brw_context
*brw
,
662 uint32_t layout_flags
)
664 if (format
== MESA_FORMAT_S_UINT8
)
665 return make_surface(brw
, target
, format
, first_level
, last_level
,
666 width0
, height0
, depth0
, num_samples
,
668 ISL_SURF_USAGE_STENCIL_BIT
|
669 ISL_SURF_USAGE_TEXTURE_BIT
,
674 const GLenum base_format
= _mesa_get_format_base_format(format
);
675 if ((base_format
== GL_DEPTH_COMPONENT
||
676 base_format
== GL_DEPTH_STENCIL
) &&
677 !force_linear_tiling(layout_flags
)) {
678 /* Fix up the Z miptree format for how we're splitting out separate
679 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
681 const mesa_format depth_only_format
=
682 intel_depth_format_for_depthstencil_format(format
);
683 struct intel_mipmap_tree
*mt
= make_surface(
684 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
685 first_level
, last_level
,
686 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
687 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
688 BO_ALLOC_FOR_RENDER
, 0, NULL
);
690 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
) &&
691 !make_separate_stencil_surface(brw
, mt
)) {
692 intel_miptree_release(&mt
);
696 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
697 intel_miptree_choose_aux_usage(brw
, mt
);
702 mesa_format tex_format
= format
;
703 mesa_format etc_format
= MESA_FORMAT_NONE
;
704 uint32_t alloc_flags
= 0;
706 format
= intel_lower_compressed_format(brw
, format
);
708 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
710 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
711 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
712 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
714 isl_tiling_flags_t tiling_flags
= force_linear_tiling(layout_flags
) ?
715 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
717 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
719 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
721 struct intel_mipmap_tree
*mt
= make_surface(
723 first_level
, last_level
,
724 width0
, height0
, depth0
,
725 num_samples
, tiling_flags
,
726 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
727 ISL_SURF_USAGE_TEXTURE_BIT
,
728 alloc_flags
, 0, NULL
);
732 mt
->etc_format
= etc_format
;
734 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
735 mt
->bo
->cache_coherent
= false;
737 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
738 intel_miptree_choose_aux_usage(brw
, mt
);
743 struct intel_mipmap_tree
*
744 intel_miptree_create(struct brw_context
*brw
,
753 uint32_t layout_flags
)
755 assert(num_samples
> 0);
757 struct intel_mipmap_tree
*mt
= miptree_create(
759 first_level
, last_level
,
760 width0
, height0
, depth0
, num_samples
,
767 if (!intel_miptree_alloc_aux(brw
, mt
)) {
768 intel_miptree_release(&mt
);
775 struct intel_mipmap_tree
*
776 intel_miptree_create_for_bo(struct brw_context
*brw
,
784 uint32_t layout_flags
)
786 struct intel_mipmap_tree
*mt
;
787 uint32_t tiling
, swizzle
;
788 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
789 const GLenum base_format
= _mesa_get_format_base_format(format
);
791 if ((base_format
== GL_DEPTH_COMPONENT
||
792 base_format
== GL_DEPTH_STENCIL
)) {
793 const mesa_format depth_only_format
=
794 intel_depth_format_for_depthstencil_format(format
);
795 mt
= make_surface(brw
, target
,
796 brw
->gen
>= 6 ? depth_only_format
: format
,
797 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
798 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
799 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
801 brw_bo_reference(bo
);
803 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
804 intel_miptree_choose_aux_usage(brw
, mt
);
807 } else if (format
== MESA_FORMAT_S_UINT8
) {
808 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
809 0, 0, width
, height
, depth
, 1,
811 ISL_SURF_USAGE_STENCIL_BIT
|
812 ISL_SURF_USAGE_TEXTURE_BIT
,
813 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
817 assert(bo
->size
>= mt
->surf
.size
);
819 brw_bo_reference(bo
);
823 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
825 /* Nothing will be able to use this miptree with the BO if the offset isn't
828 if (tiling
!= I915_TILING_NONE
)
829 assert(offset
% 4096 == 0);
831 /* miptrees can't handle negative pitch. If you need flipping of images,
832 * that's outside of the scope of the mt.
836 /* The BO already has a tiling format and we shouldn't confuse the lower
837 * layers by making it try to find a tiling format again.
839 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
840 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
842 mt
= make_surface(brw
, target
, format
,
843 0, 0, width
, height
, depth
, 1,
844 1lu << isl_tiling_from_i915_tiling(tiling
),
845 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
846 ISL_SURF_USAGE_TEXTURE_BIT
,
851 brw_bo_reference(bo
);
855 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
856 intel_miptree_choose_aux_usage(brw
, mt
);
861 static struct intel_mipmap_tree
*
862 miptree_create_for_planar_image(struct brw_context
*brw
,
863 __DRIimage
*image
, GLenum target
)
865 struct intel_image_format
*f
= image
->planar_format
;
866 struct intel_mipmap_tree
*planar_mt
= NULL
;
868 for (int i
= 0; i
< f
->nplanes
; i
++) {
869 const int index
= f
->planes
[i
].buffer_index
;
870 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
871 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
872 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
873 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
875 /* Disable creation of the texture's aux buffers because the driver
876 * exposes no EGL API to manage them. That is, there is no API for
877 * resolving the aux buffer's content to the main buffer nor for
878 * invalidating the aux buffer's content.
880 struct intel_mipmap_tree
*mt
=
881 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
882 image
->offsets
[index
],
884 image
->strides
[index
],
885 MIPTREE_LAYOUT_DISABLE_AUX
);
894 planar_mt
->plane
[i
- 1] = mt
;
900 struct intel_mipmap_tree
*
901 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
902 __DRIimage
*image
, GLenum target
,
903 enum isl_colorspace colorspace
,
904 bool is_winsys_image
)
906 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
907 assert(colorspace
== ISL_COLORSPACE_NONE
||
908 colorspace
== ISL_COLORSPACE_YUV
);
909 return miptree_create_for_planar_image(brw
, image
, target
);
912 mesa_format format
= image
->format
;
913 switch (colorspace
) {
914 case ISL_COLORSPACE_NONE
:
915 /* Keep the image format unmodified */
918 case ISL_COLORSPACE_LINEAR
:
919 format
=_mesa_get_srgb_format_linear(format
);
922 case ISL_COLORSPACE_SRGB
:
923 format
=_mesa_get_linear_format_srgb(format
);
927 unreachable("Inalid colorspace for non-planar image");
930 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
931 /* The texture storage paths in core Mesa detect if the driver does not
932 * support the user-requested format, and then searches for a
933 * fallback format. The DRIimage code bypasses core Mesa, though. So we
934 * do the fallbacks here for important formats.
936 * We must support DRM_FOURCC_XBGR8888 textures because the Android
937 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
938 * the Chrome OS compositor consumes as dma_buf EGLImages.
940 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
943 if (!brw
->ctx
.TextureFormatSupported
[format
])
946 /* If this image comes in from a window system, we have different
947 * requirements than if it comes in via an EGL import operation. Window
948 * system images can use any form of auxiliary compression we wish because
949 * they get "flushed" before being handed off to the window system and we
950 * have the opportunity to do resolves. Window system buffers also may be
951 * used for scanout so we need to flag that appropriately.
953 const uint32_t mt_layout_flags
=
954 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
956 /* Disable creation of the texture's aux buffers because the driver exposes
957 * no EGL API to manage them. That is, there is no API for resolving the aux
958 * buffer's content to the main buffer nor for invalidating the aux buffer's
961 struct intel_mipmap_tree
*mt
=
962 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
963 image
->offset
, image
->width
, image
->height
, 1,
964 image
->pitch
, mt_layout_flags
);
969 mt
->level
[0].level_x
= image
->tile_x
;
970 mt
->level
[0].level_y
= image
->tile_y
;
972 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
973 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
974 * trouble resolving back to destination image due to alignment issues.
976 if (!brw
->has_surface_tile_offset
) {
977 uint32_t draw_x
, draw_y
;
978 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
980 if (draw_x
!= 0 || draw_y
!= 0) {
981 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
982 intel_miptree_release(&mt
);
987 if (!intel_miptree_alloc_aux(brw
, mt
)) {
988 intel_miptree_release(&mt
);
996 * For a singlesample renderbuffer, this simply wraps the given BO with a
999 * For a multisample renderbuffer, this wraps the window system's
1000 * (singlesample) BO with a singlesample miptree attached to the
1001 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1002 * that will contain the actual rendering (which is lazily resolved to
1003 * irb->singlesample_mt).
1006 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1007 struct intel_renderbuffer
*irb
,
1008 struct intel_mipmap_tree
*singlesample_mt
,
1009 uint32_t width
, uint32_t height
,
1012 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1013 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1014 mesa_format format
= rb
->Format
;
1015 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1017 /* Only the front and back buffers, which are color buffers, are allocated
1018 * through the image loader.
1020 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1021 _mesa_get_format_base_format(format
) == GL_RGBA
);
1023 assert(singlesample_mt
);
1025 if (num_samples
== 1) {
1026 intel_miptree_release(&irb
->mt
);
1027 irb
->mt
= singlesample_mt
;
1029 assert(!irb
->singlesample_mt
);
1031 intel_miptree_release(&irb
->singlesample_mt
);
1032 irb
->singlesample_mt
= singlesample_mt
;
1035 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1036 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1037 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1042 if (!multisample_mt
)
1045 irb
->need_downsample
= false;
1046 intel_miptree_release(&irb
->mt
);
1047 irb
->mt
= multisample_mt
;
1053 intel_miptree_release(&irb
->mt
);
1057 struct intel_mipmap_tree
*
1058 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1062 uint32_t num_samples
)
1064 struct intel_mipmap_tree
*mt
;
1066 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1067 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1068 MIPTREE_LAYOUT_TILING_ANY
;
1070 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1071 width
, height
, depth
, num_samples
,
1079 intel_miptree_release(&mt
);
1084 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1085 struct intel_mipmap_tree
*src
)
1090 intel_miptree_release(dst
);
1094 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1101 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1103 if (aux_buf
== NULL
)
1106 brw_bo_unreference(aux_buf
->bo
);
1112 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1117 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1118 if (--(*mt
)->refcount
<= 0) {
1121 DBG("%s deleting %p\n", __func__
, *mt
);
1123 brw_bo_unreference((*mt
)->bo
);
1124 intel_miptree_release(&(*mt
)->stencil_mt
);
1125 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1126 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1127 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1128 free_aux_state_map((*mt
)->aux_state
);
1130 intel_miptree_release(&(*mt
)->plane
[0]);
1131 intel_miptree_release(&(*mt
)->plane
[1]);
1133 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1134 free((*mt
)->level
[i
].slice
);
1144 intel_get_image_dims(struct gl_texture_image
*image
,
1145 int *width
, int *height
, int *depth
)
1147 switch (image
->TexObject
->Target
) {
1148 case GL_TEXTURE_1D_ARRAY
:
1149 /* For a 1D Array texture the OpenGL API will treat the image height as
1150 * the number of array slices. For Intel hardware, we treat the 1D array
1151 * as a 2D Array with a height of 1. So, here we want to swap image
1154 assert(image
->Depth
== 1);
1155 *width
= image
->Width
;
1157 *depth
= image
->Height
;
1159 case GL_TEXTURE_CUBE_MAP
:
1160 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1161 * though we really have 6 slices.
1163 assert(image
->Depth
== 1);
1164 *width
= image
->Width
;
1165 *height
= image
->Height
;
1169 *width
= image
->Width
;
1170 *height
= image
->Height
;
1171 *depth
= image
->Depth
;
1177 * Can the image be pulled into a unified mipmap tree? This mirrors
1178 * the completeness test in a lot of ways.
1180 * Not sure whether I want to pass gl_texture_image here.
1183 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1184 struct gl_texture_image
*image
)
1186 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1187 GLuint level
= intelImage
->base
.Base
.Level
;
1188 int width
, height
, depth
;
1190 /* glTexImage* choose the texture object based on the target passed in, and
1191 * objects can't change targets over their lifetimes, so this should be
1194 assert(image
->TexObject
->Target
== mt
->target
);
1196 mesa_format mt_format
= mt
->format
;
1197 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1198 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1199 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1200 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1201 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1202 mt_format
= mt
->etc_format
;
1204 if (image
->TexFormat
!= mt_format
)
1207 intel_get_image_dims(image
, &width
, &height
, &depth
);
1209 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1212 if (level
>= mt
->surf
.levels
)
1215 const unsigned level_depth
=
1216 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1217 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1218 mt
->surf
.logical_level0_px
.array_len
;
1220 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1221 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1222 depth
== level_depth
&&
1223 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1227 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1228 GLuint level
, GLuint slice
,
1229 GLuint
*x
, GLuint
*y
)
1231 if (level
== 0 && slice
== 0) {
1232 *x
= mt
->level
[0].level_x
;
1233 *y
= mt
->level
[0].level_y
;
1237 uint32_t x_offset_sa
, y_offset_sa
;
1239 /* Miptree itself can have an offset only if it represents a single
1240 * slice in an imported buffer object.
1241 * See intel_miptree_create_for_dri_image().
1243 assert(mt
->level
[0].level_x
== 0);
1244 assert(mt
->level
[0].level_y
== 0);
1246 /* Given level is relative to level zero while the miptree may be
1247 * represent just a subset of all levels starting from 'first_level'.
1249 assert(level
>= mt
->first_level
);
1250 level
-= mt
->first_level
;
1252 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1253 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1254 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1255 &x_offset_sa
, &y_offset_sa
);
1263 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1264 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1265 * and tile_h is set to 1.
1268 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1269 uint32_t *tile_w
, uint32_t *tile_h
)
1280 case ISL_TILING_LINEAR
:
1285 unreachable("not reached");
1291 * This function computes masks that may be used to select the bits of the X
1292 * and Y coordinates that indicate the offset within a tile. If the BO is
1293 * untiled, the masks are set to 0.
1296 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1297 uint32_t *mask_x
, uint32_t *mask_y
)
1299 uint32_t tile_w_bytes
, tile_h
;
1301 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1303 *mask_x
= tile_w_bytes
/ cpp
- 1;
1304 *mask_y
= tile_h
- 1;
1308 * Compute the offset (in bytes) from the start of the BO to the given x
1309 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1310 * multiples of the tile size.
1313 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1314 uint32_t x
, uint32_t y
)
1317 uint32_t pitch
= mt
->surf
.row_pitch
;
1319 switch (mt
->surf
.tiling
) {
1321 unreachable("not reached");
1322 case ISL_TILING_LINEAR
:
1323 return y
* pitch
+ x
* cpp
;
1325 assert((x
% (512 / cpp
)) == 0);
1326 assert((y
% 8) == 0);
1327 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1329 assert((x
% (128 / cpp
)) == 0);
1330 assert((y
% 32) == 0);
1331 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1336 * Rendering with tiled buffers requires that the base address of the buffer
1337 * be aligned to a page boundary. For renderbuffers, and sometimes with
1338 * textures, we may want the surface to point at a texture image level that
1339 * isn't at a page boundary.
1341 * This function returns an appropriately-aligned base offset
1342 * according to the tiling restrictions, plus any required x/y offset
1346 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1347 GLuint level
, GLuint slice
,
1352 uint32_t mask_x
, mask_y
;
1354 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1355 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1357 *tile_x
= x
& mask_x
;
1358 *tile_y
= y
& mask_y
;
1360 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1364 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1365 struct intel_mipmap_tree
*src_mt
,
1366 unsigned src_level
, unsigned src_layer
,
1367 struct intel_mipmap_tree
*dst_mt
,
1368 unsigned dst_level
, unsigned dst_layer
,
1369 unsigned width
, unsigned height
)
1372 ptrdiff_t src_stride
, dst_stride
;
1373 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1375 intel_miptree_map(brw
, src_mt
,
1376 src_level
, src_layer
,
1379 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1382 intel_miptree_map(brw
, dst_mt
,
1383 dst_level
, dst_layer
,
1386 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1390 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1391 _mesa_get_format_name(src_mt
->format
),
1392 src_mt
, src
, src_stride
,
1393 _mesa_get_format_name(dst_mt
->format
),
1394 dst_mt
, dst
, dst_stride
,
1397 int row_size
= cpp
* width
;
1398 if (src_stride
== row_size
&&
1399 dst_stride
== row_size
) {
1400 memcpy(dst
, src
, row_size
* height
);
1402 for (int i
= 0; i
< height
; i
++) {
1403 memcpy(dst
, src
, row_size
);
1409 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1410 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1412 /* Don't forget to copy the stencil data over, too. We could have skipped
1413 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1414 * shuffling the two data sources in/out of temporary storage instead of
1415 * the direct mapping we get this way.
1417 if (dst_mt
->stencil_mt
) {
1418 assert(src_mt
->stencil_mt
);
1419 intel_miptree_copy_slice_sw(brw
,
1420 src_mt
->stencil_mt
, src_level
, src_layer
,
1421 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1427 intel_miptree_copy_slice(struct brw_context
*brw
,
1428 struct intel_mipmap_tree
*src_mt
,
1429 unsigned src_level
, unsigned src_layer
,
1430 struct intel_mipmap_tree
*dst_mt
,
1431 unsigned dst_level
, unsigned dst_layer
)
1434 mesa_format format
= src_mt
->format
;
1435 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1436 src_level
- src_mt
->first_level
);
1437 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1438 src_level
- src_mt
->first_level
);
1440 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1441 src_level
- src_mt
->first_level
));
1443 assert(src_mt
->format
== dst_mt
->format
);
1445 if (dst_mt
->compressed
) {
1447 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1448 height
= ALIGN_NPOT(height
, j
) / j
;
1449 width
= ALIGN_NPOT(width
, i
) / i
;
1452 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1453 * below won't apply since we can't do the depth's Y tiling or the
1454 * stencil's W tiling in the blitter.
1456 if (src_mt
->stencil_mt
) {
1457 intel_miptree_copy_slice_sw(brw
,
1458 src_mt
, src_level
, src_layer
,
1459 dst_mt
, dst_level
, dst_layer
,
1464 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1465 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1467 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1470 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1471 _mesa_get_format_name(src_mt
->format
),
1472 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1473 _mesa_get_format_name(dst_mt
->format
),
1474 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1477 if (!intel_miptree_blit(brw
,
1478 src_mt
, src_level
, src_layer
, 0, 0, false,
1479 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1480 width
, height
, GL_COPY
)) {
1481 perf_debug("miptree validate blit for %s failed\n",
1482 _mesa_get_format_name(format
));
1484 intel_miptree_copy_slice_sw(brw
,
1485 src_mt
, src_level
, src_layer
,
1486 dst_mt
, dst_level
, dst_layer
,
1492 * Copies the image's current data to the given miptree, and associates that
1493 * miptree with the image.
1495 * If \c invalidate is true, then the actual image data does not need to be
1496 * copied, but the image still needs to be associated to the new miptree (this
1497 * is set to true if we're about to clear the image).
1500 intel_miptree_copy_teximage(struct brw_context
*brw
,
1501 struct intel_texture_image
*intelImage
,
1502 struct intel_mipmap_tree
*dst_mt
,
1505 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1506 struct intel_texture_object
*intel_obj
=
1507 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1508 int level
= intelImage
->base
.Base
.Level
;
1509 const unsigned face
= intelImage
->base
.Base
.Face
;
1510 unsigned start_layer
, end_layer
;
1512 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1514 assert(intelImage
->base
.Base
.Height
);
1516 end_layer
= intelImage
->base
.Base
.Height
- 1;
1517 } else if (face
> 0) {
1521 assert(intelImage
->base
.Base
.Depth
);
1523 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1527 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1528 intel_miptree_copy_slice(brw
,
1534 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1535 intel_obj
->needs_validate
= true;
1539 intel_miptree_init_mcs(struct brw_context
*brw
,
1540 struct intel_mipmap_tree
*mt
,
1543 assert(mt
->mcs_buf
!= NULL
);
1545 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1547 * When MCS buffer is enabled and bound to MSRT, it is required that it
1548 * is cleared prior to any rendering.
1550 * Since we don't use the MCS buffer for any purpose other than rendering,
1551 * it makes sense to just clear it immediately upon allocation.
1553 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1555 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1556 if (unlikely(map
== NULL
)) {
1557 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1558 brw_bo_unreference(mt
->mcs_buf
->bo
);
1563 memset(data
, init_value
, mt
->mcs_buf
->size
);
1564 brw_bo_unmap(mt
->mcs_buf
->bo
);
1567 static struct intel_miptree_aux_buffer
*
1568 intel_alloc_aux_buffer(struct brw_context
*brw
,
1570 const struct isl_surf
*aux_surf
,
1571 uint32_t alloc_flags
,
1572 struct intel_mipmap_tree
*mt
)
1574 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1578 buf
->size
= aux_surf
->size
;
1579 buf
->pitch
= aux_surf
->row_pitch
;
1580 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1582 /* ISL has stricter set of alignment rules then the drm allocator.
1583 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1584 * trying to recalculate based on different format block sizes.
1586 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1587 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1593 buf
->surf
= *aux_surf
;
1599 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1600 struct intel_mipmap_tree
*mt
,
1603 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1604 assert(mt
->mcs_buf
== NULL
);
1605 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1607 /* Multisampled miptrees are only supported for single level. */
1608 assert(mt
->first_level
== 0);
1609 enum isl_aux_state
**aux_state
=
1610 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1614 struct isl_surf temp_mcs_surf
;
1616 MAYBE_UNUSED
bool ok
=
1617 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1620 /* Buffer needs to be initialised requiring the buffer to be immediately
1621 * mapped to cpu space for writing. Therefore do not use the gpu access
1622 * flag which can cause an unnecessary delay if the backing pages happened
1623 * to be just used by the GPU.
1625 const uint32_t alloc_flags
= 0;
1626 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1627 &temp_mcs_surf
, alloc_flags
, mt
);
1633 mt
->aux_state
= aux_state
;
1635 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1641 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1642 struct intel_mipmap_tree
*mt
)
1644 assert(mt
->mcs_buf
== NULL
);
1645 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1646 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1648 struct isl_surf temp_ccs_surf
;
1650 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1653 assert(temp_ccs_surf
.size
&&
1654 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1656 enum isl_aux_state
**aux_state
=
1657 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1661 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1662 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1664 * "If Software wants to enable Color Compression without Fast clear,
1665 * Software needs to initialize MCS with zeros."
1667 * A CCS value of 0 indicates that the corresponding block is in the
1668 * pass-through state which is what we want.
1670 * For CCS_D, on the other hand, we don't care as we're about to perform a
1671 * fast-clear operation. In that case, being hot in caches more useful.
1673 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1674 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1675 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1676 &temp_ccs_surf
, alloc_flags
, mt
);
1682 mt
->aux_state
= aux_state
;
1688 * Helper for intel_miptree_alloc_hiz() that sets
1689 * \c mt->level[level].has_hiz. Return true if and only if
1690 * \c has_hiz was set.
1693 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1694 struct intel_mipmap_tree
*mt
,
1697 assert(mt
->hiz_buf
);
1698 assert(mt
->surf
.size
> 0);
1700 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1701 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1702 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1704 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1705 * and the height is 4 aligned. This allows our HiZ support
1706 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1707 * we can grow the width & height to allow the HiZ op to
1708 * force the proper size alignments.
1710 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1711 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1716 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1717 mt
->level
[level
].has_hiz
= true;
1722 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1723 struct intel_mipmap_tree
*mt
)
1725 assert(mt
->hiz_buf
== NULL
);
1726 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1728 enum isl_aux_state
**aux_state
=
1729 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1733 struct isl_surf temp_hiz_surf
;
1735 MAYBE_UNUSED
bool ok
=
1736 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1739 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1740 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1741 &temp_hiz_surf
, alloc_flags
, mt
);
1748 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1749 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1751 mt
->aux_state
= aux_state
;
1758 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1760 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1761 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1762 * compress clear color so we wait until an actual fast-clear to allocate it.
1765 intel_miptree_alloc_aux(struct brw_context
*brw
,
1766 struct intel_mipmap_tree
*mt
)
1768 switch (mt
->aux_usage
) {
1769 case ISL_AUX_USAGE_NONE
:
1772 case ISL_AUX_USAGE_HIZ
:
1773 assert(!_mesa_is_format_color_format(mt
->format
));
1774 if (!intel_miptree_alloc_hiz(brw
, mt
))
1778 case ISL_AUX_USAGE_MCS
:
1779 assert(_mesa_is_format_color_format(mt
->format
));
1780 assert(mt
->surf
.samples
> 1);
1781 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1785 case ISL_AUX_USAGE_CCS_D
:
1786 /* Since CCS_D can only compress clear color so we wait until an actual
1787 * fast-clear to allocate it.
1791 case ISL_AUX_USAGE_CCS_E
:
1792 assert(_mesa_is_format_color_format(mt
->format
));
1793 assert(mt
->surf
.samples
== 1);
1794 if (!intel_miptree_alloc_ccs(brw
, mt
))
1799 unreachable("Invalid aux usage");
1804 * Can the miptree sample using the hiz buffer?
1807 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1808 struct intel_mipmap_tree
*mt
)
1810 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1811 * so keep things conservative for now and never enable it unless we're SKL+.
1821 /* It seems the hardware won't fallback to the depth buffer if some of the
1822 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1823 * of the texture to be HiZ enabled.
1825 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1826 if (!intel_miptree_level_has_hiz(mt
, level
))
1830 /* If compressed multisampling is enabled, then we use it for the auxiliary
1833 * From the BDW PRM (Volume 2d: Command Reference: Structures
1834 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1836 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1837 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1839 * There is no such blurb for 1D textures, but there is sufficient evidence
1840 * that this is broken on SKL+.
1842 return (mt
->surf
.samples
== 1 &&
1843 mt
->target
!= GL_TEXTURE_3D
&&
1844 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1848 * Does the miptree slice have hiz enabled?
1851 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1853 intel_miptree_check_level_layer(mt
, level
, 0);
1854 return mt
->level
[level
].has_hiz
;
1857 static inline uint32_t
1858 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1859 uint32_t start_level
, uint32_t num_levels
)
1861 assert(start_level
>= mt
->first_level
);
1862 assert(start_level
<= mt
->last_level
);
1864 if (num_levels
== INTEL_REMAINING_LAYERS
)
1865 num_levels
= mt
->last_level
- start_level
+ 1;
1866 /* Check for overflow */
1867 assert(start_level
+ num_levels
>= start_level
);
1868 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1873 static inline uint32_t
1874 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1875 uint32_t start_layer
, uint32_t num_layers
)
1877 assert(level
<= mt
->last_level
);
1879 const uint32_t total_num_layers
= get_num_logical_layers(mt
, level
);
1880 assert(start_layer
< total_num_layers
);
1881 if (num_layers
== INTEL_REMAINING_LAYERS
)
1882 num_layers
= total_num_layers
- start_layer
;
1883 /* Check for overflow */
1884 assert(start_layer
+ num_layers
>= start_layer
);
1885 assert(start_layer
+ num_layers
<= total_num_layers
);
1891 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1892 unsigned start_level
, unsigned num_levels
,
1893 unsigned start_layer
, unsigned num_layers
)
1895 assert(_mesa_is_format_color_format(mt
->format
));
1900 /* Clamp the level range to fit the miptree */
1901 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1903 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1904 const uint32_t level
= start_level
+ l
;
1905 const uint32_t level_layers
=
1906 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1907 for (unsigned a
= 0; a
< level_layers
; a
++) {
1908 enum isl_aux_state aux_state
=
1909 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1910 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1911 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1920 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1921 const struct intel_mipmap_tree
*mt
,
1922 unsigned level
, unsigned layer
)
1928 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1929 assert(brw
->gen
>= 8 ||
1930 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1932 /* Compression of arrayed msaa surfaces is supported. */
1933 if (mt
->surf
.samples
> 1)
1936 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1937 assert(brw
->gen
>= 8 ||
1939 mt
->surf
.logical_level0_px
.depth
== 1 &&
1940 mt
->surf
.logical_level0_px
.array_len
== 1));
1946 static enum blorp_fast_clear_op
1947 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1948 enum isl_aux_usage aux_usage
,
1949 bool fast_clear_supported
)
1951 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
1953 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
1955 assert(ccs_supported
== fast_clear_supported
);
1957 switch (aux_state
) {
1958 case ISL_AUX_STATE_CLEAR
:
1959 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1961 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1963 return BLORP_FAST_CLEAR_OP_NONE
;
1965 case ISL_AUX_STATE_PASS_THROUGH
:
1966 return BLORP_FAST_CLEAR_OP_NONE
;
1968 case ISL_AUX_STATE_RESOLVED
:
1969 case ISL_AUX_STATE_AUX_INVALID
:
1970 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1971 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1975 unreachable("Invalid aux state for CCS_D");
1978 static enum blorp_fast_clear_op
1979 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
1980 enum isl_aux_usage aux_usage
,
1981 bool fast_clear_supported
)
1983 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
1984 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1985 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1986 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1988 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
1989 assert(fast_clear_supported
);
1991 switch (aux_state
) {
1992 case ISL_AUX_STATE_CLEAR
:
1993 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1994 if (fast_clear_supported
)
1995 return BLORP_FAST_CLEAR_OP_NONE
;
1996 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
1997 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1999 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2001 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2002 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2003 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2004 else if (!fast_clear_supported
)
2005 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2007 return BLORP_FAST_CLEAR_OP_NONE
;
2009 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2010 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2011 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2013 return BLORP_FAST_CLEAR_OP_NONE
;
2015 case ISL_AUX_STATE_PASS_THROUGH
:
2016 return BLORP_FAST_CLEAR_OP_NONE
;
2018 case ISL_AUX_STATE_RESOLVED
:
2019 case ISL_AUX_STATE_AUX_INVALID
:
2023 unreachable("Invalid aux state for CCS_E");
2027 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2028 struct intel_mipmap_tree
*mt
,
2029 uint32_t level
, uint32_t layer
,
2030 enum isl_aux_usage aux_usage
,
2031 bool fast_clear_supported
)
2033 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2035 enum blorp_fast_clear_op resolve_op
;
2036 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2037 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2038 fast_clear_supported
);
2040 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2041 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2042 fast_clear_supported
);
2045 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2046 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2047 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2049 switch (resolve_op
) {
2050 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2051 /* The CCS full resolve operation destroys the CCS and sets it to the
2052 * pass-through state. (You can also think of this as being both a
2053 * resolve and an ambiguate in one operation.)
2055 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2056 ISL_AUX_STATE_PASS_THROUGH
);
2059 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2060 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2061 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2065 unreachable("Invalid resolve op");
2071 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2072 struct intel_mipmap_tree
*mt
,
2073 uint32_t level
, uint32_t layer
,
2074 enum isl_aux_usage aux_usage
)
2076 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2077 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2078 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2080 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2082 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2083 switch (aux_state
) {
2084 case ISL_AUX_STATE_CLEAR
:
2085 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2086 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2087 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2089 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2090 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2091 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2092 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2093 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2094 ISL_AUX_STATE_PARTIAL_CLEAR
);
2098 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2099 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2100 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2101 break; /* Nothing to do */
2103 case ISL_AUX_STATE_PASS_THROUGH
:
2104 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2105 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2106 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2112 case ISL_AUX_STATE_RESOLVED
:
2113 case ISL_AUX_STATE_AUX_INVALID
:
2114 unreachable("Invalid aux state for CCS_E");
2117 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2118 /* CCS_D is a bit simpler */
2119 switch (aux_state
) {
2120 case ISL_AUX_STATE_CLEAR
:
2121 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2122 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2123 ISL_AUX_STATE_PARTIAL_CLEAR
);
2126 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2127 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2128 break; /* Nothing to do */
2130 case ISL_AUX_STATE_PASS_THROUGH
:
2134 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2135 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2136 case ISL_AUX_STATE_RESOLVED
:
2137 case ISL_AUX_STATE_AUX_INVALID
:
2138 unreachable("Invalid aux state for CCS_D");
2144 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2145 struct intel_mipmap_tree
*mt
,
2147 enum isl_aux_usage aux_usage
,
2148 bool fast_clear_supported
)
2150 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2152 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2153 case ISL_AUX_STATE_CLEAR
:
2154 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2155 if (!fast_clear_supported
) {
2156 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2157 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2158 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2162 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2163 break; /* Nothing to do */
2165 case ISL_AUX_STATE_RESOLVED
:
2166 case ISL_AUX_STATE_PASS_THROUGH
:
2167 case ISL_AUX_STATE_AUX_INVALID
:
2168 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2169 unreachable("Invalid aux state for MCS");
2174 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2175 struct intel_mipmap_tree
*mt
,
2177 enum isl_aux_usage aux_usage
)
2179 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2181 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2182 case ISL_AUX_STATE_CLEAR
:
2183 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2184 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2187 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2188 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2189 break; /* Nothing to do */
2191 case ISL_AUX_STATE_RESOLVED
:
2192 case ISL_AUX_STATE_PASS_THROUGH
:
2193 case ISL_AUX_STATE_AUX_INVALID
:
2194 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2195 unreachable("Invalid aux state for MCS");
2200 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2201 struct intel_mipmap_tree
*mt
,
2202 uint32_t level
, uint32_t layer
,
2203 enum isl_aux_usage aux_usage
,
2204 bool fast_clear_supported
)
2206 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2208 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2209 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2210 case ISL_AUX_STATE_CLEAR
:
2211 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2212 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2213 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2216 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2217 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2218 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2221 case ISL_AUX_STATE_PASS_THROUGH
:
2222 case ISL_AUX_STATE_RESOLVED
:
2225 case ISL_AUX_STATE_AUX_INVALID
:
2226 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2227 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2230 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2231 unreachable("Invalid HiZ state");
2234 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2235 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2238 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2239 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2240 ISL_AUX_STATE_RESOLVED
);
2243 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2244 /* The HiZ resolve operation is actually an ambiguate */
2245 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2246 ISL_AUX_STATE_PASS_THROUGH
);
2250 unreachable("Invalid HiZ op");
2256 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2257 struct intel_mipmap_tree
*mt
,
2258 uint32_t level
, uint32_t layer
,
2259 enum isl_aux_usage aux_usage
)
2261 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2263 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2264 case ISL_AUX_STATE_CLEAR
:
2265 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2266 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2267 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2270 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2271 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2272 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2273 break; /* Nothing to do */
2275 case ISL_AUX_STATE_RESOLVED
:
2276 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2277 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2278 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2280 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2281 ISL_AUX_STATE_AUX_INVALID
);
2285 case ISL_AUX_STATE_PASS_THROUGH
:
2286 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2287 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2288 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2292 case ISL_AUX_STATE_AUX_INVALID
:
2293 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2296 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2297 unreachable("Invalid HiZ state");
2302 intel_miptree_prepare_access(struct brw_context
*brw
,
2303 struct intel_mipmap_tree
*mt
,
2304 uint32_t start_level
, uint32_t num_levels
,
2305 uint32_t start_layer
, uint32_t num_layers
,
2306 enum isl_aux_usage aux_usage
,
2307 bool fast_clear_supported
)
2309 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2311 switch (mt
->aux_usage
) {
2312 case ISL_AUX_USAGE_NONE
:
2316 case ISL_AUX_USAGE_MCS
:
2317 assert(mt
->mcs_buf
);
2318 assert(start_level
== 0 && num_levels
== 1);
2319 const uint32_t level_layers
=
2320 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2321 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2322 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2323 aux_usage
, fast_clear_supported
);
2327 case ISL_AUX_USAGE_CCS_D
:
2328 case ISL_AUX_USAGE_CCS_E
:
2332 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2333 const uint32_t level
= start_level
+ l
;
2334 const uint32_t level_layers
=
2335 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2336 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2337 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2339 aux_usage
, fast_clear_supported
);
2344 case ISL_AUX_USAGE_HIZ
:
2345 assert(mt
->hiz_buf
);
2346 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2347 const uint32_t level
= start_level
+ l
;
2348 if (!intel_miptree_level_has_hiz(mt
, level
))
2351 const uint32_t level_layers
=
2352 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2353 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2354 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2355 aux_usage
, fast_clear_supported
);
2361 unreachable("Invalid aux usage");
2366 intel_miptree_finish_write(struct brw_context
*brw
,
2367 struct intel_mipmap_tree
*mt
, uint32_t level
,
2368 uint32_t start_layer
, uint32_t num_layers
,
2369 enum isl_aux_usage aux_usage
)
2371 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2373 switch (mt
->aux_usage
) {
2374 case ISL_AUX_USAGE_NONE
:
2378 case ISL_AUX_USAGE_MCS
:
2379 assert(mt
->mcs_buf
);
2380 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2381 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2386 case ISL_AUX_USAGE_CCS_D
:
2387 case ISL_AUX_USAGE_CCS_E
:
2391 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2392 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2397 case ISL_AUX_USAGE_HIZ
:
2398 if (!intel_miptree_level_has_hiz(mt
, level
))
2401 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2402 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2408 unreachable("Invavlid aux usage");
2413 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2414 uint32_t level
, uint32_t layer
)
2416 intel_miptree_check_level_layer(mt
, level
, layer
);
2418 if (_mesa_is_format_color_format(mt
->format
)) {
2419 assert(mt
->mcs_buf
!= NULL
);
2420 assert(mt
->surf
.samples
== 1 ||
2421 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2422 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2423 unreachable("Cannot get aux state for stencil");
2425 assert(intel_miptree_level_has_hiz(mt
, level
));
2428 return mt
->aux_state
[level
][layer
];
2432 intel_miptree_set_aux_state(struct brw_context
*brw
,
2433 struct intel_mipmap_tree
*mt
, uint32_t level
,
2434 uint32_t start_layer
, uint32_t num_layers
,
2435 enum isl_aux_state aux_state
)
2437 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2439 if (_mesa_is_format_color_format(mt
->format
)) {
2440 assert(mt
->mcs_buf
!= NULL
);
2441 assert(mt
->surf
.samples
== 1 ||
2442 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2443 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2444 unreachable("Cannot get aux state for stencil");
2446 assert(intel_miptree_level_has_hiz(mt
, level
));
2449 for (unsigned a
= 0; a
< num_layers
; a
++)
2450 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2453 /* On Gen9 color buffers may be compressed by the hardware (lossless
2454 * compression). There are, however, format restrictions and care needs to be
2455 * taken that the sampler engine is capable for re-interpreting a buffer with
2456 * format different the buffer was originally written with.
2458 * For example, SRGB formats are not compressible and the sampler engine isn't
2459 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2460 * color buffer needs to be resolved so that the sampling surface can be
2461 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2465 can_texture_with_ccs(struct brw_context
*brw
,
2466 struct intel_mipmap_tree
*mt
,
2467 mesa_format view_format
)
2469 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2472 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2473 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2475 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2476 isl_mt_format
, isl_view_format
)) {
2477 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2478 _mesa_get_format_name(view_format
),
2479 _mesa_get_format_name(mt
->format
));
2487 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2488 struct intel_mipmap_tree
*mt
,
2489 enum isl_format view_format
)
2491 switch (mt
->aux_usage
) {
2492 case ISL_AUX_USAGE_HIZ
:
2493 if (intel_miptree_sample_with_hiz(brw
, mt
))
2494 return ISL_AUX_USAGE_HIZ
;
2497 case ISL_AUX_USAGE_MCS
:
2498 return ISL_AUX_USAGE_MCS
;
2500 case ISL_AUX_USAGE_CCS_D
:
2501 case ISL_AUX_USAGE_CCS_E
:
2502 if (mt
->mcs_buf
&& can_texture_with_ccs(brw
, mt
, view_format
))
2503 return ISL_AUX_USAGE_CCS_E
;
2510 return ISL_AUX_USAGE_NONE
;
2514 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2515 struct intel_mipmap_tree
*mt
,
2516 mesa_format view_format
,
2517 uint32_t start_level
, uint32_t num_levels
,
2518 uint32_t start_layer
, uint32_t num_layers
,
2519 bool *aux_supported_out
)
2521 enum isl_aux_usage aux_usage
=
2522 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2523 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2525 /* Clear color is specified as ints or floats and the conversion is done by
2526 * the sampler. If we have a texture view, we would have to perform the
2527 * clear color conversion manually. Just disable clear color.
2529 if (mt
->format
!= view_format
)
2530 clear_supported
= false;
2532 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2533 start_layer
, num_layers
,
2534 aux_usage
, clear_supported
);
2535 if (aux_supported_out
)
2536 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2540 intel_miptree_prepare_texture(struct brw_context
*brw
,
2541 struct intel_mipmap_tree
*mt
,
2542 mesa_format view_format
,
2543 bool *aux_supported_out
)
2545 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2546 0, INTEL_REMAINING_LEVELS
,
2547 0, INTEL_REMAINING_LAYERS
,
2552 intel_miptree_prepare_image(struct brw_context
*brw
,
2553 struct intel_mipmap_tree
*mt
)
2555 /* The data port doesn't understand any compression */
2556 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2557 0, INTEL_REMAINING_LAYERS
,
2558 ISL_AUX_USAGE_NONE
, false);
2562 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2563 struct intel_mipmap_tree
*mt
, uint32_t level
,
2564 uint32_t start_layer
, uint32_t num_layers
)
2566 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2567 start_layer
, num_layers
, NULL
);
2571 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2572 struct intel_mipmap_tree
*mt
,
2575 switch (mt
->aux_usage
) {
2576 case ISL_AUX_USAGE_MCS
:
2577 assert(mt
->mcs_buf
);
2578 return ISL_AUX_USAGE_MCS
;
2580 case ISL_AUX_USAGE_CCS_D
:
2581 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2582 * the single-sampled color renderbuffers because the CCS buffer isn't
2583 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2584 * enabled because otherwise the surface state will be programmed with
2585 * the linear equivalent format anyway.
2588 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2589 return ISL_AUX_USAGE_NONE
;
2590 } else if (!mt
->mcs_buf
) {
2591 return ISL_AUX_USAGE_NONE
;
2593 return ISL_AUX_USAGE_CCS_D
;
2596 case ISL_AUX_USAGE_CCS_E
: {
2597 /* Lossless compression is not supported for SRGB formats, it
2598 * should be impossible to get here with such surfaces.
2600 assert(!srgb_enabled
||
2601 _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
);
2603 return ISL_AUX_USAGE_CCS_E
;
2607 return ISL_AUX_USAGE_NONE
;
2612 intel_miptree_prepare_render(struct brw_context
*brw
,
2613 struct intel_mipmap_tree
*mt
, uint32_t level
,
2614 uint32_t start_layer
, uint32_t layer_count
,
2617 enum isl_aux_usage aux_usage
=
2618 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
);
2619 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2620 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2624 intel_miptree_finish_render(struct brw_context
*brw
,
2625 struct intel_mipmap_tree
*mt
, uint32_t level
,
2626 uint32_t start_layer
, uint32_t layer_count
,
2629 assert(_mesa_is_format_color_format(mt
->format
));
2631 enum isl_aux_usage aux_usage
=
2632 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
);
2633 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2638 intel_miptree_prepare_depth(struct brw_context
*brw
,
2639 struct intel_mipmap_tree
*mt
, uint32_t level
,
2640 uint32_t start_layer
, uint32_t layer_count
)
2642 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2643 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2647 intel_miptree_finish_depth(struct brw_context
*brw
,
2648 struct intel_mipmap_tree
*mt
, uint32_t level
,
2649 uint32_t start_layer
, uint32_t layer_count
,
2652 if (depth_written
) {
2653 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2654 mt
->hiz_buf
!= NULL
);
2659 * Make it possible to share the BO backing the given miptree with another
2660 * process or another miptree.
2662 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2663 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2664 * ensure that no MCS buffer gets allocated in the future.
2666 * HiZ is similarly unsafe with shared buffers.
2669 intel_miptree_make_shareable(struct brw_context
*brw
,
2670 struct intel_mipmap_tree
*mt
)
2672 /* MCS buffers are also used for multisample buffers, but we can't resolve
2673 * away a multisample MCS buffer because it's an integral part of how the
2674 * pixel data is stored. Fortunately this code path should never be
2675 * reached for multisample buffers.
2677 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2678 mt
->surf
.samples
== 1);
2680 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2681 0, INTEL_REMAINING_LAYERS
,
2682 ISL_AUX_USAGE_NONE
, false);
2685 brw_bo_unreference(mt
->mcs_buf
->bo
);
2689 /* Any pending MCS/CCS operations are no longer needed. Trying to
2690 * execute any will likely crash due to the missing aux buffer. So let's
2691 * delete all pending ops.
2693 free(mt
->aux_state
);
2694 mt
->aux_state
= NULL
;
2698 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2701 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2702 mt
->level
[l
].has_hiz
= false;
2705 /* Any pending HiZ operations are no longer needed. Trying to execute
2706 * any will likely crash due to the missing aux buffer. So let's delete
2709 free(mt
->aux_state
);
2710 mt
->aux_state
= NULL
;
2713 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2718 * \brief Get pointer offset into stencil buffer.
2720 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2721 * must decode the tile's layout in software.
2724 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2726 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2728 * Even though the returned offset is always positive, the return type is
2730 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2731 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2734 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2736 uint32_t tile_size
= 4096;
2737 uint32_t tile_width
= 64;
2738 uint32_t tile_height
= 64;
2739 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2741 uint32_t tile_x
= x
/ tile_width
;
2742 uint32_t tile_y
= y
/ tile_height
;
2744 /* The byte's address relative to the tile's base addres. */
2745 uint32_t byte_x
= x
% tile_width
;
2746 uint32_t byte_y
= y
% tile_height
;
2748 uintptr_t u
= tile_y
* row_size
2749 + tile_x
* tile_size
2750 + 512 * (byte_x
/ 8)
2752 + 32 * ((byte_y
/ 4) % 2)
2753 + 16 * ((byte_x
/ 4) % 2)
2754 + 8 * ((byte_y
/ 2) % 2)
2755 + 4 * ((byte_x
/ 2) % 2)
2760 /* adjust for bit6 swizzling */
2761 if (((byte_x
/ 8) % 2) == 1) {
2762 if (((byte_y
/ 8) % 2) == 0) {
2774 intel_miptree_updownsample(struct brw_context
*brw
,
2775 struct intel_mipmap_tree
*src
,
2776 struct intel_mipmap_tree
*dst
)
2778 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2779 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2780 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2781 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2783 brw_blorp_blit_miptrees(brw
,
2784 src
, 0 /* level */, 0 /* layer */,
2785 src
->format
, SWIZZLE_XYZW
,
2786 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2789 GL_NEAREST
, false, false /*mirror x, y*/,
2792 if (src
->stencil_mt
) {
2793 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2794 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2795 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2796 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2798 brw_blorp_blit_miptrees(brw
,
2799 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2800 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2801 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2802 dst
->stencil_mt
->format
,
2805 GL_NEAREST
, false, false /*mirror x, y*/,
2806 false, false /* decode/encode srgb */);
2811 intel_update_r8stencil(struct brw_context
*brw
,
2812 struct intel_mipmap_tree
*mt
)
2814 assert(brw
->gen
>= 7);
2815 struct intel_mipmap_tree
*src
=
2816 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2817 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2820 assert(src
->surf
.size
> 0);
2822 if (!mt
->r8stencil_mt
) {
2823 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2824 mt
->r8stencil_mt
= make_surface(
2827 MESA_FORMAT_R_UINT8
,
2828 src
->first_level
, src
->last_level
,
2829 src
->surf
.logical_level0_px
.width
,
2830 src
->surf
.logical_level0_px
.height
,
2831 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2832 src
->surf
.logical_level0_px
.depth
:
2833 src
->surf
.logical_level0_px
.array_len
,
2836 ISL_SURF_USAGE_TEXTURE_BIT
,
2837 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2838 assert(mt
->r8stencil_mt
);
2841 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2843 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2844 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2845 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2846 src
->surf
.phys_level0_sa
.array_len
;
2848 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2849 brw_blorp_copy_miptrees(brw
,
2853 minify(src
->surf
.logical_level0_px
.width
,
2855 minify(src
->surf
.logical_level0_px
.height
,
2860 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2861 src
->r8stencil_needs_update
= false;
2865 intel_miptree_map_raw(struct brw_context
*brw
,
2866 struct intel_mipmap_tree
*mt
,
2869 struct brw_bo
*bo
= mt
->bo
;
2871 if (brw_batch_references(&brw
->batch
, bo
))
2872 intel_batchbuffer_flush(brw
);
2874 return brw_bo_map(brw
, bo
, mode
);
2878 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2880 brw_bo_unmap(mt
->bo
);
2884 intel_miptree_map_gtt(struct brw_context
*brw
,
2885 struct intel_mipmap_tree
*mt
,
2886 struct intel_miptree_map
*map
,
2887 unsigned int level
, unsigned int slice
)
2889 unsigned int bw
, bh
;
2891 unsigned int image_x
, image_y
;
2892 intptr_t x
= map
->x
;
2893 intptr_t y
= map
->y
;
2895 /* For compressed formats, the stride is the number of bytes per
2896 * row of blocks. intel_miptree_get_image_offset() already does
2899 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2900 assert(y
% bh
== 0);
2901 assert(x
% bw
== 0);
2905 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2912 /* Note that in the case of cube maps, the caller must have passed the
2913 * slice number referencing the face.
2915 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2919 map
->stride
= mt
->surf
.row_pitch
;
2920 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2923 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2924 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2925 map
->x
, map
->y
, map
->w
, map
->h
,
2926 mt
, _mesa_get_format_name(mt
->format
),
2927 x
, y
, map
->ptr
, map
->stride
);
2931 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2933 intel_miptree_unmap_raw(mt
);
2937 intel_miptree_map_blit(struct brw_context
*brw
,
2938 struct intel_mipmap_tree
*mt
,
2939 struct intel_miptree_map
*map
,
2940 unsigned int level
, unsigned int slice
)
2942 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2943 /* first_level */ 0,
2947 MIPTREE_LAYOUT_TILING_NONE
);
2949 if (!map
->linear_mt
) {
2950 fprintf(stderr
, "Failed to allocate blit temporary\n");
2953 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
2955 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2956 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2957 * invalidate is set, since we'll be writing the whole rectangle from our
2958 * temporary buffer back out.
2960 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2961 if (!intel_miptree_copy(brw
,
2962 mt
, level
, slice
, map
->x
, map
->y
,
2963 map
->linear_mt
, 0, 0, 0, 0,
2965 fprintf(stderr
, "Failed to blit\n");
2970 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2972 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2973 map
->x
, map
->y
, map
->w
, map
->h
,
2974 mt
, _mesa_get_format_name(mt
->format
),
2975 level
, slice
, map
->ptr
, map
->stride
);
2980 intel_miptree_release(&map
->linear_mt
);
2986 intel_miptree_unmap_blit(struct brw_context
*brw
,
2987 struct intel_mipmap_tree
*mt
,
2988 struct intel_miptree_map
*map
,
2992 struct gl_context
*ctx
= &brw
->ctx
;
2994 intel_miptree_unmap_raw(map
->linear_mt
);
2996 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2997 bool ok
= intel_miptree_copy(brw
,
2998 map
->linear_mt
, 0, 0, 0, 0,
2999 mt
, level
, slice
, map
->x
, map
->y
,
3001 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3004 intel_miptree_release(&map
->linear_mt
);
3008 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3010 #if defined(USE_SSE41)
3012 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3013 struct intel_mipmap_tree
*mt
,
3014 struct intel_miptree_map
*map
,
3015 unsigned int level
, unsigned int slice
)
3017 assert(map
->mode
& GL_MAP_READ_BIT
);
3018 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3020 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3021 map
->x
, map
->y
, map
->w
, map
->h
,
3022 mt
, _mesa_get_format_name(mt
->format
),
3023 level
, slice
, map
->ptr
, map
->stride
);
3025 /* Map the original image */
3028 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3032 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3038 src
+= image_y
* mt
->surf
.row_pitch
;
3039 src
+= image_x
* mt
->cpp
;
3041 /* Due to the pixel offsets for the particular image being mapped, our
3042 * src pointer may not be 16-byte aligned. However, if the pitch is
3043 * divisible by 16, then the amount by which it's misaligned will remain
3044 * consistent from row to row.
3046 assert((mt
->surf
.row_pitch
% 16) == 0);
3047 const int misalignment
= ((uintptr_t) src
) & 15;
3049 /* Create an untiled temporary buffer for the mapping. */
3050 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3052 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3054 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3055 /* Offset the destination so it has the same misalignment as src. */
3056 map
->ptr
= map
->buffer
+ misalignment
;
3058 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3060 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3061 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3062 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3064 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3067 intel_miptree_unmap_raw(mt
);
3071 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3072 struct intel_mipmap_tree
*mt
,
3073 struct intel_miptree_map
*map
,
3077 _mesa_align_free(map
->buffer
);
3084 intel_miptree_map_s8(struct brw_context
*brw
,
3085 struct intel_mipmap_tree
*mt
,
3086 struct intel_miptree_map
*map
,
3087 unsigned int level
, unsigned int slice
)
3089 map
->stride
= map
->w
;
3090 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3094 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3095 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3096 * invalidate is set, since we'll be writing the whole rectangle from our
3097 * temporary buffer back out.
3099 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3100 uint8_t *untiled_s8_map
= map
->ptr
;
3101 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3102 unsigned int image_x
, image_y
;
3104 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3106 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3107 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3108 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3109 x
+ image_x
+ map
->x
,
3110 y
+ image_y
+ map
->y
,
3111 brw
->has_swizzling
);
3112 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3116 intel_miptree_unmap_raw(mt
);
3118 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3119 map
->x
, map
->y
, map
->w
, map
->h
,
3120 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3122 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3123 map
->x
, map
->y
, map
->w
, map
->h
,
3124 mt
, map
->ptr
, map
->stride
);
3129 intel_miptree_unmap_s8(struct brw_context
*brw
,
3130 struct intel_mipmap_tree
*mt
,
3131 struct intel_miptree_map
*map
,
3135 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3136 unsigned int image_x
, image_y
;
3137 uint8_t *untiled_s8_map
= map
->ptr
;
3138 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3140 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3142 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3143 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3144 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3145 image_x
+ x
+ map
->x
,
3146 image_y
+ y
+ map
->y
,
3147 brw
->has_swizzling
);
3148 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3152 intel_miptree_unmap_raw(mt
);
3159 intel_miptree_map_etc(struct brw_context
*brw
,
3160 struct intel_mipmap_tree
*mt
,
3161 struct intel_miptree_map
*map
,
3165 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3166 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3167 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3170 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3171 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3173 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3174 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3175 map
->w
, map
->h
, 1));
3176 map
->ptr
= map
->buffer
;
3180 intel_miptree_unmap_etc(struct brw_context
*brw
,
3181 struct intel_mipmap_tree
*mt
,
3182 struct intel_miptree_map
*map
,
3188 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3193 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3194 + image_y
* mt
->surf
.row_pitch
3195 + image_x
* mt
->cpp
;
3197 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3198 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3199 map
->ptr
, map
->stride
,
3202 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3203 map
->ptr
, map
->stride
,
3204 map
->w
, map
->h
, mt
->etc_format
);
3206 intel_miptree_unmap_raw(mt
);
3211 * Mapping function for packed depth/stencil miptrees backed by real separate
3212 * miptrees for depth and stencil.
3214 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3215 * separate from the depth buffer. Yet at the GL API level, we have to expose
3216 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3217 * be able to map that memory for texture storage and glReadPixels-type
3218 * operations. We give Mesa core that access by mallocing a temporary and
3219 * copying the data between the actual backing store and the temporary.
3222 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3223 struct intel_mipmap_tree
*mt
,
3224 struct intel_miptree_map
*map
,
3225 unsigned int level
, unsigned int slice
)
3227 struct intel_mipmap_tree
*z_mt
= mt
;
3228 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3229 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3230 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3232 map
->stride
= map
->w
* packed_bpp
;
3233 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3237 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3238 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3239 * invalidate is set, since we'll be writing the whole rectangle from our
3240 * temporary buffer back out.
3242 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3243 uint32_t *packed_map
= map
->ptr
;
3244 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3245 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3246 unsigned int s_image_x
, s_image_y
;
3247 unsigned int z_image_x
, z_image_y
;
3249 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3250 &s_image_x
, &s_image_y
);
3251 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3252 &z_image_x
, &z_image_y
);
3254 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3255 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3256 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3257 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3260 brw
->has_swizzling
);
3261 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3262 (z_mt
->surf
.row_pitch
/ 4) +
3263 (map_x
+ z_image_x
));
3264 uint8_t s
= s_map
[s_offset
];
3265 uint32_t z
= z_map
[z_offset
];
3267 if (map_z32f_x24s8
) {
3268 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3269 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3271 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3276 intel_miptree_unmap_raw(s_mt
);
3277 intel_miptree_unmap_raw(z_mt
);
3279 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3281 map
->x
, map
->y
, map
->w
, map
->h
,
3282 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3283 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3284 map
->ptr
, map
->stride
);
3286 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3287 map
->x
, map
->y
, map
->w
, map
->h
,
3288 mt
, map
->ptr
, map
->stride
);
3293 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3294 struct intel_mipmap_tree
*mt
,
3295 struct intel_miptree_map
*map
,
3299 struct intel_mipmap_tree
*z_mt
= mt
;
3300 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3301 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3303 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3304 uint32_t *packed_map
= map
->ptr
;
3305 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3306 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3307 unsigned int s_image_x
, s_image_y
;
3308 unsigned int z_image_x
, z_image_y
;
3310 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3311 &s_image_x
, &s_image_y
);
3312 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3313 &z_image_x
, &z_image_y
);
3315 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3316 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3317 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3318 x
+ s_image_x
+ map
->x
,
3319 y
+ s_image_y
+ map
->y
,
3320 brw
->has_swizzling
);
3321 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3322 (z_mt
->surf
.row_pitch
/ 4) +
3323 (x
+ z_image_x
+ map
->x
));
3325 if (map_z32f_x24s8
) {
3326 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3327 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3329 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3330 s_map
[s_offset
] = packed
>> 24;
3331 z_map
[z_offset
] = packed
;
3336 intel_miptree_unmap_raw(s_mt
);
3337 intel_miptree_unmap_raw(z_mt
);
3339 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3341 map
->x
, map
->y
, map
->w
, map
->h
,
3342 z_mt
, _mesa_get_format_name(z_mt
->format
),
3343 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3344 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3345 map
->ptr
, map
->stride
);
3352 * Create and attach a map to the miptree at (level, slice). Return the
3355 static struct intel_miptree_map
*
3356 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3365 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3370 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3371 mt
->level
[level
].slice
[slice
].map
= map
;
3383 * Release the map at (level, slice).
3386 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3390 struct intel_miptree_map
**map
;
3392 map
= &mt
->level
[level
].slice
[slice
].map
;
3398 can_blit_slice(struct intel_mipmap_tree
*mt
,
3399 unsigned int level
, unsigned int slice
)
3401 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3402 if (mt
->surf
.row_pitch
>= 32768)
3409 use_intel_mipree_map_blit(struct brw_context
*brw
,
3410 struct intel_mipmap_tree
*mt
,
3416 /* It's probably not worth swapping to the blit ring because of
3417 * all the overhead involved.
3419 !(mode
& GL_MAP_WRITE_BIT
) &&
3421 (mt
->surf
.tiling
== ISL_TILING_X
||
3422 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3423 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3424 /* Fast copy blit on skl+ supports all tiling formats. */
3426 can_blit_slice(mt
, level
, slice
))
3429 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3430 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3431 assert(can_blit_slice(mt
, level
, slice
));
3439 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3440 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3441 * arithmetic overflow.
3443 * If you call this function and use \a out_stride, then you're doing pointer
3444 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3445 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3446 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3447 * which usually have type uint32_t or GLuint.
3450 intel_miptree_map(struct brw_context
*brw
,
3451 struct intel_mipmap_tree
*mt
,
3460 ptrdiff_t *out_stride
)
3462 struct intel_miptree_map
*map
;
3464 assert(mt
->surf
.samples
== 1);
3466 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3473 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3474 map
->mode
& GL_MAP_WRITE_BIT
);
3476 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3477 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3478 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3479 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3480 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3481 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3482 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3483 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3484 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3485 #if defined(USE_SSE41)
3486 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3487 !mt
->compressed
&& cpu_has_sse4_1
&&
3488 (mt
->surf
.row_pitch
% 16 == 0)) {
3489 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3492 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3495 *out_ptr
= map
->ptr
;
3496 *out_stride
= map
->stride
;
3498 if (map
->ptr
== NULL
)
3499 intel_miptree_release_map(mt
, level
, slice
);
3503 intel_miptree_unmap(struct brw_context
*brw
,
3504 struct intel_mipmap_tree
*mt
,
3508 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3510 assert(mt
->surf
.samples
== 1);
3515 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3516 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3518 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3519 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3520 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3521 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3522 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3523 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3524 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3525 } else if (map
->linear_mt
) {
3526 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3527 #if defined(USE_SSE41)
3528 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3529 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3532 intel_miptree_unmap_gtt(mt
);
3535 intel_miptree_release_map(mt
, level
, slice
);
3539 get_isl_surf_dim(GLenum target
)
3543 case GL_TEXTURE_1D_ARRAY
:
3544 return ISL_SURF_DIM_1D
;
3547 case GL_TEXTURE_2D_ARRAY
:
3548 case GL_TEXTURE_RECTANGLE
:
3549 case GL_TEXTURE_CUBE_MAP
:
3550 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3551 case GL_TEXTURE_2D_MULTISAMPLE
:
3552 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3553 case GL_TEXTURE_EXTERNAL_OES
:
3554 return ISL_SURF_DIM_2D
;
3557 return ISL_SURF_DIM_3D
;
3560 unreachable("Invalid texture target");
3564 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3565 enum isl_tiling tiling
, GLenum target
)
3569 case GL_TEXTURE_1D_ARRAY
:
3570 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3571 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3574 case GL_TEXTURE_2D_ARRAY
:
3575 case GL_TEXTURE_RECTANGLE
:
3576 case GL_TEXTURE_2D_MULTISAMPLE
:
3577 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3578 case GL_TEXTURE_EXTERNAL_OES
:
3579 return ISL_DIM_LAYOUT_GEN4_2D
;
3581 case GL_TEXTURE_CUBE_MAP
:
3582 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3583 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3584 ISL_DIM_LAYOUT_GEN4_2D
);
3587 return (devinfo
->gen
>= 9 ?
3588 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3591 unreachable("Invalid texture target");
3595 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3596 const struct intel_mipmap_tree
*mt
)
3599 return ISL_AUX_USAGE_HIZ
;
3602 return ISL_AUX_USAGE_NONE
;
3604 return mt
->aux_usage
;