2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
67 /* MCS compression only applies to multisampled miptrees */
68 if (mt
->surf
.samples
<= 1)
71 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
75 /* See isl_surf_get_mcs_surf for details. */
76 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(mt
->format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
106 intel_tiling_supports_ccs(const struct brw_context
*brw
,
107 enum isl_tiling tiling
)
109 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
111 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
112 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
114 * - Support is limited to tiled render targets.
116 * Gen9 changes the restriction to Y-tile only.
118 if (devinfo
->gen
>= 9)
119 return tiling
== ISL_TILING_Y0
;
120 else if (devinfo
->gen
>= 7)
121 return tiling
!= ISL_TILING_LINEAR
;
127 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
128 * can be used. This doesn't (and should not) inspect any of the properties of
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p326):
134 * - Support is for non-mip-mapped and non-array surface types only.
136 * And then later, on p327:
138 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
141 * From the Skylake documentation, it is made clear that X-tiling is no longer
144 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
148 intel_miptree_supports_ccs(struct brw_context
*brw
,
149 const struct intel_mipmap_tree
*mt
)
151 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
153 /* MCS support does not exist prior to Gen7 */
154 if (devinfo
->gen
< 7)
157 /* This function applies only to non-multisampled render targets. */
158 if (mt
->surf
.samples
> 1)
161 /* MCS is only supported for color buffers */
162 if (!_mesa_is_format_color_format(mt
->format
))
165 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
168 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
169 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
170 mt
->surf
.logical_level0_px
.depth
> 1;
173 /* Multisample surfaces with the CMS layout are not layered surfaces,
174 * yet still have physical_depth0 > 1. Assert that we don't
175 * accidentally reject a multisampled surface here. We should have
176 * rejected it earlier by explicitly checking the sample count.
178 assert(mt
->surf
.samples
== 1);
181 /* Handle the hardware restrictions...
183 * All GENs have the following restriction: "MCS buffer for non-MSRT is
184 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
186 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
187 * Non-MultiSampler Render Target Restrictions) Support is for
188 * non-mip-mapped and non-array surface types only.
190 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
195 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
200 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
203 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
204 * work for 3D textures until gen9 where the layout of 3D textures changes
205 * to match 2D array textures.
207 if (devinfo
->gen
<= 8 && mt
->surf
.dim
!= ISL_SURF_DIM_2D
)
210 /* There's no point in using an MCS buffer if the surface isn't in a
213 if (!brw
->mesa_format_supports_render
[mt
->format
])
220 intel_tiling_supports_hiz(const struct brw_context
*brw
,
221 enum isl_tiling tiling
)
223 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
225 if (devinfo
->gen
< 6)
228 return tiling
== ISL_TILING_Y0
;
232 intel_miptree_supports_hiz(const struct brw_context
*brw
,
233 const struct intel_mipmap_tree
*mt
)
238 switch (mt
->format
) {
239 case MESA_FORMAT_Z_FLOAT32
:
240 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
241 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
242 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
243 case MESA_FORMAT_Z_UNORM16
:
251 * Return true if the format that will be used to access the miptree is
252 * CCS_E-compatible with the miptree's linear/non-sRGB format.
254 * Why use the linear format? Well, although the miptree may be specified with
255 * an sRGB format, the usage of that color space/format can be toggled. Since
256 * our HW tends to support more linear formats than sRGB ones, we use this
257 * format variant for check for CCS_E compatibility.
260 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
261 const struct intel_mipmap_tree
*mt
,
262 enum isl_format access_format
)
264 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
266 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
267 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
268 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
272 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
273 const struct intel_mipmap_tree
*mt
)
275 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
277 if (devinfo
->gen
< 9)
280 /* For now compression is only enabled for integer formats even though
281 * there exist supported floating point formats also. This is a heuristic
282 * decision based on current public benchmarks. In none of the cases these
283 * formats provided any improvement but a few cases were seen to regress.
284 * Hence these are left to to be enabled in the future when they are known
287 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
290 if (!intel_miptree_supports_ccs(brw
, mt
))
293 /* Many window system buffers are sRGB even if they are never rendered as
294 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
295 * surface is used as sRGB, we fall back to CCS_D.
297 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
298 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
299 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
303 * Determine depth format corresponding to a depth+stencil format,
304 * for separate stencil.
307 intel_depth_format_for_depthstencil_format(mesa_format format
) {
309 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
310 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
311 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
312 return MESA_FORMAT_Z_FLOAT32
;
319 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
320 unsigned depth0
, struct intel_mipmap_level
*table
)
322 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
324 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
326 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
327 if (!table
[level
].slice
)
334 for (unsigned level
= first_level
; level
<= last_level
; level
++)
335 free(table
[level
].slice
);
341 needs_separate_stencil(const struct brw_context
*brw
,
342 struct intel_mipmap_tree
*mt
,
345 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
347 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
350 if (devinfo
->must_use_separate_stencil
)
353 return brw
->has_separate_stencil
&&
354 intel_miptree_supports_hiz(brw
, mt
);
358 * Choose the aux usage for this miptree. This function must be called fairly
359 * late in the miptree create process after we have a tiling.
362 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
363 struct intel_mipmap_tree
*mt
)
365 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
367 if (intel_miptree_supports_mcs(brw
, mt
)) {
368 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
369 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
370 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
371 intel_miptree_supports_ccs(brw
, mt
)) {
372 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
373 intel_miptree_supports_ccs_e(brw
, mt
)) {
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
378 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
379 intel_miptree_supports_hiz(brw
, mt
)) {
380 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
383 /* We can do fast-clear on all auxiliary surface types that are
384 * allocated through the normal texture creation paths.
386 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
387 mt
->supports_fast_clear
= true;
392 * Choose an appropriate uncompressed format for a requested
393 * compressed format, if unsupported.
396 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
398 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
400 /* No need to lower ETC formats on these platforms,
401 * they are supported natively.
403 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
407 case MESA_FORMAT_ETC1_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_SRGB8
:
412 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
413 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
414 return MESA_FORMAT_B8G8R8A8_SRGB
;
415 case MESA_FORMAT_ETC2_RGBA8_EAC
:
416 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
417 return MESA_FORMAT_R8G8B8A8_UNORM
;
418 case MESA_FORMAT_ETC2_R11_EAC
:
419 return MESA_FORMAT_R_UNORM16
;
420 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
421 return MESA_FORMAT_R_SNORM16
;
422 case MESA_FORMAT_ETC2_RG11_EAC
:
423 return MESA_FORMAT_R16G16_UNORM
;
424 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
425 return MESA_FORMAT_R16G16_SNORM
;
427 /* Non ETC1 / ETC2 format */
433 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
435 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
436 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
438 return mt
->surf
.logical_level0_px
.array_len
;
441 UNUSED
static unsigned
442 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
444 /* In case of physical dimensions one needs to consider also the layout.
445 * See isl_calc_phys_level0_extent_sa().
447 if (surf
->dim
!= ISL_SURF_DIM_3D
)
448 return surf
->phys_level0_sa
.array_len
;
450 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
451 return minify(surf
->phys_level0_sa
.array_len
, level
);
453 return minify(surf
->phys_level0_sa
.depth
, level
);
456 /** \brief Assert that the level and layer are valid for the miptree. */
458 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
466 assert(level
>= mt
->first_level
);
467 assert(level
<= mt
->last_level
);
468 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
471 static enum isl_aux_state
**
472 create_aux_state_map(struct intel_mipmap_tree
*mt
,
473 enum isl_aux_state initial
)
475 const uint32_t levels
= mt
->last_level
+ 1;
477 uint32_t total_slices
= 0;
478 for (uint32_t level
= 0; level
< levels
; level
++)
479 total_slices
+= brw_get_num_logical_layers(mt
, level
);
481 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
483 /* We're going to allocate a single chunk of data for both the per-level
484 * reference array and the arrays of aux_state. This makes cleanup
485 * significantly easier.
487 const size_t total_size
= per_level_array_size
+
488 total_slices
* sizeof(enum isl_aux_state
);
489 void *data
= malloc(total_size
);
493 enum isl_aux_state
**per_level_arr
= data
;
494 enum isl_aux_state
*s
= data
+ per_level_array_size
;
495 for (uint32_t level
= 0; level
< levels
; level
++) {
496 per_level_arr
[level
] = s
;
497 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
498 for (uint32_t a
= 0; a
< level_layers
; a
++)
501 assert((void *)s
== data
+ total_size
);
503 return per_level_arr
;
507 free_aux_state_map(enum isl_aux_state
**state
)
513 need_to_retile_as_linear(struct brw_context
*brw
, unsigned blt_pitch
,
514 enum isl_tiling tiling
, unsigned samples
)
519 if (tiling
== ISL_TILING_LINEAR
)
522 if (blt_pitch
>= 32768) {
523 perf_debug("blt pitch %u too large to blit, falling back to untiled",
532 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
533 enum isl_tiling tiling
)
535 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
537 /* If the BO is too large to fit in the aperture, we need to use the
538 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
539 * handle Y-tiling, so we need to fall back to X.
541 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
542 tiling
== ISL_TILING_Y0
)
548 static struct intel_mipmap_tree
*
549 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
550 unsigned first_level
, unsigned last_level
,
551 unsigned width0
, unsigned height0
, unsigned depth0
,
552 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
553 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
554 unsigned row_pitch
, struct brw_bo
*bo
)
556 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
560 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
568 if (target
== GL_TEXTURE_CUBE_MAP
||
569 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
570 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
572 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
574 _mesa_enum_to_string(target
),
575 _mesa_get_format_name(format
),
576 num_samples
, width0
, height0
, depth0
,
577 first_level
, last_level
, mt
);
579 struct isl_surf_init_info init_info
= {
580 .dim
= get_isl_surf_dim(target
),
581 .format
= translate_tex_format(brw
, format
, false),
584 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
585 .levels
= last_level
- first_level
+ 1,
586 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
587 .samples
= num_samples
,
588 .row_pitch
= row_pitch
,
589 .usage
= isl_usage_flags
,
590 .tiling_flags
= tiling_flags
,
593 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
596 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
597 * on gen7 platforms we also need to create Y-tiled copies of stencil for
598 * texturing since the hardware can't sample from W-tiled surfaces. For
599 * everything else, check for corner cases needing special treatment.
601 bool is_depth_stencil
=
602 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
603 if (!is_depth_stencil
) {
604 if (need_to_retile_as_linear(brw
, intel_miptree_blt_pitch(mt
),
605 mt
->surf
.tiling
, mt
->surf
.samples
)) {
606 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
607 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
609 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
610 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
611 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
616 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
617 * the size may not be multiple of row_pitch.
618 * See isl_apply_surface_padding().
620 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
621 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
624 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
627 isl_tiling_to_i915_tiling(
629 mt
->surf
.row_pitch
, alloc_flags
);
636 mt
->first_level
= first_level
;
637 mt
->last_level
= last_level
;
640 mt
->aux_state
= NULL
;
641 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
642 mt
->compressed
= _mesa_is_format_compressed(format
);
643 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
648 intel_miptree_release(&mt
);
653 make_separate_stencil_surface(struct brw_context
*brw
,
654 struct intel_mipmap_tree
*mt
)
656 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
657 0, mt
->surf
.levels
- 1,
658 mt
->surf
.logical_level0_px
.width
,
659 mt
->surf
.logical_level0_px
.height
,
660 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
661 mt
->surf
.logical_level0_px
.depth
:
662 mt
->surf
.logical_level0_px
.array_len
,
663 mt
->surf
.samples
, ISL_TILING_W_BIT
,
664 ISL_SURF_USAGE_STENCIL_BIT
|
665 ISL_SURF_USAGE_TEXTURE_BIT
,
666 BO_ALLOC_BUSY
, 0, NULL
);
671 mt
->stencil_mt
->r8stencil_needs_update
= true;
676 static struct intel_mipmap_tree
*
677 miptree_create(struct brw_context
*brw
,
686 enum intel_miptree_create_flags flags
)
688 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
689 const uint32_t alloc_flags
= (flags
& MIPTREE_CREATE_BUSY
) ?
691 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
693 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
694 if (devinfo
->gen
< 6 && _mesa_is_format_color_format(format
))
695 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
698 if (_mesa_is_format_color_format(format
)) {
699 mt_fmt
= intel_lower_compressed_format(brw
, format
);
701 /* Fix up the Z miptree format for how we're splitting out separate
702 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
704 mt_fmt
= (devinfo
->gen
< 6) ? format
:
705 intel_depth_format_for_depthstencil_format(format
);
708 if (format
== MESA_FORMAT_S_UINT8
)
709 return make_surface(brw
, target
, mt_fmt
, first_level
, last_level
,
710 width0
, height0
, depth0
, num_samples
,
712 ISL_SURF_USAGE_STENCIL_BIT
|
713 ISL_SURF_USAGE_TEXTURE_BIT
,
718 const GLenum base_format
= _mesa_get_format_base_format(format
);
719 if ((base_format
== GL_DEPTH_COMPONENT
||
720 base_format
== GL_DEPTH_STENCIL
)) {
721 struct intel_mipmap_tree
*mt
= make_surface(
723 first_level
, last_level
,
724 width0
, height0
, depth0
, num_samples
, tiling_flags
,
725 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
726 alloc_flags
, 0, NULL
);
728 if (needs_separate_stencil(brw
, mt
, format
) &&
729 !make_separate_stencil_surface(brw
, mt
)) {
730 intel_miptree_release(&mt
);
734 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
735 intel_miptree_choose_aux_usage(brw
, mt
);
740 struct intel_mipmap_tree
*mt
= make_surface(
742 first_level
, last_level
,
743 width0
, height0
, depth0
,
744 num_samples
, tiling_flags
,
745 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
746 ISL_SURF_USAGE_TEXTURE_BIT
,
747 alloc_flags
, 0, NULL
);
751 mt
->etc_format
= (mt_fmt
!= format
) ? format
: MESA_FORMAT_NONE
;
753 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
754 intel_miptree_choose_aux_usage(brw
, mt
);
759 struct intel_mipmap_tree
*
760 intel_miptree_create(struct brw_context
*brw
,
769 enum intel_miptree_create_flags flags
)
771 assert(num_samples
> 0);
773 struct intel_mipmap_tree
*mt
= miptree_create(
775 first_level
, last_level
,
776 width0
, height0
, depth0
, num_samples
,
783 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
784 * compress clear color so we wait until an actual fast-clear to allocate
787 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
788 !intel_miptree_alloc_aux(brw
, mt
)) {
789 intel_miptree_release(&mt
);
796 struct intel_mipmap_tree
*
797 intel_miptree_create_for_bo(struct brw_context
*brw
,
805 enum isl_tiling tiling
,
806 enum intel_miptree_create_flags flags
)
808 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
809 struct intel_mipmap_tree
*mt
;
810 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
811 const GLenum base_format
= _mesa_get_format_base_format(format
);
813 if ((base_format
== GL_DEPTH_COMPONENT
||
814 base_format
== GL_DEPTH_STENCIL
)) {
815 const mesa_format depth_only_format
=
816 intel_depth_format_for_depthstencil_format(format
);
817 mt
= make_surface(brw
, target
,
818 devinfo
->gen
>= 6 ? depth_only_format
: format
,
819 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
820 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
825 brw_bo_reference(bo
);
827 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
828 intel_miptree_choose_aux_usage(brw
, mt
);
831 } else if (format
== MESA_FORMAT_S_UINT8
) {
832 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
833 0, 0, width
, height
, depth
, 1,
835 ISL_SURF_USAGE_STENCIL_BIT
|
836 ISL_SURF_USAGE_TEXTURE_BIT
,
841 assert(bo
->size
>= mt
->surf
.size
);
843 brw_bo_reference(bo
);
847 /* Nothing will be able to use this miptree with the BO if the offset isn't
850 if (tiling
!= ISL_TILING_LINEAR
)
851 assert(offset
% 4096 == 0);
853 /* miptrees can't handle negative pitch. If you need flipping of images,
854 * that's outside of the scope of the mt.
858 mt
= make_surface(brw
, target
, format
,
859 0, 0, width
, height
, depth
, 1,
861 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
862 ISL_SURF_USAGE_TEXTURE_BIT
,
867 brw_bo_reference(bo
);
871 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
872 intel_miptree_choose_aux_usage(brw
, mt
);
874 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
875 * only compress clear color so we wait until an actual fast-clear to
878 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
879 !intel_miptree_alloc_aux(brw
, mt
)) {
880 intel_miptree_release(&mt
);
888 static struct intel_mipmap_tree
*
889 miptree_create_for_planar_image(struct brw_context
*brw
,
890 __DRIimage
*image
, GLenum target
,
891 enum isl_tiling tiling
)
893 const struct intel_image_format
*f
= image
->planar_format
;
894 struct intel_mipmap_tree
*planar_mt
= NULL
;
896 for (int i
= 0; i
< f
->nplanes
; i
++) {
897 const int index
= f
->planes
[i
].buffer_index
;
898 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
899 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
900 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
901 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
903 /* Disable creation of the texture's aux buffers because the driver
904 * exposes no EGL API to manage them. That is, there is no API for
905 * resolving the aux buffer's content to the main buffer nor for
906 * invalidating the aux buffer's content.
908 struct intel_mipmap_tree
*mt
=
909 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
910 image
->offsets
[index
],
912 image
->strides
[index
],
914 MIPTREE_CREATE_NO_AUX
);
916 intel_miptree_release(&planar_mt
);
925 planar_mt
->plane
[i
- 1] = mt
;
928 planar_mt
->drm_modifier
= image
->modifier
;
934 create_ccs_buf_for_image(struct brw_context
*brw
,
936 struct intel_mipmap_tree
*mt
,
937 enum isl_aux_state initial_state
)
939 struct isl_surf temp_ccs_surf
;
941 /* CCS is only supported for very simple miptrees */
942 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
943 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
944 assert(mt
->surf
.samples
== 1);
945 assert(mt
->surf
.levels
== 1);
946 assert(mt
->surf
.logical_level0_px
.depth
== 1);
947 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
948 assert(mt
->first_level
== 0);
949 assert(mt
->last_level
== 0);
951 /* We shouldn't already have a CCS */
952 assert(!mt
->aux_buf
);
954 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
958 assert(image
->aux_offset
< image
->bo
->size
);
959 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
961 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
962 if (mt
->aux_buf
== NULL
)
965 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
966 if (!mt
->aux_state
) {
972 /* On gen10+ we start using an extra space in the aux buffer to store the
973 * indirect clear color. However, if we imported an image from the window
974 * system with CCS, we don't have the extra space at the end of the aux
975 * buffer. So create a new bo here that will store that clear color.
977 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
978 mt
->aux_buf
->clear_color_bo
=
979 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
980 brw
->isl_dev
.ss
.clear_color_state_size
,
981 BRW_MEMZONE_OTHER
, I915_TILING_NONE
, 0,
983 if (!mt
->aux_buf
->clear_color_bo
) {
990 mt
->aux_buf
->bo
= image
->bo
;
991 brw_bo_reference(image
->bo
);
993 mt
->aux_buf
->offset
= image
->aux_offset
;
994 mt
->aux_buf
->surf
= temp_ccs_surf
;
999 struct intel_mipmap_tree
*
1000 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1001 __DRIimage
*image
, GLenum target
,
1003 bool allow_internal_aux
)
1005 uint32_t bo_tiling
, bo_swizzle
;
1006 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1008 const struct isl_drm_modifier_info
*mod_info
=
1009 isl_drm_modifier_get_info(image
->modifier
);
1011 const enum isl_tiling tiling
=
1012 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1014 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1015 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1017 if (image
->planar_format
)
1018 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1020 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1021 /* The texture storage paths in core Mesa detect if the driver does not
1022 * support the user-requested format, and then searches for a
1023 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1024 * do the fallbacks here for important formats.
1026 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1027 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1028 * the Chrome OS compositor consumes as dma_buf EGLImages.
1030 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1033 if (!brw
->ctx
.TextureFormatSupported
[format
])
1036 enum intel_miptree_create_flags mt_create_flags
= 0;
1038 /* If this image comes in from a window system, we have different
1039 * requirements than if it comes in via an EGL import operation. Window
1040 * system images can use any form of auxiliary compression we wish because
1041 * they get "flushed" before being handed off to the window system and we
1042 * have the opportunity to do resolves. Non window-system images, on the
1043 * other hand, have no resolve point so we can't have aux without a
1046 if (!allow_internal_aux
)
1047 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1049 /* If we have a modifier which specifies aux, don't create one yet */
1050 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1051 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1053 /* Disable creation of the texture's aux buffers because the driver exposes
1054 * no EGL API to manage them. That is, there is no API for resolving the aux
1055 * buffer's content to the main buffer nor for invalidating the aux buffer's
1058 struct intel_mipmap_tree
*mt
=
1059 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1060 image
->offset
, image
->width
, image
->height
, 1,
1061 image
->pitch
, tiling
, mt_create_flags
);
1065 mt
->target
= target
;
1066 mt
->level
[0].level_x
= image
->tile_x
;
1067 mt
->level
[0].level_y
= image
->tile_y
;
1068 mt
->drm_modifier
= image
->modifier
;
1070 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1071 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1072 * trouble resolving back to destination image due to alignment issues.
1074 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1075 if (!devinfo
->has_surface_tile_offset
) {
1076 uint32_t draw_x
, draw_y
;
1077 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1079 if (draw_x
!= 0 || draw_y
!= 0) {
1080 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1081 intel_miptree_release(&mt
);
1086 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1087 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1089 mt
->aux_usage
= mod_info
->aux_usage
;
1090 /* If we are a window system buffer, then we can support fast-clears
1091 * even if the modifier doesn't support them by doing a partial resolve
1092 * as part of the flush operation.
1094 mt
->supports_fast_clear
=
1095 allow_internal_aux
|| mod_info
->supports_clear_color
;
1097 /* We don't know the actual state of the surface when we get it but we
1098 * can make a pretty good guess based on the modifier. What we do know
1099 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1100 * a worst case of compression.
1102 enum isl_aux_state initial_state
=
1103 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1105 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1106 intel_miptree_release(&mt
);
1111 /* Don't assume coherency for imported EGLimages. We don't know what
1112 * external clients are going to do with it. They may scan it out.
1114 image
->bo
->cache_coherent
= false;
1120 * For a singlesample renderbuffer, this simply wraps the given BO with a
1123 * For a multisample renderbuffer, this wraps the window system's
1124 * (singlesample) BO with a singlesample miptree attached to the
1125 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1126 * that will contain the actual rendering (which is lazily resolved to
1127 * irb->singlesample_mt).
1130 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1131 struct intel_renderbuffer
*irb
,
1132 struct intel_mipmap_tree
*singlesample_mt
,
1133 uint32_t width
, uint32_t height
,
1136 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1137 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1138 mesa_format format
= rb
->Format
;
1139 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1141 /* Only the front and back buffers, which are color buffers, are allocated
1142 * through the image loader.
1144 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1145 _mesa_get_format_base_format(format
) == GL_RGBA
);
1147 assert(singlesample_mt
);
1149 if (num_samples
== 1) {
1150 intel_miptree_release(&irb
->mt
);
1151 irb
->mt
= singlesample_mt
;
1153 assert(!irb
->singlesample_mt
);
1155 intel_miptree_release(&irb
->singlesample_mt
);
1156 irb
->singlesample_mt
= singlesample_mt
;
1159 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1160 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1161 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1166 if (!multisample_mt
)
1169 irb
->need_downsample
= false;
1170 intel_miptree_release(&irb
->mt
);
1171 irb
->mt
= multisample_mt
;
1177 intel_miptree_release(&irb
->mt
);
1181 struct intel_mipmap_tree
*
1182 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1186 uint32_t num_samples
)
1188 struct intel_mipmap_tree
*mt
;
1190 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1192 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1193 width
, height
, depth
, num_samples
,
1194 MIPTREE_CREATE_BUSY
);
1201 intel_miptree_release(&mt
);
1206 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1207 struct intel_mipmap_tree
*src
)
1212 intel_miptree_release(dst
);
1216 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1223 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1225 if (aux_buf
== NULL
)
1228 brw_bo_unreference(aux_buf
->bo
);
1229 brw_bo_unreference(aux_buf
->clear_color_bo
);
1235 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1240 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1241 if (--(*mt
)->refcount
<= 0) {
1244 DBG("%s deleting %p\n", __func__
, *mt
);
1246 brw_bo_unreference((*mt
)->bo
);
1247 intel_miptree_release(&(*mt
)->stencil_mt
);
1248 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1249 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1250 free_aux_state_map((*mt
)->aux_state
);
1252 intel_miptree_release(&(*mt
)->plane
[0]);
1253 intel_miptree_release(&(*mt
)->plane
[1]);
1255 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1256 free((*mt
)->level
[i
].slice
);
1266 intel_get_image_dims(struct gl_texture_image
*image
,
1267 int *width
, int *height
, int *depth
)
1269 switch (image
->TexObject
->Target
) {
1270 case GL_TEXTURE_1D_ARRAY
:
1271 /* For a 1D Array texture the OpenGL API will treat the image height as
1272 * the number of array slices. For Intel hardware, we treat the 1D array
1273 * as a 2D Array with a height of 1. So, here we want to swap image
1276 assert(image
->Depth
== 1);
1277 *width
= image
->Width
;
1279 *depth
= image
->Height
;
1281 case GL_TEXTURE_CUBE_MAP
:
1282 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1283 * though we really have 6 slices.
1285 assert(image
->Depth
== 1);
1286 *width
= image
->Width
;
1287 *height
= image
->Height
;
1291 *width
= image
->Width
;
1292 *height
= image
->Height
;
1293 *depth
= image
->Depth
;
1299 * Can the image be pulled into a unified mipmap tree? This mirrors
1300 * the completeness test in a lot of ways.
1302 * Not sure whether I want to pass gl_texture_image here.
1305 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1306 struct gl_texture_image
*image
)
1308 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1309 GLuint level
= intelImage
->base
.Base
.Level
;
1310 int width
, height
, depth
;
1312 /* glTexImage* choose the texture object based on the target passed in, and
1313 * objects can't change targets over their lifetimes, so this should be
1316 assert(image
->TexObject
->Target
== mt
->target
);
1318 mesa_format mt_format
= mt
->format
;
1319 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1320 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1321 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1322 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1323 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1324 mt_format
= mt
->etc_format
;
1326 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1327 _mesa_get_srgb_format_linear(mt_format
))
1330 intel_get_image_dims(image
, &width
, &height
, &depth
);
1332 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1335 if (level
>= mt
->surf
.levels
)
1338 const unsigned level_depth
=
1339 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1340 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1341 mt
->surf
.logical_level0_px
.array_len
;
1343 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1344 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1345 depth
== level_depth
&&
1346 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1350 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1351 GLuint level
, GLuint slice
,
1352 GLuint
*x
, GLuint
*y
)
1354 if (level
== 0 && slice
== 0) {
1355 *x
= mt
->level
[0].level_x
;
1356 *y
= mt
->level
[0].level_y
;
1360 uint32_t x_offset_sa
, y_offset_sa
;
1362 /* Miptree itself can have an offset only if it represents a single
1363 * slice in an imported buffer object.
1364 * See intel_miptree_create_for_dri_image().
1366 assert(mt
->level
[0].level_x
== 0);
1367 assert(mt
->level
[0].level_y
== 0);
1369 /* Given level is relative to level zero while the miptree may be
1370 * represent just a subset of all levels starting from 'first_level'.
1372 assert(level
>= mt
->first_level
);
1373 level
-= mt
->first_level
;
1375 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1376 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1377 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1378 &x_offset_sa
, &y_offset_sa
);
1386 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1387 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1388 * and tile_h is set to 1.
1391 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1392 uint32_t *tile_w
, uint32_t *tile_h
)
1403 case ISL_TILING_LINEAR
:
1408 unreachable("not reached");
1414 * This function computes masks that may be used to select the bits of the X
1415 * and Y coordinates that indicate the offset within a tile. If the BO is
1416 * untiled, the masks are set to 0.
1419 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1420 uint32_t *mask_x
, uint32_t *mask_y
)
1422 uint32_t tile_w_bytes
, tile_h
;
1424 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1426 *mask_x
= tile_w_bytes
/ cpp
- 1;
1427 *mask_y
= tile_h
- 1;
1431 * Compute the offset (in bytes) from the start of the BO to the given x
1432 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1433 * multiples of the tile size.
1436 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1437 uint32_t x
, uint32_t y
)
1440 uint32_t pitch
= mt
->surf
.row_pitch
;
1442 switch (mt
->surf
.tiling
) {
1444 unreachable("not reached");
1445 case ISL_TILING_LINEAR
:
1446 return y
* pitch
+ x
* cpp
;
1448 assert((x
% (512 / cpp
)) == 0);
1449 assert((y
% 8) == 0);
1450 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1452 assert((x
% (128 / cpp
)) == 0);
1453 assert((y
% 32) == 0);
1454 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1459 * Rendering with tiled buffers requires that the base address of the buffer
1460 * be aligned to a page boundary. For renderbuffers, and sometimes with
1461 * textures, we may want the surface to point at a texture image level that
1462 * isn't at a page boundary.
1464 * This function returns an appropriately-aligned base offset
1465 * according to the tiling restrictions, plus any required x/y offset
1469 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1470 GLuint level
, GLuint slice
,
1475 uint32_t mask_x
, mask_y
;
1477 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1478 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1480 *tile_x
= x
& mask_x
;
1481 *tile_y
= y
& mask_y
;
1483 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1487 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1488 struct intel_mipmap_tree
*src_mt
,
1489 unsigned src_level
, unsigned src_layer
,
1490 struct intel_mipmap_tree
*dst_mt
,
1491 unsigned dst_level
, unsigned dst_layer
,
1492 unsigned width
, unsigned height
)
1495 ptrdiff_t src_stride
, dst_stride
;
1496 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1498 intel_miptree_map(brw
, src_mt
,
1499 src_level
, src_layer
,
1502 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1505 intel_miptree_map(brw
, dst_mt
,
1506 dst_level
, dst_layer
,
1509 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1513 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1514 _mesa_get_format_name(src_mt
->format
),
1515 src_mt
, src
, src_stride
,
1516 _mesa_get_format_name(dst_mt
->format
),
1517 dst_mt
, dst
, dst_stride
,
1520 int row_size
= cpp
* width
;
1521 if (src_stride
== row_size
&&
1522 dst_stride
== row_size
) {
1523 memcpy(dst
, src
, row_size
* height
);
1525 for (int i
= 0; i
< height
; i
++) {
1526 memcpy(dst
, src
, row_size
);
1532 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1533 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1535 /* Don't forget to copy the stencil data over, too. We could have skipped
1536 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1537 * shuffling the two data sources in/out of temporary storage instead of
1538 * the direct mapping we get this way.
1540 if (dst_mt
->stencil_mt
) {
1541 assert(src_mt
->stencil_mt
);
1542 intel_miptree_copy_slice_sw(brw
,
1543 src_mt
->stencil_mt
, src_level
, src_layer
,
1544 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1550 intel_miptree_copy_slice(struct brw_context
*brw
,
1551 struct intel_mipmap_tree
*src_mt
,
1552 unsigned src_level
, unsigned src_layer
,
1553 struct intel_mipmap_tree
*dst_mt
,
1554 unsigned dst_level
, unsigned dst_layer
)
1557 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1558 mesa_format format
= src_mt
->format
;
1559 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1560 src_level
- src_mt
->first_level
);
1561 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1562 src_level
- src_mt
->first_level
);
1564 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1565 src_level
- src_mt
->first_level
));
1567 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1568 _mesa_get_srgb_format_linear(dst_mt
->format
));
1570 DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
1571 _mesa_get_format_name(src_mt
->format
),
1572 src_mt
, src_level
, src_layer
,
1573 _mesa_get_format_name(dst_mt
->format
),
1574 dst_mt
, dst_level
, dst_layer
,
1577 if (devinfo
->gen
>= 6) {
1578 /* On gen6 and above, we just use blorp. It's faster than the blitter
1579 * and can handle everything without software fallbacks.
1581 brw_blorp_copy_miptrees(brw
,
1582 src_mt
, src_level
, src_layer
,
1583 dst_mt
, dst_level
, dst_layer
,
1584 0, 0, 0, 0, width
, height
);
1586 if (src_mt
->stencil_mt
) {
1587 assert(dst_mt
->stencil_mt
);
1588 brw_blorp_copy_miptrees(brw
,
1589 src_mt
->stencil_mt
, src_level
, src_layer
,
1590 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1591 0, 0, 0, 0, width
, height
);
1596 if (dst_mt
->compressed
) {
1598 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1599 height
= ALIGN_NPOT(height
, j
) / j
;
1600 width
= ALIGN_NPOT(width
, i
) / i
;
1603 /* Gen4-5 doesn't support separate stencil */
1604 assert(!src_mt
->stencil_mt
);
1606 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1607 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1609 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1612 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1613 _mesa_get_format_name(src_mt
->format
),
1614 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1615 _mesa_get_format_name(dst_mt
->format
),
1616 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1619 if (!intel_miptree_blit(brw
,
1620 src_mt
, src_level
, src_layer
, 0, 0, false,
1621 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1622 width
, height
, COLOR_LOGICOP_COPY
)) {
1623 perf_debug("miptree validate blit for %s failed\n",
1624 _mesa_get_format_name(format
));
1626 intel_miptree_copy_slice_sw(brw
,
1627 src_mt
, src_level
, src_layer
,
1628 dst_mt
, dst_level
, dst_layer
,
1634 * Copies the image's current data to the given miptree, and associates that
1635 * miptree with the image.
1638 intel_miptree_copy_teximage(struct brw_context
*brw
,
1639 struct intel_texture_image
*intelImage
,
1640 struct intel_mipmap_tree
*dst_mt
)
1642 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1643 struct intel_texture_object
*intel_obj
=
1644 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1645 int level
= intelImage
->base
.Base
.Level
;
1646 const unsigned face
= intelImage
->base
.Base
.Face
;
1647 unsigned start_layer
, end_layer
;
1649 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1651 assert(intelImage
->base
.Base
.Height
);
1653 end_layer
= intelImage
->base
.Base
.Height
- 1;
1654 } else if (face
> 0) {
1658 assert(intelImage
->base
.Base
.Depth
);
1660 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1663 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1664 intel_miptree_copy_slice(brw
,
1669 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1670 intel_obj
->needs_validate
= true;
1673 static struct intel_miptree_aux_buffer
*
1674 intel_alloc_aux_buffer(struct brw_context
*brw
,
1675 const struct isl_surf
*aux_surf
,
1677 uint8_t memset_value
)
1679 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1683 uint64_t size
= aux_surf
->size
;
1685 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1686 if (has_indirect_clear
) {
1687 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1688 * will set a pointer to a dword somewhere that contains the color. So,
1689 * allocate the space for the clear color value here on the aux buffer.
1691 buf
->clear_color_offset
= size
;
1692 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1695 /* If the buffer needs to be initialised (requiring the buffer to be
1696 * immediately mapped to cpu space for writing), do not use the gpu access
1697 * flag which can cause an unnecessary delay if the backing pages happened
1698 * to be just used by the GPU.
1700 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1701 const bool needs_memset
=
1702 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1703 const uint32_t alloc_flags
=
1704 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1706 /* ISL has stricter set of alignment rules then the drm allocator.
1707 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1708 * trying to recalculate based on different format block sizes.
1710 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1711 BRW_MEMZONE_OTHER
, I915_TILING_Y
,
1712 aux_surf
->row_pitch
, alloc_flags
);
1718 /* Initialize the bo to the desired value */
1720 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1722 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1724 intel_miptree_aux_buffer_free(buf
);
1728 /* Memset the aux_surf portion of the BO. */
1730 memset(map
, memset_value
, aux_surf
->size
);
1732 /* Zero the indirect clear color to match ::fast_clear_color. */
1733 if (has_indirect_clear
) {
1734 memset((char *)map
+ buf
->clear_color_offset
, 0,
1735 brw
->isl_dev
.ss
.clear_color_state_size
);
1738 brw_bo_unmap(buf
->bo
);
1741 if (has_indirect_clear
) {
1742 buf
->clear_color_bo
= buf
->bo
;
1743 brw_bo_reference(buf
->clear_color_bo
);
1746 buf
->surf
= *aux_surf
;
1753 * Helper for intel_miptree_alloc_aux() that sets
1754 * \c mt->level[level].has_hiz. Return true if and only if
1755 * \c has_hiz was set.
1758 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1759 struct intel_mipmap_tree
*mt
,
1762 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1764 assert(mt
->aux_buf
);
1765 assert(mt
->surf
.size
> 0);
1767 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1768 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1769 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1771 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1772 * and the height is 4 aligned. This allows our HiZ support
1773 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1774 * we can grow the width & height to allow the HiZ op to
1775 * force the proper size alignments.
1777 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1778 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1783 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1784 mt
->level
[level
].has_hiz
= true;
1790 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1792 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1793 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1794 * compress clear color so we wait until an actual fast-clear to allocate it.
1797 intel_miptree_alloc_aux(struct brw_context
*brw
,
1798 struct intel_mipmap_tree
*mt
)
1800 assert(mt
->aux_buf
== NULL
);
1802 /* Get the aux buf allocation parameters for this miptree. */
1803 enum isl_aux_state initial_state
;
1804 uint8_t memset_value
;
1805 struct isl_surf aux_surf
;
1806 MAYBE_UNUSED
bool aux_surf_ok
;
1808 switch (mt
->aux_usage
) {
1809 case ISL_AUX_USAGE_NONE
:
1813 case ISL_AUX_USAGE_HIZ
:
1814 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1815 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1817 case ISL_AUX_USAGE_MCS
:
1818 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1820 * When MCS buffer is enabled and bound to MSRT, it is required that
1821 * it is cleared prior to any rendering.
1823 * Since we don't use the MCS buffer for any purpose other than
1824 * rendering, it makes sense to just clear it immediately upon
1827 * Note: the clear value for MCS buffers is all 1's, so we memset to
1830 initial_state
= ISL_AUX_STATE_CLEAR
;
1831 memset_value
= 0xFF;
1832 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1834 case ISL_AUX_USAGE_CCS_D
:
1835 case ISL_AUX_USAGE_CCS_E
:
1836 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1837 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1840 * "If Software wants to enable Color Compression without Fast
1841 * clear, Software needs to initialize MCS with zeros."
1843 * A CCS value of 0 indicates that the corresponding block is in the
1844 * pass-through state which is what we want.
1846 * For CCS_D, do the same thing. On gen9+, this avoids having any
1847 * undefined bits in the aux buffer.
1849 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1852 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1856 /* We should have a valid aux_surf. */
1857 assert(aux_surf_ok
);
1859 /* No work is needed for a zero-sized auxiliary buffer. */
1860 if (aux_surf
.size
== 0)
1863 /* Create the aux_state for the auxiliary buffer. */
1864 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1865 if (mt
->aux_state
== NULL
)
1868 /* Allocate the auxiliary buffer. */
1869 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1870 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1872 if (mt
->aux_buf
== NULL
) {
1873 free_aux_state_map(mt
->aux_state
);
1874 mt
->aux_state
= NULL
;
1878 /* Perform aux_usage-specific initialization. */
1879 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1880 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1881 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1889 * Can the miptree sample using the hiz buffer?
1892 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1893 struct intel_mipmap_tree
*mt
)
1895 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1897 if (!devinfo
->has_sample_with_hiz
) {
1905 /* It seems the hardware won't fallback to the depth buffer if some of the
1906 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1907 * of the texture to be HiZ enabled.
1909 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1910 if (!intel_miptree_level_has_hiz(mt
, level
))
1914 /* If compressed multisampling is enabled, then we use it for the auxiliary
1917 * From the BDW PRM (Volume 2d: Command Reference: Structures
1918 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1920 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1921 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1923 * There is no such blurb for 1D textures, but there is sufficient evidence
1924 * that this is broken on SKL+.
1926 return (mt
->surf
.samples
== 1 &&
1927 mt
->target
!= GL_TEXTURE_3D
&&
1928 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1932 * Does the miptree slice have hiz enabled?
1935 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1937 intel_miptree_check_level_layer(mt
, level
, 0);
1938 return mt
->level
[level
].has_hiz
;
1941 static inline uint32_t
1942 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1943 uint32_t start_level
, uint32_t num_levels
)
1945 assert(start_level
>= mt
->first_level
);
1946 assert(start_level
<= mt
->last_level
);
1948 if (num_levels
== INTEL_REMAINING_LAYERS
)
1949 num_levels
= mt
->last_level
- start_level
+ 1;
1950 /* Check for overflow */
1951 assert(start_level
+ num_levels
>= start_level
);
1952 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1957 static inline uint32_t
1958 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1959 uint32_t start_layer
, uint32_t num_layers
)
1961 assert(level
<= mt
->last_level
);
1963 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1964 assert(start_layer
< total_num_layers
);
1965 if (num_layers
== INTEL_REMAINING_LAYERS
)
1966 num_layers
= total_num_layers
- start_layer
;
1967 /* Check for overflow */
1968 assert(start_layer
+ num_layers
>= start_layer
);
1969 assert(start_layer
+ num_layers
<= total_num_layers
);
1975 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1976 unsigned start_level
, unsigned num_levels
,
1977 unsigned start_layer
, unsigned num_layers
)
1979 assert(_mesa_is_format_color_format(mt
->format
));
1984 /* Clamp the level range to fit the miptree */
1985 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1987 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1988 const uint32_t level
= start_level
+ l
;
1989 const uint32_t level_layers
=
1990 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1991 for (unsigned a
= 0; a
< level_layers
; a
++) {
1992 enum isl_aux_state aux_state
=
1993 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1994 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1995 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2004 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2005 const struct intel_mipmap_tree
*mt
,
2006 unsigned level
, unsigned layer
)
2011 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2012 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2013 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2015 /* Compression of arrayed msaa surfaces is supported. */
2016 if (mt
->surf
.samples
> 1)
2019 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2020 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2022 mt
->surf
.logical_level0_px
.depth
== 1 &&
2023 mt
->surf
.logical_level0_px
.array_len
== 1));
2029 static enum isl_aux_op
2030 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2031 enum isl_aux_usage aux_usage
,
2032 bool fast_clear_supported
)
2034 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2036 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2038 assert(ccs_supported
== fast_clear_supported
);
2040 switch (aux_state
) {
2041 case ISL_AUX_STATE_CLEAR
:
2042 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2044 return ISL_AUX_OP_FULL_RESOLVE
;
2046 return ISL_AUX_OP_NONE
;
2048 case ISL_AUX_STATE_PASS_THROUGH
:
2049 return ISL_AUX_OP_NONE
;
2051 case ISL_AUX_STATE_RESOLVED
:
2052 case ISL_AUX_STATE_AUX_INVALID
:
2053 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2054 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2058 unreachable("Invalid aux state for CCS_D");
2061 static enum isl_aux_op
2062 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2063 enum isl_aux_usage aux_usage
,
2064 bool fast_clear_supported
)
2066 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2067 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2068 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2069 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2071 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2072 assert(fast_clear_supported
);
2074 switch (aux_state
) {
2075 case ISL_AUX_STATE_CLEAR
:
2076 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2077 if (fast_clear_supported
)
2078 return ISL_AUX_OP_NONE
;
2079 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2080 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2082 return ISL_AUX_OP_FULL_RESOLVE
;
2084 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2085 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2086 return ISL_AUX_OP_FULL_RESOLVE
;
2087 else if (!fast_clear_supported
)
2088 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2090 return ISL_AUX_OP_NONE
;
2092 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2093 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2094 return ISL_AUX_OP_FULL_RESOLVE
;
2096 return ISL_AUX_OP_NONE
;
2098 case ISL_AUX_STATE_PASS_THROUGH
:
2099 return ISL_AUX_OP_NONE
;
2101 case ISL_AUX_STATE_RESOLVED
:
2102 case ISL_AUX_STATE_AUX_INVALID
:
2106 unreachable("Invalid aux state for CCS_E");
2110 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2111 struct intel_mipmap_tree
*mt
,
2112 uint32_t level
, uint32_t layer
,
2113 enum isl_aux_usage aux_usage
,
2114 bool fast_clear_supported
)
2116 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2118 enum isl_aux_op resolve_op
;
2119 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2120 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2121 fast_clear_supported
);
2123 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2124 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2125 fast_clear_supported
);
2128 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2129 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2130 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2132 switch (resolve_op
) {
2133 case ISL_AUX_OP_FULL_RESOLVE
:
2134 /* The CCS full resolve operation destroys the CCS and sets it to the
2135 * pass-through state. (You can also think of this as being both a
2136 * resolve and an ambiguate in one operation.)
2138 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2139 ISL_AUX_STATE_PASS_THROUGH
);
2142 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2143 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2144 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2148 unreachable("Invalid resolve op");
2154 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2155 struct intel_mipmap_tree
*mt
,
2156 uint32_t level
, uint32_t layer
,
2157 enum isl_aux_usage aux_usage
)
2159 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2160 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2161 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2163 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2165 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2166 switch (aux_state
) {
2167 case ISL_AUX_STATE_CLEAR
:
2168 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2169 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2170 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2172 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2173 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2174 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2175 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2176 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2177 ISL_AUX_STATE_PARTIAL_CLEAR
);
2181 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2182 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2183 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2184 break; /* Nothing to do */
2186 case ISL_AUX_STATE_PASS_THROUGH
:
2187 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2188 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2189 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2195 case ISL_AUX_STATE_RESOLVED
:
2196 case ISL_AUX_STATE_AUX_INVALID
:
2197 unreachable("Invalid aux state for CCS_E");
2200 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2201 /* CCS_D is a bit simpler */
2202 switch (aux_state
) {
2203 case ISL_AUX_STATE_CLEAR
:
2204 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2205 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2206 ISL_AUX_STATE_PARTIAL_CLEAR
);
2209 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2210 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2211 break; /* Nothing to do */
2213 case ISL_AUX_STATE_PASS_THROUGH
:
2217 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2218 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2219 case ISL_AUX_STATE_RESOLVED
:
2220 case ISL_AUX_STATE_AUX_INVALID
:
2221 unreachable("Invalid aux state for CCS_D");
2227 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2228 struct intel_mipmap_tree
*mt
,
2230 enum isl_aux_usage aux_usage
,
2231 bool fast_clear_supported
)
2233 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2235 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2236 case ISL_AUX_STATE_CLEAR
:
2237 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2238 if (!fast_clear_supported
) {
2239 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2240 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2241 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2245 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2246 break; /* Nothing to do */
2248 case ISL_AUX_STATE_RESOLVED
:
2249 case ISL_AUX_STATE_PASS_THROUGH
:
2250 case ISL_AUX_STATE_AUX_INVALID
:
2251 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2252 unreachable("Invalid aux state for MCS");
2257 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2258 struct intel_mipmap_tree
*mt
,
2260 enum isl_aux_usage aux_usage
)
2262 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2264 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2265 case ISL_AUX_STATE_CLEAR
:
2266 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2267 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2270 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2271 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2272 break; /* Nothing to do */
2274 case ISL_AUX_STATE_RESOLVED
:
2275 case ISL_AUX_STATE_PASS_THROUGH
:
2276 case ISL_AUX_STATE_AUX_INVALID
:
2277 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2278 unreachable("Invalid aux state for MCS");
2283 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2284 struct intel_mipmap_tree
*mt
,
2285 uint32_t level
, uint32_t layer
,
2286 enum isl_aux_usage aux_usage
,
2287 bool fast_clear_supported
)
2289 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2291 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2292 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2293 case ISL_AUX_STATE_CLEAR
:
2294 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2295 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2296 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2299 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2300 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2301 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2304 case ISL_AUX_STATE_PASS_THROUGH
:
2305 case ISL_AUX_STATE_RESOLVED
:
2308 case ISL_AUX_STATE_AUX_INVALID
:
2309 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2310 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2313 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2314 unreachable("Invalid HiZ state");
2317 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2318 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2321 case ISL_AUX_OP_FULL_RESOLVE
:
2322 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2323 ISL_AUX_STATE_RESOLVED
);
2326 case ISL_AUX_OP_AMBIGUATE
:
2327 /* The HiZ resolve operation is actually an ambiguate */
2328 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2329 ISL_AUX_STATE_PASS_THROUGH
);
2333 unreachable("Invalid HiZ op");
2339 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2340 struct intel_mipmap_tree
*mt
,
2341 uint32_t level
, uint32_t layer
,
2342 enum isl_aux_usage aux_usage
)
2344 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2346 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2347 case ISL_AUX_STATE_CLEAR
:
2348 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2349 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2350 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2353 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2354 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2355 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2356 break; /* Nothing to do */
2358 case ISL_AUX_STATE_RESOLVED
:
2359 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2360 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2361 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2363 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2364 ISL_AUX_STATE_AUX_INVALID
);
2368 case ISL_AUX_STATE_PASS_THROUGH
:
2369 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2370 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2371 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2375 case ISL_AUX_STATE_AUX_INVALID
:
2376 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2379 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2380 unreachable("Invalid HiZ state");
2385 intel_miptree_prepare_access(struct brw_context
*brw
,
2386 struct intel_mipmap_tree
*mt
,
2387 uint32_t start_level
, uint32_t num_levels
,
2388 uint32_t start_layer
, uint32_t num_layers
,
2389 enum isl_aux_usage aux_usage
,
2390 bool fast_clear_supported
)
2392 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2394 switch (mt
->aux_usage
) {
2395 case ISL_AUX_USAGE_NONE
:
2399 case ISL_AUX_USAGE_MCS
:
2400 assert(mt
->aux_buf
);
2401 assert(start_level
== 0 && num_levels
== 1);
2402 const uint32_t level_layers
=
2403 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2404 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2405 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2406 aux_usage
, fast_clear_supported
);
2410 case ISL_AUX_USAGE_CCS_D
:
2411 case ISL_AUX_USAGE_CCS_E
:
2415 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2416 const uint32_t level
= start_level
+ l
;
2417 const uint32_t level_layers
=
2418 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2419 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2420 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2422 aux_usage
, fast_clear_supported
);
2427 case ISL_AUX_USAGE_HIZ
:
2428 assert(mt
->aux_buf
);
2429 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2430 const uint32_t level
= start_level
+ l
;
2431 if (!intel_miptree_level_has_hiz(mt
, level
))
2434 const uint32_t level_layers
=
2435 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2436 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2437 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2438 aux_usage
, fast_clear_supported
);
2444 unreachable("Invalid aux usage");
2449 intel_miptree_finish_write(struct brw_context
*brw
,
2450 struct intel_mipmap_tree
*mt
, uint32_t level
,
2451 uint32_t start_layer
, uint32_t num_layers
,
2452 enum isl_aux_usage aux_usage
)
2454 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2455 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2457 switch (mt
->aux_usage
) {
2458 case ISL_AUX_USAGE_NONE
:
2459 if (mt
->format
== MESA_FORMAT_S_UINT8
&& devinfo
->gen
<= 7)
2460 mt
->r8stencil_needs_update
= true;
2463 case ISL_AUX_USAGE_MCS
:
2464 assert(mt
->aux_buf
);
2465 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2466 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2471 case ISL_AUX_USAGE_CCS_D
:
2472 case ISL_AUX_USAGE_CCS_E
:
2476 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2477 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2482 case ISL_AUX_USAGE_HIZ
:
2483 if (!intel_miptree_level_has_hiz(mt
, level
))
2486 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2487 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2493 unreachable("Invavlid aux usage");
2498 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2499 uint32_t level
, uint32_t layer
)
2501 intel_miptree_check_level_layer(mt
, level
, layer
);
2503 if (_mesa_is_format_color_format(mt
->format
)) {
2504 assert(mt
->aux_buf
!= NULL
);
2505 assert(mt
->surf
.samples
== 1 ||
2506 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2507 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2508 unreachable("Cannot get aux state for stencil");
2510 assert(intel_miptree_level_has_hiz(mt
, level
));
2513 return mt
->aux_state
[level
][layer
];
2517 intel_miptree_set_aux_state(struct brw_context
*brw
,
2518 struct intel_mipmap_tree
*mt
, uint32_t level
,
2519 uint32_t start_layer
, uint32_t num_layers
,
2520 enum isl_aux_state aux_state
)
2522 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2524 if (_mesa_is_format_color_format(mt
->format
)) {
2525 assert(mt
->aux_buf
!= NULL
);
2526 assert(mt
->surf
.samples
== 1 ||
2527 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2528 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2529 unreachable("Cannot get aux state for stencil");
2531 assert(intel_miptree_level_has_hiz(mt
, level
));
2534 for (unsigned a
= 0; a
< num_layers
; a
++) {
2535 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2536 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2537 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2542 /* On Gen9 color buffers may be compressed by the hardware (lossless
2543 * compression). There are, however, format restrictions and care needs to be
2544 * taken that the sampler engine is capable for re-interpreting a buffer with
2545 * format different the buffer was originally written with.
2547 * For example, SRGB formats are not compressible and the sampler engine isn't
2548 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2549 * color buffer needs to be resolved so that the sampling surface can be
2550 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2554 can_texture_with_ccs(struct brw_context
*brw
,
2555 struct intel_mipmap_tree
*mt
,
2556 enum isl_format view_format
)
2558 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2561 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2563 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2564 isl_format_get_layout(view_format
)->name
,
2565 _mesa_get_format_name(mt
->format
));
2573 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2574 struct intel_mipmap_tree
*mt
,
2575 enum isl_format view_format
)
2577 switch (mt
->aux_usage
) {
2578 case ISL_AUX_USAGE_HIZ
:
2579 if (intel_miptree_sample_with_hiz(brw
, mt
))
2580 return ISL_AUX_USAGE_HIZ
;
2583 case ISL_AUX_USAGE_MCS
:
2584 return ISL_AUX_USAGE_MCS
;
2586 case ISL_AUX_USAGE_CCS_D
:
2587 case ISL_AUX_USAGE_CCS_E
:
2589 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2590 return ISL_AUX_USAGE_NONE
;
2593 /* If we don't have any unresolved color, report an aux usage of
2594 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2595 * aux surface and we can save some bandwidth.
2597 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2598 0, INTEL_REMAINING_LAYERS
))
2599 return ISL_AUX_USAGE_NONE
;
2601 if (can_texture_with_ccs(brw
, mt
, view_format
))
2602 return ISL_AUX_USAGE_CCS_E
;
2609 return ISL_AUX_USAGE_NONE
;
2613 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2615 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2616 * values so sRGB curve application was a no-op for all fast-clearable
2619 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2620 * values, the hardware interprets the floats, not as what would be
2621 * returned from the sampler (or written by the shader), but as being
2622 * between format conversion and sRGB curve application. This means that
2623 * we can switch between sRGB and UNORM without having to whack the clear
2626 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2630 intel_miptree_prepare_texture(struct brw_context
*brw
,
2631 struct intel_mipmap_tree
*mt
,
2632 enum isl_format view_format
,
2633 uint32_t start_level
, uint32_t num_levels
,
2634 uint32_t start_layer
, uint32_t num_layers
)
2636 enum isl_aux_usage aux_usage
=
2637 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2638 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2640 /* Clear color is specified as ints or floats and the conversion is done by
2641 * the sampler. If we have a texture view, we would have to perform the
2642 * clear color conversion manually. Just disable clear color.
2644 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2645 clear_supported
= false;
2647 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2648 start_layer
, num_layers
,
2649 aux_usage
, clear_supported
);
2653 intel_miptree_prepare_image(struct brw_context
*brw
,
2654 struct intel_mipmap_tree
*mt
)
2656 /* The data port doesn't understand any compression */
2657 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2658 0, INTEL_REMAINING_LAYERS
,
2659 ISL_AUX_USAGE_NONE
, false);
2663 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2664 struct intel_mipmap_tree
*mt
,
2665 enum isl_format render_format
,
2667 bool draw_aux_disabled
)
2669 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2671 if (draw_aux_disabled
)
2672 return ISL_AUX_USAGE_NONE
;
2674 switch (mt
->aux_usage
) {
2675 case ISL_AUX_USAGE_MCS
:
2676 assert(mt
->aux_buf
);
2677 return ISL_AUX_USAGE_MCS
;
2679 case ISL_AUX_USAGE_CCS_D
:
2680 case ISL_AUX_USAGE_CCS_E
:
2682 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2683 return ISL_AUX_USAGE_NONE
;
2686 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2687 * formats. However, there are issues with blending where it doesn't
2688 * properly apply the sRGB curve to the clear color when blending.
2690 if (devinfo
->gen
>= 9 && blend_enabled
&&
2691 isl_format_is_srgb(render_format
) &&
2692 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2693 return ISL_AUX_USAGE_NONE
;
2695 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2696 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2698 return ISL_AUX_USAGE_CCS_E
;
2700 /* Otherwise, we have to fall back to CCS_D */
2701 return ISL_AUX_USAGE_CCS_D
;
2704 return ISL_AUX_USAGE_NONE
;
2709 intel_miptree_prepare_render(struct brw_context
*brw
,
2710 struct intel_mipmap_tree
*mt
, uint32_t level
,
2711 uint32_t start_layer
, uint32_t layer_count
,
2712 enum isl_aux_usage aux_usage
)
2714 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2715 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2719 intel_miptree_finish_render(struct brw_context
*brw
,
2720 struct intel_mipmap_tree
*mt
, uint32_t level
,
2721 uint32_t start_layer
, uint32_t layer_count
,
2722 enum isl_aux_usage aux_usage
)
2724 assert(_mesa_is_format_color_format(mt
->format
));
2726 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2731 intel_miptree_prepare_depth(struct brw_context
*brw
,
2732 struct intel_mipmap_tree
*mt
, uint32_t level
,
2733 uint32_t start_layer
, uint32_t layer_count
)
2735 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2736 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2740 intel_miptree_finish_depth(struct brw_context
*brw
,
2741 struct intel_mipmap_tree
*mt
, uint32_t level
,
2742 uint32_t start_layer
, uint32_t layer_count
,
2745 if (depth_written
) {
2746 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2747 mt
->aux_buf
!= NULL
);
2752 intel_miptree_prepare_external(struct brw_context
*brw
,
2753 struct intel_mipmap_tree
*mt
)
2755 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2756 bool supports_fast_clear
= false;
2758 const struct isl_drm_modifier_info
*mod_info
=
2759 isl_drm_modifier_get_info(mt
->drm_modifier
);
2761 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2762 /* CCS_E is the only supported aux for external images and it's only
2763 * supported on very simple images.
2765 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2766 assert(_mesa_is_format_color_format(mt
->format
));
2767 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2768 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2769 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2770 assert(mt
->surf
.samples
== 1);
2771 assert(mt
->aux_buf
!= NULL
);
2773 aux_usage
= mod_info
->aux_usage
;
2774 supports_fast_clear
= mod_info
->supports_clear_color
;
2777 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2778 0, INTEL_REMAINING_LAYERS
,
2779 aux_usage
, supports_fast_clear
);
2783 intel_miptree_finish_external(struct brw_context
*brw
,
2784 struct intel_mipmap_tree
*mt
)
2789 /* We don't know the actual aux state of the aux surface. The previous
2790 * owner could have given it to us in a number of different states.
2791 * Because we don't know the aux state, we reset the aux state to the
2792 * least common denominator of possible valid states.
2794 enum isl_aux_state default_aux_state
=
2795 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2796 assert(mt
->last_level
== mt
->first_level
);
2797 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2802 * Make it possible to share the BO backing the given miptree with another
2803 * process or another miptree.
2805 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2806 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2807 * ensure that no MCS buffer gets allocated in the future.
2809 * HiZ is similarly unsafe with shared buffers.
2812 intel_miptree_make_shareable(struct brw_context
*brw
,
2813 struct intel_mipmap_tree
*mt
)
2815 /* MCS buffers are also used for multisample buffers, but we can't resolve
2816 * away a multisample MCS buffer because it's an integral part of how the
2817 * pixel data is stored. Fortunately this code path should never be
2818 * reached for multisample buffers.
2820 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2821 mt
->surf
.samples
== 1);
2823 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2824 0, INTEL_REMAINING_LAYERS
,
2825 ISL_AUX_USAGE_NONE
, false);
2828 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2831 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2832 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2833 mt
->level
[l
].has_hiz
= false;
2836 free(mt
->aux_state
);
2837 mt
->aux_state
= NULL
;
2838 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2841 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2842 mt
->supports_fast_clear
= false;
2847 * \brief Get pointer offset into stencil buffer.
2849 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2850 * must decode the tile's layout in software.
2853 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2855 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2857 * Even though the returned offset is always positive, the return type is
2859 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2860 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2863 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2865 uint32_t tile_size
= 4096;
2866 uint32_t tile_width
= 64;
2867 uint32_t tile_height
= 64;
2868 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2870 uint32_t tile_x
= x
/ tile_width
;
2871 uint32_t tile_y
= y
/ tile_height
;
2873 /* The byte's address relative to the tile's base addres. */
2874 uint32_t byte_x
= x
% tile_width
;
2875 uint32_t byte_y
= y
% tile_height
;
2877 uintptr_t u
= tile_y
* row_size
2878 + tile_x
* tile_size
2879 + 512 * (byte_x
/ 8)
2881 + 32 * ((byte_y
/ 4) % 2)
2882 + 16 * ((byte_x
/ 4) % 2)
2883 + 8 * ((byte_y
/ 2) % 2)
2884 + 4 * ((byte_x
/ 2) % 2)
2889 /* adjust for bit6 swizzling */
2890 if (((byte_x
/ 8) % 2) == 1) {
2891 if (((byte_y
/ 8) % 2) == 0) {
2903 intel_miptree_updownsample(struct brw_context
*brw
,
2904 struct intel_mipmap_tree
*src
,
2905 struct intel_mipmap_tree
*dst
)
2907 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2908 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2909 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2910 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2912 brw_blorp_blit_miptrees(brw
,
2913 src
, 0 /* level */, 0 /* layer */,
2914 src
->format
, SWIZZLE_XYZW
,
2915 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2918 GL_NEAREST
, false, false /*mirror x, y*/,
2921 if (src
->stencil_mt
) {
2922 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2923 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2924 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2925 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2927 brw_blorp_blit_miptrees(brw
,
2928 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2929 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2930 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2931 dst
->stencil_mt
->format
,
2934 GL_NEAREST
, false, false /*mirror x, y*/,
2935 false, false /* decode/encode srgb */);
2940 intel_update_r8stencil(struct brw_context
*brw
,
2941 struct intel_mipmap_tree
*mt
)
2943 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2945 assert(devinfo
->gen
>= 7);
2946 struct intel_mipmap_tree
*src
=
2947 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2948 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2951 assert(src
->surf
.size
> 0);
2953 if (!mt
->r8stencil_mt
) {
2954 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2955 mt
->r8stencil_mt
= make_surface(
2958 MESA_FORMAT_R_UINT8
,
2959 src
->first_level
, src
->last_level
,
2960 src
->surf
.logical_level0_px
.width
,
2961 src
->surf
.logical_level0_px
.height
,
2962 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2963 src
->surf
.logical_level0_px
.depth
:
2964 src
->surf
.logical_level0_px
.array_len
,
2967 ISL_SURF_USAGE_TEXTURE_BIT
,
2968 BO_ALLOC_BUSY
, 0, NULL
);
2969 assert(mt
->r8stencil_mt
);
2972 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2974 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2975 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2976 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2977 src
->surf
.phys_level0_sa
.array_len
;
2979 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2980 brw_blorp_copy_miptrees(brw
,
2984 minify(src
->surf
.logical_level0_px
.width
,
2986 minify(src
->surf
.logical_level0_px
.height
,
2991 brw_cache_flush_for_read(brw
, dst
->bo
);
2992 src
->r8stencil_needs_update
= false;
2996 intel_miptree_map_raw(struct brw_context
*brw
,
2997 struct intel_mipmap_tree
*mt
,
3000 struct brw_bo
*bo
= mt
->bo
;
3002 if (brw_batch_references(&brw
->batch
, bo
))
3003 intel_batchbuffer_flush(brw
);
3005 return brw_bo_map(brw
, bo
, mode
);
3009 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3011 brw_bo_unmap(mt
->bo
);
3015 intel_miptree_unmap_gtt(struct brw_context
*brw
,
3016 struct intel_mipmap_tree
*mt
,
3017 struct intel_miptree_map
*map
,
3018 unsigned int level
, unsigned int slice
)
3020 intel_miptree_unmap_raw(mt
);
3024 intel_miptree_map_gtt(struct brw_context
*brw
,
3025 struct intel_mipmap_tree
*mt
,
3026 struct intel_miptree_map
*map
,
3027 unsigned int level
, unsigned int slice
)
3029 unsigned int bw
, bh
;
3031 unsigned int image_x
, image_y
;
3032 intptr_t x
= map
->x
;
3033 intptr_t y
= map
->y
;
3035 /* For compressed formats, the stride is the number of bytes per
3036 * row of blocks. intel_miptree_get_image_offset() already does
3039 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3040 assert(y
% bh
== 0);
3041 assert(x
% bw
== 0);
3045 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3046 map
->mode
& GL_MAP_WRITE_BIT
);
3048 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3055 /* Note that in the case of cube maps, the caller must have passed the
3056 * slice number referencing the face.
3058 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3062 map
->stride
= mt
->surf
.row_pitch
;
3063 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3066 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3067 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3068 map
->x
, map
->y
, map
->w
, map
->h
,
3069 mt
, _mesa_get_format_name(mt
->format
),
3070 x
, y
, map
->ptr
, map
->stride
);
3072 map
->unmap
= intel_miptree_unmap_gtt
;
3076 intel_miptree_unmap_blit(struct brw_context
*brw
,
3077 struct intel_mipmap_tree
*mt
,
3078 struct intel_miptree_map
*map
,
3082 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3083 struct gl_context
*ctx
= &brw
->ctx
;
3085 intel_miptree_unmap_raw(map
->linear_mt
);
3087 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3088 if (devinfo
->gen
>= 6) {
3089 brw_blorp_copy_miptrees(brw
, map
->linear_mt
, 0, 0,
3091 0, 0, map
->x
, map
->y
, map
->w
, map
->h
);
3093 bool ok
= intel_miptree_copy(brw
,
3094 map
->linear_mt
, 0, 0, 0, 0,
3095 mt
, level
, slice
, map
->x
, map
->y
,
3097 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3101 intel_miptree_release(&map
->linear_mt
);
3105 intel_miptree_map_blit(struct brw_context
*brw
,
3106 struct intel_mipmap_tree
*mt
,
3107 struct intel_miptree_map
*map
,
3108 unsigned int level
, unsigned int slice
)
3110 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3111 map
->linear_mt
= make_surface(brw
, GL_TEXTURE_2D
, mt
->format
,
3112 0, 0, map
->w
, map
->h
, 1, 1,
3113 ISL_TILING_LINEAR_BIT
,
3114 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
3115 ISL_SURF_USAGE_TEXTURE_BIT
,
3118 if (!map
->linear_mt
) {
3119 fprintf(stderr
, "Failed to allocate blit temporary\n");
3122 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3124 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3125 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3126 * invalidate is set, since we'll be writing the whole rectangle from our
3127 * temporary buffer back out.
3129 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3130 if (devinfo
->gen
>= 6) {
3131 brw_blorp_copy_miptrees(brw
, mt
, level
, slice
,
3132 map
->linear_mt
, 0, 0,
3133 map
->x
, map
->y
, 0, 0, map
->w
, map
->h
);
3135 if (!intel_miptree_copy(brw
,
3136 mt
, level
, slice
, map
->x
, map
->y
,
3137 map
->linear_mt
, 0, 0, 0, 0,
3139 fprintf(stderr
, "Failed to blit\n");
3145 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3147 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3148 map
->x
, map
->y
, map
->w
, map
->h
,
3149 mt
, _mesa_get_format_name(mt
->format
),
3150 level
, slice
, map
->ptr
, map
->stride
);
3152 map
->unmap
= intel_miptree_unmap_blit
;
3156 intel_miptree_release(&map
->linear_mt
);
3162 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3164 #if defined(USE_SSE41)
3166 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3167 struct intel_mipmap_tree
*mt
,
3168 struct intel_miptree_map
*map
,
3172 _mesa_align_free(map
->buffer
);
3178 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3179 struct intel_mipmap_tree
*mt
,
3180 struct intel_miptree_map
*map
,
3181 unsigned int level
, unsigned int slice
)
3183 assert(map
->mode
& GL_MAP_READ_BIT
);
3184 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3186 intel_miptree_access_raw(brw
, mt
, level
, slice
, false);
3188 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3189 map
->x
, map
->y
, map
->w
, map
->h
,
3190 mt
, _mesa_get_format_name(mt
->format
),
3191 level
, slice
, map
->ptr
, map
->stride
);
3193 /* Map the original image */
3196 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3200 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3206 src
+= image_y
* mt
->surf
.row_pitch
;
3207 src
+= image_x
* mt
->cpp
;
3209 /* Due to the pixel offsets for the particular image being mapped, our
3210 * src pointer may not be 16-byte aligned. However, if the pitch is
3211 * divisible by 16, then the amount by which it's misaligned will remain
3212 * consistent from row to row.
3214 assert((mt
->surf
.row_pitch
% 16) == 0);
3215 const int misalignment
= ((uintptr_t) src
) & 15;
3217 /* Create an untiled temporary buffer for the mapping. */
3218 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3220 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3222 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3223 /* Offset the destination so it has the same misalignment as src. */
3224 map
->ptr
= map
->buffer
+ misalignment
;
3226 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3228 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3229 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3230 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3232 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3235 intel_miptree_unmap_raw(mt
);
3237 map
->unmap
= intel_miptree_unmap_movntdqa
;
3242 intel_miptree_unmap_s8(struct brw_context
*brw
,
3243 struct intel_mipmap_tree
*mt
,
3244 struct intel_miptree_map
*map
,
3248 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3249 unsigned int image_x
, image_y
;
3250 uint8_t *untiled_s8_map
= map
->ptr
;
3251 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3253 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3255 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3256 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3257 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3258 image_x
+ x
+ map
->x
,
3259 image_y
+ y
+ map
->y
,
3260 brw
->has_swizzling
);
3261 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3265 intel_miptree_unmap_raw(mt
);
3272 intel_miptree_map_s8(struct brw_context
*brw
,
3273 struct intel_mipmap_tree
*mt
,
3274 struct intel_miptree_map
*map
,
3275 unsigned int level
, unsigned int slice
)
3277 map
->stride
= map
->w
;
3278 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3282 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3283 map
->mode
& GL_MAP_WRITE_BIT
);
3285 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3286 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3287 * invalidate is set, since we'll be writing the whole rectangle from our
3288 * temporary buffer back out.
3290 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3291 uint8_t *untiled_s8_map
= map
->ptr
;
3292 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3293 unsigned int image_x
, image_y
;
3295 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3297 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3298 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3299 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3300 x
+ image_x
+ map
->x
,
3301 y
+ image_y
+ map
->y
,
3302 brw
->has_swizzling
);
3303 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3307 intel_miptree_unmap_raw(mt
);
3309 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3310 map
->x
, map
->y
, map
->w
, map
->h
,
3311 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3313 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3314 map
->x
, map
->y
, map
->w
, map
->h
,
3315 mt
, map
->ptr
, map
->stride
);
3318 map
->unmap
= intel_miptree_unmap_s8
;
3322 intel_miptree_unmap_etc(struct brw_context
*brw
,
3323 struct intel_mipmap_tree
*mt
,
3324 struct intel_miptree_map
*map
,
3330 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3335 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3336 + image_y
* mt
->surf
.row_pitch
3337 + image_x
* mt
->cpp
;
3339 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3340 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3341 map
->ptr
, map
->stride
,
3344 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3345 map
->ptr
, map
->stride
,
3346 map
->w
, map
->h
, mt
->etc_format
, true);
3348 intel_miptree_unmap_raw(mt
);
3353 intel_miptree_map_etc(struct brw_context
*brw
,
3354 struct intel_mipmap_tree
*mt
,
3355 struct intel_miptree_map
*map
,
3359 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3360 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3361 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3364 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3365 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3367 intel_miptree_access_raw(brw
, mt
, level
, slice
, true);
3369 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3370 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3371 map
->w
, map
->h
, 1));
3372 map
->ptr
= map
->buffer
;
3373 map
->unmap
= intel_miptree_unmap_etc
;
3377 * Mapping functions for packed depth/stencil miptrees backed by real separate
3378 * miptrees for depth and stencil.
3380 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3381 * separate from the depth buffer. Yet at the GL API level, we have to expose
3382 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3383 * be able to map that memory for texture storage and glReadPixels-type
3384 * operations. We give Mesa core that access by mallocing a temporary and
3385 * copying the data between the actual backing store and the temporary.
3388 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3389 struct intel_mipmap_tree
*mt
,
3390 struct intel_miptree_map
*map
,
3394 struct intel_mipmap_tree
*z_mt
= mt
;
3395 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3396 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3398 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3399 uint32_t *packed_map
= map
->ptr
;
3400 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3401 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3402 unsigned int s_image_x
, s_image_y
;
3403 unsigned int z_image_x
, z_image_y
;
3405 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3406 &s_image_x
, &s_image_y
);
3407 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3408 &z_image_x
, &z_image_y
);
3410 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3411 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3412 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3413 x
+ s_image_x
+ map
->x
,
3414 y
+ s_image_y
+ map
->y
,
3415 brw
->has_swizzling
);
3416 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3417 (z_mt
->surf
.row_pitch
/ 4) +
3418 (x
+ z_image_x
+ map
->x
));
3420 if (map_z32f_x24s8
) {
3421 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3422 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3424 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3425 s_map
[s_offset
] = packed
>> 24;
3426 z_map
[z_offset
] = packed
;
3431 intel_miptree_unmap_raw(s_mt
);
3432 intel_miptree_unmap_raw(z_mt
);
3434 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3436 map
->x
, map
->y
, map
->w
, map
->h
,
3437 z_mt
, _mesa_get_format_name(z_mt
->format
),
3438 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3439 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3440 map
->ptr
, map
->stride
);
3447 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3448 struct intel_mipmap_tree
*mt
,
3449 struct intel_miptree_map
*map
,
3450 unsigned int level
, unsigned int slice
)
3452 struct intel_mipmap_tree
*z_mt
= mt
;
3453 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3454 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3455 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3457 map
->stride
= map
->w
* packed_bpp
;
3458 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3462 intel_miptree_access_raw(brw
, z_mt
, level
, slice
,
3463 map
->mode
& GL_MAP_WRITE_BIT
);
3464 intel_miptree_access_raw(brw
, s_mt
, level
, slice
,
3465 map
->mode
& GL_MAP_WRITE_BIT
);
3467 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3468 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3469 * invalidate is set, since we'll be writing the whole rectangle from our
3470 * temporary buffer back out.
3472 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3473 uint32_t *packed_map
= map
->ptr
;
3474 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3475 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3476 unsigned int s_image_x
, s_image_y
;
3477 unsigned int z_image_x
, z_image_y
;
3479 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3480 &s_image_x
, &s_image_y
);
3481 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3482 &z_image_x
, &z_image_y
);
3484 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3485 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3486 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3487 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3490 brw
->has_swizzling
);
3491 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3492 (z_mt
->surf
.row_pitch
/ 4) +
3493 (map_x
+ z_image_x
));
3494 uint8_t s
= s_map
[s_offset
];
3495 uint32_t z
= z_map
[z_offset
];
3497 if (map_z32f_x24s8
) {
3498 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3499 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3501 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3506 intel_miptree_unmap_raw(s_mt
);
3507 intel_miptree_unmap_raw(z_mt
);
3509 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3511 map
->x
, map
->y
, map
->w
, map
->h
,
3512 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3513 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3514 map
->ptr
, map
->stride
);
3516 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3517 map
->x
, map
->y
, map
->w
, map
->h
,
3518 mt
, map
->ptr
, map
->stride
);
3521 map
->unmap
= intel_miptree_unmap_depthstencil
;
3525 * Create and attach a map to the miptree at (level, slice). Return the
3528 static struct intel_miptree_map
*
3529 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3538 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3543 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3544 mt
->level
[level
].slice
[slice
].map
= map
;
3556 * Release the map at (level, slice).
3559 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3563 struct intel_miptree_map
**map
;
3565 map
= &mt
->level
[level
].slice
[slice
].map
;
3571 can_blit_slice(struct intel_mipmap_tree
*mt
,
3572 unsigned int level
, unsigned int slice
)
3574 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3575 if (intel_miptree_blt_pitch(mt
) >= 32768)
3582 use_intel_mipree_map_blit(struct brw_context
*brw
,
3583 struct intel_mipmap_tree
*mt
,
3588 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3590 if (devinfo
->has_llc
&&
3591 /* It's probably not worth swapping to the blit ring because of
3592 * all the overhead involved.
3594 !(mode
& GL_MAP_WRITE_BIT
) &&
3596 (mt
->surf
.tiling
== ISL_TILING_X
||
3597 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3598 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3599 /* Fast copy blit on skl+ supports all tiling formats. */
3600 devinfo
->gen
>= 9) &&
3601 can_blit_slice(mt
, level
, slice
))
3604 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3605 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3606 assert(can_blit_slice(mt
, level
, slice
));
3614 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3615 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3616 * arithmetic overflow.
3618 * If you call this function and use \a out_stride, then you're doing pointer
3619 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3620 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3621 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3622 * which usually have type uint32_t or GLuint.
3625 intel_miptree_map(struct brw_context
*brw
,
3626 struct intel_mipmap_tree
*mt
,
3635 ptrdiff_t *out_stride
)
3637 struct intel_miptree_map
*map
;
3639 assert(mt
->surf
.samples
== 1);
3641 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3648 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3649 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3650 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3651 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3652 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3653 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3654 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3655 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3656 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3657 #if defined(USE_SSE41)
3658 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3659 !mt
->compressed
&& cpu_has_sse4_1
&&
3660 (mt
->surf
.row_pitch
% 16 == 0)) {
3661 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3664 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3667 *out_ptr
= map
->ptr
;
3668 *out_stride
= map
->stride
;
3670 if (map
->ptr
== NULL
)
3671 intel_miptree_release_map(mt
, level
, slice
);
3675 intel_miptree_unmap(struct brw_context
*brw
,
3676 struct intel_mipmap_tree
*mt
,
3680 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3682 assert(mt
->surf
.samples
== 1);
3687 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3688 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3691 map
->unmap(brw
, mt
, map
, level
, slice
);
3693 intel_miptree_release_map(mt
, level
, slice
);
3697 get_isl_surf_dim(GLenum target
)
3701 case GL_TEXTURE_1D_ARRAY
:
3702 return ISL_SURF_DIM_1D
;
3705 case GL_TEXTURE_2D_ARRAY
:
3706 case GL_TEXTURE_RECTANGLE
:
3707 case GL_TEXTURE_CUBE_MAP
:
3708 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3709 case GL_TEXTURE_2D_MULTISAMPLE
:
3710 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3711 case GL_TEXTURE_EXTERNAL_OES
:
3712 return ISL_SURF_DIM_2D
;
3715 return ISL_SURF_DIM_3D
;
3718 unreachable("Invalid texture target");
3722 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3723 enum isl_tiling tiling
, GLenum target
)
3727 case GL_TEXTURE_1D_ARRAY
:
3728 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3729 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3732 case GL_TEXTURE_2D_ARRAY
:
3733 case GL_TEXTURE_RECTANGLE
:
3734 case GL_TEXTURE_2D_MULTISAMPLE
:
3735 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3736 case GL_TEXTURE_EXTERNAL_OES
:
3737 return ISL_DIM_LAYOUT_GEN4_2D
;
3739 case GL_TEXTURE_CUBE_MAP
:
3740 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3741 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3742 ISL_DIM_LAYOUT_GEN4_2D
);
3745 return (devinfo
->gen
>= 9 ?
3746 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3749 unreachable("Invalid texture target");
3753 intel_miptree_set_clear_color(struct brw_context
*brw
,
3754 struct intel_mipmap_tree
*mt
,
3755 union isl_color_value clear_color
)
3757 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3758 mt
->fast_clear_color
= clear_color
;
3759 if (mt
->aux_buf
->clear_color_bo
) {
3760 /* We can't update the clear color while the hardware is still using
3761 * the previous one for a resolve or sampling from it. Make sure that
3762 * there are no pending commands at this point.
3764 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3765 for (int i
= 0; i
< 4; i
++) {
3766 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3767 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3768 mt
->fast_clear_color
.u32
[i
]);
3770 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3772 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3778 union isl_color_value
3779 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3780 const struct intel_mipmap_tree
*mt
,
3781 enum isl_format view_format
, bool sampling
,
3782 struct brw_bo
**clear_color_bo
,
3783 uint32_t *clear_color_offset
)
3785 assert(mt
->aux_buf
);
3787 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3788 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3789 * we switch to using the inline clear color and do the sRGB color
3790 * conversion process defined in the OpenGL spec. The red, green, and
3791 * blue channels take part in gamma correction, while the alpha channel
3794 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3795 for (unsigned i
= 0; i
< 3; i
++) {
3796 srgb_decoded_value
.f32
[i
] =
3797 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3799 *clear_color_bo
= 0;
3800 *clear_color_offset
= 0;
3801 return srgb_decoded_value
;
3803 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3804 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3805 return mt
->fast_clear_color
;