2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
,
125 enum isl_tiling tiling
)
127 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
128 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
130 * - Support is limited to tiled render targets.
132 * Gen9 changes the restriction to Y-tile only.
135 return tiling
== ISL_TILING_Y0
;
136 else if (brw
->gen
>= 7)
137 return tiling
!= ISL_TILING_LINEAR
;
143 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
144 * can be used. This doesn't (and should not) inspect any of the properties of
147 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
148 * beneath the "Fast Color Clear" bullet (p326):
150 * - Support is for non-mip-mapped and non-array surface types only.
152 * And then later, on p327:
154 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
157 * From the Skylake documentation, it is made clear that X-tiling is no longer
160 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
164 intel_miptree_supports_ccs(struct brw_context
*brw
,
165 const struct intel_mipmap_tree
*mt
)
167 /* MCS support does not exist prior to Gen7 */
171 /* This function applies only to non-multisampled render targets. */
172 if (mt
->surf
.samples
> 1)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
186 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
187 const bool arrayed
= mt
->physical_depth0
!= 1;
190 /* Multisample surfaces with the CMS layout are not layered surfaces,
191 * yet still have physical_depth0 > 1. Assert that we don't
192 * accidentally reject a multisampled surface here. We should have
193 * rejected it earlier by explicitly checking the sample count.
195 assert(mt
->surf
.samples
== 1);
198 /* Handle the hardware restrictions...
200 * All GENs have the following restriction: "MCS buffer for non-MSRT is
201 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
203 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
204 * Non-MultiSampler Render Target Restrictions) Support is for
205 * non-mip-mapped and non-array surface types only.
207 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
208 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
209 * surfaces are supported with MCS buffer layout with these alignments in
210 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
212 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
213 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
214 * surfaces are supported with MCS buffer layout with these alignments in
215 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
217 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
220 /* There's no point in using an MCS buffer if the surface isn't in a
223 if (!brw
->mesa_format_supports_render
[mt
->format
])
227 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
228 const enum isl_format isl_format
=
229 brw_isl_format_for_mesa_format(linear_format
);
230 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
236 intel_tiling_supports_hiz(const struct brw_context
*brw
,
237 enum isl_tiling tiling
)
242 return tiling
== ISL_TILING_Y0
;
246 intel_miptree_supports_hiz(const struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
252 switch (mt
->format
) {
253 case MESA_FORMAT_Z_FLOAT32
:
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
256 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
257 case MESA_FORMAT_Z_UNORM16
:
265 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
266 const struct intel_mipmap_tree
*mt
)
268 /* For now compression is only enabled for integer formats even though
269 * there exist supported floating point formats also. This is a heuristic
270 * decision based on current public benchmarks. In none of the cases these
271 * formats provided any improvement but a few cases were seen to regress.
272 * Hence these are left to to be enabled in the future when they are known
275 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
278 if (!intel_miptree_supports_ccs(brw
, mt
))
281 /* Fast clear can be also used to clear srgb surfaces by using equivalent
282 * linear format. This trick, however, can't be extended to be used with
283 * lossless compression and therefore a check is needed to see if the format
286 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
290 * Determine depth format corresponding to a depth+stencil format,
291 * for separate stencil.
294 intel_depth_format_for_depthstencil_format(mesa_format format
) {
296 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
297 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
298 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
299 return MESA_FORMAT_Z_FLOAT32
;
306 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
307 unsigned depth0
, struct intel_mipmap_level
*table
)
309 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
311 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
313 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
314 if (!table
[level
].slice
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++)
322 free(table
[level
].slice
);
328 needs_separate_stencil(const struct brw_context
*brw
,
329 struct intel_mipmap_tree
*mt
,
330 mesa_format format
, uint32_t layout_flags
)
333 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
336 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
339 if (brw
->must_use_separate_stencil
)
342 return brw
->has_separate_stencil
&&
343 intel_miptree_supports_hiz(brw
, mt
);
347 * @param for_bo Indicates that the caller is
348 * intel_miptree_create_for_bo(). If true, then do not create
351 static struct intel_mipmap_tree
*
352 intel_miptree_create_layout(struct brw_context
*brw
,
361 uint32_t layout_flags
)
363 assert(num_samples
> 0);
365 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
369 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
370 _mesa_enum_to_string(target
),
371 _mesa_get_format_name(format
),
372 first_level
, last_level
, depth0
, mt
);
374 if (target
== GL_TEXTURE_1D_ARRAY
)
375 assert(height0
== 1);
379 mt
->first_level
= first_level
;
380 mt
->last_level
= last_level
;
381 mt
->logical_width0
= width0
;
382 mt
->logical_height0
= height0
;
383 mt
->logical_depth0
= depth0
;
384 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
385 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
386 mt
->supports_fast_clear
= false;
387 mt
->aux_state
= NULL
;
388 mt
->cpp
= _mesa_get_format_bytes(format
);
389 mt
->surf
.samples
= num_samples
;
390 mt
->compressed
= _mesa_is_format_compressed(format
);
391 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
394 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
395 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
397 int depth_multiply
= 1;
398 if (num_samples
> 1) {
399 /* Adjust width/height/depth for MSAA */
400 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
401 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
402 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
403 * "If the surface is multisampled and it is a depth or stencil
404 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
405 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
408 * +----------------------------------------------------------------+
409 * | Num Multisamples | W_l = | H_l = |
410 * +----------------------------------------------------------------+
411 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
412 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
413 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
414 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
415 * +----------------------------------------------------------------+
418 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
419 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
420 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
422 * Another more complicated explanation for these adjustments comes
423 * from the Sandybridge PRM, volume 4, part 1, page 31:
425 * "Any of the other messages (sample*, LOD, load4) used with a
426 * (4x) multisampled surface will in-effect sample a surface with
427 * double the height and width as that indicated in the surface
428 * state. Each pixel position on the original-sized surface is
429 * replaced with a 2x2 of samples with the following arrangement:
434 * Thus, when sampling from a multisampled texture, it behaves as
435 * though the layout in memory for (x,y,sample) is:
437 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
438 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
440 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
441 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
443 * However, the actual layout of multisampled data in memory is:
445 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
446 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
448 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
449 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
451 * This pattern repeats for each 2x2 pixel block.
453 * As a result, when calculating the size of our 4-sample buffer for
454 * an odd width or height, we have to align before scaling up because
455 * sample 3 is in that bottom right 2x2 block.
457 switch (num_samples
) {
459 assert(brw
->gen
>= 8);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2);
464 width0
= ALIGN(width0
, 2) * 2;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 2;
472 width0
= ALIGN(width0
, 2) * 4;
473 height0
= ALIGN(height0
, 2) * 4;
476 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
479 unreachable("not reached");
482 /* Non-interleaved */
483 depth_multiply
= num_samples
;
484 depth0
*= depth_multiply
;
488 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->surf
.msaa_layout
) {
508 case ISL_MSAA_LAYOUT_NONE
:
509 case ISL_MSAA_LAYOUT_INTERLEAVED
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case ISL_MSAA_LAYOUT_ARRAY
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
519 assert(depth0
== 6 * depth_multiply
);
521 mt
->physical_width0
= width0
;
522 mt
->physical_height0
= height0
;
523 mt
->physical_depth0
= depth0
;
525 assert(!needs_separate_stencil(brw
, mt
, format
, layout_flags
));
528 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
529 * multisampled or have an AUX buffer attached to it.
531 * GEN | MSRT | AUX_CCS_* or AUX_MCS
532 * -------------------------------------------
533 * 9 | HALIGN_16 | HALIGN_16
534 * 8 | HALIGN_ANY | HALIGN_16
538 if (intel_miptree_supports_ccs(brw
, mt
)) {
539 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
540 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
541 } else if (brw
->gen
>= 9 && num_samples
> 1) {
542 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
544 const UNUSED
bool is_lossless_compressed_aux
=
545 brw
->gen
>= 9 && num_samples
== 1 &&
546 mt
->format
== MESA_FORMAT_R_UINT32
;
548 /* For now, nothing else has this requirement */
549 assert(is_lossless_compressed_aux
||
550 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
553 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
554 intel_miptree_release(&mt
);
563 * Choose the aux usage for this miptree. This function must be called fairly
564 * late in the miptree create process after we have a tiling.
567 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
568 struct intel_mipmap_tree
*mt
)
570 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
572 const unsigned no_flags
= 0;
573 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
574 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
575 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
576 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
577 intel_miptree_supports_ccs(brw
, mt
)) {
578 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
579 brw
->gen
>= 9 && !mt
->is_scanout
&&
580 intel_miptree_supports_ccs_e(brw
, mt
)) {
581 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
583 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
585 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
586 intel_miptree_supports_hiz(brw
, mt
)) {
587 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
590 /* We can do fast-clear on all auxiliary surface types that are
591 * allocated through the normal texture creation paths.
593 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
594 mt
->supports_fast_clear
= true;
599 * Choose an appropriate uncompressed format for a requested
600 * compressed format, if unsupported.
603 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
605 /* No need to lower ETC formats on these platforms,
606 * they are supported natively.
608 if (brw
->gen
>= 8 || brw
->is_baytrail
)
612 case MESA_FORMAT_ETC1_RGB8
:
613 return MESA_FORMAT_R8G8B8X8_UNORM
;
614 case MESA_FORMAT_ETC2_RGB8
:
615 return MESA_FORMAT_R8G8B8X8_UNORM
;
616 case MESA_FORMAT_ETC2_SRGB8
:
617 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
618 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
619 return MESA_FORMAT_B8G8R8A8_SRGB
;
620 case MESA_FORMAT_ETC2_RGBA8_EAC
:
621 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
622 return MESA_FORMAT_R8G8B8A8_UNORM
;
623 case MESA_FORMAT_ETC2_R11_EAC
:
624 return MESA_FORMAT_R_UNORM16
;
625 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
626 return MESA_FORMAT_R_SNORM16
;
627 case MESA_FORMAT_ETC2_RG11_EAC
:
628 return MESA_FORMAT_R16G16_UNORM
;
629 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
630 return MESA_FORMAT_R16G16_SNORM
;
632 /* Non ETC1 / ETC2 format */
638 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
640 /* In case of physical dimensions one needs to consider also the layout.
641 * See isl_calc_phys_level0_extent_sa().
643 if (surf
->dim
!= ISL_SURF_DIM_3D
)
644 return surf
->phys_level0_sa
.array_len
;
646 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
647 return minify(surf
->phys_level0_sa
.array_len
, level
);
649 return minify(surf
->phys_level0_sa
.depth
, level
);
652 /** \brief Assert that the level and layer are valid for the miptree. */
654 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
662 assert(level
>= mt
->first_level
);
663 assert(level
<= mt
->last_level
);
665 if (mt
->surf
.size
> 0)
666 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
668 assert(layer
< mt
->level
[level
].depth
);
671 static enum isl_aux_state
**
672 create_aux_state_map(struct intel_mipmap_tree
*mt
,
673 enum isl_aux_state initial
)
675 const uint32_t levels
= mt
->last_level
+ 1;
677 uint32_t total_slices
= 0;
678 for (uint32_t level
= 0; level
< levels
; level
++) {
679 if (mt
->surf
.size
> 0)
680 total_slices
+= get_num_phys_layers(&mt
->surf
, level
);
682 total_slices
+= mt
->level
[level
].depth
;
685 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
687 /* We're going to allocate a single chunk of data for both the per-level
688 * reference array and the arrays of aux_state. This makes cleanup
689 * significantly easier.
691 const size_t total_size
= per_level_array_size
+
692 total_slices
* sizeof(enum isl_aux_state
);
693 void *data
= malloc(total_size
);
697 enum isl_aux_state
**per_level_arr
= data
;
698 enum isl_aux_state
*s
= data
+ per_level_array_size
;
699 for (uint32_t level
= 0; level
< levels
; level
++) {
700 per_level_arr
[level
] = s
;
702 unsigned level_depth
;
703 if (mt
->surf
.size
> 0)
704 level_depth
= get_num_phys_layers(&mt
->surf
, level
);
706 level_depth
= mt
->level
[level
].depth
;
708 for (uint32_t a
= 0; a
< level_depth
; a
++)
711 assert((void *)s
== data
+ total_size
);
713 return per_level_arr
;
717 free_aux_state_map(enum isl_aux_state
**state
)
723 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
724 enum isl_tiling tiling
, unsigned samples
)
729 if (tiling
== ISL_TILING_LINEAR
)
732 /* If the width is much smaller than a tile, don't bother tiling. */
736 if (ALIGN(row_pitch
, 512) >= 32768) {
737 perf_debug("row pitch %u too large to blit, falling back to untiled",
746 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
747 enum isl_tiling tiling
)
749 /* If the BO is too large to fit in the aperture, we need to use the
750 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
751 * handle Y-tiling, so we need to fall back to X.
753 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
754 tiling
== ISL_TILING_Y0
)
760 static struct intel_mipmap_tree
*
761 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
762 unsigned first_level
, unsigned last_level
,
763 unsigned width0
, unsigned height0
, unsigned depth0
,
764 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
765 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
766 unsigned row_pitch
, struct brw_bo
*bo
)
768 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
772 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
780 if (target
== GL_TEXTURE_CUBE_MAP
||
781 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
782 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
784 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
786 _mesa_enum_to_string(target
),
787 _mesa_get_format_name(format
),
788 num_samples
, width0
, height0
, depth0
,
789 first_level
, last_level
, mt
);
791 struct isl_surf_init_info init_info
= {
792 .dim
= get_isl_surf_dim(target
),
793 .format
= translate_tex_format(brw
, format
, false),
796 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
797 .levels
= last_level
- first_level
+ 1,
798 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
799 .samples
= num_samples
,
800 .row_pitch
= row_pitch
,
801 .usage
= isl_usage_flags
,
802 .tiling_flags
= tiling_flags
,
805 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
808 /* In case caller doesn't specifically request Y-tiling (needed
809 * unconditionally for depth), check for corner cases needing special
812 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
813 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
814 mt
->surf
.tiling
, mt
->surf
.samples
)) {
815 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
816 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
818 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
819 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
820 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
825 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
826 * the size may not be multiple of row_pitch.
827 * See isl_apply_surface_padding().
829 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
830 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
833 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
835 isl_tiling_to_i915_tiling(
837 mt
->surf
.row_pitch
, alloc_flags
);
844 mt
->first_level
= first_level
;
845 mt
->last_level
= last_level
;
848 mt
->aux_state
= NULL
;
849 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
850 mt
->compressed
= _mesa_is_format_compressed(format
);
855 intel_miptree_release(&mt
);
860 make_separate_stencil_surface(struct brw_context
*brw
,
861 struct intel_mipmap_tree
*mt
)
863 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
864 0, mt
->surf
.levels
- 1,
865 mt
->surf
.logical_level0_px
.width
,
866 mt
->surf
.logical_level0_px
.height
,
867 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
868 mt
->surf
.logical_level0_px
.depth
:
869 mt
->surf
.logical_level0_px
.array_len
,
870 mt
->surf
.samples
, ISL_TILING_W_BIT
,
871 ISL_SURF_USAGE_STENCIL_BIT
|
872 ISL_SURF_USAGE_TEXTURE_BIT
,
873 BO_ALLOC_FOR_RENDER
, 0, NULL
);
878 mt
->stencil_mt
->r8stencil_needs_update
= true;
884 force_linear_tiling(uint32_t layout_flags
)
886 /* ANY includes NONE and Y bit. */
887 if (layout_flags
& MIPTREE_LAYOUT_TILING_Y
)
890 return layout_flags
& MIPTREE_LAYOUT_TILING_NONE
;
893 static struct intel_mipmap_tree
*
894 miptree_create(struct brw_context
*brw
,
903 uint32_t layout_flags
)
905 if (format
== MESA_FORMAT_S_UINT8
)
906 return make_surface(brw
, target
, format
, first_level
, last_level
,
907 width0
, height0
, depth0
, num_samples
,
909 ISL_SURF_USAGE_STENCIL_BIT
|
910 ISL_SURF_USAGE_TEXTURE_BIT
,
915 const GLenum base_format
= _mesa_get_format_base_format(format
);
916 if ((base_format
== GL_DEPTH_COMPONENT
||
917 base_format
== GL_DEPTH_STENCIL
) &&
918 !force_linear_tiling(layout_flags
)) {
919 /* Fix up the Z miptree format for how we're splitting out separate
920 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
922 const mesa_format depth_only_format
=
923 intel_depth_format_for_depthstencil_format(format
);
924 struct intel_mipmap_tree
*mt
= make_surface(
925 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
926 first_level
, last_level
,
927 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
928 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
929 BO_ALLOC_FOR_RENDER
, 0, NULL
);
931 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
) &&
932 !make_separate_stencil_surface(brw
, mt
)) {
933 intel_miptree_release(&mt
);
937 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
938 intel_miptree_choose_aux_usage(brw
, mt
);
943 struct intel_mipmap_tree
*mt
;
944 mesa_format tex_format
= format
;
945 mesa_format etc_format
= MESA_FORMAT_NONE
;
946 uint32_t alloc_flags
= 0;
948 format
= intel_lower_compressed_format(brw
, format
);
950 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
952 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
953 mt
= intel_miptree_create_layout(brw
, target
, format
,
954 first_level
, last_level
, width0
,
955 height0
, depth0
, num_samples
,
960 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
961 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
963 mt
->etc_format
= etc_format
;
965 if (format
== MESA_FORMAT_S_UINT8
) {
966 /* Align to size of W tile, 64x64. */
967 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
968 ALIGN(mt
->total_width
, 64),
969 ALIGN(mt
->total_height
, 64),
971 isl_tiling_to_i915_tiling(
976 /* The stencil buffer has quirky pitch requirements. From the
977 * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
978 * dword 1 bits 16:0 - Surface Pitch):
980 * The pitch must be set to 2x the value computed based on width, as
981 * the stencil buffer is stored with two rows interleaved.
983 * While the Ivybridge PRM lacks this comment, the BSpec contains the
984 * same text, and experiments indicate that this is necessary.
986 mt
->surf
.row_pitch
*= 2;
988 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
989 mt
->total_width
, mt
->total_height
,
991 isl_tiling_to_i915_tiling(
997 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
998 mt
->bo
->cache_coherent
= false;
1000 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1001 intel_miptree_choose_aux_usage(brw
, mt
);
1006 struct intel_mipmap_tree
*
1007 intel_miptree_create(struct brw_context
*brw
,
1016 uint32_t layout_flags
)
1018 assert(num_samples
> 0);
1020 struct intel_mipmap_tree
*mt
= miptree_create(
1021 brw
, target
, format
,
1022 first_level
, last_level
,
1023 width0
, height0
, depth0
, num_samples
,
1028 if (need_to_retile_as_x(brw
, mt
->bo
->size
, mt
->surf
.tiling
)) {
1029 const uint32_t alloc_flags
=
1030 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
1031 BO_ALLOC_FOR_RENDER
: 0;
1032 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
1033 mt
->total_width
, mt
->total_height
);
1035 mt
->surf
.tiling
= ISL_TILING_X
;
1036 brw_bo_unreference(mt
->bo
);
1037 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
1038 mt
->total_width
, mt
->total_height
, mt
->cpp
,
1039 isl_tiling_to_i915_tiling(
1041 &mt
->surf
.row_pitch
, alloc_flags
);
1047 intel_miptree_release(&mt
);
1051 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1052 intel_miptree_release(&mt
);
1059 struct intel_mipmap_tree
*
1060 intel_miptree_create_for_bo(struct brw_context
*brw
,
1068 uint32_t layout_flags
)
1070 struct intel_mipmap_tree
*mt
;
1071 uint32_t tiling
, swizzle
;
1072 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
1073 const GLenum base_format
= _mesa_get_format_base_format(format
);
1075 if ((base_format
== GL_DEPTH_COMPONENT
||
1076 base_format
== GL_DEPTH_STENCIL
)) {
1077 const mesa_format depth_only_format
=
1078 intel_depth_format_for_depthstencil_format(format
);
1079 mt
= make_surface(brw
, target
,
1080 brw
->gen
>= 6 ? depth_only_format
: format
,
1081 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
1082 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
1083 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1085 brw_bo_reference(bo
);
1087 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1088 intel_miptree_choose_aux_usage(brw
, mt
);
1091 } else if (format
== MESA_FORMAT_S_UINT8
) {
1092 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
1093 0, 0, width
, height
, depth
, 1,
1095 ISL_SURF_USAGE_STENCIL_BIT
|
1096 ISL_SURF_USAGE_TEXTURE_BIT
,
1097 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1101 assert(bo
->size
>= mt
->surf
.size
);
1103 brw_bo_reference(bo
);
1107 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
1109 /* Nothing will be able to use this miptree with the BO if the offset isn't
1112 if (tiling
!= I915_TILING_NONE
)
1113 assert(offset
% 4096 == 0);
1115 /* miptrees can't handle negative pitch. If you need flipping of images,
1116 * that's outside of the scope of the mt.
1120 /* The BO already has a tiling format and we shouldn't confuse the lower
1121 * layers by making it try to find a tiling format again.
1123 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
1124 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
1126 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
1127 mt
= intel_miptree_create_layout(brw
, target
, format
,
1129 width
, height
, depth
,
1130 1 /* num_samples */,
1135 brw_bo_reference(bo
);
1137 mt
->surf
.row_pitch
= pitch
;
1138 mt
->offset
= offset
;
1139 mt
->surf
.tiling
= isl_tiling_from_i915_tiling(tiling
);
1141 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1142 intel_miptree_choose_aux_usage(brw
, mt
);
1147 static struct intel_mipmap_tree
*
1148 miptree_create_for_planar_image(struct brw_context
*brw
,
1149 __DRIimage
*image
, GLenum target
)
1151 struct intel_image_format
*f
= image
->planar_format
;
1152 struct intel_mipmap_tree
*planar_mt
= NULL
;
1154 for (int i
= 0; i
< f
->nplanes
; i
++) {
1155 const int index
= f
->planes
[i
].buffer_index
;
1156 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1157 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1158 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1159 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1161 /* Disable creation of the texture's aux buffers because the driver
1162 * exposes no EGL API to manage them. That is, there is no API for
1163 * resolving the aux buffer's content to the main buffer nor for
1164 * invalidating the aux buffer's content.
1166 struct intel_mipmap_tree
*mt
=
1167 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1168 image
->offsets
[index
],
1170 image
->strides
[index
],
1171 MIPTREE_LAYOUT_DISABLE_AUX
);
1175 mt
->target
= target
;
1180 planar_mt
->plane
[i
- 1] = mt
;
1186 struct intel_mipmap_tree
*
1187 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1188 __DRIimage
*image
, GLenum target
,
1189 enum isl_colorspace colorspace
,
1190 bool is_winsys_image
)
1192 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1193 assert(colorspace
== ISL_COLORSPACE_NONE
||
1194 colorspace
== ISL_COLORSPACE_YUV
);
1195 return miptree_create_for_planar_image(brw
, image
, target
);
1198 mesa_format format
= image
->format
;
1199 switch (colorspace
) {
1200 case ISL_COLORSPACE_NONE
:
1201 /* Keep the image format unmodified */
1204 case ISL_COLORSPACE_LINEAR
:
1205 format
=_mesa_get_srgb_format_linear(format
);
1208 case ISL_COLORSPACE_SRGB
:
1209 format
=_mesa_get_linear_format_srgb(format
);
1213 unreachable("Inalid colorspace for non-planar image");
1216 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1217 /* The texture storage paths in core Mesa detect if the driver does not
1218 * support the user-requested format, and then searches for a
1219 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1220 * do the fallbacks here for important formats.
1222 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1223 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1224 * the Chrome OS compositor consumes as dma_buf EGLImages.
1226 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1229 if (!brw
->ctx
.TextureFormatSupported
[format
])
1232 /* If this image comes in from a window system, we have different
1233 * requirements than if it comes in via an EGL import operation. Window
1234 * system images can use any form of auxiliary compression we wish because
1235 * they get "flushed" before being handed off to the window system and we
1236 * have the opportunity to do resolves. Window system buffers also may be
1237 * used for scanout so we need to flag that appropriately.
1239 const uint32_t mt_layout_flags
=
1240 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1242 /* Disable creation of the texture's aux buffers because the driver exposes
1243 * no EGL API to manage them. That is, there is no API for resolving the aux
1244 * buffer's content to the main buffer nor for invalidating the aux buffer's
1247 struct intel_mipmap_tree
*mt
=
1248 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1249 image
->offset
, image
->width
, image
->height
, 1,
1250 image
->pitch
, mt_layout_flags
);
1254 mt
->target
= target
;
1255 mt
->level
[0].level_x
= image
->tile_x
;
1256 mt
->level
[0].level_y
= image
->tile_y
;
1257 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1258 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1260 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1261 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1262 * trouble resolving back to destination image due to alignment issues.
1264 if (!brw
->has_surface_tile_offset
) {
1265 uint32_t draw_x
, draw_y
;
1266 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1268 if (draw_x
!= 0 || draw_y
!= 0) {
1269 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1270 intel_miptree_release(&mt
);
1275 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1276 intel_miptree_release(&mt
);
1284 * For a singlesample renderbuffer, this simply wraps the given BO with a
1287 * For a multisample renderbuffer, this wraps the window system's
1288 * (singlesample) BO with a singlesample miptree attached to the
1289 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1290 * that will contain the actual rendering (which is lazily resolved to
1291 * irb->singlesample_mt).
1294 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1295 struct intel_renderbuffer
*irb
,
1296 struct intel_mipmap_tree
*singlesample_mt
,
1297 uint32_t width
, uint32_t height
,
1300 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1301 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1302 mesa_format format
= rb
->Format
;
1303 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1305 /* Only the front and back buffers, which are color buffers, are allocated
1306 * through the image loader.
1308 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1309 _mesa_get_format_base_format(format
) == GL_RGBA
);
1311 assert(singlesample_mt
);
1313 if (num_samples
== 1) {
1314 intel_miptree_release(&irb
->mt
);
1315 irb
->mt
= singlesample_mt
;
1317 assert(!irb
->singlesample_mt
);
1319 intel_miptree_release(&irb
->singlesample_mt
);
1320 irb
->singlesample_mt
= singlesample_mt
;
1323 irb
->mt
->logical_width0
!= width
||
1324 irb
->mt
->logical_height0
!= height
) {
1325 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1330 if (!multisample_mt
)
1333 irb
->need_downsample
= false;
1334 intel_miptree_release(&irb
->mt
);
1335 irb
->mt
= multisample_mt
;
1341 intel_miptree_release(&irb
->mt
);
1345 struct intel_mipmap_tree
*
1346 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1350 uint32_t num_samples
)
1352 struct intel_mipmap_tree
*mt
;
1354 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1355 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1356 MIPTREE_LAYOUT_TILING_ANY
|
1357 MIPTREE_LAYOUT_FOR_SCANOUT
;
1359 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1360 width
, height
, depth
, num_samples
,
1368 intel_miptree_release(&mt
);
1373 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1374 struct intel_mipmap_tree
*src
)
1379 intel_miptree_release(dst
);
1383 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1390 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1392 if (aux_buf
== NULL
)
1395 brw_bo_unreference(aux_buf
->bo
);
1401 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1406 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1407 if (--(*mt
)->refcount
<= 0) {
1410 DBG("%s deleting %p\n", __func__
, *mt
);
1412 brw_bo_unreference((*mt
)->bo
);
1413 intel_miptree_release(&(*mt
)->stencil_mt
);
1414 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1415 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1416 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1417 free_aux_state_map((*mt
)->aux_state
);
1419 intel_miptree_release(&(*mt
)->plane
[0]);
1420 intel_miptree_release(&(*mt
)->plane
[1]);
1422 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1423 free((*mt
)->level
[i
].slice
);
1433 intel_get_image_dims(struct gl_texture_image
*image
,
1434 int *width
, int *height
, int *depth
)
1436 switch (image
->TexObject
->Target
) {
1437 case GL_TEXTURE_1D_ARRAY
:
1438 /* For a 1D Array texture the OpenGL API will treat the image height as
1439 * the number of array slices. For Intel hardware, we treat the 1D array
1440 * as a 2D Array with a height of 1. So, here we want to swap image
1443 assert(image
->Depth
== 1);
1444 *width
= image
->Width
;
1446 *depth
= image
->Height
;
1448 case GL_TEXTURE_CUBE_MAP
:
1449 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1450 * though we really have 6 slices.
1452 assert(image
->Depth
== 1);
1453 *width
= image
->Width
;
1454 *height
= image
->Height
;
1458 *width
= image
->Width
;
1459 *height
= image
->Height
;
1460 *depth
= image
->Depth
;
1466 * Can the image be pulled into a unified mipmap tree? This mirrors
1467 * the completeness test in a lot of ways.
1469 * Not sure whether I want to pass gl_texture_image here.
1472 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1473 struct gl_texture_image
*image
)
1475 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1476 GLuint level
= intelImage
->base
.Base
.Level
;
1477 int width
, height
, depth
;
1479 /* glTexImage* choose the texture object based on the target passed in, and
1480 * objects can't change targets over their lifetimes, so this should be
1483 assert(image
->TexObject
->Target
== mt
->target
);
1485 mesa_format mt_format
= mt
->format
;
1486 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1487 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1488 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1489 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1490 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1491 mt_format
= mt
->etc_format
;
1493 if (image
->TexFormat
!= mt_format
)
1496 intel_get_image_dims(image
, &width
, &height
, &depth
);
1498 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1501 if (mt
->surf
.size
> 0) {
1502 if (level
>= mt
->surf
.levels
)
1505 const unsigned level_depth
=
1506 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1507 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1508 mt
->surf
.logical_level0_px
.array_len
;
1510 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1511 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1512 depth
== level_depth
&&
1513 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1516 int level_depth
= mt
->level
[level
].depth
;
1517 if (mt
->surf
.samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1518 level_depth
/= mt
->surf
.samples
;
1520 /* Test image dimensions against the base level image adjusted for
1521 * minification. This will also catch images not present in the
1522 * tree, changed targets, etc.
1524 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1525 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1526 depth
!= level_depth
) {
1530 /* Core uses sample number of zero to indicate single-sampled. */
1531 if (MAX2(image
->NumSamples
, 1) != mt
->surf
.samples
)
1539 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1541 GLuint x
, GLuint y
, GLuint d
)
1543 mt
->level
[level
].depth
= d
;
1544 mt
->level
[level
].level_x
= x
;
1545 mt
->level
[level
].level_y
= y
;
1547 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1550 assert(mt
->level
[level
].slice
);
1552 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1553 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1558 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1559 GLuint level
, GLuint img
,
1562 if (img
== 0 && level
== 0)
1563 assert(x
== 0 && y
== 0);
1565 assert(img
< mt
->level
[level
].depth
);
1567 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1568 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1570 DBG("%s level %d img %d pos %d,%d\n",
1571 __func__
, level
, img
,
1572 mt
->level
[level
].slice
[img
].x_offset
,
1573 mt
->level
[level
].slice
[img
].y_offset
);
1577 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1578 GLuint level
, GLuint slice
,
1579 GLuint
*x
, GLuint
*y
)
1581 if (level
== 0 && slice
== 0) {
1582 *x
= mt
->level
[0].level_x
;
1583 *y
= mt
->level
[0].level_y
;
1587 if (mt
->surf
.size
> 0) {
1588 uint32_t x_offset_sa
, y_offset_sa
;
1590 /* Miptree itself can have an offset only if it represents a single
1591 * slice in an imported buffer object.
1592 * See intel_miptree_create_for_dri_image().
1594 assert(mt
->level
[0].level_x
== 0);
1595 assert(mt
->level
[0].level_y
== 0);
1597 /* Given level is relative to level zero while the miptree may be
1598 * represent just a subset of all levels starting from 'first_level'.
1600 assert(level
>= mt
->first_level
);
1601 level
-= mt
->first_level
;
1603 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1604 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1605 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1606 &x_offset_sa
, &y_offset_sa
);
1613 assert(slice
< mt
->level
[level
].depth
);
1615 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1616 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1621 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1622 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1623 * and tile_h is set to 1.
1626 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1627 uint32_t *tile_w
, uint32_t *tile_h
)
1638 case ISL_TILING_LINEAR
:
1643 unreachable("not reached");
1649 * This function computes masks that may be used to select the bits of the X
1650 * and Y coordinates that indicate the offset within a tile. If the BO is
1651 * untiled, the masks are set to 0.
1654 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1655 uint32_t *mask_x
, uint32_t *mask_y
)
1657 uint32_t tile_w_bytes
, tile_h
;
1659 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1661 *mask_x
= tile_w_bytes
/ cpp
- 1;
1662 *mask_y
= tile_h
- 1;
1666 * Compute the offset (in bytes) from the start of the BO to the given x
1667 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1668 * multiples of the tile size.
1671 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1672 uint32_t x
, uint32_t y
)
1675 uint32_t pitch
= mt
->surf
.row_pitch
;
1677 switch (mt
->surf
.tiling
) {
1679 unreachable("not reached");
1680 case ISL_TILING_LINEAR
:
1681 return y
* pitch
+ x
* cpp
;
1683 assert((x
% (512 / cpp
)) == 0);
1684 assert((y
% 8) == 0);
1685 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1687 assert((x
% (128 / cpp
)) == 0);
1688 assert((y
% 32) == 0);
1689 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1694 * Rendering with tiled buffers requires that the base address of the buffer
1695 * be aligned to a page boundary. For renderbuffers, and sometimes with
1696 * textures, we may want the surface to point at a texture image level that
1697 * isn't at a page boundary.
1699 * This function returns an appropriately-aligned base offset
1700 * according to the tiling restrictions, plus any required x/y offset
1704 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1705 GLuint level
, GLuint slice
,
1710 uint32_t mask_x
, mask_y
;
1712 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1713 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1715 *tile_x
= x
& mask_x
;
1716 *tile_y
= y
& mask_y
;
1718 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1722 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1723 struct intel_mipmap_tree
*src_mt
,
1724 unsigned src_level
, unsigned src_layer
,
1725 struct intel_mipmap_tree
*dst_mt
,
1726 unsigned dst_level
, unsigned dst_layer
,
1727 unsigned width
, unsigned height
)
1730 ptrdiff_t src_stride
, dst_stride
;
1731 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1732 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1734 intel_miptree_map(brw
, src_mt
,
1735 src_level
, src_layer
,
1738 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1741 intel_miptree_map(brw
, dst_mt
,
1742 dst_level
, dst_layer
,
1745 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1749 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1750 _mesa_get_format_name(src_mt
->format
),
1751 src_mt
, src
, src_stride
,
1752 _mesa_get_format_name(dst_mt
->format
),
1753 dst_mt
, dst
, dst_stride
,
1756 int row_size
= cpp
* width
;
1757 if (src_stride
== row_size
&&
1758 dst_stride
== row_size
) {
1759 memcpy(dst
, src
, row_size
* height
);
1761 for (int i
= 0; i
< height
; i
++) {
1762 memcpy(dst
, src
, row_size
);
1768 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1769 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1771 /* Don't forget to copy the stencil data over, too. We could have skipped
1772 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1773 * shuffling the two data sources in/out of temporary storage instead of
1774 * the direct mapping we get this way.
1776 if (dst_mt
->stencil_mt
) {
1777 assert(src_mt
->stencil_mt
);
1778 intel_miptree_copy_slice_sw(brw
,
1779 src_mt
->stencil_mt
, src_level
, src_layer
,
1780 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1786 intel_miptree_copy_slice(struct brw_context
*brw
,
1787 struct intel_mipmap_tree
*src_mt
,
1788 unsigned src_level
, unsigned src_layer
,
1789 struct intel_mipmap_tree
*dst_mt
,
1790 unsigned dst_level
, unsigned dst_layer
)
1793 mesa_format format
= src_mt
->format
;
1794 uint32_t width
, height
;
1796 if (src_mt
->surf
.size
> 0) {
1797 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1798 src_level
- src_mt
->first_level
);
1799 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1800 src_level
- src_mt
->first_level
);
1803 get_num_phys_layers(&src_mt
->surf
,
1804 src_level
- src_mt
->first_level
));
1806 width
= minify(src_mt
->physical_width0
,
1807 src_level
- src_mt
->first_level
);
1808 height
= minify(src_mt
->physical_height0
,
1809 src_level
- src_mt
->first_level
);
1810 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1813 assert(src_mt
->format
== dst_mt
->format
);
1815 if (dst_mt
->compressed
) {
1817 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1818 height
= ALIGN_NPOT(height
, j
) / j
;
1819 width
= ALIGN_NPOT(width
, i
) / i
;
1822 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1823 * below won't apply since we can't do the depth's Y tiling or the
1824 * stencil's W tiling in the blitter.
1826 if (src_mt
->stencil_mt
) {
1827 intel_miptree_copy_slice_sw(brw
,
1828 src_mt
, src_level
, src_layer
,
1829 dst_mt
, dst_level
, dst_layer
,
1834 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1835 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1837 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1840 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1841 _mesa_get_format_name(src_mt
->format
),
1842 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1843 _mesa_get_format_name(dst_mt
->format
),
1844 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1847 if (!intel_miptree_blit(brw
,
1848 src_mt
, src_level
, src_layer
, 0, 0, false,
1849 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1850 width
, height
, GL_COPY
)) {
1851 perf_debug("miptree validate blit for %s failed\n",
1852 _mesa_get_format_name(format
));
1854 intel_miptree_copy_slice_sw(brw
,
1855 src_mt
, src_level
, src_layer
,
1856 dst_mt
, dst_level
, dst_layer
,
1862 * Copies the image's current data to the given miptree, and associates that
1863 * miptree with the image.
1865 * If \c invalidate is true, then the actual image data does not need to be
1866 * copied, but the image still needs to be associated to the new miptree (this
1867 * is set to true if we're about to clear the image).
1870 intel_miptree_copy_teximage(struct brw_context
*brw
,
1871 struct intel_texture_image
*intelImage
,
1872 struct intel_mipmap_tree
*dst_mt
,
1875 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1876 struct intel_texture_object
*intel_obj
=
1877 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1878 int level
= intelImage
->base
.Base
.Level
;
1879 const unsigned face
= intelImage
->base
.Base
.Face
;
1880 unsigned start_layer
, end_layer
;
1882 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1884 assert(intelImage
->base
.Base
.Height
);
1886 end_layer
= intelImage
->base
.Base
.Height
- 1;
1887 } else if (face
> 0) {
1891 assert(intelImage
->base
.Base
.Depth
);
1893 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1897 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1898 intel_miptree_copy_slice(brw
,
1904 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1905 intel_obj
->needs_validate
= true;
1909 intel_miptree_init_mcs(struct brw_context
*brw
,
1910 struct intel_mipmap_tree
*mt
,
1913 assert(mt
->mcs_buf
!= NULL
);
1915 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1917 * When MCS buffer is enabled and bound to MSRT, it is required that it
1918 * is cleared prior to any rendering.
1920 * Since we don't use the MCS buffer for any purpose other than rendering,
1921 * it makes sense to just clear it immediately upon allocation.
1923 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1925 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1926 if (unlikely(map
== NULL
)) {
1927 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1928 brw_bo_unreference(mt
->mcs_buf
->bo
);
1933 memset(data
, init_value
, mt
->mcs_buf
->size
);
1934 brw_bo_unmap(mt
->mcs_buf
->bo
);
1937 static struct intel_miptree_aux_buffer
*
1938 intel_alloc_aux_buffer(struct brw_context
*brw
,
1940 const struct isl_surf
*aux_surf
,
1941 uint32_t alloc_flags
,
1942 struct intel_mipmap_tree
*mt
)
1944 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1948 buf
->size
= aux_surf
->size
;
1949 buf
->pitch
= aux_surf
->row_pitch
;
1950 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1952 /* ISL has stricter set of alignment rules then the drm allocator.
1953 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1954 * trying to recalculate based on different format block sizes.
1956 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1957 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1963 buf
->surf
= *aux_surf
;
1969 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1970 struct intel_mipmap_tree
*mt
,
1973 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1974 assert(mt
->mcs_buf
== NULL
);
1975 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1977 /* Multisampled miptrees are only supported for single level. */
1978 assert(mt
->first_level
== 0);
1979 enum isl_aux_state
**aux_state
=
1980 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1984 struct isl_surf temp_main_surf
;
1985 struct isl_surf temp_mcs_surf
;
1987 /* Create first an ISL presentation for the main color surface and let ISL
1988 * calculate equivalent MCS surface against it.
1990 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1991 MAYBE_UNUSED
bool ok
=
1992 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1995 /* Buffer needs to be initialised requiring the buffer to be immediately
1996 * mapped to cpu space for writing. Therefore do not use the gpu access
1997 * flag which can cause an unnecessary delay if the backing pages happened
1998 * to be just used by the GPU.
2000 const uint32_t alloc_flags
= 0;
2001 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
2002 &temp_mcs_surf
, alloc_flags
, mt
);
2008 mt
->aux_state
= aux_state
;
2010 intel_miptree_init_mcs(brw
, mt
, 0xFF);
2016 intel_miptree_alloc_ccs(struct brw_context
*brw
,
2017 struct intel_mipmap_tree
*mt
)
2019 assert(mt
->mcs_buf
== NULL
);
2020 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
2021 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2023 struct isl_surf temp_main_surf
;
2024 struct isl_surf temp_ccs_surf
;
2026 /* Create first an ISL presentation for the main color surface and let ISL
2027 * calculate equivalent CCS surface against it.
2029 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
2030 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
2034 assert(temp_ccs_surf
.size
&&
2035 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
2037 enum isl_aux_state
**aux_state
=
2038 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
2042 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
2043 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
2045 * "If Software wants to enable Color Compression without Fast clear,
2046 * Software needs to initialize MCS with zeros."
2048 * A CCS value of 0 indicates that the corresponding block is in the
2049 * pass-through state which is what we want.
2051 * For CCS_D, on the other hand, we don't care as we're about to perform a
2052 * fast-clear operation. In that case, being hot in caches more useful.
2054 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
2055 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
2056 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
2057 &temp_ccs_surf
, alloc_flags
, mt
);
2063 mt
->aux_state
= aux_state
;
2069 * Helper for intel_miptree_alloc_hiz() that sets
2070 * \c mt->level[level].has_hiz. Return true if and only if
2071 * \c has_hiz was set.
2074 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
2075 struct intel_mipmap_tree
*mt
,
2078 assert(mt
->hiz_buf
);
2079 assert(mt
->surf
.size
> 0);
2081 if (brw
->gen
>= 8 || brw
->is_haswell
) {
2082 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
2083 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
2085 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
2086 * and the height is 4 aligned. This allows our HiZ support
2087 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
2088 * we can grow the width & height to allow the HiZ op to
2089 * force the proper size alignments.
2091 if (level
> 0 && ((width
& 7) || (height
& 3))) {
2092 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
2097 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
2098 mt
->level
[level
].has_hiz
= true;
2103 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2104 struct intel_mipmap_tree
*mt
)
2106 assert(mt
->hiz_buf
== NULL
);
2107 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
2109 enum isl_aux_state
**aux_state
=
2110 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
2114 struct isl_surf temp_hiz_surf
;
2116 MAYBE_UNUSED
bool ok
=
2117 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
2120 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
2121 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
2122 &temp_hiz_surf
, alloc_flags
, mt
);
2129 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2130 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2132 mt
->aux_state
= aux_state
;
2139 * Allocate the initial aux surface for a miptree based on mt->aux_usage
2141 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
2142 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
2143 * compress clear color so we wait until an actual fast-clear to allocate it.
2146 intel_miptree_alloc_aux(struct brw_context
*brw
,
2147 struct intel_mipmap_tree
*mt
)
2149 switch (mt
->aux_usage
) {
2150 case ISL_AUX_USAGE_NONE
:
2153 case ISL_AUX_USAGE_HIZ
:
2154 assert(!_mesa_is_format_color_format(mt
->format
));
2155 if (!intel_miptree_alloc_hiz(brw
, mt
))
2159 case ISL_AUX_USAGE_MCS
:
2160 assert(_mesa_is_format_color_format(mt
->format
));
2161 assert(mt
->surf
.samples
> 1);
2162 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
2166 case ISL_AUX_USAGE_CCS_D
:
2167 /* Since CCS_D can only compress clear color so we wait until an actual
2168 * fast-clear to allocate it.
2172 case ISL_AUX_USAGE_CCS_E
:
2173 assert(_mesa_is_format_color_format(mt
->format
));
2174 assert(mt
->surf
.samples
== 1);
2175 if (!intel_miptree_alloc_ccs(brw
, mt
))
2180 unreachable("Invalid aux usage");
2185 * Can the miptree sample using the hiz buffer?
2188 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2189 struct intel_mipmap_tree
*mt
)
2191 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2192 * so keep things conservative for now and never enable it unless we're SKL+.
2202 /* It seems the hardware won't fallback to the depth buffer if some of the
2203 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2204 * of the texture to be HiZ enabled.
2206 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
2207 if (!intel_miptree_level_has_hiz(mt
, level
))
2211 /* If compressed multisampling is enabled, then we use it for the auxiliary
2214 * From the BDW PRM (Volume 2d: Command Reference: Structures
2215 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2217 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2218 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2220 * There is no such blurb for 1D textures, but there is sufficient evidence
2221 * that this is broken on SKL+.
2223 return (mt
->surf
.samples
== 1 &&
2224 mt
->target
!= GL_TEXTURE_3D
&&
2225 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2229 * Does the miptree slice have hiz enabled?
2232 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2234 intel_miptree_check_level_layer(mt
, level
, 0);
2235 return mt
->level
[level
].has_hiz
;
2239 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2240 unsigned start_level
, unsigned num_levels
,
2241 unsigned start_layer
, unsigned num_layers
)
2243 assert(_mesa_is_format_color_format(mt
->format
));
2248 /* Clamp the level range to fit the miptree */
2249 assert(start_level
+ num_levels
>= start_level
);
2250 const uint32_t last_level
=
2251 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2252 start_level
= MAX2(mt
->first_level
, start_level
);
2253 num_levels
= last_level
- start_level
+ 1;
2255 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2256 uint32_t level_layers
= mt
->surf
.size
> 0 ?
2257 get_num_phys_layers(&mt
->surf
, level
) : mt
->level
[level
].depth
;
2259 level_layers
= MIN2(num_layers
, level_layers
);
2261 for (unsigned a
= 0; a
< level_layers
; a
++) {
2262 enum isl_aux_state aux_state
=
2263 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2264 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2265 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2274 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2275 const struct intel_mipmap_tree
*mt
,
2276 unsigned level
, unsigned layer
)
2282 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2283 assert(brw
->gen
>= 8 ||
2284 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2286 /* Compression of arrayed msaa surfaces is supported. */
2287 if (mt
->surf
.samples
> 1)
2290 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2291 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2297 static enum blorp_fast_clear_op
2298 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2299 bool ccs_supported
, bool fast_clear_supported
)
2301 assert(ccs_supported
== fast_clear_supported
);
2303 switch (aux_state
) {
2304 case ISL_AUX_STATE_CLEAR
:
2305 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2307 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2309 return BLORP_FAST_CLEAR_OP_NONE
;
2311 case ISL_AUX_STATE_PASS_THROUGH
:
2312 return BLORP_FAST_CLEAR_OP_NONE
;
2314 case ISL_AUX_STATE_RESOLVED
:
2315 case ISL_AUX_STATE_AUX_INVALID
:
2316 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2320 unreachable("Invalid aux state for CCS_D");
2323 static enum blorp_fast_clear_op
2324 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2325 bool ccs_supported
, bool fast_clear_supported
)
2327 switch (aux_state
) {
2328 case ISL_AUX_STATE_CLEAR
:
2329 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2331 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2332 else if (!fast_clear_supported
)
2333 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2335 return BLORP_FAST_CLEAR_OP_NONE
;
2337 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2339 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2341 return BLORP_FAST_CLEAR_OP_NONE
;
2343 case ISL_AUX_STATE_PASS_THROUGH
:
2344 return BLORP_FAST_CLEAR_OP_NONE
;
2346 case ISL_AUX_STATE_RESOLVED
:
2347 case ISL_AUX_STATE_AUX_INVALID
:
2351 unreachable("Invalid aux state for CCS_E");
2355 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 uint32_t level
, uint32_t layer
,
2359 bool fast_clear_supported
)
2361 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2363 enum blorp_fast_clear_op resolve_op
;
2364 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2365 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2366 fast_clear_supported
);
2368 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2369 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2370 fast_clear_supported
);
2373 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2374 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2375 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2377 switch (resolve_op
) {
2378 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2379 /* The CCS full resolve operation destroys the CCS and sets it to the
2380 * pass-through state. (You can also think of this as being both a
2381 * resolve and an ambiguate in one operation.)
2383 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2384 ISL_AUX_STATE_PASS_THROUGH
);
2387 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2388 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2389 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2393 unreachable("Invalid resolve op");
2399 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2400 struct intel_mipmap_tree
*mt
,
2401 uint32_t level
, uint32_t layer
,
2402 bool written_with_ccs
)
2404 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2406 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2407 switch (aux_state
) {
2408 case ISL_AUX_STATE_CLEAR
:
2409 assert(written_with_ccs
);
2410 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2411 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2414 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2415 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2416 assert(written_with_ccs
);
2417 break; /* Nothing to do */
2419 case ISL_AUX_STATE_PASS_THROUGH
:
2420 if (written_with_ccs
) {
2421 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2422 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2428 case ISL_AUX_STATE_RESOLVED
:
2429 case ISL_AUX_STATE_AUX_INVALID
:
2430 unreachable("Invalid aux state for CCS_E");
2433 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2434 /* CCS_D is a bit simpler */
2435 switch (aux_state
) {
2436 case ISL_AUX_STATE_CLEAR
:
2437 assert(written_with_ccs
);
2438 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2439 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2442 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2443 assert(written_with_ccs
);
2444 break; /* Nothing to do */
2446 case ISL_AUX_STATE_PASS_THROUGH
:
2450 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2451 case ISL_AUX_STATE_RESOLVED
:
2452 case ISL_AUX_STATE_AUX_INVALID
:
2453 unreachable("Invalid aux state for CCS_D");
2459 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2460 struct intel_mipmap_tree
*mt
,
2461 uint32_t level
, uint32_t layer
,
2462 bool written_with_aux
)
2464 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2465 case ISL_AUX_STATE_CLEAR
:
2466 assert(written_with_aux
);
2467 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2468 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2471 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2472 assert(written_with_aux
);
2473 break; /* Nothing to do */
2475 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2476 case ISL_AUX_STATE_RESOLVED
:
2477 case ISL_AUX_STATE_PASS_THROUGH
:
2478 case ISL_AUX_STATE_AUX_INVALID
:
2479 unreachable("Invalid aux state for MCS");
2484 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2485 struct intel_mipmap_tree
*mt
,
2486 uint32_t level
, uint32_t layer
,
2487 bool hiz_supported
, bool fast_clear_supported
)
2489 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2490 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2491 case ISL_AUX_STATE_CLEAR
:
2492 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2493 if (!hiz_supported
|| !fast_clear_supported
)
2494 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2497 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2499 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2502 case ISL_AUX_STATE_PASS_THROUGH
:
2503 case ISL_AUX_STATE_RESOLVED
:
2506 case ISL_AUX_STATE_AUX_INVALID
:
2508 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2512 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2513 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2516 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2517 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2518 ISL_AUX_STATE_RESOLVED
);
2521 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2522 /* The HiZ resolve operation is actually an ambiguate */
2523 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2524 ISL_AUX_STATE_PASS_THROUGH
);
2528 unreachable("Invalid HiZ op");
2534 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2535 struct intel_mipmap_tree
*mt
,
2536 uint32_t level
, uint32_t layer
,
2537 bool written_with_hiz
)
2539 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2540 case ISL_AUX_STATE_CLEAR
:
2541 assert(written_with_hiz
);
2542 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2543 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2546 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2547 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2548 assert(written_with_hiz
);
2549 break; /* Nothing to do */
2551 case ISL_AUX_STATE_RESOLVED
:
2552 if (written_with_hiz
) {
2553 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2554 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2556 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2557 ISL_AUX_STATE_AUX_INVALID
);
2561 case ISL_AUX_STATE_PASS_THROUGH
:
2562 if (written_with_hiz
) {
2563 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2564 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2568 case ISL_AUX_STATE_AUX_INVALID
:
2569 assert(!written_with_hiz
);
2574 static inline uint32_t
2575 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2576 uint32_t start_level
, uint32_t num_levels
)
2578 assert(start_level
>= mt
->first_level
);
2579 assert(start_level
<= mt
->last_level
);
2581 if (num_levels
== INTEL_REMAINING_LAYERS
)
2582 num_levels
= mt
->last_level
- start_level
+ 1;
2583 /* Check for overflow */
2584 assert(start_level
+ num_levels
>= start_level
);
2585 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2590 static inline uint32_t
2591 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2592 uint32_t start_layer
, uint32_t num_layers
)
2594 assert(level
<= mt
->last_level
);
2595 uint32_t total_num_layers
;
2597 if (mt
->surf
.size
> 0)
2598 total_num_layers
= get_num_phys_layers(&mt
->surf
, level
);
2600 total_num_layers
= mt
->level
[level
].depth
;
2602 assert(start_layer
< total_num_layers
);
2603 if (num_layers
== INTEL_REMAINING_LAYERS
)
2604 num_layers
= total_num_layers
- start_layer
;
2605 /* Check for overflow */
2606 assert(start_layer
+ num_layers
>= start_layer
);
2607 assert(start_layer
+ num_layers
<= total_num_layers
);
2613 intel_miptree_prepare_access(struct brw_context
*brw
,
2614 struct intel_mipmap_tree
*mt
,
2615 uint32_t start_level
, uint32_t num_levels
,
2616 uint32_t start_layer
, uint32_t num_layers
,
2617 bool aux_supported
, bool fast_clear_supported
)
2619 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2621 if (_mesa_is_format_color_format(mt
->format
)) {
2625 if (mt
->surf
.samples
> 1) {
2626 /* Nothing to do for MSAA */
2627 assert(aux_supported
&& fast_clear_supported
);
2629 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2630 const uint32_t level
= start_level
+ l
;
2631 const uint32_t level_layers
=
2632 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2633 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2634 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2635 start_layer
+ a
, aux_supported
,
2636 fast_clear_supported
);
2640 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2641 /* Nothing to do for stencil */
2646 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2647 const uint32_t level
= start_level
+ l
;
2648 if (!intel_miptree_level_has_hiz(mt
, level
))
2651 const uint32_t level_layers
=
2652 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2653 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2654 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2656 fast_clear_supported
);
2663 intel_miptree_finish_write(struct brw_context
*brw
,
2664 struct intel_mipmap_tree
*mt
, uint32_t level
,
2665 uint32_t start_layer
, uint32_t num_layers
,
2666 bool written_with_aux
)
2668 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2670 if (_mesa_is_format_color_format(mt
->format
)) {
2674 if (mt
->surf
.samples
> 1) {
2675 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2676 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2680 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2681 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2685 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2686 /* Nothing to do for stencil */
2688 if (!intel_miptree_level_has_hiz(mt
, level
))
2691 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2692 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2699 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2700 uint32_t level
, uint32_t layer
)
2702 intel_miptree_check_level_layer(mt
, level
, layer
);
2704 if (_mesa_is_format_color_format(mt
->format
)) {
2705 assert(mt
->mcs_buf
!= NULL
);
2706 assert(mt
->surf
.samples
== 1 ||
2707 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2708 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2709 unreachable("Cannot get aux state for stencil");
2711 assert(intel_miptree_level_has_hiz(mt
, level
));
2714 return mt
->aux_state
[level
][layer
];
2718 intel_miptree_set_aux_state(struct brw_context
*brw
,
2719 struct intel_mipmap_tree
*mt
, uint32_t level
,
2720 uint32_t start_layer
, uint32_t num_layers
,
2721 enum isl_aux_state aux_state
)
2723 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2725 if (_mesa_is_format_color_format(mt
->format
)) {
2726 assert(mt
->mcs_buf
!= NULL
);
2727 assert(mt
->surf
.samples
== 1 ||
2728 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2729 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2730 unreachable("Cannot get aux state for stencil");
2732 assert(intel_miptree_level_has_hiz(mt
, level
));
2735 for (unsigned a
= 0; a
< num_layers
; a
++)
2736 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2739 /* On Gen9 color buffers may be compressed by the hardware (lossless
2740 * compression). There are, however, format restrictions and care needs to be
2741 * taken that the sampler engine is capable for re-interpreting a buffer with
2742 * format different the buffer was originally written with.
2744 * For example, SRGB formats are not compressible and the sampler engine isn't
2745 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2746 * color buffer needs to be resolved so that the sampling surface can be
2747 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2751 can_texture_with_ccs(struct brw_context
*brw
,
2752 struct intel_mipmap_tree
*mt
,
2753 mesa_format view_format
)
2755 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2758 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2759 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2761 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2762 isl_mt_format
, isl_view_format
)) {
2763 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2764 _mesa_get_format_name(view_format
),
2765 _mesa_get_format_name(mt
->format
));
2773 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2774 struct intel_mipmap_tree
*mt
,
2775 mesa_format view_format
,
2776 uint32_t start_level
, uint32_t num_levels
,
2777 uint32_t start_layer
, uint32_t num_layers
,
2778 bool *aux_supported_out
)
2780 bool aux_supported
, clear_supported
;
2781 if (_mesa_is_format_color_format(mt
->format
)) {
2782 if (mt
->surf
.samples
> 1) {
2783 aux_supported
= clear_supported
= true;
2785 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2787 /* Clear color is specified as ints or floats and the conversion is
2788 * done by the sampler. If we have a texture view, we would have to
2789 * perform the clear color conversion manually. Just disable clear
2792 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2794 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2795 aux_supported
= clear_supported
= false;
2797 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2800 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2801 start_layer
, num_layers
,
2802 aux_supported
, clear_supported
);
2803 if (aux_supported_out
)
2804 *aux_supported_out
= aux_supported
;
2808 intel_miptree_prepare_texture(struct brw_context
*brw
,
2809 struct intel_mipmap_tree
*mt
,
2810 mesa_format view_format
,
2811 bool *aux_supported_out
)
2813 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2814 0, INTEL_REMAINING_LEVELS
,
2815 0, INTEL_REMAINING_LAYERS
,
2820 intel_miptree_prepare_image(struct brw_context
*brw
,
2821 struct intel_mipmap_tree
*mt
)
2823 /* The data port doesn't understand any compression */
2824 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2825 0, INTEL_REMAINING_LAYERS
, false, false);
2829 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2830 struct intel_mipmap_tree
*mt
, uint32_t level
,
2831 uint32_t start_layer
, uint32_t num_layers
)
2833 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2834 start_layer
, num_layers
, NULL
);
2838 intel_miptree_prepare_render(struct brw_context
*brw
,
2839 struct intel_mipmap_tree
*mt
, uint32_t level
,
2840 uint32_t start_layer
, uint32_t layer_count
,
2843 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2844 * the single-sampled color renderbuffers because the CCS buffer isn't
2845 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2846 * enabled because otherwise the surface state will be programmed with
2847 * the linear equivalent format anyway.
2849 if (brw
->gen
== 9 && srgb_enabled
&& mt
->surf
.samples
== 1 &&
2850 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2852 /* Lossless compression is not supported for SRGB formats, it
2853 * should be impossible to get here with such surfaces.
2855 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2856 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2862 intel_miptree_finish_render(struct brw_context
*brw
,
2863 struct intel_mipmap_tree
*mt
, uint32_t level
,
2864 uint32_t start_layer
, uint32_t layer_count
)
2866 assert(_mesa_is_format_color_format(mt
->format
));
2867 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2868 mt
->mcs_buf
!= NULL
);
2872 intel_miptree_prepare_depth(struct brw_context
*brw
,
2873 struct intel_mipmap_tree
*mt
, uint32_t level
,
2874 uint32_t start_layer
, uint32_t layer_count
)
2876 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2877 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2881 intel_miptree_finish_depth(struct brw_context
*brw
,
2882 struct intel_mipmap_tree
*mt
, uint32_t level
,
2883 uint32_t start_layer
, uint32_t layer_count
,
2886 if (depth_written
) {
2887 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2888 mt
->hiz_buf
!= NULL
);
2893 * Make it possible to share the BO backing the given miptree with another
2894 * process or another miptree.
2896 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2897 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2898 * ensure that no MCS buffer gets allocated in the future.
2900 * HiZ is similarly unsafe with shared buffers.
2903 intel_miptree_make_shareable(struct brw_context
*brw
,
2904 struct intel_mipmap_tree
*mt
)
2906 /* MCS buffers are also used for multisample buffers, but we can't resolve
2907 * away a multisample MCS buffer because it's an integral part of how the
2908 * pixel data is stored. Fortunately this code path should never be
2909 * reached for multisample buffers.
2911 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2912 mt
->surf
.samples
== 1);
2914 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2915 0, INTEL_REMAINING_LAYERS
, false, false);
2918 brw_bo_unreference(mt
->mcs_buf
->bo
);
2922 /* Any pending MCS/CCS operations are no longer needed. Trying to
2923 * execute any will likely crash due to the missing aux buffer. So let's
2924 * delete all pending ops.
2926 free(mt
->aux_state
);
2927 mt
->aux_state
= NULL
;
2931 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2934 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2935 mt
->level
[l
].has_hiz
= false;
2938 /* Any pending HiZ operations are no longer needed. Trying to execute
2939 * any will likely crash due to the missing aux buffer. So let's delete
2942 free(mt
->aux_state
);
2943 mt
->aux_state
= NULL
;
2946 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2951 * \brief Get pointer offset into stencil buffer.
2953 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2954 * must decode the tile's layout in software.
2957 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2959 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2961 * Even though the returned offset is always positive, the return type is
2963 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2964 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2967 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2969 uint32_t tile_size
= 4096;
2970 uint32_t tile_width
= 64;
2971 uint32_t tile_height
= 64;
2972 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2974 uint32_t tile_x
= x
/ tile_width
;
2975 uint32_t tile_y
= y
/ tile_height
;
2977 /* The byte's address relative to the tile's base addres. */
2978 uint32_t byte_x
= x
% tile_width
;
2979 uint32_t byte_y
= y
% tile_height
;
2981 uintptr_t u
= tile_y
* row_size
2982 + tile_x
* tile_size
2983 + 512 * (byte_x
/ 8)
2985 + 32 * ((byte_y
/ 4) % 2)
2986 + 16 * ((byte_x
/ 4) % 2)
2987 + 8 * ((byte_y
/ 2) % 2)
2988 + 4 * ((byte_x
/ 2) % 2)
2993 /* adjust for bit6 swizzling */
2994 if (((byte_x
/ 8) % 2) == 1) {
2995 if (((byte_y
/ 8) % 2) == 0) {
3007 intel_miptree_updownsample(struct brw_context
*brw
,
3008 struct intel_mipmap_tree
*src
,
3009 struct intel_mipmap_tree
*dst
)
3011 unsigned src_w
, src_h
, dst_w
, dst_h
;
3013 if (src
->surf
.size
> 0) {
3014 src_w
= src
->surf
.logical_level0_px
.width
;
3015 src_h
= src
->surf
.logical_level0_px
.height
;
3017 src_w
= src
->logical_width0
;
3018 src_h
= src
->logical_height0
;
3021 if (dst
->surf
.size
> 0) {
3022 dst_w
= dst
->surf
.logical_level0_px
.width
;
3023 dst_h
= dst
->surf
.logical_level0_px
.height
;
3025 dst_w
= dst
->logical_width0
;
3026 dst_h
= dst
->logical_height0
;
3029 brw_blorp_blit_miptrees(brw
,
3030 src
, 0 /* level */, 0 /* layer */,
3031 src
->format
, SWIZZLE_XYZW
,
3032 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
3035 GL_NEAREST
, false, false /*mirror x, y*/,
3038 if (src
->stencil_mt
) {
3039 if (src
->stencil_mt
->surf
.size
> 0) {
3040 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
3041 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
3043 src_w
= src
->stencil_mt
->logical_width0
;
3044 src_h
= src
->stencil_mt
->logical_height0
;
3047 if (dst
->stencil_mt
->surf
.size
> 0) {
3048 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
3049 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
3051 dst_w
= dst
->stencil_mt
->logical_width0
;
3052 dst_h
= dst
->stencil_mt
->logical_height0
;
3055 brw_blorp_blit_miptrees(brw
,
3056 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
3057 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
3058 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
3059 dst
->stencil_mt
->format
,
3062 GL_NEAREST
, false, false /*mirror x, y*/,
3063 false, false /* decode/encode srgb */);
3068 intel_update_r8stencil(struct brw_context
*brw
,
3069 struct intel_mipmap_tree
*mt
)
3071 assert(brw
->gen
>= 7);
3072 struct intel_mipmap_tree
*src
=
3073 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3074 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
3077 assert(src
->surf
.size
> 0);
3079 if (!mt
->r8stencil_mt
) {
3080 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3081 mt
->r8stencil_mt
= make_surface(
3084 MESA_FORMAT_R_UINT8
,
3085 src
->first_level
, src
->last_level
,
3086 src
->surf
.logical_level0_px
.width
,
3087 src
->surf
.logical_level0_px
.height
,
3088 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3089 src
->surf
.logical_level0_px
.depth
:
3090 src
->surf
.logical_level0_px
.array_len
,
3093 ISL_SURF_USAGE_TEXTURE_BIT
,
3094 BO_ALLOC_FOR_RENDER
, 0, NULL
);
3095 assert(mt
->r8stencil_mt
);
3098 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3100 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3101 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3102 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3103 src
->surf
.phys_level0_sa
.array_len
;
3105 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3106 brw_blorp_copy_miptrees(brw
,
3110 minify(src
->surf
.logical_level0_px
.width
,
3112 minify(src
->surf
.logical_level0_px
.height
,
3117 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3118 src
->r8stencil_needs_update
= false;
3122 intel_miptree_map_raw(struct brw_context
*brw
,
3123 struct intel_mipmap_tree
*mt
,
3126 struct brw_bo
*bo
= mt
->bo
;
3128 if (brw_batch_references(&brw
->batch
, bo
))
3129 intel_batchbuffer_flush(brw
);
3131 return brw_bo_map(brw
, bo
, mode
);
3135 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3137 brw_bo_unmap(mt
->bo
);
3141 intel_miptree_map_gtt(struct brw_context
*brw
,
3142 struct intel_mipmap_tree
*mt
,
3143 struct intel_miptree_map
*map
,
3144 unsigned int level
, unsigned int slice
)
3146 unsigned int bw
, bh
;
3148 unsigned int image_x
, image_y
;
3149 intptr_t x
= map
->x
;
3150 intptr_t y
= map
->y
;
3152 /* For compressed formats, the stride is the number of bytes per
3153 * row of blocks. intel_miptree_get_image_offset() already does
3156 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3157 assert(y
% bh
== 0);
3158 assert(x
% bw
== 0);
3162 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3169 /* Note that in the case of cube maps, the caller must have passed the
3170 * slice number referencing the face.
3172 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3176 map
->stride
= mt
->surf
.row_pitch
;
3177 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3180 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3181 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3182 map
->x
, map
->y
, map
->w
, map
->h
,
3183 mt
, _mesa_get_format_name(mt
->format
),
3184 x
, y
, map
->ptr
, map
->stride
);
3188 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3190 intel_miptree_unmap_raw(mt
);
3194 intel_miptree_map_blit(struct brw_context
*brw
,
3195 struct intel_mipmap_tree
*mt
,
3196 struct intel_miptree_map
*map
,
3197 unsigned int level
, unsigned int slice
)
3199 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3200 /* first_level */ 0,
3204 MIPTREE_LAYOUT_TILING_NONE
);
3206 if (!map
->linear_mt
) {
3207 fprintf(stderr
, "Failed to allocate blit temporary\n");
3210 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3212 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3213 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3214 * invalidate is set, since we'll be writing the whole rectangle from our
3215 * temporary buffer back out.
3217 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3218 if (!intel_miptree_copy(brw
,
3219 mt
, level
, slice
, map
->x
, map
->y
,
3220 map
->linear_mt
, 0, 0, 0, 0,
3222 fprintf(stderr
, "Failed to blit\n");
3227 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3229 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3230 map
->x
, map
->y
, map
->w
, map
->h
,
3231 mt
, _mesa_get_format_name(mt
->format
),
3232 level
, slice
, map
->ptr
, map
->stride
);
3237 intel_miptree_release(&map
->linear_mt
);
3243 intel_miptree_unmap_blit(struct brw_context
*brw
,
3244 struct intel_mipmap_tree
*mt
,
3245 struct intel_miptree_map
*map
,
3249 struct gl_context
*ctx
= &brw
->ctx
;
3251 intel_miptree_unmap_raw(map
->linear_mt
);
3253 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3254 bool ok
= intel_miptree_copy(brw
,
3255 map
->linear_mt
, 0, 0, 0, 0,
3256 mt
, level
, slice
, map
->x
, map
->y
,
3258 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3261 intel_miptree_release(&map
->linear_mt
);
3265 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3267 #if defined(USE_SSE41)
3269 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3270 struct intel_mipmap_tree
*mt
,
3271 struct intel_miptree_map
*map
,
3272 unsigned int level
, unsigned int slice
)
3274 assert(map
->mode
& GL_MAP_READ_BIT
);
3275 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3277 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3278 map
->x
, map
->y
, map
->w
, map
->h
,
3279 mt
, _mesa_get_format_name(mt
->format
),
3280 level
, slice
, map
->ptr
, map
->stride
);
3282 /* Map the original image */
3285 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3289 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3295 src
+= image_y
* mt
->surf
.row_pitch
;
3296 src
+= image_x
* mt
->cpp
;
3298 /* Due to the pixel offsets for the particular image being mapped, our
3299 * src pointer may not be 16-byte aligned. However, if the pitch is
3300 * divisible by 16, then the amount by which it's misaligned will remain
3301 * consistent from row to row.
3303 assert((mt
->surf
.row_pitch
% 16) == 0);
3304 const int misalignment
= ((uintptr_t) src
) & 15;
3306 /* Create an untiled temporary buffer for the mapping. */
3307 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3309 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3311 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3312 /* Offset the destination so it has the same misalignment as src. */
3313 map
->ptr
= map
->buffer
+ misalignment
;
3315 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3317 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3318 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3319 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3321 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3324 intel_miptree_unmap_raw(mt
);
3328 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3329 struct intel_mipmap_tree
*mt
,
3330 struct intel_miptree_map
*map
,
3334 _mesa_align_free(map
->buffer
);
3341 intel_miptree_map_s8(struct brw_context
*brw
,
3342 struct intel_mipmap_tree
*mt
,
3343 struct intel_miptree_map
*map
,
3344 unsigned int level
, unsigned int slice
)
3346 map
->stride
= map
->w
;
3347 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3351 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3352 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3353 * invalidate is set, since we'll be writing the whole rectangle from our
3354 * temporary buffer back out.
3356 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3357 uint8_t *untiled_s8_map
= map
->ptr
;
3358 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3359 unsigned int image_x
, image_y
;
3361 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3363 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3364 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3365 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3366 x
+ image_x
+ map
->x
,
3367 y
+ image_y
+ map
->y
,
3368 brw
->has_swizzling
);
3369 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3373 intel_miptree_unmap_raw(mt
);
3375 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3376 map
->x
, map
->y
, map
->w
, map
->h
,
3377 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3379 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3380 map
->x
, map
->y
, map
->w
, map
->h
,
3381 mt
, map
->ptr
, map
->stride
);
3386 intel_miptree_unmap_s8(struct brw_context
*brw
,
3387 struct intel_mipmap_tree
*mt
,
3388 struct intel_miptree_map
*map
,
3392 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3393 unsigned int image_x
, image_y
;
3394 uint8_t *untiled_s8_map
= map
->ptr
;
3395 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3397 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3399 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3400 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3401 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3402 image_x
+ x
+ map
->x
,
3403 image_y
+ y
+ map
->y
,
3404 brw
->has_swizzling
);
3405 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3409 intel_miptree_unmap_raw(mt
);
3416 intel_miptree_map_etc(struct brw_context
*brw
,
3417 struct intel_mipmap_tree
*mt
,
3418 struct intel_miptree_map
*map
,
3422 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3423 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3424 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3427 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3428 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3430 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3431 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3432 map
->w
, map
->h
, 1));
3433 map
->ptr
= map
->buffer
;
3437 intel_miptree_unmap_etc(struct brw_context
*brw
,
3438 struct intel_mipmap_tree
*mt
,
3439 struct intel_miptree_map
*map
,
3445 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3450 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3451 + image_y
* mt
->surf
.row_pitch
3452 + image_x
* mt
->cpp
;
3454 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3455 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3456 map
->ptr
, map
->stride
,
3459 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3460 map
->ptr
, map
->stride
,
3461 map
->w
, map
->h
, mt
->etc_format
);
3463 intel_miptree_unmap_raw(mt
);
3468 * Mapping function for packed depth/stencil miptrees backed by real separate
3469 * miptrees for depth and stencil.
3471 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3472 * separate from the depth buffer. Yet at the GL API level, we have to expose
3473 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3474 * be able to map that memory for texture storage and glReadPixels-type
3475 * operations. We give Mesa core that access by mallocing a temporary and
3476 * copying the data between the actual backing store and the temporary.
3479 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3480 struct intel_mipmap_tree
*mt
,
3481 struct intel_miptree_map
*map
,
3482 unsigned int level
, unsigned int slice
)
3484 struct intel_mipmap_tree
*z_mt
= mt
;
3485 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3486 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3487 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3489 map
->stride
= map
->w
* packed_bpp
;
3490 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3494 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3495 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3496 * invalidate is set, since we'll be writing the whole rectangle from our
3497 * temporary buffer back out.
3499 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3500 uint32_t *packed_map
= map
->ptr
;
3501 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3502 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3503 unsigned int s_image_x
, s_image_y
;
3504 unsigned int z_image_x
, z_image_y
;
3506 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3507 &s_image_x
, &s_image_y
);
3508 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3509 &z_image_x
, &z_image_y
);
3511 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3512 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3513 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3514 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3517 brw
->has_swizzling
);
3518 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3519 (z_mt
->surf
.row_pitch
/ 4) +
3520 (map_x
+ z_image_x
));
3521 uint8_t s
= s_map
[s_offset
];
3522 uint32_t z
= z_map
[z_offset
];
3524 if (map_z32f_x24s8
) {
3525 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3526 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3528 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3533 intel_miptree_unmap_raw(s_mt
);
3534 intel_miptree_unmap_raw(z_mt
);
3536 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3538 map
->x
, map
->y
, map
->w
, map
->h
,
3539 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3540 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3541 map
->ptr
, map
->stride
);
3543 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3544 map
->x
, map
->y
, map
->w
, map
->h
,
3545 mt
, map
->ptr
, map
->stride
);
3550 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3551 struct intel_mipmap_tree
*mt
,
3552 struct intel_miptree_map
*map
,
3556 struct intel_mipmap_tree
*z_mt
= mt
;
3557 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3558 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3560 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3561 uint32_t *packed_map
= map
->ptr
;
3562 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3563 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3564 unsigned int s_image_x
, s_image_y
;
3565 unsigned int z_image_x
, z_image_y
;
3567 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3568 &s_image_x
, &s_image_y
);
3569 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3570 &z_image_x
, &z_image_y
);
3572 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3573 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3574 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3575 x
+ s_image_x
+ map
->x
,
3576 y
+ s_image_y
+ map
->y
,
3577 brw
->has_swizzling
);
3578 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3579 (z_mt
->surf
.row_pitch
/ 4) +
3580 (x
+ z_image_x
+ map
->x
));
3582 if (map_z32f_x24s8
) {
3583 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3584 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3586 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3587 s_map
[s_offset
] = packed
>> 24;
3588 z_map
[z_offset
] = packed
;
3593 intel_miptree_unmap_raw(s_mt
);
3594 intel_miptree_unmap_raw(z_mt
);
3596 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3598 map
->x
, map
->y
, map
->w
, map
->h
,
3599 z_mt
, _mesa_get_format_name(z_mt
->format
),
3600 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3601 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3602 map
->ptr
, map
->stride
);
3609 * Create and attach a map to the miptree at (level, slice). Return the
3612 static struct intel_miptree_map
*
3613 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3622 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3627 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3628 mt
->level
[level
].slice
[slice
].map
= map
;
3640 * Release the map at (level, slice).
3643 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3647 struct intel_miptree_map
**map
;
3649 map
= &mt
->level
[level
].slice
[slice
].map
;
3655 can_blit_slice(struct intel_mipmap_tree
*mt
,
3656 unsigned int level
, unsigned int slice
)
3658 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3659 if (mt
->surf
.row_pitch
>= 32768)
3666 use_intel_mipree_map_blit(struct brw_context
*brw
,
3667 struct intel_mipmap_tree
*mt
,
3673 /* It's probably not worth swapping to the blit ring because of
3674 * all the overhead involved.
3676 !(mode
& GL_MAP_WRITE_BIT
) &&
3678 (mt
->surf
.tiling
== ISL_TILING_X
||
3679 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3680 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3681 /* Fast copy blit on skl+ supports all tiling formats. */
3683 can_blit_slice(mt
, level
, slice
))
3686 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3687 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3688 assert(can_blit_slice(mt
, level
, slice
));
3696 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3697 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3698 * arithmetic overflow.
3700 * If you call this function and use \a out_stride, then you're doing pointer
3701 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3702 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3703 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3704 * which usually have type uint32_t or GLuint.
3707 intel_miptree_map(struct brw_context
*brw
,
3708 struct intel_mipmap_tree
*mt
,
3717 ptrdiff_t *out_stride
)
3719 struct intel_miptree_map
*map
;
3721 assert(mt
->surf
.samples
== 1);
3723 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3730 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3731 map
->mode
& GL_MAP_WRITE_BIT
);
3733 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3734 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3735 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3736 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3737 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3738 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3739 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3740 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3741 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3742 #if defined(USE_SSE41)
3743 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3744 !mt
->compressed
&& cpu_has_sse4_1
&&
3745 (mt
->surf
.row_pitch
% 16 == 0)) {
3746 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3749 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3752 *out_ptr
= map
->ptr
;
3753 *out_stride
= map
->stride
;
3755 if (map
->ptr
== NULL
)
3756 intel_miptree_release_map(mt
, level
, slice
);
3760 intel_miptree_unmap(struct brw_context
*brw
,
3761 struct intel_mipmap_tree
*mt
,
3765 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3767 assert(mt
->surf
.samples
== 1);
3772 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3773 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3775 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3776 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3777 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3778 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3779 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3780 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3781 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3782 } else if (map
->linear_mt
) {
3783 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3784 #if defined(USE_SSE41)
3785 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3786 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3789 intel_miptree_unmap_gtt(mt
);
3792 intel_miptree_release_map(mt
, level
, slice
);
3796 get_isl_surf_dim(GLenum target
)
3800 case GL_TEXTURE_1D_ARRAY
:
3801 return ISL_SURF_DIM_1D
;
3804 case GL_TEXTURE_2D_ARRAY
:
3805 case GL_TEXTURE_RECTANGLE
:
3806 case GL_TEXTURE_CUBE_MAP
:
3807 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3808 case GL_TEXTURE_2D_MULTISAMPLE
:
3809 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3810 case GL_TEXTURE_EXTERNAL_OES
:
3811 return ISL_SURF_DIM_2D
;
3814 return ISL_SURF_DIM_3D
;
3817 unreachable("Invalid texture target");
3821 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3822 enum isl_tiling tiling
, GLenum target
)
3826 case GL_TEXTURE_1D_ARRAY
:
3827 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3828 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3831 case GL_TEXTURE_2D_ARRAY
:
3832 case GL_TEXTURE_RECTANGLE
:
3833 case GL_TEXTURE_2D_MULTISAMPLE
:
3834 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3835 case GL_TEXTURE_EXTERNAL_OES
:
3836 return ISL_DIM_LAYOUT_GEN4_2D
;
3838 case GL_TEXTURE_CUBE_MAP
:
3839 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3840 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3841 ISL_DIM_LAYOUT_GEN4_2D
);
3844 return (devinfo
->gen
>= 9 ?
3845 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3848 unreachable("Invalid texture target");
3852 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3854 if (mt
->format
== MESA_FORMAT_S_UINT8
)
3855 return ISL_TILING_W
;
3856 return mt
->surf
.tiling
;
3860 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3861 const struct intel_mipmap_tree
*mt
,
3862 struct isl_surf
*surf
)
3864 assert(mt
->array_layout
!= GEN6_HIZ_STENCIL
);
3866 surf
->dim
= get_isl_surf_dim(mt
->target
);
3867 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3868 mt
->surf
.tiling
, mt
->target
);
3869 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3870 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3871 surf
->row_pitch
= mt
->surf
.row_pitch
;
3872 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3874 if (brw
->gen
>= 9) {
3875 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3876 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3877 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3879 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3880 * alignment in terms of surface elements like we want.
3882 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3885 /* On earlier gens it's stored in pixels. */
3887 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3888 surf
->image_alignment_el
=
3889 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3892 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3893 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3894 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3895 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3896 surf
->logical_level0_px
.array_len
= 1;
3898 surf
->logical_level0_px
.depth
= 1;
3899 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3902 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3903 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3904 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3905 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3906 surf
->phys_level0_sa
.array_len
= 1;
3908 surf
->phys_level0_sa
.depth
= 1;
3909 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3912 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3913 surf
->samples
= mt
->surf
.samples
;
3915 surf
->size
= 0; /* TODO */
3916 surf
->alignment
= 0; /* TODO */
3918 switch (surf
->dim_layout
) {
3919 case ISL_DIM_LAYOUT_GEN4_2D
:
3920 case ISL_DIM_LAYOUT_GEN4_3D
:
3921 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3922 if (brw
->gen
>= 9) {
3923 surf
->array_pitch_el_rows
= mt
->qpitch
;
3926 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3927 assert(mt
->qpitch
% bh
== 0);
3928 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3931 case ISL_DIM_LAYOUT_GEN9_1D
:
3932 surf
->array_pitch_el_rows
= 1;
3936 switch (mt
->array_layout
) {
3937 case ALL_LOD_IN_EACH_SLICE
:
3938 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3940 case ALL_SLICES_AT_EACH_LOD
:
3941 case GEN6_HIZ_STENCIL
:
3942 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3945 unreachable("Invalid array layout");
3948 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3949 switch (base_format
) {
3950 case GL_DEPTH_COMPONENT
:
3951 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3953 case GL_STENCIL_INDEX
:
3954 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3956 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3958 case GL_DEPTH_STENCIL
:
3959 /* In this case we only texture from the depth part */
3960 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3961 ISL_SURF_USAGE_TEXTURE_BIT
;
3964 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3965 if (brw
->mesa_format_supports_render
[mt
->format
])
3966 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3970 if (_mesa_is_cube_map_texture(mt
->target
))
3971 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3975 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3976 const struct intel_mipmap_tree
*mt
)
3979 return ISL_AUX_USAGE_HIZ
;
3982 return ISL_AUX_USAGE_NONE
;
3984 return mt
->aux_usage
;