2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
289 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
290 unsigned depth0
, struct intel_mipmap_level
*table
)
292 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
294 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
296 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
297 if (!table
[level
].slice
)
304 for (unsigned level
= first_level
; level
<= last_level
; level
++)
305 free(table
[level
].slice
);
311 * @param for_bo Indicates that the caller is
312 * intel_miptree_create_for_bo(). If true, then do not create
315 static struct intel_mipmap_tree
*
316 intel_miptree_create_layout(struct brw_context
*brw
,
325 uint32_t layout_flags
)
327 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
331 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
332 _mesa_enum_to_string(target
),
333 _mesa_get_format_name(format
),
334 first_level
, last_level
, depth0
, mt
);
336 if (target
== GL_TEXTURE_1D_ARRAY
)
337 assert(height0
== 1);
341 mt
->first_level
= first_level
;
342 mt
->last_level
= last_level
;
343 mt
->logical_width0
= width0
;
344 mt
->logical_height0
= height0
;
345 mt
->logical_depth0
= depth0
;
346 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
347 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
348 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
349 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
350 mt
->aux_state
= NULL
;
351 mt
->cpp
= _mesa_get_format_bytes(format
);
352 mt
->num_samples
= num_samples
;
353 mt
->compressed
= _mesa_is_format_compressed(format
);
354 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
357 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
358 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
360 int depth_multiply
= 1;
361 if (num_samples
> 1) {
362 /* Adjust width/height/depth for MSAA */
363 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
364 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
365 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
366 * "If the surface is multisampled and it is a depth or stencil
367 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
368 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
371 * +----------------------------------------------------------------+
372 * | Num Multisamples | W_l = | H_l = |
373 * +----------------------------------------------------------------+
374 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
375 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
376 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
377 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
378 * +----------------------------------------------------------------+
381 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
382 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
383 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
385 * Another more complicated explanation for these adjustments comes
386 * from the Sandybridge PRM, volume 4, part 1, page 31:
388 * "Any of the other messages (sample*, LOD, load4) used with a
389 * (4x) multisampled surface will in-effect sample a surface with
390 * double the height and width as that indicated in the surface
391 * state. Each pixel position on the original-sized surface is
392 * replaced with a 2x2 of samples with the following arrangement:
397 * Thus, when sampling from a multisampled texture, it behaves as
398 * though the layout in memory for (x,y,sample) is:
400 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
401 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
403 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
404 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
406 * However, the actual layout of multisampled data in memory is:
408 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
409 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
411 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
412 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
414 * This pattern repeats for each 2x2 pixel block.
416 * As a result, when calculating the size of our 4-sample buffer for
417 * an odd width or height, we have to align before scaling up because
418 * sample 3 is in that bottom right 2x2 block.
420 switch (num_samples
) {
422 assert(brw
->gen
>= 8);
423 width0
= ALIGN(width0
, 2) * 2;
424 height0
= ALIGN(height0
, 2);
427 width0
= ALIGN(width0
, 2) * 2;
428 height0
= ALIGN(height0
, 2) * 2;
431 width0
= ALIGN(width0
, 2) * 4;
432 height0
= ALIGN(height0
, 2) * 2;
435 width0
= ALIGN(width0
, 2) * 4;
436 height0
= ALIGN(height0
, 2) * 4;
439 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
442 unreachable("not reached");
445 /* Non-interleaved */
446 depth_multiply
= num_samples
;
447 depth0
*= depth_multiply
;
451 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
457 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
458 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
459 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
460 * used on Gen8 to make it pick a qpitch value which doesn't include space
461 * for the mipmaps. On Gen9 this is not necessary because it will
462 * automatically pick a packed qpitch value whenever mt->first_level ==
464 * TODO: can we use it elsewhere?
465 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
468 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
470 switch (mt
->msaa_layout
) {
471 case INTEL_MSAA_LAYOUT_NONE
:
472 case INTEL_MSAA_LAYOUT_IMS
:
473 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
475 case INTEL_MSAA_LAYOUT_UMS
:
476 case INTEL_MSAA_LAYOUT_CMS
:
477 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
482 if (target
== GL_TEXTURE_CUBE_MAP
)
483 assert(depth0
== 6 * depth_multiply
);
485 mt
->physical_width0
= width0
;
486 mt
->physical_height0
= height0
;
487 mt
->physical_depth0
= depth0
;
489 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
490 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
491 (brw
->must_use_separate_stencil
||
492 (brw
->has_separate_stencil
&&
493 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
494 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
496 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
499 mt
->stencil_mt
= intel_miptree_create(brw
,
510 if (!mt
->stencil_mt
) {
511 intel_miptree_release(&mt
);
514 mt
->stencil_mt
->r8stencil_needs_update
= true;
516 /* Fix up the Z miptree format for how we're splitting out separate
517 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
519 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
522 if (format
== mt
->format
) {
523 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
524 _mesa_get_format_name(mt
->format
));
528 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
529 mt
->array_layout
= GEN6_HIZ_STENCIL
;
532 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
533 * multisampled or have an AUX buffer attached to it.
535 * GEN | MSRT | AUX_CCS_* or AUX_MCS
536 * -------------------------------------------
537 * 9 | HALIGN_16 | HALIGN_16
538 * 8 | HALIGN_ANY | HALIGN_16
542 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
543 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
544 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
545 } else if (brw
->gen
>= 9 && num_samples
> 1) {
546 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
548 const UNUSED
bool is_lossless_compressed_aux
=
549 brw
->gen
>= 9 && num_samples
== 1 &&
550 mt
->format
== MESA_FORMAT_R_UINT32
;
552 /* For now, nothing else has this requirement */
553 assert(is_lossless_compressed_aux
||
554 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
557 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
558 intel_miptree_release(&mt
);
562 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
563 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
570 * Choose an appropriate uncompressed format for a requested
571 * compressed format, if unsupported.
574 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
576 /* No need to lower ETC formats on these platforms,
577 * they are supported natively.
579 if (brw
->gen
>= 8 || brw
->is_baytrail
)
583 case MESA_FORMAT_ETC1_RGB8
:
584 return MESA_FORMAT_R8G8B8X8_UNORM
;
585 case MESA_FORMAT_ETC2_RGB8
:
586 return MESA_FORMAT_R8G8B8X8_UNORM
;
587 case MESA_FORMAT_ETC2_SRGB8
:
588 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
589 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
590 return MESA_FORMAT_B8G8R8A8_SRGB
;
591 case MESA_FORMAT_ETC2_RGBA8_EAC
:
592 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
593 return MESA_FORMAT_R8G8B8A8_UNORM
;
594 case MESA_FORMAT_ETC2_R11_EAC
:
595 return MESA_FORMAT_R_UNORM16
;
596 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
597 return MESA_FORMAT_R_SNORM16
;
598 case MESA_FORMAT_ETC2_RG11_EAC
:
599 return MESA_FORMAT_R16G16_UNORM
;
600 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
601 return MESA_FORMAT_R16G16_SNORM
;
603 /* Non ETC1 / ETC2 format */
608 /** \brief Assert that the level and layer are valid for the miptree. */
610 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
618 assert(level
>= mt
->first_level
);
619 assert(level
<= mt
->last_level
);
621 if (mt
->surf
.size
> 0)
622 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
623 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
624 mt
->surf
.phys_level0_sa
.array_len
));
626 assert(layer
< mt
->level
[level
].depth
);
629 static enum isl_aux_state
**
630 create_aux_state_map(struct intel_mipmap_tree
*mt
,
631 enum isl_aux_state initial
)
633 const uint32_t levels
= mt
->last_level
+ 1;
635 uint32_t total_slices
= 0;
636 for (uint32_t level
= 0; level
< levels
; level
++)
637 total_slices
+= mt
->level
[level
].depth
;
639 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
641 /* We're going to allocate a single chunk of data for both the per-level
642 * reference array and the arrays of aux_state. This makes cleanup
643 * significantly easier.
645 const size_t total_size
= per_level_array_size
+
646 total_slices
* sizeof(enum isl_aux_state
);
647 void *data
= malloc(total_size
);
651 enum isl_aux_state
**per_level_arr
= data
;
652 enum isl_aux_state
*s
= data
+ per_level_array_size
;
653 for (uint32_t level
= 0; level
< levels
; level
++) {
654 per_level_arr
[level
] = s
;
655 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
658 assert((void *)s
== data
+ total_size
);
660 return per_level_arr
;
664 free_aux_state_map(enum isl_aux_state
**state
)
669 static struct intel_mipmap_tree
*
670 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
671 unsigned first_level
, unsigned last_level
,
672 unsigned width0
, unsigned height0
, unsigned depth0
,
673 unsigned num_samples
, enum isl_tiling isl_tiling
,
674 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
677 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
681 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
687 if (target
== GL_TEXTURE_CUBE_MAP
||
688 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
689 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
691 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
693 _mesa_enum_to_string(target
),
694 _mesa_get_format_name(format
),
695 num_samples
, width0
, height0
, depth0
,
696 first_level
, last_level
, mt
);
698 struct isl_surf_init_info init_info
= {
699 .dim
= get_isl_surf_dim(target
),
700 .format
= translate_tex_format(brw
, format
, false),
703 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
704 .levels
= last_level
- first_level
+ 1,
705 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
706 .samples
= MAX2(num_samples
, 1),
707 .usage
= isl_usage_flags
,
708 .tiling_flags
= 1u << isl_tiling
711 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
714 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
717 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
719 isl_tiling_to_bufmgr_tiling(isl_tiling
),
720 mt
->surf
.row_pitch
, alloc_flags
);
727 mt
->first_level
= first_level
;
728 mt
->last_level
= last_level
;
732 mt
->aux_state
= NULL
;
737 intel_miptree_release(&mt
);
741 static struct intel_mipmap_tree
*
742 miptree_create(struct brw_context
*brw
,
751 uint32_t layout_flags
)
753 struct intel_mipmap_tree
*mt
;
754 mesa_format tex_format
= format
;
755 mesa_format etc_format
= MESA_FORMAT_NONE
;
756 uint32_t alloc_flags
= 0;
758 format
= intel_lower_compressed_format(brw
, format
);
760 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
762 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
763 mt
= intel_miptree_create_layout(brw
, target
, format
,
764 first_level
, last_level
, width0
,
765 height0
, depth0
, num_samples
,
770 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
771 mt
->tiling
= I915_TILING_Y
;
773 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
774 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
776 mt
->etc_format
= etc_format
;
778 if (format
== MESA_FORMAT_S_UINT8
) {
779 /* Align to size of W tile, 64x64. */
780 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
781 ALIGN(mt
->total_width
, 64),
782 ALIGN(mt
->total_height
, 64),
783 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
786 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
787 mt
->total_width
, mt
->total_height
,
788 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
792 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
793 mt
->bo
->cache_coherent
= false;
798 struct intel_mipmap_tree
*
799 intel_miptree_create(struct brw_context
*brw
,
808 uint32_t layout_flags
)
810 struct intel_mipmap_tree
*mt
= miptree_create(
812 first_level
, last_level
,
813 width0
, height0
, depth0
, num_samples
,
816 /* If the BO is too large to fit in the aperture, we need to use the
817 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
818 * handle Y-tiling, so we need to fall back to X.
820 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
821 mt
->tiling
== I915_TILING_Y
) {
822 const uint32_t alloc_flags
=
823 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
824 BO_ALLOC_FOR_RENDER
: 0;
825 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
826 mt
->total_width
, mt
->total_height
);
828 mt
->tiling
= I915_TILING_X
;
829 brw_bo_unreference(mt
->bo
);
830 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
831 mt
->total_width
, mt
->total_height
, mt
->cpp
,
832 mt
->tiling
, &mt
->pitch
, alloc_flags
);
838 intel_miptree_release(&mt
);
843 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
844 assert(mt
->num_samples
> 1);
845 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
846 intel_miptree_release(&mt
);
851 /* If this miptree is capable of supporting fast color clears, set
852 * fast_clear_state appropriately to ensure that fast clears will occur.
853 * Allocation of the MCS miptree will be deferred until the first fast
854 * clear actually occurs or when compressed single sampled buffer is
855 * written by the GPU for the first time.
857 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
858 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
859 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
860 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
862 /* On Gen9+ clients are not currently capable of consuming compressed
863 * single-sampled buffers. Disabling compression allows us to skip
866 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
867 const bool is_lossless_compressed
=
868 unlikely(!lossless_compression_disabled
) &&
869 brw
->gen
>= 9 && !mt
->is_scanout
&&
870 intel_miptree_supports_lossless_compressed(brw
, mt
);
872 if (is_lossless_compressed
) {
873 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
880 struct intel_mipmap_tree
*
881 intel_miptree_create_for_bo(struct brw_context
*brw
,
889 uint32_t layout_flags
)
891 struct intel_mipmap_tree
*mt
;
892 uint32_t tiling
, swizzle
;
895 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
897 /* Nothing will be able to use this miptree with the BO if the offset isn't
900 if (tiling
!= I915_TILING_NONE
)
901 assert(offset
% 4096 == 0);
903 /* miptrees can't handle negative pitch. If you need flipping of images,
904 * that's outside of the scope of the mt.
908 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
910 /* The BO already has a tiling format and we shouldn't confuse the lower
911 * layers by making it try to find a tiling format again.
913 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
914 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
916 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
917 mt
= intel_miptree_create_layout(brw
, target
, format
,
919 width
, height
, depth
, 0,
924 brw_bo_reference(bo
);
934 * For a singlesample renderbuffer, this simply wraps the given BO with a
937 * For a multisample renderbuffer, this wraps the window system's
938 * (singlesample) BO with a singlesample miptree attached to the
939 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
940 * that will contain the actual rendering (which is lazily resolved to
941 * irb->singlesample_mt).
944 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
945 struct intel_renderbuffer
*irb
,
947 uint32_t width
, uint32_t height
,
950 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
951 struct intel_mipmap_tree
*multisample_mt
= NULL
;
952 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
953 mesa_format format
= rb
->Format
;
954 int num_samples
= rb
->NumSamples
;
956 /* Only the front and back buffers, which are color buffers, are allocated
957 * through the image loader.
959 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
960 _mesa_get_format_base_format(format
) == GL_RGBA
);
962 singlesample_mt
= intel_miptree_create_for_bo(intel
,
970 MIPTREE_LAYOUT_FOR_SCANOUT
);
971 if (!singlesample_mt
)
974 /* If this miptree is capable of supporting fast color clears, set
975 * mcs_state appropriately to ensure that fast clears will occur.
976 * Allocation of the MCS miptree will be deferred until the first fast
977 * clear actually occurs.
979 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
980 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
981 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
984 if (num_samples
== 0) {
985 intel_miptree_release(&irb
->mt
);
986 irb
->mt
= singlesample_mt
;
988 assert(!irb
->singlesample_mt
);
990 intel_miptree_release(&irb
->singlesample_mt
);
991 irb
->singlesample_mt
= singlesample_mt
;
994 irb
->mt
->logical_width0
!= width
||
995 irb
->mt
->logical_height0
!= height
) {
996 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1001 if (!multisample_mt
)
1004 irb
->need_downsample
= false;
1005 intel_miptree_release(&irb
->mt
);
1006 irb
->mt
= multisample_mt
;
1012 intel_miptree_release(&irb
->singlesample_mt
);
1013 intel_miptree_release(&irb
->mt
);
1017 struct intel_mipmap_tree
*
1018 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1022 uint32_t num_samples
)
1024 struct intel_mipmap_tree
*mt
;
1027 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1028 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1029 MIPTREE_LAYOUT_TILING_ANY
|
1030 MIPTREE_LAYOUT_FOR_SCANOUT
;
1032 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1033 width
, height
, depth
, num_samples
,
1038 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
1039 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1047 intel_miptree_release(&mt
);
1052 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1053 struct intel_mipmap_tree
*src
)
1058 intel_miptree_release(dst
);
1062 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1069 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
1071 if (hiz_buf
== NULL
)
1075 intel_miptree_release(&hiz_buf
->mt
);
1077 brw_bo_unreference(hiz_buf
->aux_base
.bo
);
1083 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1088 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1089 if (--(*mt
)->refcount
<= 0) {
1092 DBG("%s deleting %p\n", __func__
, *mt
);
1094 brw_bo_unreference((*mt
)->bo
);
1095 intel_miptree_release(&(*mt
)->stencil_mt
);
1096 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1097 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
1098 if ((*mt
)->mcs_buf
) {
1099 brw_bo_unreference((*mt
)->mcs_buf
->bo
);
1100 free((*mt
)->mcs_buf
);
1102 free_aux_state_map((*mt
)->aux_state
);
1104 intel_miptree_release(&(*mt
)->plane
[0]);
1105 intel_miptree_release(&(*mt
)->plane
[1]);
1107 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1108 free((*mt
)->level
[i
].slice
);
1118 intel_get_image_dims(struct gl_texture_image
*image
,
1119 int *width
, int *height
, int *depth
)
1121 switch (image
->TexObject
->Target
) {
1122 case GL_TEXTURE_1D_ARRAY
:
1123 /* For a 1D Array texture the OpenGL API will treat the image height as
1124 * the number of array slices. For Intel hardware, we treat the 1D array
1125 * as a 2D Array with a height of 1. So, here we want to swap image
1128 assert(image
->Depth
== 1);
1129 *width
= image
->Width
;
1131 *depth
= image
->Height
;
1133 case GL_TEXTURE_CUBE_MAP
:
1134 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1135 * though we really have 6 slices.
1137 assert(image
->Depth
== 1);
1138 *width
= image
->Width
;
1139 *height
= image
->Height
;
1143 *width
= image
->Width
;
1144 *height
= image
->Height
;
1145 *depth
= image
->Depth
;
1151 * Can the image be pulled into a unified mipmap tree? This mirrors
1152 * the completeness test in a lot of ways.
1154 * Not sure whether I want to pass gl_texture_image here.
1157 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1158 struct gl_texture_image
*image
)
1160 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1161 GLuint level
= intelImage
->base
.Base
.Level
;
1162 int width
, height
, depth
;
1164 /* glTexImage* choose the texture object based on the target passed in, and
1165 * objects can't change targets over their lifetimes, so this should be
1168 assert(image
->TexObject
->Target
== mt
->target
);
1170 mesa_format mt_format
= mt
->format
;
1171 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1172 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1173 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1174 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1175 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1176 mt_format
= mt
->etc_format
;
1178 if (image
->TexFormat
!= mt_format
)
1181 intel_get_image_dims(image
, &width
, &height
, &depth
);
1183 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1186 if (mt
->surf
.size
> 0) {
1187 if (level
>= mt
->surf
.levels
)
1190 const unsigned level_depth
=
1191 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1192 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1193 mt
->surf
.logical_level0_px
.array_len
;
1195 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1196 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1197 depth
== level_depth
&&
1198 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1201 int level_depth
= mt
->level
[level
].depth
;
1202 if (mt
->num_samples
> 1) {
1203 switch (mt
->msaa_layout
) {
1204 case INTEL_MSAA_LAYOUT_NONE
:
1205 case INTEL_MSAA_LAYOUT_IMS
:
1207 case INTEL_MSAA_LAYOUT_UMS
:
1208 case INTEL_MSAA_LAYOUT_CMS
:
1209 level_depth
/= mt
->num_samples
;
1214 /* Test image dimensions against the base level image adjusted for
1215 * minification. This will also catch images not present in the
1216 * tree, changed targets, etc.
1218 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1219 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1220 depth
!= level_depth
) {
1224 if (image
->NumSamples
!= mt
->num_samples
)
1232 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1234 GLuint x
, GLuint y
, GLuint d
)
1236 mt
->level
[level
].depth
= d
;
1237 mt
->level
[level
].level_x
= x
;
1238 mt
->level
[level
].level_y
= y
;
1240 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1243 assert(mt
->level
[level
].slice
);
1245 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1246 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1251 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1252 GLuint level
, GLuint img
,
1255 if (img
== 0 && level
== 0)
1256 assert(x
== 0 && y
== 0);
1258 assert(img
< mt
->level
[level
].depth
);
1260 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1261 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1263 DBG("%s level %d img %d pos %d,%d\n",
1264 __func__
, level
, img
,
1265 mt
->level
[level
].slice
[img
].x_offset
,
1266 mt
->level
[level
].slice
[img
].y_offset
);
1270 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1271 GLuint level
, GLuint slice
,
1272 GLuint
*x
, GLuint
*y
)
1274 if (mt
->surf
.size
> 0) {
1275 uint32_t x_offset_sa
, y_offset_sa
;
1277 /* Given level is relative to level zero while the miptree may be
1278 * represent just a subset of all levels starting from 'first_level'.
1280 assert(level
>= mt
->first_level
);
1281 level
-= mt
->first_level
;
1283 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1284 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1285 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1286 &x_offset_sa
, &y_offset_sa
);
1293 assert(slice
< mt
->level
[level
].depth
);
1295 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1296 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1301 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1302 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1303 * and tile_h is set to 1.
1306 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1307 uint32_t *tile_w
, uint32_t *tile_h
)
1318 case I915_TILING_NONE
:
1323 unreachable("not reached");
1329 * This function computes masks that may be used to select the bits of the X
1330 * and Y coordinates that indicate the offset within a tile. If the BO is
1331 * untiled, the masks are set to 0.
1334 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1335 uint32_t *mask_x
, uint32_t *mask_y
)
1337 uint32_t tile_w_bytes
, tile_h
;
1339 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1341 *mask_x
= tile_w_bytes
/ cpp
- 1;
1342 *mask_y
= tile_h
- 1;
1346 * Compute the offset (in bytes) from the start of the BO to the given x
1347 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1348 * multiples of the tile size.
1351 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1352 uint32_t x
, uint32_t y
)
1355 uint32_t pitch
= mt
->pitch
;
1356 uint32_t tiling
= mt
->tiling
;
1360 unreachable("not reached");
1361 case I915_TILING_NONE
:
1362 return y
* pitch
+ x
* cpp
;
1364 assert((x
% (512 / cpp
)) == 0);
1365 assert((y
% 8) == 0);
1366 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1368 assert((x
% (128 / cpp
)) == 0);
1369 assert((y
% 32) == 0);
1370 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1375 * Rendering with tiled buffers requires that the base address of the buffer
1376 * be aligned to a page boundary. For renderbuffers, and sometimes with
1377 * textures, we may want the surface to point at a texture image level that
1378 * isn't at a page boundary.
1380 * This function returns an appropriately-aligned base offset
1381 * according to the tiling restrictions, plus any required x/y offset
1385 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1386 GLuint level
, GLuint slice
,
1391 uint32_t mask_x
, mask_y
;
1393 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1394 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1396 *tile_x
= x
& mask_x
;
1397 *tile_y
= y
& mask_y
;
1399 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1403 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1404 struct intel_mipmap_tree
*src_mt
,
1405 unsigned src_level
, unsigned src_layer
,
1406 struct intel_mipmap_tree
*dst_mt
,
1407 unsigned dst_level
, unsigned dst_layer
,
1408 unsigned width
, unsigned height
)
1411 ptrdiff_t src_stride
, dst_stride
;
1412 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1413 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1415 intel_miptree_map(brw
, src_mt
,
1416 src_level
, src_layer
,
1419 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1422 intel_miptree_map(brw
, dst_mt
,
1423 dst_level
, dst_layer
,
1426 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1430 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1431 _mesa_get_format_name(src_mt
->format
),
1432 src_mt
, src
, src_stride
,
1433 _mesa_get_format_name(dst_mt
->format
),
1434 dst_mt
, dst
, dst_stride
,
1437 int row_size
= cpp
* width
;
1438 if (src_stride
== row_size
&&
1439 dst_stride
== row_size
) {
1440 memcpy(dst
, src
, row_size
* height
);
1442 for (int i
= 0; i
< height
; i
++) {
1443 memcpy(dst
, src
, row_size
);
1449 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1450 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1452 /* Don't forget to copy the stencil data over, too. We could have skipped
1453 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1454 * shuffling the two data sources in/out of temporary storage instead of
1455 * the direct mapping we get this way.
1457 if (dst_mt
->stencil_mt
) {
1458 assert(src_mt
->stencil_mt
);
1459 intel_miptree_copy_slice_sw(brw
,
1460 src_mt
->stencil_mt
, src_level
, src_layer
,
1461 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1467 intel_miptree_copy_slice(struct brw_context
*brw
,
1468 struct intel_mipmap_tree
*src_mt
,
1469 unsigned src_level
, unsigned src_layer
,
1470 struct intel_mipmap_tree
*dst_mt
,
1471 unsigned dst_level
, unsigned dst_layer
)
1474 mesa_format format
= src_mt
->format
;
1475 uint32_t width
, height
;
1477 if (src_mt
->surf
.size
> 0) {
1478 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1479 src_level
- src_mt
->first_level
);
1480 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1481 src_level
- src_mt
->first_level
);
1483 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1484 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1485 src_level
- src_mt
->first_level
));
1487 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1489 width
= minify(src_mt
->physical_width0
,
1490 src_level
- src_mt
->first_level
);
1491 height
= minify(src_mt
->physical_height0
,
1492 src_level
- src_mt
->first_level
);
1493 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1496 assert(src_mt
->format
== dst_mt
->format
);
1498 if (dst_mt
->compressed
) {
1500 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1501 height
= ALIGN_NPOT(height
, j
) / j
;
1502 width
= ALIGN_NPOT(width
, i
) / i
;
1505 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1506 * below won't apply since we can't do the depth's Y tiling or the
1507 * stencil's W tiling in the blitter.
1509 if (src_mt
->stencil_mt
) {
1510 intel_miptree_copy_slice_sw(brw
,
1511 src_mt
, src_level
, src_layer
,
1512 dst_mt
, dst_level
, dst_layer
,
1517 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1518 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1520 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1523 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1524 _mesa_get_format_name(src_mt
->format
),
1525 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1526 _mesa_get_format_name(dst_mt
->format
),
1527 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1530 if (!intel_miptree_blit(brw
,
1531 src_mt
, src_level
, src_layer
, 0, 0, false,
1532 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1533 width
, height
, GL_COPY
)) {
1534 perf_debug("miptree validate blit for %s failed\n",
1535 _mesa_get_format_name(format
));
1537 intel_miptree_copy_slice_sw(brw
,
1538 src_mt
, src_level
, src_layer
,
1539 dst_mt
, dst_level
, dst_layer
,
1545 * Copies the image's current data to the given miptree, and associates that
1546 * miptree with the image.
1548 * If \c invalidate is true, then the actual image data does not need to be
1549 * copied, but the image still needs to be associated to the new miptree (this
1550 * is set to true if we're about to clear the image).
1553 intel_miptree_copy_teximage(struct brw_context
*brw
,
1554 struct intel_texture_image
*intelImage
,
1555 struct intel_mipmap_tree
*dst_mt
,
1558 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1559 struct intel_texture_object
*intel_obj
=
1560 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1561 int level
= intelImage
->base
.Base
.Level
;
1562 const unsigned face
= intelImage
->base
.Base
.Face
;
1563 unsigned start_layer
, end_layer
;
1565 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1567 assert(intelImage
->base
.Base
.Height
);
1569 end_layer
= intelImage
->base
.Base
.Height
- 1;
1570 } else if (face
> 0) {
1574 assert(intelImage
->base
.Base
.Depth
);
1576 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1580 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1581 intel_miptree_copy_slice(brw
,
1587 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1588 intel_obj
->needs_validate
= true;
1592 intel_miptree_init_mcs(struct brw_context
*brw
,
1593 struct intel_mipmap_tree
*mt
,
1596 assert(mt
->mcs_buf
!= NULL
);
1598 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1600 * When MCS buffer is enabled and bound to MSRT, it is required that it
1601 * is cleared prior to any rendering.
1603 * Since we don't use the MCS buffer for any purpose other than rendering,
1604 * it makes sense to just clear it immediately upon allocation.
1606 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1608 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1609 if (unlikely(map
== NULL
)) {
1610 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1611 brw_bo_unreference(mt
->mcs_buf
->bo
);
1616 memset(data
, init_value
, mt
->mcs_buf
->size
);
1617 brw_bo_unmap(mt
->mcs_buf
->bo
);
1620 static struct intel_miptree_aux_buffer
*
1621 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1622 struct intel_mipmap_tree
*mt
,
1625 unsigned mcs_height
,
1626 uint32_t layout_flags
)
1628 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1629 struct intel_mipmap_tree
*temp_mt
;
1634 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1636 * "The MCS surface must be stored as Tile Y."
1638 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1639 temp_mt
= miptree_create(brw
,
1647 0 /* num_samples */,
1654 buf
->bo
= temp_mt
->bo
;
1655 buf
->offset
= temp_mt
->offset
;
1656 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1657 buf
->pitch
= temp_mt
->pitch
;
1658 buf
->qpitch
= temp_mt
->qpitch
;
1660 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1661 * structure should go away. We use miptree create simply as a means to make
1662 * sure all the constraints for the buffer are satisfied.
1664 brw_bo_reference(temp_mt
->bo
);
1665 intel_miptree_release(&temp_mt
);
1671 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1672 struct intel_mipmap_tree
*mt
,
1675 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1676 assert(mt
->mcs_buf
== NULL
);
1677 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1679 /* Choose the correct format for the MCS buffer. All that really matters
1680 * is that we allocate the right buffer size, since we'll always be
1681 * accessing this miptree using MCS-specific hardware mechanisms, which
1682 * infer the correct format based on num_samples.
1685 switch (num_samples
) {
1688 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1691 format
= MESA_FORMAT_R_UNORM8
;
1694 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1695 * for each sample, plus 8 padding bits).
1697 format
= MESA_FORMAT_R_UINT32
;
1700 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1703 format
= MESA_FORMAT_RG_UINT32
;
1706 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1709 /* Multisampled miptrees are only supported for single level. */
1710 assert(mt
->first_level
== 0);
1711 enum isl_aux_state
**aux_state
=
1712 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1717 intel_mcs_miptree_buf_create(brw
, mt
,
1720 mt
->logical_height0
,
1721 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1727 mt
->aux_state
= aux_state
;
1729 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1735 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1736 struct intel_mipmap_tree
*mt
,
1737 bool is_lossless_compressed
)
1739 assert(mt
->mcs_buf
== NULL
);
1740 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1742 struct isl_surf temp_main_surf
;
1743 struct isl_surf temp_ccs_surf
;
1745 /* Create first an ISL presentation for the main color surface and let ISL
1746 * calculate equivalent CCS surface against it.
1748 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1749 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1752 assert(temp_ccs_surf
.size
&&
1753 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1755 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1759 enum isl_aux_state
**aux_state
=
1760 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1766 buf
->size
= temp_ccs_surf
.size
;
1767 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1768 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1770 /* In case of compression mcs buffer needs to be initialised requiring the
1771 * buffer to be immediately mapped to cpu space for writing. Therefore do
1772 * not use the gpu access flag which can cause an unnecessary delay if the
1773 * backing pages happened to be just used by the GPU.
1775 const uint32_t alloc_flags
=
1776 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1778 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree", buf
->size
,
1779 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1787 mt
->aux_state
= aux_state
;
1789 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1790 * used for lossless compression which requires similar initialisation
1791 * as multi-sample compression.
1793 if (is_lossless_compressed
) {
1794 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1795 * resolve. Initialize it accordingly in case the first renderer is
1796 * cpu (or other none compression aware party).
1798 * This is also explicitly stated in the spec (MCS Buffer for Render
1800 * "If Software wants to enable Color Compression without Fast clear,
1801 * Software needs to initialize MCS with zeros."
1803 intel_miptree_init_mcs(brw
, mt
, 0);
1804 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1811 * Helper for intel_miptree_alloc_hiz() that sets
1812 * \c mt->level[level].has_hiz. Return true if and only if
1813 * \c has_hiz was set.
1816 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1817 struct intel_mipmap_tree
*mt
,
1820 assert(mt
->hiz_buf
);
1822 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1823 uint32_t width
= minify(mt
->physical_width0
, level
);
1824 uint32_t height
= minify(mt
->physical_height0
, level
);
1826 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1827 * and the height is 4 aligned. This allows our HiZ support
1828 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1829 * we can grow the width & height to allow the HiZ op to
1830 * force the proper size alignments.
1832 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1833 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1838 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1839 mt
->level
[level
].has_hiz
= true;
1845 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1846 * buffer dimensions and allocates a bo for the hiz buffer.
1848 static struct intel_miptree_hiz_buffer
*
1849 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1850 struct intel_mipmap_tree
*mt
)
1852 unsigned z_width
= mt
->logical_width0
;
1853 unsigned z_height
= mt
->logical_height0
;
1854 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1855 unsigned hz_width
, hz_height
;
1856 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1861 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1862 * adjustments required for Z_Height and Z_Width based on multisampling.
1864 switch (mt
->num_samples
) {
1878 unreachable("unsupported sample count");
1881 const unsigned vertical_align
= 8; /* 'j' in the docs */
1882 const unsigned H0
= z_height
;
1883 const unsigned h0
= ALIGN(H0
, vertical_align
);
1884 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1885 const unsigned Z0
= z_depth
;
1887 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1888 hz_width
= ALIGN(z_width
, 16);
1890 if (mt
->target
== GL_TEXTURE_3D
) {
1894 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1895 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1896 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1897 hz_height
+= h_i
* Z_i
;
1898 H_i
= minify(H_i
, 1);
1899 Z_i
= minify(Z_i
, 1);
1902 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1904 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1906 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1907 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1908 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1911 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
1912 hz_width
, hz_height
, 1,
1913 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1914 BO_ALLOC_FOR_RENDER
);
1915 if (!buf
->aux_base
.bo
) {
1920 buf
->aux_base
.size
= hz_width
* hz_height
;
1927 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1928 * buffer dimensions and allocates a bo for the hiz buffer.
1930 static struct intel_miptree_hiz_buffer
*
1931 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1932 struct intel_mipmap_tree
*mt
)
1934 unsigned z_width
= mt
->logical_width0
;
1935 unsigned z_height
= mt
->logical_height0
;
1936 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1937 unsigned hz_width
, hz_height
;
1938 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1943 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1944 * adjustments required for Z_Height and Z_Width based on multisampling.
1947 switch (mt
->num_samples
) {
1961 unreachable("unsupported sample count");
1965 const unsigned vertical_align
= 8; /* 'j' in the docs */
1966 const unsigned H0
= z_height
;
1967 const unsigned h0
= ALIGN(H0
, vertical_align
);
1968 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1969 const unsigned Z0
= z_depth
;
1971 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1972 hz_width
= ALIGN(z_width
, 16);
1976 unsigned sum_h_i
= 0;
1977 unsigned hz_height_3d_sum
= 0;
1978 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1979 unsigned i
= level
- mt
->first_level
;
1980 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1981 /* sum(i=2 to m; h_i) */
1985 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1986 hz_height_3d_sum
+= h_i
* Z_i
;
1987 H_i
= minify(H_i
, 1);
1988 Z_i
= minify(Z_i
, 1);
1990 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1991 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1993 if (mt
->target
== GL_TEXTURE_3D
) {
1994 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1995 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1997 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1998 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
2001 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
2002 hz_width
, hz_height
, 1,
2003 I915_TILING_Y
, &buf
->aux_base
.pitch
,
2004 BO_ALLOC_FOR_RENDER
);
2005 if (!buf
->aux_base
.bo
) {
2010 buf
->aux_base
.size
= hz_width
* hz_height
;
2016 static struct intel_miptree_hiz_buffer
*
2017 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
2018 struct intel_mipmap_tree
*mt
)
2020 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
2021 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
2024 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
2029 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
2030 buf
->mt
= intel_miptree_create(brw
,
2036 mt
->logical_height0
,
2045 buf
->aux_base
.bo
= buf
->mt
->bo
;
2046 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
2047 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
2048 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
* 2;
2054 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
2055 struct intel_mipmap_tree
*mt
)
2060 if (mt
->hiz_buf
!= NULL
)
2063 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
2066 switch (mt
->format
) {
2067 case MESA_FORMAT_Z_FLOAT32
:
2068 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
2069 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
2070 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
2071 case MESA_FORMAT_Z_UNORM16
:
2079 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2080 struct intel_mipmap_tree
*mt
)
2082 assert(mt
->hiz_buf
== NULL
);
2083 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
2085 enum isl_aux_state
**aux_state
=
2086 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
2090 if (brw
->gen
== 7) {
2091 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
2092 } else if (brw
->gen
>= 8) {
2093 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
2095 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
2103 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2104 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2106 mt
->aux_state
= aux_state
;
2112 * Can the miptree sample using the hiz buffer?
2115 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2116 struct intel_mipmap_tree
*mt
)
2118 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2119 * so keep things conservative for now and never enable it unless we're SKL+.
2129 /* It seems the hardware won't fallback to the depth buffer if some of the
2130 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2131 * of the texture to be HiZ enabled.
2133 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2134 if (!intel_miptree_level_has_hiz(mt
, level
))
2138 /* If compressed multisampling is enabled, then we use it for the auxiliary
2141 * From the BDW PRM (Volume 2d: Command Reference: Structures
2142 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2144 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2145 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2147 * There is no such blurb for 1D textures, but there is sufficient evidence
2148 * that this is broken on SKL+.
2150 return (mt
->num_samples
<= 1 &&
2151 mt
->target
!= GL_TEXTURE_3D
&&
2152 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2156 * Does the miptree slice have hiz enabled?
2159 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2161 intel_miptree_check_level_layer(mt
, level
, 0);
2162 return mt
->level
[level
].has_hiz
;
2166 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2167 unsigned start_level
, unsigned num_levels
,
2168 unsigned start_layer
, unsigned num_layers
)
2170 assert(_mesa_is_format_color_format(mt
->format
));
2175 /* Clamp the level range to fit the miptree */
2176 assert(start_level
+ num_levels
>= start_level
);
2177 const uint32_t last_level
=
2178 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2179 start_level
= MAX2(mt
->first_level
, start_level
);
2180 num_levels
= last_level
- start_level
+ 1;
2182 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2183 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2184 for (unsigned a
= 0; a
< level_layers
; a
++) {
2185 enum isl_aux_state aux_state
=
2186 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2187 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2188 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2197 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2198 const struct intel_mipmap_tree
*mt
,
2199 unsigned level
, unsigned layer
)
2202 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2205 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2206 assert(brw
->gen
>= 8 ||
2207 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2209 /* Compression of arrayed msaa surfaces is supported. */
2210 if (mt
->num_samples
> 1)
2213 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2214 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2220 static enum blorp_fast_clear_op
2221 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2222 bool ccs_supported
, bool fast_clear_supported
)
2224 assert(ccs_supported
== fast_clear_supported
);
2226 switch (aux_state
) {
2227 case ISL_AUX_STATE_CLEAR
:
2228 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2230 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2232 return BLORP_FAST_CLEAR_OP_NONE
;
2234 case ISL_AUX_STATE_PASS_THROUGH
:
2235 return BLORP_FAST_CLEAR_OP_NONE
;
2237 case ISL_AUX_STATE_RESOLVED
:
2238 case ISL_AUX_STATE_AUX_INVALID
:
2239 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2243 unreachable("Invalid aux state for CCS_D");
2246 static enum blorp_fast_clear_op
2247 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2248 bool ccs_supported
, bool fast_clear_supported
)
2250 switch (aux_state
) {
2251 case ISL_AUX_STATE_CLEAR
:
2252 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2254 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2255 else if (!fast_clear_supported
)
2256 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2258 return BLORP_FAST_CLEAR_OP_NONE
;
2260 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2262 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2264 return BLORP_FAST_CLEAR_OP_NONE
;
2266 case ISL_AUX_STATE_PASS_THROUGH
:
2267 return BLORP_FAST_CLEAR_OP_NONE
;
2269 case ISL_AUX_STATE_RESOLVED
:
2270 case ISL_AUX_STATE_AUX_INVALID
:
2274 unreachable("Invalid aux state for CCS_E");
2278 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2279 struct intel_mipmap_tree
*mt
,
2280 uint32_t level
, uint32_t layer
,
2282 bool fast_clear_supported
)
2284 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2286 enum blorp_fast_clear_op resolve_op
;
2287 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2288 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2289 fast_clear_supported
);
2291 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2292 fast_clear_supported
);
2295 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2296 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2297 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2299 switch (resolve_op
) {
2300 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2301 /* The CCS full resolve operation destroys the CCS and sets it to the
2302 * pass-through state. (You can also think of this as being both a
2303 * resolve and an ambiguate in one operation.)
2305 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2306 ISL_AUX_STATE_PASS_THROUGH
);
2309 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2310 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2311 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2315 unreachable("Invalid resolve op");
2321 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2322 struct intel_mipmap_tree
*mt
,
2323 uint32_t level
, uint32_t layer
,
2324 bool written_with_ccs
)
2326 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2328 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2329 switch (aux_state
) {
2330 case ISL_AUX_STATE_CLEAR
:
2331 assert(written_with_ccs
);
2332 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2333 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2336 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2337 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2338 assert(written_with_ccs
);
2339 break; /* Nothing to do */
2341 case ISL_AUX_STATE_PASS_THROUGH
:
2342 if (written_with_ccs
) {
2343 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2344 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2350 case ISL_AUX_STATE_RESOLVED
:
2351 case ISL_AUX_STATE_AUX_INVALID
:
2352 unreachable("Invalid aux state for CCS_E");
2355 /* CCS_D is a bit simpler */
2356 switch (aux_state
) {
2357 case ISL_AUX_STATE_CLEAR
:
2358 assert(written_with_ccs
);
2359 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2360 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2363 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2364 assert(written_with_ccs
);
2365 break; /* Nothing to do */
2367 case ISL_AUX_STATE_PASS_THROUGH
:
2371 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2372 case ISL_AUX_STATE_RESOLVED
:
2373 case ISL_AUX_STATE_AUX_INVALID
:
2374 unreachable("Invalid aux state for CCS_D");
2380 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2381 struct intel_mipmap_tree
*mt
,
2382 uint32_t level
, uint32_t layer
,
2383 bool written_with_aux
)
2385 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2386 case ISL_AUX_STATE_CLEAR
:
2387 assert(written_with_aux
);
2388 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2389 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2392 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2393 assert(written_with_aux
);
2394 break; /* Nothing to do */
2396 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2397 case ISL_AUX_STATE_RESOLVED
:
2398 case ISL_AUX_STATE_PASS_THROUGH
:
2399 case ISL_AUX_STATE_AUX_INVALID
:
2400 unreachable("Invalid aux state for MCS");
2405 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2406 struct intel_mipmap_tree
*mt
,
2407 uint32_t level
, uint32_t layer
,
2408 bool hiz_supported
, bool fast_clear_supported
)
2410 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2411 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2412 case ISL_AUX_STATE_CLEAR
:
2413 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2414 if (!hiz_supported
|| !fast_clear_supported
)
2415 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2418 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2420 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2423 case ISL_AUX_STATE_PASS_THROUGH
:
2424 case ISL_AUX_STATE_RESOLVED
:
2427 case ISL_AUX_STATE_AUX_INVALID
:
2429 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2433 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2434 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2437 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2438 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2439 ISL_AUX_STATE_RESOLVED
);
2442 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2443 /* The HiZ resolve operation is actually an ambiguate */
2444 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2445 ISL_AUX_STATE_PASS_THROUGH
);
2449 unreachable("Invalid HiZ op");
2455 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2456 struct intel_mipmap_tree
*mt
,
2457 uint32_t level
, uint32_t layer
,
2458 bool written_with_hiz
)
2460 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2461 case ISL_AUX_STATE_CLEAR
:
2462 assert(written_with_hiz
);
2463 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2464 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2467 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2468 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2469 assert(written_with_hiz
);
2470 break; /* Nothing to do */
2472 case ISL_AUX_STATE_RESOLVED
:
2473 if (written_with_hiz
) {
2474 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2475 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2477 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2478 ISL_AUX_STATE_AUX_INVALID
);
2482 case ISL_AUX_STATE_PASS_THROUGH
:
2483 if (written_with_hiz
) {
2484 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2485 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2489 case ISL_AUX_STATE_AUX_INVALID
:
2490 assert(!written_with_hiz
);
2495 static inline uint32_t
2496 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2497 uint32_t start_level
, uint32_t num_levels
)
2499 assert(start_level
>= mt
->first_level
);
2500 assert(start_level
<= mt
->last_level
);
2502 if (num_levels
== INTEL_REMAINING_LAYERS
)
2503 num_levels
= mt
->last_level
- start_level
+ 1;
2504 /* Check for overflow */
2505 assert(start_level
+ num_levels
>= start_level
);
2506 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2511 static inline uint32_t
2512 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2513 uint32_t start_layer
, uint32_t num_layers
)
2515 assert(level
<= mt
->last_level
);
2516 uint32_t total_num_layers
= mt
->level
[level
].depth
;
2518 assert(start_layer
< total_num_layers
);
2519 if (num_layers
== INTEL_REMAINING_LAYERS
)
2520 num_layers
= total_num_layers
- start_layer
;
2521 /* Check for overflow */
2522 assert(start_layer
+ num_layers
>= start_layer
);
2523 assert(start_layer
+ num_layers
<= total_num_layers
);
2529 intel_miptree_prepare_access(struct brw_context
*brw
,
2530 struct intel_mipmap_tree
*mt
,
2531 uint32_t start_level
, uint32_t num_levels
,
2532 uint32_t start_layer
, uint32_t num_layers
,
2533 bool aux_supported
, bool fast_clear_supported
)
2535 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2537 if (_mesa_is_format_color_format(mt
->format
)) {
2541 if (mt
->num_samples
> 1) {
2542 /* Nothing to do for MSAA */
2543 assert(aux_supported
&& fast_clear_supported
);
2545 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2546 const uint32_t level
= start_level
+ l
;
2547 const uint32_t level_layers
=
2548 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2549 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2550 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2551 start_layer
+ a
, aux_supported
,
2552 fast_clear_supported
);
2556 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2557 /* Nothing to do for stencil */
2562 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2563 const uint32_t level
= start_level
+ l
;
2564 if (!intel_miptree_level_has_hiz(mt
, level
))
2567 const uint32_t level_layers
=
2568 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2569 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2570 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2572 fast_clear_supported
);
2579 intel_miptree_finish_write(struct brw_context
*brw
,
2580 struct intel_mipmap_tree
*mt
, uint32_t level
,
2581 uint32_t start_layer
, uint32_t num_layers
,
2582 bool written_with_aux
)
2584 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2586 if (_mesa_is_format_color_format(mt
->format
)) {
2590 if (mt
->num_samples
> 1) {
2591 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2592 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2596 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2597 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2601 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2602 /* Nothing to do for stencil */
2604 if (!intel_miptree_level_has_hiz(mt
, level
))
2607 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2608 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2615 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2616 uint32_t level
, uint32_t layer
)
2618 intel_miptree_check_level_layer(mt
, level
, layer
);
2620 if (_mesa_is_format_color_format(mt
->format
)) {
2621 assert(mt
->mcs_buf
!= NULL
);
2622 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2623 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2624 unreachable("Cannot get aux state for stencil");
2626 assert(intel_miptree_level_has_hiz(mt
, level
));
2629 return mt
->aux_state
[level
][layer
];
2633 intel_miptree_set_aux_state(struct brw_context
*brw
,
2634 struct intel_mipmap_tree
*mt
, uint32_t level
,
2635 uint32_t start_layer
, uint32_t num_layers
,
2636 enum isl_aux_state aux_state
)
2638 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2640 if (_mesa_is_format_color_format(mt
->format
)) {
2641 assert(mt
->mcs_buf
!= NULL
);
2642 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2643 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2644 unreachable("Cannot get aux state for stencil");
2646 assert(intel_miptree_level_has_hiz(mt
, level
));
2649 for (unsigned a
= 0; a
< num_layers
; a
++)
2650 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2653 /* On Gen9 color buffers may be compressed by the hardware (lossless
2654 * compression). There are, however, format restrictions and care needs to be
2655 * taken that the sampler engine is capable for re-interpreting a buffer with
2656 * format different the buffer was originally written with.
2658 * For example, SRGB formats are not compressible and the sampler engine isn't
2659 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2660 * color buffer needs to be resolved so that the sampling surface can be
2661 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2665 can_texture_with_ccs(struct brw_context
*brw
,
2666 struct intel_mipmap_tree
*mt
,
2667 mesa_format view_format
)
2669 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2672 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2673 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2675 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2676 isl_mt_format
, isl_view_format
)) {
2677 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2678 _mesa_get_format_name(view_format
),
2679 _mesa_get_format_name(mt
->format
));
2687 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2688 struct intel_mipmap_tree
*mt
,
2689 mesa_format view_format
,
2690 uint32_t start_level
, uint32_t num_levels
,
2691 uint32_t start_layer
, uint32_t num_layers
,
2692 bool *aux_supported_out
)
2694 bool aux_supported
, clear_supported
;
2695 if (_mesa_is_format_color_format(mt
->format
)) {
2696 if (mt
->num_samples
> 1) {
2697 aux_supported
= clear_supported
= true;
2699 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2701 /* Clear color is specified as ints or floats and the conversion is
2702 * done by the sampler. If we have a texture view, we would have to
2703 * perform the clear color conversion manually. Just disable clear
2706 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2708 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2709 aux_supported
= clear_supported
= false;
2711 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2714 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2715 start_layer
, num_layers
,
2716 aux_supported
, clear_supported
);
2717 if (aux_supported_out
)
2718 *aux_supported_out
= aux_supported
;
2722 intel_miptree_prepare_texture(struct brw_context
*brw
,
2723 struct intel_mipmap_tree
*mt
,
2724 mesa_format view_format
,
2725 bool *aux_supported_out
)
2727 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2728 0, INTEL_REMAINING_LEVELS
,
2729 0, INTEL_REMAINING_LAYERS
,
2734 intel_miptree_prepare_image(struct brw_context
*brw
,
2735 struct intel_mipmap_tree
*mt
)
2737 /* The data port doesn't understand any compression */
2738 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2739 0, INTEL_REMAINING_LAYERS
, false, false);
2743 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2744 struct intel_mipmap_tree
*mt
, uint32_t level
,
2745 uint32_t start_layer
, uint32_t num_layers
)
2747 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2748 start_layer
, num_layers
, NULL
);
2752 intel_miptree_prepare_render(struct brw_context
*brw
,
2753 struct intel_mipmap_tree
*mt
, uint32_t level
,
2754 uint32_t start_layer
, uint32_t layer_count
,
2757 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2758 * the single-sampled color renderbuffers because the CCS buffer isn't
2759 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2760 * enabled because otherwise the surface state will be programmed with
2761 * the linear equivalent format anyway.
2763 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2764 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2766 /* Lossless compression is not supported for SRGB formats, it
2767 * should be impossible to get here with such surfaces.
2769 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2770 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2774 /* For layered rendering non-compressed fast cleared buffers need to be
2775 * resolved. Surface state can carry only one fast color clear value
2776 * while each layer may have its own fast clear color value. For
2777 * compressed buffers color value is available in the color buffer.
2779 if (layer_count
> 1 &&
2780 !(mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) &&
2781 !intel_miptree_is_lossless_compressed(brw
, mt
)) {
2782 assert(brw
->gen
>= 8);
2784 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2790 intel_miptree_finish_render(struct brw_context
*brw
,
2791 struct intel_mipmap_tree
*mt
, uint32_t level
,
2792 uint32_t start_layer
, uint32_t layer_count
)
2794 assert(_mesa_is_format_color_format(mt
->format
));
2795 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2796 mt
->mcs_buf
!= NULL
);
2800 intel_miptree_prepare_depth(struct brw_context
*brw
,
2801 struct intel_mipmap_tree
*mt
, uint32_t level
,
2802 uint32_t start_layer
, uint32_t layer_count
)
2804 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2805 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2809 intel_miptree_finish_depth(struct brw_context
*brw
,
2810 struct intel_mipmap_tree
*mt
, uint32_t level
,
2811 uint32_t start_layer
, uint32_t layer_count
,
2814 if (depth_written
) {
2815 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2816 mt
->hiz_buf
!= NULL
);
2821 * Make it possible to share the BO backing the given miptree with another
2822 * process or another miptree.
2824 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2825 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2826 * ensure that no MCS buffer gets allocated in the future.
2828 * HiZ is similarly unsafe with shared buffers.
2831 intel_miptree_make_shareable(struct brw_context
*brw
,
2832 struct intel_mipmap_tree
*mt
)
2834 /* MCS buffers are also used for multisample buffers, but we can't resolve
2835 * away a multisample MCS buffer because it's an integral part of how the
2836 * pixel data is stored. Fortunately this code path should never be
2837 * reached for multisample buffers.
2839 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2841 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2842 0, INTEL_REMAINING_LAYERS
, false, false);
2845 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2846 brw_bo_unreference(mt
->mcs_buf
->bo
);
2850 /* Any pending MCS/CCS operations are no longer needed. Trying to
2851 * execute any will likely crash due to the missing aux buffer. So let's
2852 * delete all pending ops.
2854 free(mt
->aux_state
);
2855 mt
->aux_state
= NULL
;
2859 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2860 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2863 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2864 mt
->level
[l
].has_hiz
= false;
2867 /* Any pending HiZ operations are no longer needed. Trying to execute
2868 * any will likely crash due to the missing aux buffer. So let's delete
2871 free(mt
->aux_state
);
2872 mt
->aux_state
= NULL
;
2878 * \brief Get pointer offset into stencil buffer.
2880 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2881 * must decode the tile's layout in software.
2884 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2886 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2888 * Even though the returned offset is always positive, the return type is
2890 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2891 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2894 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2896 uint32_t tile_size
= 4096;
2897 uint32_t tile_width
= 64;
2898 uint32_t tile_height
= 64;
2899 uint32_t row_size
= 64 * stride
;
2901 uint32_t tile_x
= x
/ tile_width
;
2902 uint32_t tile_y
= y
/ tile_height
;
2904 /* The byte's address relative to the tile's base addres. */
2905 uint32_t byte_x
= x
% tile_width
;
2906 uint32_t byte_y
= y
% tile_height
;
2908 uintptr_t u
= tile_y
* row_size
2909 + tile_x
* tile_size
2910 + 512 * (byte_x
/ 8)
2912 + 32 * ((byte_y
/ 4) % 2)
2913 + 16 * ((byte_x
/ 4) % 2)
2914 + 8 * ((byte_y
/ 2) % 2)
2915 + 4 * ((byte_x
/ 2) % 2)
2920 /* adjust for bit6 swizzling */
2921 if (((byte_x
/ 8) % 2) == 1) {
2922 if (((byte_y
/ 8) % 2) == 0) {
2934 intel_miptree_updownsample(struct brw_context
*brw
,
2935 struct intel_mipmap_tree
*src
,
2936 struct intel_mipmap_tree
*dst
)
2938 unsigned src_w
, src_h
, dst_w
, dst_h
;
2940 if (src
->surf
.size
> 0) {
2941 src_w
= src
->surf
.logical_level0_px
.width
;
2942 src_h
= src
->surf
.logical_level0_px
.height
;
2944 src_w
= src
->logical_width0
;
2945 src_h
= src
->logical_height0
;
2948 if (dst
->surf
.size
> 0) {
2949 dst_w
= dst
->surf
.logical_level0_px
.width
;
2950 dst_h
= dst
->surf
.logical_level0_px
.height
;
2952 dst_w
= dst
->logical_width0
;
2953 dst_h
= dst
->logical_height0
;
2956 brw_blorp_blit_miptrees(brw
,
2957 src
, 0 /* level */, 0 /* layer */,
2958 src
->format
, SWIZZLE_XYZW
,
2959 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2962 GL_NEAREST
, false, false /*mirror x, y*/,
2965 if (src
->stencil_mt
) {
2966 if (src
->stencil_mt
->surf
.size
> 0) {
2967 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2968 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2970 src_w
= src
->stencil_mt
->logical_width0
;
2971 src_h
= src
->stencil_mt
->logical_height0
;
2974 if (dst
->stencil_mt
->surf
.size
> 0) {
2975 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2976 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2978 dst_w
= dst
->stencil_mt
->logical_width0
;
2979 dst_h
= dst
->stencil_mt
->logical_height0
;
2982 brw_blorp_blit_miptrees(brw
,
2983 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2984 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2985 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2986 dst
->stencil_mt
->format
,
2989 GL_NEAREST
, false, false /*mirror x, y*/,
2990 false, false /* decode/encode srgb */);
2995 intel_update_r8stencil(struct brw_context
*brw
,
2996 struct intel_mipmap_tree
*mt
)
2998 assert(brw
->gen
>= 7);
2999 struct intel_mipmap_tree
*src
=
3000 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3001 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
3004 if (!mt
->r8stencil_mt
) {
3005 const uint32_t r8stencil_flags
=
3006 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
3007 MIPTREE_LAYOUT_DISABLE_AUX
;
3008 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3009 mt
->r8stencil_mt
= intel_miptree_create(brw
,
3011 MESA_FORMAT_R_UINT8
,
3014 src
->logical_width0
,
3015 src
->logical_height0
,
3016 src
->logical_depth0
,
3019 assert(mt
->r8stencil_mt
);
3022 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3024 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3025 const unsigned depth
= src
->level
[level
].depth
;
3027 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3028 brw_blorp_copy_miptrees(brw
,
3032 minify(src
->logical_width0
, level
),
3033 minify(src
->logical_height0
, level
));
3037 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3038 src
->r8stencil_needs_update
= false;
3042 intel_miptree_map_raw(struct brw_context
*brw
,
3043 struct intel_mipmap_tree
*mt
,
3046 struct brw_bo
*bo
= mt
->bo
;
3048 if (brw_batch_references(&brw
->batch
, bo
))
3049 intel_batchbuffer_flush(brw
);
3051 return brw_bo_map(brw
, bo
, mode
);
3055 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3057 brw_bo_unmap(mt
->bo
);
3061 intel_miptree_map_gtt(struct brw_context
*brw
,
3062 struct intel_mipmap_tree
*mt
,
3063 struct intel_miptree_map
*map
,
3064 unsigned int level
, unsigned int slice
)
3066 unsigned int bw
, bh
;
3068 unsigned int image_x
, image_y
;
3069 intptr_t x
= map
->x
;
3070 intptr_t y
= map
->y
;
3072 /* For compressed formats, the stride is the number of bytes per
3073 * row of blocks. intel_miptree_get_image_offset() already does
3076 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3077 assert(y
% bh
== 0);
3078 assert(x
% bw
== 0);
3082 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
3087 /* Note that in the case of cube maps, the caller must have passed the
3088 * slice number referencing the face.
3090 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3094 map
->stride
= mt
->pitch
;
3095 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3098 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3099 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3100 map
->x
, map
->y
, map
->w
, map
->h
,
3101 mt
, _mesa_get_format_name(mt
->format
),
3102 x
, y
, map
->ptr
, map
->stride
);
3106 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3108 intel_miptree_unmap_raw(mt
);
3112 intel_miptree_map_blit(struct brw_context
*brw
,
3113 struct intel_mipmap_tree
*mt
,
3114 struct intel_miptree_map
*map
,
3115 unsigned int level
, unsigned int slice
)
3117 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3118 /* first_level */ 0,
3122 MIPTREE_LAYOUT_TILING_NONE
);
3124 if (!map
->linear_mt
) {
3125 fprintf(stderr
, "Failed to allocate blit temporary\n");
3128 map
->stride
= map
->linear_mt
->pitch
;
3130 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3131 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3132 * invalidate is set, since we'll be writing the whole rectangle from our
3133 * temporary buffer back out.
3135 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3136 if (!intel_miptree_copy(brw
,
3137 mt
, level
, slice
, map
->x
, map
->y
,
3138 map
->linear_mt
, 0, 0, 0, 0,
3140 fprintf(stderr
, "Failed to blit\n");
3145 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3147 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3148 map
->x
, map
->y
, map
->w
, map
->h
,
3149 mt
, _mesa_get_format_name(mt
->format
),
3150 level
, slice
, map
->ptr
, map
->stride
);
3155 intel_miptree_release(&map
->linear_mt
);
3161 intel_miptree_unmap_blit(struct brw_context
*brw
,
3162 struct intel_mipmap_tree
*mt
,
3163 struct intel_miptree_map
*map
,
3167 struct gl_context
*ctx
= &brw
->ctx
;
3169 intel_miptree_unmap_raw(map
->linear_mt
);
3171 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3172 bool ok
= intel_miptree_copy(brw
,
3173 map
->linear_mt
, 0, 0, 0, 0,
3174 mt
, level
, slice
, map
->x
, map
->y
,
3176 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3179 intel_miptree_release(&map
->linear_mt
);
3183 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3185 #if defined(USE_SSE41)
3187 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3188 struct intel_mipmap_tree
*mt
,
3189 struct intel_miptree_map
*map
,
3190 unsigned int level
, unsigned int slice
)
3192 assert(map
->mode
& GL_MAP_READ_BIT
);
3193 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3195 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3196 map
->x
, map
->y
, map
->w
, map
->h
,
3197 mt
, _mesa_get_format_name(mt
->format
),
3198 level
, slice
, map
->ptr
, map
->stride
);
3200 /* Map the original image */
3203 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3207 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3213 src
+= image_y
* mt
->pitch
;
3214 src
+= image_x
* mt
->cpp
;
3216 /* Due to the pixel offsets for the particular image being mapped, our
3217 * src pointer may not be 16-byte aligned. However, if the pitch is
3218 * divisible by 16, then the amount by which it's misaligned will remain
3219 * consistent from row to row.
3221 assert((mt
->pitch
% 16) == 0);
3222 const int misalignment
= ((uintptr_t) src
) & 15;
3224 /* Create an untiled temporary buffer for the mapping. */
3225 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3227 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3229 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3230 /* Offset the destination so it has the same misalignment as src. */
3231 map
->ptr
= map
->buffer
+ misalignment
;
3233 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3235 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3236 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3237 void *src_ptr
= src
+ y
* mt
->pitch
;
3239 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3242 intel_miptree_unmap_raw(mt
);
3246 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3247 struct intel_mipmap_tree
*mt
,
3248 struct intel_miptree_map
*map
,
3252 _mesa_align_free(map
->buffer
);
3259 intel_miptree_map_s8(struct brw_context
*brw
,
3260 struct intel_mipmap_tree
*mt
,
3261 struct intel_miptree_map
*map
,
3262 unsigned int level
, unsigned int slice
)
3264 map
->stride
= map
->w
;
3265 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3269 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3270 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3271 * invalidate is set, since we'll be writing the whole rectangle from our
3272 * temporary buffer back out.
3274 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3275 uint8_t *untiled_s8_map
= map
->ptr
;
3276 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3277 unsigned int image_x
, image_y
;
3279 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3281 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3282 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3283 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3284 x
+ image_x
+ map
->x
,
3285 y
+ image_y
+ map
->y
,
3286 brw
->has_swizzling
);
3287 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3291 intel_miptree_unmap_raw(mt
);
3293 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3294 map
->x
, map
->y
, map
->w
, map
->h
,
3295 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3297 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3298 map
->x
, map
->y
, map
->w
, map
->h
,
3299 mt
, map
->ptr
, map
->stride
);
3304 intel_miptree_unmap_s8(struct brw_context
*brw
,
3305 struct intel_mipmap_tree
*mt
,
3306 struct intel_miptree_map
*map
,
3310 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3311 unsigned int image_x
, image_y
;
3312 uint8_t *untiled_s8_map
= map
->ptr
;
3313 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3315 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3317 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3318 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3319 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3320 image_x
+ x
+ map
->x
,
3321 image_y
+ y
+ map
->y
,
3322 brw
->has_swizzling
);
3323 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3327 intel_miptree_unmap_raw(mt
);
3334 intel_miptree_map_etc(struct brw_context
*brw
,
3335 struct intel_mipmap_tree
*mt
,
3336 struct intel_miptree_map
*map
,
3340 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3341 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3342 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3345 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3346 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3348 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3349 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3350 map
->w
, map
->h
, 1));
3351 map
->ptr
= map
->buffer
;
3355 intel_miptree_unmap_etc(struct brw_context
*brw
,
3356 struct intel_mipmap_tree
*mt
,
3357 struct intel_miptree_map
*map
,
3363 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3368 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3369 + image_y
* mt
->pitch
3370 + image_x
* mt
->cpp
;
3372 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3373 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3374 map
->ptr
, map
->stride
,
3377 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3378 map
->ptr
, map
->stride
,
3379 map
->w
, map
->h
, mt
->etc_format
);
3381 intel_miptree_unmap_raw(mt
);
3386 * Mapping function for packed depth/stencil miptrees backed by real separate
3387 * miptrees for depth and stencil.
3389 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3390 * separate from the depth buffer. Yet at the GL API level, we have to expose
3391 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3392 * be able to map that memory for texture storage and glReadPixels-type
3393 * operations. We give Mesa core that access by mallocing a temporary and
3394 * copying the data between the actual backing store and the temporary.
3397 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3398 struct intel_mipmap_tree
*mt
,
3399 struct intel_miptree_map
*map
,
3400 unsigned int level
, unsigned int slice
)
3402 struct intel_mipmap_tree
*z_mt
= mt
;
3403 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3404 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3405 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3407 map
->stride
= map
->w
* packed_bpp
;
3408 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3412 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3413 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3414 * invalidate is set, since we'll be writing the whole rectangle from our
3415 * temporary buffer back out.
3417 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3418 uint32_t *packed_map
= map
->ptr
;
3419 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3420 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3421 unsigned int s_image_x
, s_image_y
;
3422 unsigned int z_image_x
, z_image_y
;
3424 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3425 &s_image_x
, &s_image_y
);
3426 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3427 &z_image_x
, &z_image_y
);
3429 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3430 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3431 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3432 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3435 brw
->has_swizzling
);
3436 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3438 (map_x
+ z_image_x
));
3439 uint8_t s
= s_map
[s_offset
];
3440 uint32_t z
= z_map
[z_offset
];
3442 if (map_z32f_x24s8
) {
3443 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3444 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3446 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3451 intel_miptree_unmap_raw(s_mt
);
3452 intel_miptree_unmap_raw(z_mt
);
3454 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3456 map
->x
, map
->y
, map
->w
, map
->h
,
3457 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3458 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3459 map
->ptr
, map
->stride
);
3461 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3462 map
->x
, map
->y
, map
->w
, map
->h
,
3463 mt
, map
->ptr
, map
->stride
);
3468 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3469 struct intel_mipmap_tree
*mt
,
3470 struct intel_miptree_map
*map
,
3474 struct intel_mipmap_tree
*z_mt
= mt
;
3475 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3476 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3478 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3479 uint32_t *packed_map
= map
->ptr
;
3480 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3481 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3482 unsigned int s_image_x
, s_image_y
;
3483 unsigned int z_image_x
, z_image_y
;
3485 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3486 &s_image_x
, &s_image_y
);
3487 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3488 &z_image_x
, &z_image_y
);
3490 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3491 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3492 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3493 x
+ s_image_x
+ map
->x
,
3494 y
+ s_image_y
+ map
->y
,
3495 brw
->has_swizzling
);
3496 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3498 (x
+ z_image_x
+ map
->x
));
3500 if (map_z32f_x24s8
) {
3501 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3502 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3504 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3505 s_map
[s_offset
] = packed
>> 24;
3506 z_map
[z_offset
] = packed
;
3511 intel_miptree_unmap_raw(s_mt
);
3512 intel_miptree_unmap_raw(z_mt
);
3514 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3516 map
->x
, map
->y
, map
->w
, map
->h
,
3517 z_mt
, _mesa_get_format_name(z_mt
->format
),
3518 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3519 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3520 map
->ptr
, map
->stride
);
3527 * Create and attach a map to the miptree at (level, slice). Return the
3530 static struct intel_miptree_map
*
3531 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3540 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3545 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3546 mt
->level
[level
].slice
[slice
].map
= map
;
3558 * Release the map at (level, slice).
3561 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3565 struct intel_miptree_map
**map
;
3567 map
= &mt
->level
[level
].slice
[slice
].map
;
3573 can_blit_slice(struct intel_mipmap_tree
*mt
,
3574 unsigned int level
, unsigned int slice
)
3576 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3577 if (mt
->pitch
>= 32768)
3584 use_intel_mipree_map_blit(struct brw_context
*brw
,
3585 struct intel_mipmap_tree
*mt
,
3591 /* It's probably not worth swapping to the blit ring because of
3592 * all the overhead involved.
3594 !(mode
& GL_MAP_WRITE_BIT
) &&
3596 (mt
->tiling
== I915_TILING_X
||
3597 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3598 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3599 /* Fast copy blit on skl+ supports all tiling formats. */
3601 can_blit_slice(mt
, level
, slice
))
3604 if (mt
->tiling
!= I915_TILING_NONE
&&
3605 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3606 assert(can_blit_slice(mt
, level
, slice
));
3614 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3615 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3616 * arithmetic overflow.
3618 * If you call this function and use \a out_stride, then you're doing pointer
3619 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3620 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3621 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3622 * which usually have type uint32_t or GLuint.
3625 intel_miptree_map(struct brw_context
*brw
,
3626 struct intel_mipmap_tree
*mt
,
3635 ptrdiff_t *out_stride
)
3637 struct intel_miptree_map
*map
;
3639 assert(mt
->num_samples
<= 1);
3641 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3648 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3649 map
->mode
& GL_MAP_WRITE_BIT
);
3651 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3652 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3653 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3654 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3655 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3656 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3657 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3658 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3659 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3660 #if defined(USE_SSE41)
3661 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3662 !mt
->compressed
&& cpu_has_sse4_1
&&
3663 (mt
->pitch
% 16 == 0)) {
3664 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3667 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3670 *out_ptr
= map
->ptr
;
3671 *out_stride
= map
->stride
;
3673 if (map
->ptr
== NULL
)
3674 intel_miptree_release_map(mt
, level
, slice
);
3678 intel_miptree_unmap(struct brw_context
*brw
,
3679 struct intel_mipmap_tree
*mt
,
3683 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3685 assert(mt
->num_samples
<= 1);
3690 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3691 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3693 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3694 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3695 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3696 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3697 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3698 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3699 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3700 } else if (map
->linear_mt
) {
3701 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3702 #if defined(USE_SSE41)
3703 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3704 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3707 intel_miptree_unmap_gtt(mt
);
3710 intel_miptree_release_map(mt
, level
, slice
);
3714 get_isl_surf_dim(GLenum target
)
3718 case GL_TEXTURE_1D_ARRAY
:
3719 return ISL_SURF_DIM_1D
;
3722 case GL_TEXTURE_2D_ARRAY
:
3723 case GL_TEXTURE_RECTANGLE
:
3724 case GL_TEXTURE_CUBE_MAP
:
3725 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3726 case GL_TEXTURE_2D_MULTISAMPLE
:
3727 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3728 case GL_TEXTURE_EXTERNAL_OES
:
3729 return ISL_SURF_DIM_2D
;
3732 return ISL_SURF_DIM_3D
;
3735 unreachable("Invalid texture target");
3739 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3740 GLenum target
, enum miptree_array_layout array_layout
)
3742 if (array_layout
== GEN6_HIZ_STENCIL
)
3743 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3747 case GL_TEXTURE_1D_ARRAY
:
3748 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3749 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3752 case GL_TEXTURE_2D_ARRAY
:
3753 case GL_TEXTURE_RECTANGLE
:
3754 case GL_TEXTURE_2D_MULTISAMPLE
:
3755 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3756 case GL_TEXTURE_EXTERNAL_OES
:
3757 return ISL_DIM_LAYOUT_GEN4_2D
;
3759 case GL_TEXTURE_CUBE_MAP
:
3760 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3761 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3762 ISL_DIM_LAYOUT_GEN4_2D
);
3765 return (devinfo
->gen
>= 9 ?
3766 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3769 unreachable("Invalid texture target");
3773 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3775 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3776 return ISL_TILING_W
;
3778 switch (mt
->tiling
) {
3779 case I915_TILING_NONE
:
3780 return ISL_TILING_LINEAR
;
3782 return ISL_TILING_X
;
3784 return ISL_TILING_Y0
;
3786 unreachable("Invalid tiling mode");
3792 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3793 const struct intel_mipmap_tree
*mt
,
3794 struct isl_surf
*surf
)
3796 surf
->dim
= get_isl_surf_dim(mt
->target
);
3797 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3798 mt
->tiling
, mt
->target
,
3801 if (mt
->num_samples
> 1) {
3802 switch (mt
->msaa_layout
) {
3803 case INTEL_MSAA_LAYOUT_IMS
:
3804 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3806 case INTEL_MSAA_LAYOUT_UMS
:
3807 case INTEL_MSAA_LAYOUT_CMS
:
3808 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3811 unreachable("Invalid MSAA layout");
3814 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3817 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3819 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3820 /* The ISL definition of row_pitch matches the surface state pitch field
3821 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3822 * the factor of 2 for W-tiling in row_pitch.
3824 surf
->row_pitch
= 2 * mt
->pitch
;
3826 surf
->row_pitch
= mt
->pitch
;
3829 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3831 if (brw
->gen
>= 9) {
3832 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3833 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3834 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3836 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3837 * alignment in terms of surface elements like we want.
3839 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3842 /* On earlier gens it's stored in pixels. */
3844 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3845 surf
->image_alignment_el
=
3846 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3849 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3850 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3851 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3852 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3853 surf
->logical_level0_px
.array_len
= 1;
3855 surf
->logical_level0_px
.depth
= 1;
3856 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3859 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3860 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3861 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3862 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3863 surf
->phys_level0_sa
.array_len
= 1;
3865 surf
->phys_level0_sa
.depth
= 1;
3866 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3869 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3870 surf
->samples
= MAX2(mt
->num_samples
, 1);
3872 surf
->size
= 0; /* TODO */
3873 surf
->alignment
= 0; /* TODO */
3875 switch (surf
->dim_layout
) {
3876 case ISL_DIM_LAYOUT_GEN4_2D
:
3877 case ISL_DIM_LAYOUT_GEN4_3D
:
3878 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3879 if (brw
->gen
>= 9) {
3880 surf
->array_pitch_el_rows
= mt
->qpitch
;
3883 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3884 assert(mt
->qpitch
% bh
== 0);
3885 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3888 case ISL_DIM_LAYOUT_GEN9_1D
:
3889 surf
->array_pitch_el_rows
= 1;
3893 switch (mt
->array_layout
) {
3894 case ALL_LOD_IN_EACH_SLICE
:
3895 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3897 case ALL_SLICES_AT_EACH_LOD
:
3898 case GEN6_HIZ_STENCIL
:
3899 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3902 unreachable("Invalid array layout");
3905 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3906 switch (base_format
) {
3907 case GL_DEPTH_COMPONENT
:
3908 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3910 case GL_STENCIL_INDEX
:
3911 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3913 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3915 case GL_DEPTH_STENCIL
:
3916 /* In this case we only texture from the depth part */
3917 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3918 ISL_SURF_USAGE_TEXTURE_BIT
;
3921 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3922 if (brw
->format_supported_as_render_target
[mt
->format
])
3923 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3927 if (_mesa_is_cube_map_texture(mt
->target
))
3928 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3931 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3932 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3933 * PASS IT INTO isl_surf_fill_state.
3936 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3937 const struct intel_mipmap_tree
*mt
,
3938 struct isl_surf
*surf
,
3939 enum isl_aux_usage
*usage
)
3941 uint32_t aux_pitch
, aux_qpitch
;
3943 aux_pitch
= mt
->mcs_buf
->pitch
;
3944 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3946 if (mt
->num_samples
> 1) {
3947 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3948 *usage
= ISL_AUX_USAGE_MCS
;
3949 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3950 assert(brw
->gen
>= 9);
3951 *usage
= ISL_AUX_USAGE_CCS_E
;
3952 } else if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0) {
3953 *usage
= ISL_AUX_USAGE_CCS_D
;
3955 unreachable("Invalid MCS miptree");
3957 } else if (mt
->hiz_buf
) {
3958 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3959 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3961 *usage
= ISL_AUX_USAGE_HIZ
;
3963 *usage
= ISL_AUX_USAGE_NONE
;
3967 /* Start with a copy of the original surface. */
3968 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3970 /* Figure out the format and tiling of the auxiliary surface */
3972 case ISL_AUX_USAGE_NONE
:
3973 unreachable("Invalid auxiliary usage");
3975 case ISL_AUX_USAGE_HIZ
:
3976 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3979 case ISL_AUX_USAGE_MCS
:
3982 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3983 * HALIGN 16 must be used."
3986 assert(mt
->halign
== 16);
3988 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3991 case ISL_AUX_USAGE_CCS_D
:
3992 case ISL_AUX_USAGE_CCS_E
:
3994 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3996 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3998 * From the hardware spec for GEN9:
4000 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
4001 * HALIGN 16 must be used."
4003 assert(mt
->num_samples
<= 1);
4005 assert(mt
->halign
== 16);
4007 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
4011 /* We want the pitch of the actual aux buffer. */
4012 surf
->row_pitch
= aux_pitch
;
4014 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
4015 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
4016 * in elements of the primary color surface so we have to divide by the
4017 * compression block height.
4019 surf
->array_pitch_el_rows
=
4020 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;