2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
,
125 enum isl_tiling tiling
)
127 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
128 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
130 * - Support is limited to tiled render targets.
132 * Gen9 changes the restriction to Y-tile only.
135 return tiling
== ISL_TILING_Y0
;
136 else if (brw
->gen
>= 7)
137 return tiling
!= ISL_TILING_LINEAR
;
143 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
144 * can be used. This doesn't (and should not) inspect any of the properties of
147 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
148 * beneath the "Fast Color Clear" bullet (p326):
150 * - Support is for non-mip-mapped and non-array surface types only.
152 * And then later, on p327:
154 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
157 * From the Skylake documentation, it is made clear that X-tiling is no longer
160 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
164 intel_miptree_supports_ccs(struct brw_context
*brw
,
165 const struct intel_mipmap_tree
*mt
)
167 /* MCS support does not exist prior to Gen7 */
171 /* This function applies only to non-multisampled render targets. */
172 if (mt
->surf
.samples
> 1)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
186 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
187 const bool arrayed
= mt
->physical_depth0
!= 1;
190 /* Multisample surfaces with the CMS layout are not layered surfaces,
191 * yet still have physical_depth0 > 1. Assert that we don't
192 * accidentally reject a multisampled surface here. We should have
193 * rejected it earlier by explicitly checking the sample count.
195 assert(mt
->surf
.samples
== 1);
198 /* Handle the hardware restrictions...
200 * All GENs have the following restriction: "MCS buffer for non-MSRT is
201 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
203 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
204 * Non-MultiSampler Render Target Restrictions) Support is for
205 * non-mip-mapped and non-array surface types only.
207 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
208 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
209 * surfaces are supported with MCS buffer layout with these alignments in
210 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
212 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
213 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
214 * surfaces are supported with MCS buffer layout with these alignments in
215 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
217 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
220 /* There's no point in using an MCS buffer if the surface isn't in a
223 if (!brw
->mesa_format_supports_render
[mt
->format
])
227 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
228 const enum isl_format isl_format
=
229 brw_isl_format_for_mesa_format(linear_format
);
230 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
236 intel_tiling_supports_hiz(const struct brw_context
*brw
,
237 enum isl_tiling tiling
)
242 return tiling
== ISL_TILING_Y0
;
246 intel_miptree_supports_hiz(const struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
252 switch (mt
->format
) {
253 case MESA_FORMAT_Z_FLOAT32
:
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
256 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
257 case MESA_FORMAT_Z_UNORM16
:
265 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
266 const struct intel_mipmap_tree
*mt
)
268 /* For now compression is only enabled for integer formats even though
269 * there exist supported floating point formats also. This is a heuristic
270 * decision based on current public benchmarks. In none of the cases these
271 * formats provided any improvement but a few cases were seen to regress.
272 * Hence these are left to to be enabled in the future when they are known
275 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
278 if (!intel_miptree_supports_ccs(brw
, mt
))
281 /* Fast clear can be also used to clear srgb surfaces by using equivalent
282 * linear format. This trick, however, can't be extended to be used with
283 * lossless compression and therefore a check is needed to see if the format
286 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
290 * Determine depth format corresponding to a depth+stencil format,
291 * for separate stencil.
294 intel_depth_format_for_depthstencil_format(mesa_format format
) {
296 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
297 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
298 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
299 return MESA_FORMAT_Z_FLOAT32
;
306 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
307 unsigned depth0
, struct intel_mipmap_level
*table
)
309 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
311 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
313 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
314 if (!table
[level
].slice
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++)
322 free(table
[level
].slice
);
328 needs_separate_stencil(const struct brw_context
*brw
,
329 struct intel_mipmap_tree
*mt
,
330 mesa_format format
, uint32_t layout_flags
)
333 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
336 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
339 if (brw
->must_use_separate_stencil
)
342 return brw
->has_separate_stencil
&&
343 intel_miptree_supports_hiz(brw
, mt
);
347 * @param for_bo Indicates that the caller is
348 * intel_miptree_create_for_bo(). If true, then do not create
351 static struct intel_mipmap_tree
*
352 intel_miptree_create_layout(struct brw_context
*brw
,
361 uint32_t layout_flags
)
363 assert(num_samples
> 0);
365 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
369 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
370 _mesa_enum_to_string(target
),
371 _mesa_get_format_name(format
),
372 first_level
, last_level
, depth0
, mt
);
374 if (target
== GL_TEXTURE_1D_ARRAY
)
375 assert(height0
== 1);
379 mt
->first_level
= first_level
;
380 mt
->last_level
= last_level
;
381 mt
->logical_width0
= width0
;
382 mt
->logical_height0
= height0
;
383 mt
->logical_depth0
= depth0
;
384 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
385 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
386 mt
->supports_fast_clear
= false;
387 mt
->aux_state
= NULL
;
388 mt
->cpp
= _mesa_get_format_bytes(format
);
389 mt
->surf
.samples
= num_samples
;
390 mt
->compressed
= _mesa_is_format_compressed(format
);
391 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
394 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
395 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
397 int depth_multiply
= 1;
398 if (num_samples
> 1) {
399 /* Adjust width/height/depth for MSAA */
400 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
401 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
402 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
403 * "If the surface is multisampled and it is a depth or stencil
404 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
405 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
408 * +----------------------------------------------------------------+
409 * | Num Multisamples | W_l = | H_l = |
410 * +----------------------------------------------------------------+
411 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
412 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
413 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
414 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
415 * +----------------------------------------------------------------+
418 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
419 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
420 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
422 * Another more complicated explanation for these adjustments comes
423 * from the Sandybridge PRM, volume 4, part 1, page 31:
425 * "Any of the other messages (sample*, LOD, load4) used with a
426 * (4x) multisampled surface will in-effect sample a surface with
427 * double the height and width as that indicated in the surface
428 * state. Each pixel position on the original-sized surface is
429 * replaced with a 2x2 of samples with the following arrangement:
434 * Thus, when sampling from a multisampled texture, it behaves as
435 * though the layout in memory for (x,y,sample) is:
437 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
438 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
440 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
441 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
443 * However, the actual layout of multisampled data in memory is:
445 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
446 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
448 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
449 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
451 * This pattern repeats for each 2x2 pixel block.
453 * As a result, when calculating the size of our 4-sample buffer for
454 * an odd width or height, we have to align before scaling up because
455 * sample 3 is in that bottom right 2x2 block.
457 switch (num_samples
) {
459 assert(brw
->gen
>= 8);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2);
464 width0
= ALIGN(width0
, 2) * 2;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 2;
472 width0
= ALIGN(width0
, 2) * 4;
473 height0
= ALIGN(height0
, 2) * 4;
476 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
479 unreachable("not reached");
482 /* Non-interleaved */
483 depth_multiply
= num_samples
;
484 depth0
*= depth_multiply
;
488 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->surf
.msaa_layout
) {
508 case ISL_MSAA_LAYOUT_NONE
:
509 case ISL_MSAA_LAYOUT_INTERLEAVED
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case ISL_MSAA_LAYOUT_ARRAY
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
519 assert(depth0
== 6 * depth_multiply
);
521 mt
->physical_width0
= width0
;
522 mt
->physical_height0
= height0
;
523 mt
->physical_depth0
= depth0
;
525 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
)) {
526 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
528 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
531 mt
->stencil_mt
= intel_miptree_create(brw
,
542 if (!mt
->stencil_mt
) {
543 intel_miptree_release(&mt
);
546 mt
->stencil_mt
->r8stencil_needs_update
= true;
548 /* Fix up the Z miptree format for how we're splitting out separate
549 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
551 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
554 if (format
== mt
->format
) {
555 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
556 _mesa_get_format_name(mt
->format
));
560 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
561 mt
->array_layout
= GEN6_HIZ_STENCIL
;
564 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
565 * multisampled or have an AUX buffer attached to it.
567 * GEN | MSRT | AUX_CCS_* or AUX_MCS
568 * -------------------------------------------
569 * 9 | HALIGN_16 | HALIGN_16
570 * 8 | HALIGN_ANY | HALIGN_16
574 if (intel_miptree_supports_ccs(brw
, mt
)) {
575 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
576 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
577 } else if (brw
->gen
>= 9 && num_samples
> 1) {
578 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
580 const UNUSED
bool is_lossless_compressed_aux
=
581 brw
->gen
>= 9 && num_samples
== 1 &&
582 mt
->format
== MESA_FORMAT_R_UINT32
;
584 /* For now, nothing else has this requirement */
585 assert(is_lossless_compressed_aux
||
586 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
589 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
590 intel_miptree_release(&mt
);
599 * Choose the aux usage for this miptree. This function must be called fairly
600 * late in the miptree create process after we have a tiling.
603 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
604 struct intel_mipmap_tree
*mt
)
606 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
608 const unsigned no_flags
= 0;
609 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
610 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
611 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
612 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
613 intel_miptree_supports_ccs(brw
, mt
)) {
614 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
615 brw
->gen
>= 9 && !mt
->is_scanout
&&
616 intel_miptree_supports_ccs_e(brw
, mt
)) {
617 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
619 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
621 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
622 intel_miptree_supports_hiz(brw
, mt
)) {
623 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
626 /* We can do fast-clear on all auxiliary surface types that are
627 * allocated through the normal texture creation paths.
629 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
630 mt
->supports_fast_clear
= true;
635 * Choose an appropriate uncompressed format for a requested
636 * compressed format, if unsupported.
639 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
641 /* No need to lower ETC formats on these platforms,
642 * they are supported natively.
644 if (brw
->gen
>= 8 || brw
->is_baytrail
)
648 case MESA_FORMAT_ETC1_RGB8
:
649 return MESA_FORMAT_R8G8B8X8_UNORM
;
650 case MESA_FORMAT_ETC2_RGB8
:
651 return MESA_FORMAT_R8G8B8X8_UNORM
;
652 case MESA_FORMAT_ETC2_SRGB8
:
653 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
654 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
655 return MESA_FORMAT_B8G8R8A8_SRGB
;
656 case MESA_FORMAT_ETC2_RGBA8_EAC
:
657 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
658 return MESA_FORMAT_R8G8B8A8_UNORM
;
659 case MESA_FORMAT_ETC2_R11_EAC
:
660 return MESA_FORMAT_R_UNORM16
;
661 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
662 return MESA_FORMAT_R_SNORM16
;
663 case MESA_FORMAT_ETC2_RG11_EAC
:
664 return MESA_FORMAT_R16G16_UNORM
;
665 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
666 return MESA_FORMAT_R16G16_SNORM
;
668 /* Non ETC1 / ETC2 format */
673 /** \brief Assert that the level and layer are valid for the miptree. */
675 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
683 assert(level
>= mt
->first_level
);
684 assert(level
<= mt
->last_level
);
686 if (mt
->surf
.size
> 0)
687 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
688 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
689 mt
->surf
.phys_level0_sa
.array_len
));
691 assert(layer
< mt
->level
[level
].depth
);
694 static enum isl_aux_state
**
695 create_aux_state_map(struct intel_mipmap_tree
*mt
,
696 enum isl_aux_state initial
)
698 const uint32_t levels
= mt
->last_level
+ 1;
700 uint32_t total_slices
= 0;
701 for (uint32_t level
= 0; level
< levels
; level
++)
702 total_slices
+= mt
->level
[level
].depth
;
704 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
706 /* We're going to allocate a single chunk of data for both the per-level
707 * reference array and the arrays of aux_state. This makes cleanup
708 * significantly easier.
710 const size_t total_size
= per_level_array_size
+
711 total_slices
* sizeof(enum isl_aux_state
);
712 void *data
= malloc(total_size
);
716 enum isl_aux_state
**per_level_arr
= data
;
717 enum isl_aux_state
*s
= data
+ per_level_array_size
;
718 for (uint32_t level
= 0; level
< levels
; level
++) {
719 per_level_arr
[level
] = s
;
720 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
723 assert((void *)s
== data
+ total_size
);
725 return per_level_arr
;
729 free_aux_state_map(enum isl_aux_state
**state
)
734 static struct intel_mipmap_tree
*
735 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
736 unsigned first_level
, unsigned last_level
,
737 unsigned width0
, unsigned height0
, unsigned depth0
,
738 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
739 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
740 unsigned row_pitch
, struct brw_bo
*bo
)
742 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
746 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
754 if (target
== GL_TEXTURE_CUBE_MAP
||
755 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
756 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
758 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
760 _mesa_enum_to_string(target
),
761 _mesa_get_format_name(format
),
762 num_samples
, width0
, height0
, depth0
,
763 first_level
, last_level
, mt
);
765 struct isl_surf_init_info init_info
= {
766 .dim
= get_isl_surf_dim(target
),
767 .format
= translate_tex_format(brw
, format
, false),
770 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
771 .levels
= last_level
- first_level
+ 1,
772 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
773 .samples
= num_samples
,
774 .row_pitch
= row_pitch
,
775 .usage
= isl_usage_flags
,
776 .tiling_flags
= tiling_flags
,
779 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
782 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
785 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
787 isl_tiling_to_i915_tiling(
789 mt
->surf
.row_pitch
, alloc_flags
);
796 mt
->first_level
= first_level
;
797 mt
->last_level
= last_level
;
800 mt
->aux_state
= NULL
;
801 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
806 intel_miptree_release(&mt
);
810 static struct intel_mipmap_tree
*
811 miptree_create(struct brw_context
*brw
,
820 uint32_t layout_flags
)
822 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
823 return make_surface(brw
, target
, format
, first_level
, last_level
,
824 width0
, height0
, depth0
, num_samples
,
826 ISL_SURF_USAGE_STENCIL_BIT
|
827 ISL_SURF_USAGE_TEXTURE_BIT
,
828 BO_ALLOC_FOR_RENDER
, 0, NULL
);
830 struct intel_mipmap_tree
*mt
;
831 mesa_format tex_format
= format
;
832 mesa_format etc_format
= MESA_FORMAT_NONE
;
833 uint32_t alloc_flags
= 0;
835 format
= intel_lower_compressed_format(brw
, format
);
837 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
839 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
840 mt
= intel_miptree_create_layout(brw
, target
, format
,
841 first_level
, last_level
, width0
,
842 height0
, depth0
, num_samples
,
847 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
848 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
850 mt
->etc_format
= etc_format
;
852 if (format
== MESA_FORMAT_S_UINT8
) {
853 /* Align to size of W tile, 64x64. */
854 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
855 ALIGN(mt
->total_width
, 64),
856 ALIGN(mt
->total_height
, 64),
858 isl_tiling_to_i915_tiling(
863 /* The stencil buffer has quirky pitch requirements. From the
864 * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
865 * dword 1 bits 16:0 - Surface Pitch):
867 * The pitch must be set to 2x the value computed based on width, as
868 * the stencil buffer is stored with two rows interleaved.
870 * While the Ivybridge PRM lacks this comment, the BSpec contains the
871 * same text, and experiments indicate that this is necessary.
873 mt
->surf
.row_pitch
*= 2;
875 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
876 mt
->total_width
, mt
->total_height
,
878 isl_tiling_to_i915_tiling(
884 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
885 mt
->bo
->cache_coherent
= false;
887 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
888 intel_miptree_choose_aux_usage(brw
, mt
);
893 struct intel_mipmap_tree
*
894 intel_miptree_create(struct brw_context
*brw
,
903 uint32_t layout_flags
)
905 assert(num_samples
> 0);
907 struct intel_mipmap_tree
*mt
= miptree_create(
909 first_level
, last_level
,
910 width0
, height0
, depth0
, num_samples
,
915 /* If the BO is too large to fit in the aperture, we need to use the
916 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
917 * handle Y-tiling, so we need to fall back to X.
919 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
920 mt
->surf
.tiling
== ISL_TILING_Y0
) {
921 const uint32_t alloc_flags
=
922 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
923 BO_ALLOC_FOR_RENDER
: 0;
924 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
925 mt
->total_width
, mt
->total_height
);
927 mt
->surf
.tiling
= ISL_TILING_X
;
928 brw_bo_unreference(mt
->bo
);
929 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
930 mt
->total_width
, mt
->total_height
, mt
->cpp
,
931 isl_tiling_to_i915_tiling(
933 &mt
->surf
.row_pitch
, alloc_flags
);
939 intel_miptree_release(&mt
);
943 if (!intel_miptree_alloc_aux(brw
, mt
)) {
944 intel_miptree_release(&mt
);
951 struct intel_mipmap_tree
*
952 intel_miptree_create_for_bo(struct brw_context
*brw
,
960 uint32_t layout_flags
)
962 struct intel_mipmap_tree
*mt
;
963 uint32_t tiling
, swizzle
;
964 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
966 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
967 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
968 0, 0, width
, height
, depth
, 1,
970 ISL_SURF_USAGE_STENCIL_BIT
|
971 ISL_SURF_USAGE_TEXTURE_BIT
,
972 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
976 assert(bo
->size
>= mt
->surf
.size
);
978 brw_bo_reference(bo
);
982 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
984 /* Nothing will be able to use this miptree with the BO if the offset isn't
987 if (tiling
!= I915_TILING_NONE
)
988 assert(offset
% 4096 == 0);
990 /* miptrees can't handle negative pitch. If you need flipping of images,
991 * that's outside of the scope of the mt.
995 /* The BO already has a tiling format and we shouldn't confuse the lower
996 * layers by making it try to find a tiling format again.
998 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
999 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
1001 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
1002 mt
= intel_miptree_create_layout(brw
, target
, format
,
1004 width
, height
, depth
,
1005 1 /* num_samples */,
1010 brw_bo_reference(bo
);
1012 mt
->surf
.row_pitch
= pitch
;
1013 mt
->offset
= offset
;
1014 mt
->surf
.tiling
= isl_tiling_from_i915_tiling(tiling
);
1016 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1017 intel_miptree_choose_aux_usage(brw
, mt
);
1022 static struct intel_mipmap_tree
*
1023 miptree_create_for_planar_image(struct brw_context
*brw
,
1024 __DRIimage
*image
, GLenum target
)
1026 struct intel_image_format
*f
= image
->planar_format
;
1027 struct intel_mipmap_tree
*planar_mt
= NULL
;
1029 for (int i
= 0; i
< f
->nplanes
; i
++) {
1030 const int index
= f
->planes
[i
].buffer_index
;
1031 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1032 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1033 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1034 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1036 /* Disable creation of the texture's aux buffers because the driver
1037 * exposes no EGL API to manage them. That is, there is no API for
1038 * resolving the aux buffer's content to the main buffer nor for
1039 * invalidating the aux buffer's content.
1041 struct intel_mipmap_tree
*mt
=
1042 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1043 image
->offsets
[index
],
1045 image
->strides
[index
],
1046 MIPTREE_LAYOUT_DISABLE_AUX
);
1050 mt
->target
= target
;
1055 planar_mt
->plane
[i
- 1] = mt
;
1061 struct intel_mipmap_tree
*
1062 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1063 __DRIimage
*image
, GLenum target
,
1064 enum isl_colorspace colorspace
,
1065 bool is_winsys_image
)
1067 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1068 assert(colorspace
== ISL_COLORSPACE_NONE
||
1069 colorspace
== ISL_COLORSPACE_YUV
);
1070 return miptree_create_for_planar_image(brw
, image
, target
);
1073 mesa_format format
= image
->format
;
1074 switch (colorspace
) {
1075 case ISL_COLORSPACE_NONE
:
1076 /* Keep the image format unmodified */
1079 case ISL_COLORSPACE_LINEAR
:
1080 format
=_mesa_get_srgb_format_linear(format
);
1083 case ISL_COLORSPACE_SRGB
:
1084 format
=_mesa_get_linear_format_srgb(format
);
1088 unreachable("Inalid colorspace for non-planar image");
1091 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1092 /* The texture storage paths in core Mesa detect if the driver does not
1093 * support the user-requested format, and then searches for a
1094 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1095 * do the fallbacks here for important formats.
1097 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1098 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1099 * the Chrome OS compositor consumes as dma_buf EGLImages.
1101 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1104 if (!brw
->ctx
.TextureFormatSupported
[format
])
1107 /* If this image comes in from a window system, we have different
1108 * requirements than if it comes in via an EGL import operation. Window
1109 * system images can use any form of auxiliary compression we wish because
1110 * they get "flushed" before being handed off to the window system and we
1111 * have the opportunity to do resolves. Window system buffers also may be
1112 * used for scanout so we need to flag that appropriately.
1114 const uint32_t mt_layout_flags
=
1115 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1117 /* Disable creation of the texture's aux buffers because the driver exposes
1118 * no EGL API to manage them. That is, there is no API for resolving the aux
1119 * buffer's content to the main buffer nor for invalidating the aux buffer's
1122 struct intel_mipmap_tree
*mt
=
1123 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1124 image
->offset
, image
->width
, image
->height
, 1,
1125 image
->pitch
, mt_layout_flags
);
1129 mt
->target
= target
;
1130 mt
->level
[0].level_x
= image
->tile_x
;
1131 mt
->level
[0].level_y
= image
->tile_y
;
1132 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1133 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1135 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1136 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1137 * trouble resolving back to destination image due to alignment issues.
1139 if (!brw
->has_surface_tile_offset
) {
1140 uint32_t draw_x
, draw_y
;
1141 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1143 if (draw_x
!= 0 || draw_y
!= 0) {
1144 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1145 intel_miptree_release(&mt
);
1150 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1151 intel_miptree_release(&mt
);
1159 * For a singlesample renderbuffer, this simply wraps the given BO with a
1162 * For a multisample renderbuffer, this wraps the window system's
1163 * (singlesample) BO with a singlesample miptree attached to the
1164 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1165 * that will contain the actual rendering (which is lazily resolved to
1166 * irb->singlesample_mt).
1169 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1170 struct intel_renderbuffer
*irb
,
1171 struct intel_mipmap_tree
*singlesample_mt
,
1172 uint32_t width
, uint32_t height
,
1175 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1176 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1177 mesa_format format
= rb
->Format
;
1178 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1180 /* Only the front and back buffers, which are color buffers, are allocated
1181 * through the image loader.
1183 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1184 _mesa_get_format_base_format(format
) == GL_RGBA
);
1186 assert(singlesample_mt
);
1188 if (num_samples
== 1) {
1189 intel_miptree_release(&irb
->mt
);
1190 irb
->mt
= singlesample_mt
;
1192 assert(!irb
->singlesample_mt
);
1194 intel_miptree_release(&irb
->singlesample_mt
);
1195 irb
->singlesample_mt
= singlesample_mt
;
1198 irb
->mt
->logical_width0
!= width
||
1199 irb
->mt
->logical_height0
!= height
) {
1200 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1205 if (!multisample_mt
)
1208 irb
->need_downsample
= false;
1209 intel_miptree_release(&irb
->mt
);
1210 irb
->mt
= multisample_mt
;
1216 intel_miptree_release(&irb
->mt
);
1220 struct intel_mipmap_tree
*
1221 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1225 uint32_t num_samples
)
1227 struct intel_mipmap_tree
*mt
;
1229 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1230 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1231 MIPTREE_LAYOUT_TILING_ANY
|
1232 MIPTREE_LAYOUT_FOR_SCANOUT
;
1234 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1235 width
, height
, depth
, num_samples
,
1243 intel_miptree_release(&mt
);
1248 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1249 struct intel_mipmap_tree
*src
)
1254 intel_miptree_release(dst
);
1258 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1265 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1267 if (aux_buf
== NULL
)
1270 brw_bo_unreference(aux_buf
->bo
);
1276 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1281 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1282 if (--(*mt
)->refcount
<= 0) {
1285 DBG("%s deleting %p\n", __func__
, *mt
);
1287 brw_bo_unreference((*mt
)->bo
);
1288 intel_miptree_release(&(*mt
)->stencil_mt
);
1289 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1290 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1291 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1292 free_aux_state_map((*mt
)->aux_state
);
1294 intel_miptree_release(&(*mt
)->plane
[0]);
1295 intel_miptree_release(&(*mt
)->plane
[1]);
1297 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1298 free((*mt
)->level
[i
].slice
);
1308 intel_get_image_dims(struct gl_texture_image
*image
,
1309 int *width
, int *height
, int *depth
)
1311 switch (image
->TexObject
->Target
) {
1312 case GL_TEXTURE_1D_ARRAY
:
1313 /* For a 1D Array texture the OpenGL API will treat the image height as
1314 * the number of array slices. For Intel hardware, we treat the 1D array
1315 * as a 2D Array with a height of 1. So, here we want to swap image
1318 assert(image
->Depth
== 1);
1319 *width
= image
->Width
;
1321 *depth
= image
->Height
;
1323 case GL_TEXTURE_CUBE_MAP
:
1324 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1325 * though we really have 6 slices.
1327 assert(image
->Depth
== 1);
1328 *width
= image
->Width
;
1329 *height
= image
->Height
;
1333 *width
= image
->Width
;
1334 *height
= image
->Height
;
1335 *depth
= image
->Depth
;
1341 * Can the image be pulled into a unified mipmap tree? This mirrors
1342 * the completeness test in a lot of ways.
1344 * Not sure whether I want to pass gl_texture_image here.
1347 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1348 struct gl_texture_image
*image
)
1350 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1351 GLuint level
= intelImage
->base
.Base
.Level
;
1352 int width
, height
, depth
;
1354 /* glTexImage* choose the texture object based on the target passed in, and
1355 * objects can't change targets over their lifetimes, so this should be
1358 assert(image
->TexObject
->Target
== mt
->target
);
1360 mesa_format mt_format
= mt
->format
;
1361 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1362 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1363 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1364 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1365 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1366 mt_format
= mt
->etc_format
;
1368 if (image
->TexFormat
!= mt_format
)
1371 intel_get_image_dims(image
, &width
, &height
, &depth
);
1373 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1376 if (mt
->surf
.size
> 0) {
1377 if (level
>= mt
->surf
.levels
)
1380 const unsigned level_depth
=
1381 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1382 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1383 mt
->surf
.logical_level0_px
.array_len
;
1385 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1386 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1387 depth
== level_depth
&&
1388 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1391 int level_depth
= mt
->level
[level
].depth
;
1392 if (mt
->surf
.samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1393 level_depth
/= mt
->surf
.samples
;
1395 /* Test image dimensions against the base level image adjusted for
1396 * minification. This will also catch images not present in the
1397 * tree, changed targets, etc.
1399 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1400 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1401 depth
!= level_depth
) {
1405 /* Core uses sample number of zero to indicate single-sampled. */
1406 if (MAX2(image
->NumSamples
, 1) != mt
->surf
.samples
)
1414 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1416 GLuint x
, GLuint y
, GLuint d
)
1418 mt
->level
[level
].depth
= d
;
1419 mt
->level
[level
].level_x
= x
;
1420 mt
->level
[level
].level_y
= y
;
1422 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1425 assert(mt
->level
[level
].slice
);
1427 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1428 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1433 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1434 GLuint level
, GLuint img
,
1437 if (img
== 0 && level
== 0)
1438 assert(x
== 0 && y
== 0);
1440 assert(img
< mt
->level
[level
].depth
);
1442 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1443 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1445 DBG("%s level %d img %d pos %d,%d\n",
1446 __func__
, level
, img
,
1447 mt
->level
[level
].slice
[img
].x_offset
,
1448 mt
->level
[level
].slice
[img
].y_offset
);
1452 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1453 GLuint level
, GLuint slice
,
1454 GLuint
*x
, GLuint
*y
)
1456 if (level
== 0 && slice
== 0) {
1457 *x
= mt
->level
[0].level_x
;
1458 *y
= mt
->level
[0].level_y
;
1462 if (mt
->surf
.size
> 0) {
1463 uint32_t x_offset_sa
, y_offset_sa
;
1465 /* Miptree itself can have an offset only if it represents a single
1466 * slice in an imported buffer object.
1467 * See intel_miptree_create_for_dri_image().
1469 assert(mt
->level
[0].level_x
== 0);
1470 assert(mt
->level
[0].level_y
== 0);
1472 /* Given level is relative to level zero while the miptree may be
1473 * represent just a subset of all levels starting from 'first_level'.
1475 assert(level
>= mt
->first_level
);
1476 level
-= mt
->first_level
;
1478 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1479 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1480 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1481 &x_offset_sa
, &y_offset_sa
);
1488 assert(slice
< mt
->level
[level
].depth
);
1490 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1491 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1496 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1497 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1498 * and tile_h is set to 1.
1501 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1502 uint32_t *tile_w
, uint32_t *tile_h
)
1513 case ISL_TILING_LINEAR
:
1518 unreachable("not reached");
1524 * This function computes masks that may be used to select the bits of the X
1525 * and Y coordinates that indicate the offset within a tile. If the BO is
1526 * untiled, the masks are set to 0.
1529 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1530 uint32_t *mask_x
, uint32_t *mask_y
)
1532 uint32_t tile_w_bytes
, tile_h
;
1534 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1536 *mask_x
= tile_w_bytes
/ cpp
- 1;
1537 *mask_y
= tile_h
- 1;
1541 * Compute the offset (in bytes) from the start of the BO to the given x
1542 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1543 * multiples of the tile size.
1546 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1547 uint32_t x
, uint32_t y
)
1550 uint32_t pitch
= mt
->surf
.row_pitch
;
1552 switch (mt
->surf
.tiling
) {
1554 unreachable("not reached");
1555 case ISL_TILING_LINEAR
:
1556 return y
* pitch
+ x
* cpp
;
1558 assert((x
% (512 / cpp
)) == 0);
1559 assert((y
% 8) == 0);
1560 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1562 assert((x
% (128 / cpp
)) == 0);
1563 assert((y
% 32) == 0);
1564 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1569 * Rendering with tiled buffers requires that the base address of the buffer
1570 * be aligned to a page boundary. For renderbuffers, and sometimes with
1571 * textures, we may want the surface to point at a texture image level that
1572 * isn't at a page boundary.
1574 * This function returns an appropriately-aligned base offset
1575 * according to the tiling restrictions, plus any required x/y offset
1579 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1580 GLuint level
, GLuint slice
,
1585 uint32_t mask_x
, mask_y
;
1587 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1588 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1590 *tile_x
= x
& mask_x
;
1591 *tile_y
= y
& mask_y
;
1593 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1597 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1598 struct intel_mipmap_tree
*src_mt
,
1599 unsigned src_level
, unsigned src_layer
,
1600 struct intel_mipmap_tree
*dst_mt
,
1601 unsigned dst_level
, unsigned dst_layer
,
1602 unsigned width
, unsigned height
)
1605 ptrdiff_t src_stride
, dst_stride
;
1606 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1607 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1609 intel_miptree_map(brw
, src_mt
,
1610 src_level
, src_layer
,
1613 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1616 intel_miptree_map(brw
, dst_mt
,
1617 dst_level
, dst_layer
,
1620 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1624 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1625 _mesa_get_format_name(src_mt
->format
),
1626 src_mt
, src
, src_stride
,
1627 _mesa_get_format_name(dst_mt
->format
),
1628 dst_mt
, dst
, dst_stride
,
1631 int row_size
= cpp
* width
;
1632 if (src_stride
== row_size
&&
1633 dst_stride
== row_size
) {
1634 memcpy(dst
, src
, row_size
* height
);
1636 for (int i
= 0; i
< height
; i
++) {
1637 memcpy(dst
, src
, row_size
);
1643 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1644 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1646 /* Don't forget to copy the stencil data over, too. We could have skipped
1647 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1648 * shuffling the two data sources in/out of temporary storage instead of
1649 * the direct mapping we get this way.
1651 if (dst_mt
->stencil_mt
) {
1652 assert(src_mt
->stencil_mt
);
1653 intel_miptree_copy_slice_sw(brw
,
1654 src_mt
->stencil_mt
, src_level
, src_layer
,
1655 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1661 intel_miptree_copy_slice(struct brw_context
*brw
,
1662 struct intel_mipmap_tree
*src_mt
,
1663 unsigned src_level
, unsigned src_layer
,
1664 struct intel_mipmap_tree
*dst_mt
,
1665 unsigned dst_level
, unsigned dst_layer
)
1668 mesa_format format
= src_mt
->format
;
1669 uint32_t width
, height
;
1671 if (src_mt
->surf
.size
> 0) {
1672 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1673 src_level
- src_mt
->first_level
);
1674 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1675 src_level
- src_mt
->first_level
);
1677 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1678 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1679 src_level
- src_mt
->first_level
));
1681 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1683 width
= minify(src_mt
->physical_width0
,
1684 src_level
- src_mt
->first_level
);
1685 height
= minify(src_mt
->physical_height0
,
1686 src_level
- src_mt
->first_level
);
1687 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1690 assert(src_mt
->format
== dst_mt
->format
);
1692 if (dst_mt
->compressed
) {
1694 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1695 height
= ALIGN_NPOT(height
, j
) / j
;
1696 width
= ALIGN_NPOT(width
, i
) / i
;
1699 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1700 * below won't apply since we can't do the depth's Y tiling or the
1701 * stencil's W tiling in the blitter.
1703 if (src_mt
->stencil_mt
) {
1704 intel_miptree_copy_slice_sw(brw
,
1705 src_mt
, src_level
, src_layer
,
1706 dst_mt
, dst_level
, dst_layer
,
1711 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1712 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1714 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1717 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1718 _mesa_get_format_name(src_mt
->format
),
1719 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1720 _mesa_get_format_name(dst_mt
->format
),
1721 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1724 if (!intel_miptree_blit(brw
,
1725 src_mt
, src_level
, src_layer
, 0, 0, false,
1726 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1727 width
, height
, GL_COPY
)) {
1728 perf_debug("miptree validate blit for %s failed\n",
1729 _mesa_get_format_name(format
));
1731 intel_miptree_copy_slice_sw(brw
,
1732 src_mt
, src_level
, src_layer
,
1733 dst_mt
, dst_level
, dst_layer
,
1739 * Copies the image's current data to the given miptree, and associates that
1740 * miptree with the image.
1742 * If \c invalidate is true, then the actual image data does not need to be
1743 * copied, but the image still needs to be associated to the new miptree (this
1744 * is set to true if we're about to clear the image).
1747 intel_miptree_copy_teximage(struct brw_context
*brw
,
1748 struct intel_texture_image
*intelImage
,
1749 struct intel_mipmap_tree
*dst_mt
,
1752 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1753 struct intel_texture_object
*intel_obj
=
1754 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1755 int level
= intelImage
->base
.Base
.Level
;
1756 const unsigned face
= intelImage
->base
.Base
.Face
;
1757 unsigned start_layer
, end_layer
;
1759 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1761 assert(intelImage
->base
.Base
.Height
);
1763 end_layer
= intelImage
->base
.Base
.Height
- 1;
1764 } else if (face
> 0) {
1768 assert(intelImage
->base
.Base
.Depth
);
1770 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1774 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1775 intel_miptree_copy_slice(brw
,
1781 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1782 intel_obj
->needs_validate
= true;
1786 intel_miptree_init_mcs(struct brw_context
*brw
,
1787 struct intel_mipmap_tree
*mt
,
1790 assert(mt
->mcs_buf
!= NULL
);
1792 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1794 * When MCS buffer is enabled and bound to MSRT, it is required that it
1795 * is cleared prior to any rendering.
1797 * Since we don't use the MCS buffer for any purpose other than rendering,
1798 * it makes sense to just clear it immediately upon allocation.
1800 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1802 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1803 if (unlikely(map
== NULL
)) {
1804 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1805 brw_bo_unreference(mt
->mcs_buf
->bo
);
1810 memset(data
, init_value
, mt
->mcs_buf
->size
);
1811 brw_bo_unmap(mt
->mcs_buf
->bo
);
1814 static struct intel_miptree_aux_buffer
*
1815 intel_alloc_aux_buffer(struct brw_context
*brw
,
1817 const struct isl_surf
*aux_surf
,
1818 uint32_t alloc_flags
,
1819 struct intel_mipmap_tree
*mt
)
1821 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1825 buf
->size
= aux_surf
->size
;
1826 buf
->pitch
= aux_surf
->row_pitch
;
1827 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1829 /* ISL has stricter set of alignment rules then the drm allocator.
1830 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1831 * trying to recalculate based on different format block sizes.
1833 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1834 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1840 buf
->surf
= *aux_surf
;
1846 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1847 struct intel_mipmap_tree
*mt
,
1850 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1851 assert(mt
->mcs_buf
== NULL
);
1852 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1854 /* Multisampled miptrees are only supported for single level. */
1855 assert(mt
->first_level
== 0);
1856 enum isl_aux_state
**aux_state
=
1857 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1861 struct isl_surf temp_main_surf
;
1862 struct isl_surf temp_mcs_surf
;
1864 /* Create first an ISL presentation for the main color surface and let ISL
1865 * calculate equivalent MCS surface against it.
1867 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1868 MAYBE_UNUSED
bool ok
=
1869 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1872 /* Buffer needs to be initialised requiring the buffer to be immediately
1873 * mapped to cpu space for writing. Therefore do not use the gpu access
1874 * flag which can cause an unnecessary delay if the backing pages happened
1875 * to be just used by the GPU.
1877 const uint32_t alloc_flags
= 0;
1878 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1879 &temp_mcs_surf
, alloc_flags
, mt
);
1885 mt
->aux_state
= aux_state
;
1887 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1893 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1894 struct intel_mipmap_tree
*mt
)
1896 assert(mt
->mcs_buf
== NULL
);
1897 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1898 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1900 struct isl_surf temp_main_surf
;
1901 struct isl_surf temp_ccs_surf
;
1903 /* Create first an ISL presentation for the main color surface and let ISL
1904 * calculate equivalent CCS surface against it.
1906 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1907 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1911 assert(temp_ccs_surf
.size
&&
1912 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1914 enum isl_aux_state
**aux_state
=
1915 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1919 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1920 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1922 * "If Software wants to enable Color Compression without Fast clear,
1923 * Software needs to initialize MCS with zeros."
1925 * A CCS value of 0 indicates that the corresponding block is in the
1926 * pass-through state which is what we want.
1928 * For CCS_D, on the other hand, we don't care as we're about to perform a
1929 * fast-clear operation. In that case, being hot in caches more useful.
1931 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1932 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1933 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1934 &temp_ccs_surf
, alloc_flags
, mt
);
1940 mt
->aux_state
= aux_state
;
1946 * Helper for intel_miptree_alloc_hiz() that sets
1947 * \c mt->level[level].has_hiz. Return true if and only if
1948 * \c has_hiz was set.
1951 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1952 struct intel_mipmap_tree
*mt
,
1955 assert(mt
->hiz_buf
);
1957 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1958 uint32_t width
= minify(mt
->physical_width0
, level
);
1959 uint32_t height
= minify(mt
->physical_height0
, level
);
1961 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1962 * and the height is 4 aligned. This allows our HiZ support
1963 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1964 * we can grow the width & height to allow the HiZ op to
1965 * force the proper size alignments.
1967 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1968 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1973 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1974 mt
->level
[level
].has_hiz
= true;
1979 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1980 struct intel_mipmap_tree
*mt
)
1982 assert(mt
->hiz_buf
== NULL
);
1983 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1985 enum isl_aux_state
**aux_state
=
1986 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1990 struct isl_surf temp_main_surf
;
1991 struct isl_surf temp_hiz_surf
;
1993 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1994 MAYBE_UNUSED
bool ok
=
1995 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1998 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1999 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
2000 &temp_hiz_surf
, alloc_flags
, mt
);
2007 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2008 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2010 mt
->aux_state
= aux_state
;
2017 * Allocate the initial aux surface for a miptree based on mt->aux_usage
2019 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
2020 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
2021 * compress clear color so we wait until an actual fast-clear to allocate it.
2024 intel_miptree_alloc_aux(struct brw_context
*brw
,
2025 struct intel_mipmap_tree
*mt
)
2027 switch (mt
->aux_usage
) {
2028 case ISL_AUX_USAGE_NONE
:
2031 case ISL_AUX_USAGE_HIZ
:
2032 assert(!_mesa_is_format_color_format(mt
->format
));
2033 if (!intel_miptree_alloc_hiz(brw
, mt
))
2037 case ISL_AUX_USAGE_MCS
:
2038 assert(_mesa_is_format_color_format(mt
->format
));
2039 assert(mt
->surf
.samples
> 1);
2040 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
2044 case ISL_AUX_USAGE_CCS_D
:
2045 /* Since CCS_D can only compress clear color so we wait until an actual
2046 * fast-clear to allocate it.
2050 case ISL_AUX_USAGE_CCS_E
:
2051 assert(_mesa_is_format_color_format(mt
->format
));
2052 assert(mt
->surf
.samples
== 1);
2053 if (!intel_miptree_alloc_ccs(brw
, mt
))
2058 unreachable("Invalid aux usage");
2063 * Can the miptree sample using the hiz buffer?
2066 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2067 struct intel_mipmap_tree
*mt
)
2069 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2070 * so keep things conservative for now and never enable it unless we're SKL+.
2080 /* It seems the hardware won't fallback to the depth buffer if some of the
2081 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2082 * of the texture to be HiZ enabled.
2084 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2085 if (!intel_miptree_level_has_hiz(mt
, level
))
2089 /* If compressed multisampling is enabled, then we use it for the auxiliary
2092 * From the BDW PRM (Volume 2d: Command Reference: Structures
2093 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2095 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2096 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2098 * There is no such blurb for 1D textures, but there is sufficient evidence
2099 * that this is broken on SKL+.
2101 return (mt
->surf
.samples
== 1 &&
2102 mt
->target
!= GL_TEXTURE_3D
&&
2103 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2107 * Does the miptree slice have hiz enabled?
2110 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2112 intel_miptree_check_level_layer(mt
, level
, 0);
2113 return mt
->level
[level
].has_hiz
;
2117 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2118 unsigned start_level
, unsigned num_levels
,
2119 unsigned start_layer
, unsigned num_layers
)
2121 assert(_mesa_is_format_color_format(mt
->format
));
2126 /* Clamp the level range to fit the miptree */
2127 assert(start_level
+ num_levels
>= start_level
);
2128 const uint32_t last_level
=
2129 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2130 start_level
= MAX2(mt
->first_level
, start_level
);
2131 num_levels
= last_level
- start_level
+ 1;
2133 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2134 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2135 for (unsigned a
= 0; a
< level_layers
; a
++) {
2136 enum isl_aux_state aux_state
=
2137 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2138 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2139 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2148 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2149 const struct intel_mipmap_tree
*mt
,
2150 unsigned level
, unsigned layer
)
2156 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2157 assert(brw
->gen
>= 8 ||
2158 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2160 /* Compression of arrayed msaa surfaces is supported. */
2161 if (mt
->surf
.samples
> 1)
2164 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2165 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2171 static enum blorp_fast_clear_op
2172 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2173 bool ccs_supported
, bool fast_clear_supported
)
2175 assert(ccs_supported
== fast_clear_supported
);
2177 switch (aux_state
) {
2178 case ISL_AUX_STATE_CLEAR
:
2179 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2181 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2183 return BLORP_FAST_CLEAR_OP_NONE
;
2185 case ISL_AUX_STATE_PASS_THROUGH
:
2186 return BLORP_FAST_CLEAR_OP_NONE
;
2188 case ISL_AUX_STATE_RESOLVED
:
2189 case ISL_AUX_STATE_AUX_INVALID
:
2190 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2194 unreachable("Invalid aux state for CCS_D");
2197 static enum blorp_fast_clear_op
2198 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2199 bool ccs_supported
, bool fast_clear_supported
)
2201 switch (aux_state
) {
2202 case ISL_AUX_STATE_CLEAR
:
2203 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2205 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2206 else if (!fast_clear_supported
)
2207 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2209 return BLORP_FAST_CLEAR_OP_NONE
;
2211 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2213 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2215 return BLORP_FAST_CLEAR_OP_NONE
;
2217 case ISL_AUX_STATE_PASS_THROUGH
:
2218 return BLORP_FAST_CLEAR_OP_NONE
;
2220 case ISL_AUX_STATE_RESOLVED
:
2221 case ISL_AUX_STATE_AUX_INVALID
:
2225 unreachable("Invalid aux state for CCS_E");
2229 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2230 struct intel_mipmap_tree
*mt
,
2231 uint32_t level
, uint32_t layer
,
2233 bool fast_clear_supported
)
2235 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2237 enum blorp_fast_clear_op resolve_op
;
2238 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2239 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2240 fast_clear_supported
);
2242 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2243 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2244 fast_clear_supported
);
2247 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2248 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2249 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2251 switch (resolve_op
) {
2252 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2253 /* The CCS full resolve operation destroys the CCS and sets it to the
2254 * pass-through state. (You can also think of this as being both a
2255 * resolve and an ambiguate in one operation.)
2257 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2258 ISL_AUX_STATE_PASS_THROUGH
);
2261 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2262 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2263 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2267 unreachable("Invalid resolve op");
2273 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2274 struct intel_mipmap_tree
*mt
,
2275 uint32_t level
, uint32_t layer
,
2276 bool written_with_ccs
)
2278 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2280 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2281 switch (aux_state
) {
2282 case ISL_AUX_STATE_CLEAR
:
2283 assert(written_with_ccs
);
2284 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2285 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2288 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2289 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2290 assert(written_with_ccs
);
2291 break; /* Nothing to do */
2293 case ISL_AUX_STATE_PASS_THROUGH
:
2294 if (written_with_ccs
) {
2295 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2296 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2302 case ISL_AUX_STATE_RESOLVED
:
2303 case ISL_AUX_STATE_AUX_INVALID
:
2304 unreachable("Invalid aux state for CCS_E");
2307 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2308 /* CCS_D is a bit simpler */
2309 switch (aux_state
) {
2310 case ISL_AUX_STATE_CLEAR
:
2311 assert(written_with_ccs
);
2312 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2313 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2316 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2317 assert(written_with_ccs
);
2318 break; /* Nothing to do */
2320 case ISL_AUX_STATE_PASS_THROUGH
:
2324 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2325 case ISL_AUX_STATE_RESOLVED
:
2326 case ISL_AUX_STATE_AUX_INVALID
:
2327 unreachable("Invalid aux state for CCS_D");
2333 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2334 struct intel_mipmap_tree
*mt
,
2335 uint32_t level
, uint32_t layer
,
2336 bool written_with_aux
)
2338 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2339 case ISL_AUX_STATE_CLEAR
:
2340 assert(written_with_aux
);
2341 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2342 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2345 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2346 assert(written_with_aux
);
2347 break; /* Nothing to do */
2349 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2350 case ISL_AUX_STATE_RESOLVED
:
2351 case ISL_AUX_STATE_PASS_THROUGH
:
2352 case ISL_AUX_STATE_AUX_INVALID
:
2353 unreachable("Invalid aux state for MCS");
2358 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2359 struct intel_mipmap_tree
*mt
,
2360 uint32_t level
, uint32_t layer
,
2361 bool hiz_supported
, bool fast_clear_supported
)
2363 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2364 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2365 case ISL_AUX_STATE_CLEAR
:
2366 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2367 if (!hiz_supported
|| !fast_clear_supported
)
2368 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2371 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2373 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2376 case ISL_AUX_STATE_PASS_THROUGH
:
2377 case ISL_AUX_STATE_RESOLVED
:
2380 case ISL_AUX_STATE_AUX_INVALID
:
2382 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2386 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2387 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2390 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2391 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2392 ISL_AUX_STATE_RESOLVED
);
2395 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2396 /* The HiZ resolve operation is actually an ambiguate */
2397 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2398 ISL_AUX_STATE_PASS_THROUGH
);
2402 unreachable("Invalid HiZ op");
2408 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2409 struct intel_mipmap_tree
*mt
,
2410 uint32_t level
, uint32_t layer
,
2411 bool written_with_hiz
)
2413 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2414 case ISL_AUX_STATE_CLEAR
:
2415 assert(written_with_hiz
);
2416 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2417 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2420 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2421 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2422 assert(written_with_hiz
);
2423 break; /* Nothing to do */
2425 case ISL_AUX_STATE_RESOLVED
:
2426 if (written_with_hiz
) {
2427 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2428 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2430 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2431 ISL_AUX_STATE_AUX_INVALID
);
2435 case ISL_AUX_STATE_PASS_THROUGH
:
2436 if (written_with_hiz
) {
2437 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2438 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2442 case ISL_AUX_STATE_AUX_INVALID
:
2443 assert(!written_with_hiz
);
2448 static inline uint32_t
2449 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2450 uint32_t start_level
, uint32_t num_levels
)
2452 assert(start_level
>= mt
->first_level
);
2453 assert(start_level
<= mt
->last_level
);
2455 if (num_levels
== INTEL_REMAINING_LAYERS
)
2456 num_levels
= mt
->last_level
- start_level
+ 1;
2457 /* Check for overflow */
2458 assert(start_level
+ num_levels
>= start_level
);
2459 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2464 static inline uint32_t
2465 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2466 uint32_t start_layer
, uint32_t num_layers
)
2468 assert(level
<= mt
->last_level
);
2469 uint32_t total_num_layers
;
2471 if (mt
->surf
.size
> 0)
2472 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2473 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2474 mt
->surf
.phys_level0_sa
.array_len
;
2476 total_num_layers
= mt
->level
[level
].depth
;
2478 assert(start_layer
< total_num_layers
);
2479 if (num_layers
== INTEL_REMAINING_LAYERS
)
2480 num_layers
= total_num_layers
- start_layer
;
2481 /* Check for overflow */
2482 assert(start_layer
+ num_layers
>= start_layer
);
2483 assert(start_layer
+ num_layers
<= total_num_layers
);
2489 intel_miptree_prepare_access(struct brw_context
*brw
,
2490 struct intel_mipmap_tree
*mt
,
2491 uint32_t start_level
, uint32_t num_levels
,
2492 uint32_t start_layer
, uint32_t num_layers
,
2493 bool aux_supported
, bool fast_clear_supported
)
2495 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2497 if (_mesa_is_format_color_format(mt
->format
)) {
2501 if (mt
->surf
.samples
> 1) {
2502 /* Nothing to do for MSAA */
2503 assert(aux_supported
&& fast_clear_supported
);
2505 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2506 const uint32_t level
= start_level
+ l
;
2507 const uint32_t level_layers
=
2508 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2509 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2510 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2511 start_layer
+ a
, aux_supported
,
2512 fast_clear_supported
);
2516 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2517 /* Nothing to do for stencil */
2522 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2523 const uint32_t level
= start_level
+ l
;
2524 if (!intel_miptree_level_has_hiz(mt
, level
))
2527 const uint32_t level_layers
=
2528 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2529 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2530 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2532 fast_clear_supported
);
2539 intel_miptree_finish_write(struct brw_context
*brw
,
2540 struct intel_mipmap_tree
*mt
, uint32_t level
,
2541 uint32_t start_layer
, uint32_t num_layers
,
2542 bool written_with_aux
)
2544 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2546 if (_mesa_is_format_color_format(mt
->format
)) {
2550 if (mt
->surf
.samples
> 1) {
2551 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2552 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2556 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2557 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2561 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2562 /* Nothing to do for stencil */
2564 if (!intel_miptree_level_has_hiz(mt
, level
))
2567 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2568 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2575 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2576 uint32_t level
, uint32_t layer
)
2578 intel_miptree_check_level_layer(mt
, level
, layer
);
2580 if (_mesa_is_format_color_format(mt
->format
)) {
2581 assert(mt
->mcs_buf
!= NULL
);
2582 assert(mt
->surf
.samples
== 1 ||
2583 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2584 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2585 unreachable("Cannot get aux state for stencil");
2587 assert(intel_miptree_level_has_hiz(mt
, level
));
2590 return mt
->aux_state
[level
][layer
];
2594 intel_miptree_set_aux_state(struct brw_context
*brw
,
2595 struct intel_mipmap_tree
*mt
, uint32_t level
,
2596 uint32_t start_layer
, uint32_t num_layers
,
2597 enum isl_aux_state aux_state
)
2599 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2601 if (_mesa_is_format_color_format(mt
->format
)) {
2602 assert(mt
->mcs_buf
!= NULL
);
2603 assert(mt
->surf
.samples
== 1 ||
2604 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2605 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2606 unreachable("Cannot get aux state for stencil");
2608 assert(intel_miptree_level_has_hiz(mt
, level
));
2611 for (unsigned a
= 0; a
< num_layers
; a
++)
2612 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2615 /* On Gen9 color buffers may be compressed by the hardware (lossless
2616 * compression). There are, however, format restrictions and care needs to be
2617 * taken that the sampler engine is capable for re-interpreting a buffer with
2618 * format different the buffer was originally written with.
2620 * For example, SRGB formats are not compressible and the sampler engine isn't
2621 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2622 * color buffer needs to be resolved so that the sampling surface can be
2623 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2627 can_texture_with_ccs(struct brw_context
*brw
,
2628 struct intel_mipmap_tree
*mt
,
2629 mesa_format view_format
)
2631 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2634 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2635 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2637 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2638 isl_mt_format
, isl_view_format
)) {
2639 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2640 _mesa_get_format_name(view_format
),
2641 _mesa_get_format_name(mt
->format
));
2649 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2650 struct intel_mipmap_tree
*mt
,
2651 mesa_format view_format
,
2652 uint32_t start_level
, uint32_t num_levels
,
2653 uint32_t start_layer
, uint32_t num_layers
,
2654 bool *aux_supported_out
)
2656 bool aux_supported
, clear_supported
;
2657 if (_mesa_is_format_color_format(mt
->format
)) {
2658 if (mt
->surf
.samples
> 1) {
2659 aux_supported
= clear_supported
= true;
2661 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2663 /* Clear color is specified as ints or floats and the conversion is
2664 * done by the sampler. If we have a texture view, we would have to
2665 * perform the clear color conversion manually. Just disable clear
2668 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2670 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2671 aux_supported
= clear_supported
= false;
2673 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2676 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2677 start_layer
, num_layers
,
2678 aux_supported
, clear_supported
);
2679 if (aux_supported_out
)
2680 *aux_supported_out
= aux_supported
;
2684 intel_miptree_prepare_texture(struct brw_context
*brw
,
2685 struct intel_mipmap_tree
*mt
,
2686 mesa_format view_format
,
2687 bool *aux_supported_out
)
2689 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2690 0, INTEL_REMAINING_LEVELS
,
2691 0, INTEL_REMAINING_LAYERS
,
2696 intel_miptree_prepare_image(struct brw_context
*brw
,
2697 struct intel_mipmap_tree
*mt
)
2699 /* The data port doesn't understand any compression */
2700 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2701 0, INTEL_REMAINING_LAYERS
, false, false);
2705 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2706 struct intel_mipmap_tree
*mt
, uint32_t level
,
2707 uint32_t start_layer
, uint32_t num_layers
)
2709 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2710 start_layer
, num_layers
, NULL
);
2714 intel_miptree_prepare_render(struct brw_context
*brw
,
2715 struct intel_mipmap_tree
*mt
, uint32_t level
,
2716 uint32_t start_layer
, uint32_t layer_count
,
2719 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2720 * the single-sampled color renderbuffers because the CCS buffer isn't
2721 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2722 * enabled because otherwise the surface state will be programmed with
2723 * the linear equivalent format anyway.
2725 if (brw
->gen
== 9 && srgb_enabled
&& mt
->surf
.samples
== 1 &&
2726 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2728 /* Lossless compression is not supported for SRGB formats, it
2729 * should be impossible to get here with such surfaces.
2731 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2732 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2738 intel_miptree_finish_render(struct brw_context
*brw
,
2739 struct intel_mipmap_tree
*mt
, uint32_t level
,
2740 uint32_t start_layer
, uint32_t layer_count
)
2742 assert(_mesa_is_format_color_format(mt
->format
));
2743 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2744 mt
->mcs_buf
!= NULL
);
2748 intel_miptree_prepare_depth(struct brw_context
*brw
,
2749 struct intel_mipmap_tree
*mt
, uint32_t level
,
2750 uint32_t start_layer
, uint32_t layer_count
)
2752 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2753 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2757 intel_miptree_finish_depth(struct brw_context
*brw
,
2758 struct intel_mipmap_tree
*mt
, uint32_t level
,
2759 uint32_t start_layer
, uint32_t layer_count
,
2762 if (depth_written
) {
2763 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2764 mt
->hiz_buf
!= NULL
);
2769 * Make it possible to share the BO backing the given miptree with another
2770 * process or another miptree.
2772 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2773 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2774 * ensure that no MCS buffer gets allocated in the future.
2776 * HiZ is similarly unsafe with shared buffers.
2779 intel_miptree_make_shareable(struct brw_context
*brw
,
2780 struct intel_mipmap_tree
*mt
)
2782 /* MCS buffers are also used for multisample buffers, but we can't resolve
2783 * away a multisample MCS buffer because it's an integral part of how the
2784 * pixel data is stored. Fortunately this code path should never be
2785 * reached for multisample buffers.
2787 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2788 mt
->surf
.samples
== 1);
2790 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2791 0, INTEL_REMAINING_LAYERS
, false, false);
2794 brw_bo_unreference(mt
->mcs_buf
->bo
);
2798 /* Any pending MCS/CCS operations are no longer needed. Trying to
2799 * execute any will likely crash due to the missing aux buffer. So let's
2800 * delete all pending ops.
2802 free(mt
->aux_state
);
2803 mt
->aux_state
= NULL
;
2807 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2810 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2811 mt
->level
[l
].has_hiz
= false;
2814 /* Any pending HiZ operations are no longer needed. Trying to execute
2815 * any will likely crash due to the missing aux buffer. So let's delete
2818 free(mt
->aux_state
);
2819 mt
->aux_state
= NULL
;
2822 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2827 * \brief Get pointer offset into stencil buffer.
2829 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2830 * must decode the tile's layout in software.
2833 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2835 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2837 * Even though the returned offset is always positive, the return type is
2839 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2840 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2843 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2845 uint32_t tile_size
= 4096;
2846 uint32_t tile_width
= 64;
2847 uint32_t tile_height
= 64;
2848 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2850 uint32_t tile_x
= x
/ tile_width
;
2851 uint32_t tile_y
= y
/ tile_height
;
2853 /* The byte's address relative to the tile's base addres. */
2854 uint32_t byte_x
= x
% tile_width
;
2855 uint32_t byte_y
= y
% tile_height
;
2857 uintptr_t u
= tile_y
* row_size
2858 + tile_x
* tile_size
2859 + 512 * (byte_x
/ 8)
2861 + 32 * ((byte_y
/ 4) % 2)
2862 + 16 * ((byte_x
/ 4) % 2)
2863 + 8 * ((byte_y
/ 2) % 2)
2864 + 4 * ((byte_x
/ 2) % 2)
2869 /* adjust for bit6 swizzling */
2870 if (((byte_x
/ 8) % 2) == 1) {
2871 if (((byte_y
/ 8) % 2) == 0) {
2883 intel_miptree_updownsample(struct brw_context
*brw
,
2884 struct intel_mipmap_tree
*src
,
2885 struct intel_mipmap_tree
*dst
)
2887 unsigned src_w
, src_h
, dst_w
, dst_h
;
2889 if (src
->surf
.size
> 0) {
2890 src_w
= src
->surf
.logical_level0_px
.width
;
2891 src_h
= src
->surf
.logical_level0_px
.height
;
2893 src_w
= src
->logical_width0
;
2894 src_h
= src
->logical_height0
;
2897 if (dst
->surf
.size
> 0) {
2898 dst_w
= dst
->surf
.logical_level0_px
.width
;
2899 dst_h
= dst
->surf
.logical_level0_px
.height
;
2901 dst_w
= dst
->logical_width0
;
2902 dst_h
= dst
->logical_height0
;
2905 brw_blorp_blit_miptrees(brw
,
2906 src
, 0 /* level */, 0 /* layer */,
2907 src
->format
, SWIZZLE_XYZW
,
2908 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2911 GL_NEAREST
, false, false /*mirror x, y*/,
2914 if (src
->stencil_mt
) {
2915 if (src
->stencil_mt
->surf
.size
> 0) {
2916 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2917 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2919 src_w
= src
->stencil_mt
->logical_width0
;
2920 src_h
= src
->stencil_mt
->logical_height0
;
2923 if (dst
->stencil_mt
->surf
.size
> 0) {
2924 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2925 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2927 dst_w
= dst
->stencil_mt
->logical_width0
;
2928 dst_h
= dst
->stencil_mt
->logical_height0
;
2931 brw_blorp_blit_miptrees(brw
,
2932 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2933 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2934 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2935 dst
->stencil_mt
->format
,
2938 GL_NEAREST
, false, false /*mirror x, y*/,
2939 false, false /* decode/encode srgb */);
2944 intel_update_r8stencil(struct brw_context
*brw
,
2945 struct intel_mipmap_tree
*mt
)
2947 assert(brw
->gen
>= 7);
2948 struct intel_mipmap_tree
*src
=
2949 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2950 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2953 if (!mt
->r8stencil_mt
) {
2954 const uint32_t r8stencil_flags
=
2955 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2956 MIPTREE_LAYOUT_DISABLE_AUX
;
2957 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2958 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2960 MESA_FORMAT_R_UINT8
,
2963 src
->logical_width0
,
2964 src
->logical_height0
,
2965 src
->logical_depth0
,
2968 assert(mt
->r8stencil_mt
);
2971 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2973 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2974 const unsigned depth
= src
->level
[level
].depth
;
2976 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2977 brw_blorp_copy_miptrees(brw
,
2981 minify(src
->logical_width0
, level
),
2982 minify(src
->logical_height0
, level
));
2986 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2987 src
->r8stencil_needs_update
= false;
2991 intel_miptree_map_raw(struct brw_context
*brw
,
2992 struct intel_mipmap_tree
*mt
,
2995 struct brw_bo
*bo
= mt
->bo
;
2997 if (brw_batch_references(&brw
->batch
, bo
))
2998 intel_batchbuffer_flush(brw
);
3000 return brw_bo_map(brw
, bo
, mode
);
3004 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3006 brw_bo_unmap(mt
->bo
);
3010 intel_miptree_map_gtt(struct brw_context
*brw
,
3011 struct intel_mipmap_tree
*mt
,
3012 struct intel_miptree_map
*map
,
3013 unsigned int level
, unsigned int slice
)
3015 unsigned int bw
, bh
;
3017 unsigned int image_x
, image_y
;
3018 intptr_t x
= map
->x
;
3019 intptr_t y
= map
->y
;
3021 /* For compressed formats, the stride is the number of bytes per
3022 * row of blocks. intel_miptree_get_image_offset() already does
3025 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3026 assert(y
% bh
== 0);
3027 assert(x
% bw
== 0);
3031 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3038 /* Note that in the case of cube maps, the caller must have passed the
3039 * slice number referencing the face.
3041 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3045 map
->stride
= mt
->surf
.row_pitch
;
3046 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3049 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3050 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3051 map
->x
, map
->y
, map
->w
, map
->h
,
3052 mt
, _mesa_get_format_name(mt
->format
),
3053 x
, y
, map
->ptr
, map
->stride
);
3057 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3059 intel_miptree_unmap_raw(mt
);
3063 intel_miptree_map_blit(struct brw_context
*brw
,
3064 struct intel_mipmap_tree
*mt
,
3065 struct intel_miptree_map
*map
,
3066 unsigned int level
, unsigned int slice
)
3068 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3069 /* first_level */ 0,
3073 MIPTREE_LAYOUT_TILING_NONE
);
3075 if (!map
->linear_mt
) {
3076 fprintf(stderr
, "Failed to allocate blit temporary\n");
3079 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3081 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3082 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3083 * invalidate is set, since we'll be writing the whole rectangle from our
3084 * temporary buffer back out.
3086 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3087 if (!intel_miptree_copy(brw
,
3088 mt
, level
, slice
, map
->x
, map
->y
,
3089 map
->linear_mt
, 0, 0, 0, 0,
3091 fprintf(stderr
, "Failed to blit\n");
3096 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3098 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3099 map
->x
, map
->y
, map
->w
, map
->h
,
3100 mt
, _mesa_get_format_name(mt
->format
),
3101 level
, slice
, map
->ptr
, map
->stride
);
3106 intel_miptree_release(&map
->linear_mt
);
3112 intel_miptree_unmap_blit(struct brw_context
*brw
,
3113 struct intel_mipmap_tree
*mt
,
3114 struct intel_miptree_map
*map
,
3118 struct gl_context
*ctx
= &brw
->ctx
;
3120 intel_miptree_unmap_raw(map
->linear_mt
);
3122 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3123 bool ok
= intel_miptree_copy(brw
,
3124 map
->linear_mt
, 0, 0, 0, 0,
3125 mt
, level
, slice
, map
->x
, map
->y
,
3127 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3130 intel_miptree_release(&map
->linear_mt
);
3134 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3136 #if defined(USE_SSE41)
3138 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3139 struct intel_mipmap_tree
*mt
,
3140 struct intel_miptree_map
*map
,
3141 unsigned int level
, unsigned int slice
)
3143 assert(map
->mode
& GL_MAP_READ_BIT
);
3144 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3146 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3147 map
->x
, map
->y
, map
->w
, map
->h
,
3148 mt
, _mesa_get_format_name(mt
->format
),
3149 level
, slice
, map
->ptr
, map
->stride
);
3151 /* Map the original image */
3154 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3158 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3164 src
+= image_y
* mt
->surf
.row_pitch
;
3165 src
+= image_x
* mt
->cpp
;
3167 /* Due to the pixel offsets for the particular image being mapped, our
3168 * src pointer may not be 16-byte aligned. However, if the pitch is
3169 * divisible by 16, then the amount by which it's misaligned will remain
3170 * consistent from row to row.
3172 assert((mt
->surf
.row_pitch
% 16) == 0);
3173 const int misalignment
= ((uintptr_t) src
) & 15;
3175 /* Create an untiled temporary buffer for the mapping. */
3176 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3178 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3180 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3181 /* Offset the destination so it has the same misalignment as src. */
3182 map
->ptr
= map
->buffer
+ misalignment
;
3184 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3186 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3187 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3188 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3190 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3193 intel_miptree_unmap_raw(mt
);
3197 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3198 struct intel_mipmap_tree
*mt
,
3199 struct intel_miptree_map
*map
,
3203 _mesa_align_free(map
->buffer
);
3210 intel_miptree_map_s8(struct brw_context
*brw
,
3211 struct intel_mipmap_tree
*mt
,
3212 struct intel_miptree_map
*map
,
3213 unsigned int level
, unsigned int slice
)
3215 map
->stride
= map
->w
;
3216 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3220 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3221 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3222 * invalidate is set, since we'll be writing the whole rectangle from our
3223 * temporary buffer back out.
3225 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3226 uint8_t *untiled_s8_map
= map
->ptr
;
3227 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3228 unsigned int image_x
, image_y
;
3230 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3232 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3233 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3234 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3235 x
+ image_x
+ map
->x
,
3236 y
+ image_y
+ map
->y
,
3237 brw
->has_swizzling
);
3238 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3242 intel_miptree_unmap_raw(mt
);
3244 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3245 map
->x
, map
->y
, map
->w
, map
->h
,
3246 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3248 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3249 map
->x
, map
->y
, map
->w
, map
->h
,
3250 mt
, map
->ptr
, map
->stride
);
3255 intel_miptree_unmap_s8(struct brw_context
*brw
,
3256 struct intel_mipmap_tree
*mt
,
3257 struct intel_miptree_map
*map
,
3261 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3262 unsigned int image_x
, image_y
;
3263 uint8_t *untiled_s8_map
= map
->ptr
;
3264 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3266 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3268 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3269 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3270 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3271 image_x
+ x
+ map
->x
,
3272 image_y
+ y
+ map
->y
,
3273 brw
->has_swizzling
);
3274 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3278 intel_miptree_unmap_raw(mt
);
3285 intel_miptree_map_etc(struct brw_context
*brw
,
3286 struct intel_mipmap_tree
*mt
,
3287 struct intel_miptree_map
*map
,
3291 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3292 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3293 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3296 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3297 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3299 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3300 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3301 map
->w
, map
->h
, 1));
3302 map
->ptr
= map
->buffer
;
3306 intel_miptree_unmap_etc(struct brw_context
*brw
,
3307 struct intel_mipmap_tree
*mt
,
3308 struct intel_miptree_map
*map
,
3314 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3319 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3320 + image_y
* mt
->surf
.row_pitch
3321 + image_x
* mt
->cpp
;
3323 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3324 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3325 map
->ptr
, map
->stride
,
3328 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3329 map
->ptr
, map
->stride
,
3330 map
->w
, map
->h
, mt
->etc_format
);
3332 intel_miptree_unmap_raw(mt
);
3337 * Mapping function for packed depth/stencil miptrees backed by real separate
3338 * miptrees for depth and stencil.
3340 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3341 * separate from the depth buffer. Yet at the GL API level, we have to expose
3342 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3343 * be able to map that memory for texture storage and glReadPixels-type
3344 * operations. We give Mesa core that access by mallocing a temporary and
3345 * copying the data between the actual backing store and the temporary.
3348 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3349 struct intel_mipmap_tree
*mt
,
3350 struct intel_miptree_map
*map
,
3351 unsigned int level
, unsigned int slice
)
3353 struct intel_mipmap_tree
*z_mt
= mt
;
3354 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3355 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3356 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3358 map
->stride
= map
->w
* packed_bpp
;
3359 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3363 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3364 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3365 * invalidate is set, since we'll be writing the whole rectangle from our
3366 * temporary buffer back out.
3368 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3369 uint32_t *packed_map
= map
->ptr
;
3370 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3371 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3372 unsigned int s_image_x
, s_image_y
;
3373 unsigned int z_image_x
, z_image_y
;
3375 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3376 &s_image_x
, &s_image_y
);
3377 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3378 &z_image_x
, &z_image_y
);
3380 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3381 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3382 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3383 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3386 brw
->has_swizzling
);
3387 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3388 (z_mt
->surf
.row_pitch
/ 4) +
3389 (map_x
+ z_image_x
));
3390 uint8_t s
= s_map
[s_offset
];
3391 uint32_t z
= z_map
[z_offset
];
3393 if (map_z32f_x24s8
) {
3394 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3395 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3397 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3402 intel_miptree_unmap_raw(s_mt
);
3403 intel_miptree_unmap_raw(z_mt
);
3405 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3407 map
->x
, map
->y
, map
->w
, map
->h
,
3408 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3409 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3410 map
->ptr
, map
->stride
);
3412 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3413 map
->x
, map
->y
, map
->w
, map
->h
,
3414 mt
, map
->ptr
, map
->stride
);
3419 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3420 struct intel_mipmap_tree
*mt
,
3421 struct intel_miptree_map
*map
,
3425 struct intel_mipmap_tree
*z_mt
= mt
;
3426 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3427 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3429 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3430 uint32_t *packed_map
= map
->ptr
;
3431 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3432 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3433 unsigned int s_image_x
, s_image_y
;
3434 unsigned int z_image_x
, z_image_y
;
3436 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3437 &s_image_x
, &s_image_y
);
3438 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3439 &z_image_x
, &z_image_y
);
3441 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3442 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3443 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3444 x
+ s_image_x
+ map
->x
,
3445 y
+ s_image_y
+ map
->y
,
3446 brw
->has_swizzling
);
3447 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3448 (z_mt
->surf
.row_pitch
/ 4) +
3449 (x
+ z_image_x
+ map
->x
));
3451 if (map_z32f_x24s8
) {
3452 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3453 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3455 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3456 s_map
[s_offset
] = packed
>> 24;
3457 z_map
[z_offset
] = packed
;
3462 intel_miptree_unmap_raw(s_mt
);
3463 intel_miptree_unmap_raw(z_mt
);
3465 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3467 map
->x
, map
->y
, map
->w
, map
->h
,
3468 z_mt
, _mesa_get_format_name(z_mt
->format
),
3469 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3470 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3471 map
->ptr
, map
->stride
);
3478 * Create and attach a map to the miptree at (level, slice). Return the
3481 static struct intel_miptree_map
*
3482 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3491 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3496 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3497 mt
->level
[level
].slice
[slice
].map
= map
;
3509 * Release the map at (level, slice).
3512 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3516 struct intel_miptree_map
**map
;
3518 map
= &mt
->level
[level
].slice
[slice
].map
;
3524 can_blit_slice(struct intel_mipmap_tree
*mt
,
3525 unsigned int level
, unsigned int slice
)
3527 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3528 if (mt
->surf
.row_pitch
>= 32768)
3535 use_intel_mipree_map_blit(struct brw_context
*brw
,
3536 struct intel_mipmap_tree
*mt
,
3542 /* It's probably not worth swapping to the blit ring because of
3543 * all the overhead involved.
3545 !(mode
& GL_MAP_WRITE_BIT
) &&
3547 (mt
->surf
.tiling
== ISL_TILING_X
||
3548 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3549 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3550 /* Fast copy blit on skl+ supports all tiling formats. */
3552 can_blit_slice(mt
, level
, slice
))
3555 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3556 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3557 assert(can_blit_slice(mt
, level
, slice
));
3565 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3566 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3567 * arithmetic overflow.
3569 * If you call this function and use \a out_stride, then you're doing pointer
3570 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3571 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3572 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3573 * which usually have type uint32_t or GLuint.
3576 intel_miptree_map(struct brw_context
*brw
,
3577 struct intel_mipmap_tree
*mt
,
3586 ptrdiff_t *out_stride
)
3588 struct intel_miptree_map
*map
;
3590 assert(mt
->surf
.samples
== 1);
3592 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3599 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3600 map
->mode
& GL_MAP_WRITE_BIT
);
3602 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3603 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3604 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3605 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3606 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3607 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3608 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3609 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3610 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3611 #if defined(USE_SSE41)
3612 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3613 !mt
->compressed
&& cpu_has_sse4_1
&&
3614 (mt
->surf
.row_pitch
% 16 == 0)) {
3615 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3618 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3621 *out_ptr
= map
->ptr
;
3622 *out_stride
= map
->stride
;
3624 if (map
->ptr
== NULL
)
3625 intel_miptree_release_map(mt
, level
, slice
);
3629 intel_miptree_unmap(struct brw_context
*brw
,
3630 struct intel_mipmap_tree
*mt
,
3634 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3636 assert(mt
->surf
.samples
== 1);
3641 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3642 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3644 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3645 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3646 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3647 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3648 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3649 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3650 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3651 } else if (map
->linear_mt
) {
3652 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3653 #if defined(USE_SSE41)
3654 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3655 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3658 intel_miptree_unmap_gtt(mt
);
3661 intel_miptree_release_map(mt
, level
, slice
);
3665 get_isl_surf_dim(GLenum target
)
3669 case GL_TEXTURE_1D_ARRAY
:
3670 return ISL_SURF_DIM_1D
;
3673 case GL_TEXTURE_2D_ARRAY
:
3674 case GL_TEXTURE_RECTANGLE
:
3675 case GL_TEXTURE_CUBE_MAP
:
3676 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3677 case GL_TEXTURE_2D_MULTISAMPLE
:
3678 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3679 case GL_TEXTURE_EXTERNAL_OES
:
3680 return ISL_SURF_DIM_2D
;
3683 return ISL_SURF_DIM_3D
;
3686 unreachable("Invalid texture target");
3690 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3691 enum isl_tiling tiling
, GLenum target
,
3692 enum miptree_array_layout array_layout
)
3694 if (array_layout
== GEN6_HIZ_STENCIL
)
3695 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3699 case GL_TEXTURE_1D_ARRAY
:
3700 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3701 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3704 case GL_TEXTURE_2D_ARRAY
:
3705 case GL_TEXTURE_RECTANGLE
:
3706 case GL_TEXTURE_2D_MULTISAMPLE
:
3707 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3708 case GL_TEXTURE_EXTERNAL_OES
:
3709 return ISL_DIM_LAYOUT_GEN4_2D
;
3711 case GL_TEXTURE_CUBE_MAP
:
3712 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3713 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3714 ISL_DIM_LAYOUT_GEN4_2D
);
3717 return (devinfo
->gen
>= 9 ?
3718 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3721 unreachable("Invalid texture target");
3725 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3727 if (mt
->format
== MESA_FORMAT_S_UINT8
)
3728 return ISL_TILING_W
;
3729 return mt
->surf
.tiling
;
3733 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3734 const struct intel_mipmap_tree
*mt
,
3735 struct isl_surf
*surf
)
3737 surf
->dim
= get_isl_surf_dim(mt
->target
);
3738 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3739 mt
->surf
.tiling
, mt
->target
,
3741 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3742 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3743 surf
->row_pitch
= mt
->surf
.row_pitch
;
3744 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3746 if (brw
->gen
>= 9) {
3747 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3748 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3749 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3751 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3752 * alignment in terms of surface elements like we want.
3754 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3757 /* On earlier gens it's stored in pixels. */
3759 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3760 surf
->image_alignment_el
=
3761 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3764 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3765 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3766 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3767 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3768 surf
->logical_level0_px
.array_len
= 1;
3770 surf
->logical_level0_px
.depth
= 1;
3771 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3774 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3775 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3776 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3777 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3778 surf
->phys_level0_sa
.array_len
= 1;
3780 surf
->phys_level0_sa
.depth
= 1;
3781 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3784 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3785 surf
->samples
= mt
->surf
.samples
;
3787 surf
->size
= 0; /* TODO */
3788 surf
->alignment
= 0; /* TODO */
3790 switch (surf
->dim_layout
) {
3791 case ISL_DIM_LAYOUT_GEN4_2D
:
3792 case ISL_DIM_LAYOUT_GEN4_3D
:
3793 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3794 if (brw
->gen
>= 9) {
3795 surf
->array_pitch_el_rows
= mt
->qpitch
;
3798 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3799 assert(mt
->qpitch
% bh
== 0);
3800 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3803 case ISL_DIM_LAYOUT_GEN9_1D
:
3804 surf
->array_pitch_el_rows
= 1;
3808 switch (mt
->array_layout
) {
3809 case ALL_LOD_IN_EACH_SLICE
:
3810 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3812 case ALL_SLICES_AT_EACH_LOD
:
3813 case GEN6_HIZ_STENCIL
:
3814 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3817 unreachable("Invalid array layout");
3820 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3821 switch (base_format
) {
3822 case GL_DEPTH_COMPONENT
:
3823 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3825 case GL_STENCIL_INDEX
:
3826 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3828 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3830 case GL_DEPTH_STENCIL
:
3831 /* In this case we only texture from the depth part */
3832 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3833 ISL_SURF_USAGE_TEXTURE_BIT
;
3836 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3837 if (brw
->mesa_format_supports_render
[mt
->format
])
3838 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3842 if (_mesa_is_cube_map_texture(mt
->target
))
3843 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3847 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3848 const struct intel_mipmap_tree
*mt
)
3851 return ISL_AUX_USAGE_HIZ
;
3854 return ISL_AUX_USAGE_NONE
;
3856 return mt
->aux_usage
;