2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return isl_format_supports_lossless_compression(&brw
->screen
->devinfo
,
271 /* On Gen9 support for color buffer compression was extended to single
272 * sampled surfaces. This is a helper considering both auxiliary buffer
273 * type and number of samples telling if the given miptree represents
274 * the new single sampled case - also called lossless compression.
277 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
278 const struct intel_mipmap_tree
*mt
)
280 /* Only available from Gen9 onwards. */
284 /* Compression always requires auxiliary buffer. */
288 /* Single sample compression is represented re-using msaa compression
289 * layout type: "Compressed Multisampled Surfaces".
291 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
294 /* And finally distinguish between msaa and single sample case. */
295 return mt
->num_samples
<= 1;
299 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
300 const struct intel_mipmap_tree
*mt
)
302 /* For now compression is only enabled for integer formats even though
303 * there exist supported floating point formats also. This is a heuristic
304 * decision based on current public benchmarks. In none of the cases these
305 * formats provided any improvement but a few cases were seen to regress.
306 * Hence these are left to to be enabled in the future when they are known
309 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
312 /* Fast clear mechanism and lossless compression go hand in hand. */
313 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
316 /* Fast clear can be also used to clear srgb surfaces by using equivalent
317 * linear format. This trick, however, can't be extended to be used with
318 * lossless compression and therefore a check is needed to see if the format
321 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
325 * Determine depth format corresponding to a depth+stencil format,
326 * for separate stencil.
329 intel_depth_format_for_depthstencil_format(mesa_format format
) {
331 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
332 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
333 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
334 return MESA_FORMAT_Z_FLOAT32
;
342 * @param for_bo Indicates that the caller is
343 * intel_miptree_create_for_bo(). If true, then do not create
346 static struct intel_mipmap_tree
*
347 intel_miptree_create_layout(struct brw_context
*brw
,
356 uint32_t layout_flags
)
358 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
362 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
363 _mesa_enum_to_string(target
),
364 _mesa_get_format_name(format
),
365 first_level
, last_level
, depth0
, mt
);
367 if (target
== GL_TEXTURE_1D_ARRAY
)
368 assert(height0
== 1);
372 mt
->first_level
= first_level
;
373 mt
->last_level
= last_level
;
374 mt
->logical_width0
= width0
;
375 mt
->logical_height0
= height0
;
376 mt
->logical_depth0
= depth0
;
377 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
378 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
379 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
380 exec_list_make_empty(&mt
->hiz_map
);
381 mt
->cpp
= _mesa_get_format_bytes(format
);
382 mt
->num_samples
= num_samples
;
383 mt
->compressed
= _mesa_is_format_compressed(format
);
384 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
387 int depth_multiply
= 1;
388 if (num_samples
> 1) {
389 /* Adjust width/height/depth for MSAA */
390 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
391 mt
->disable_aux_buffers
);
392 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
393 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
394 * "If the surface is multisampled and it is a depth or stencil
395 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
396 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
399 * +----------------------------------------------------------------+
400 * | Num Multisamples | W_l = | H_l = |
401 * +----------------------------------------------------------------+
402 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
403 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
404 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
405 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
406 * +----------------------------------------------------------------+
409 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
410 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
411 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
413 * Another more complicated explanation for these adjustments comes
414 * from the Sandybridge PRM, volume 4, part 1, page 31:
416 * "Any of the other messages (sample*, LOD, load4) used with a
417 * (4x) multisampled surface will in-effect sample a surface with
418 * double the height and width as that indicated in the surface
419 * state. Each pixel position on the original-sized surface is
420 * replaced with a 2x2 of samples with the following arrangement:
425 * Thus, when sampling from a multisampled texture, it behaves as
426 * though the layout in memory for (x,y,sample) is:
428 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
429 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
431 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
432 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
434 * However, the actual layout of multisampled data in memory is:
436 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
437 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
439 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
440 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
442 * This pattern repeats for each 2x2 pixel block.
444 * As a result, when calculating the size of our 4-sample buffer for
445 * an odd width or height, we have to align before scaling up because
446 * sample 3 is in that bottom right 2x2 block.
448 switch (num_samples
) {
450 assert(brw
->gen
>= 8);
451 width0
= ALIGN(width0
, 2) * 2;
452 height0
= ALIGN(height0
, 2);
455 width0
= ALIGN(width0
, 2) * 2;
456 height0
= ALIGN(height0
, 2) * 2;
459 width0
= ALIGN(width0
, 2) * 4;
460 height0
= ALIGN(height0
, 2) * 2;
463 width0
= ALIGN(width0
, 2) * 4;
464 height0
= ALIGN(height0
, 2) * 4;
467 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
470 unreachable("not reached");
473 /* Non-interleaved */
474 depth_multiply
= num_samples
;
475 depth0
*= depth_multiply
;
479 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
480 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
481 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
482 * used on Gen8 to make it pick a qpitch value which doesn't include space
483 * for the mipmaps. On Gen9 this is not necessary because it will
484 * automatically pick a packed qpitch value whenever mt->first_level ==
486 * TODO: can we use it elsewhere?
487 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
490 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
492 switch (mt
->msaa_layout
) {
493 case INTEL_MSAA_LAYOUT_NONE
:
494 case INTEL_MSAA_LAYOUT_IMS
:
495 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
497 case INTEL_MSAA_LAYOUT_UMS
:
498 case INTEL_MSAA_LAYOUT_CMS
:
499 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
504 if (target
== GL_TEXTURE_CUBE_MAP
)
505 assert(depth0
== 6 * depth_multiply
);
507 mt
->physical_width0
= width0
;
508 mt
->physical_height0
= height0
;
509 mt
->physical_depth0
= depth0
;
511 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
512 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
513 (brw
->must_use_separate_stencil
||
514 (brw
->has_separate_stencil
&&
515 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
516 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
518 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
519 MIPTREE_LAYOUT_TILING_ANY
;
522 mt
->stencil_mt
= intel_miptree_create(brw
,
533 if (!mt
->stencil_mt
) {
534 intel_miptree_release(&mt
);
537 mt
->stencil_mt
->r8stencil_needs_update
= true;
539 /* Fix up the Z miptree format for how we're splitting out separate
540 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
542 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
545 if (format
== mt
->format
) {
546 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
547 _mesa_get_format_name(mt
->format
));
551 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
552 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
555 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
556 * multisampled or have an AUX buffer attached to it.
558 * GEN | MSRT | AUX_CCS_* or AUX_MCS
559 * -------------------------------------------
560 * 9 | HALIGN_16 | HALIGN_16
561 * 8 | HALIGN_ANY | HALIGN_16
565 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
566 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
567 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
568 } else if (brw
->gen
>= 9 && num_samples
> 1) {
569 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
571 const UNUSED
bool is_lossless_compressed_aux
=
572 brw
->gen
>= 9 && num_samples
== 1 &&
573 mt
->format
== MESA_FORMAT_R_UINT32
;
575 /* For now, nothing else has this requirement */
576 assert(is_lossless_compressed_aux
||
577 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
580 brw_miptree_layout(brw
, mt
, layout_flags
);
582 if (mt
->disable_aux_buffers
)
583 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
590 * Choose an appropriate uncompressed format for a requested
591 * compressed format, if unsupported.
594 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
596 /* No need to lower ETC formats on these platforms,
597 * they are supported natively.
599 if (brw
->gen
>= 8 || brw
->is_baytrail
)
603 case MESA_FORMAT_ETC1_RGB8
:
604 return MESA_FORMAT_R8G8B8X8_UNORM
;
605 case MESA_FORMAT_ETC2_RGB8
:
606 return MESA_FORMAT_R8G8B8X8_UNORM
;
607 case MESA_FORMAT_ETC2_SRGB8
:
608 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
609 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
610 return MESA_FORMAT_B8G8R8A8_SRGB
;
611 case MESA_FORMAT_ETC2_RGBA8_EAC
:
612 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
613 return MESA_FORMAT_R8G8B8A8_UNORM
;
614 case MESA_FORMAT_ETC2_R11_EAC
:
615 return MESA_FORMAT_R_UNORM16
;
616 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
617 return MESA_FORMAT_R_SNORM16
;
618 case MESA_FORMAT_ETC2_RG11_EAC
:
619 return MESA_FORMAT_R16G16_UNORM
;
620 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
621 return MESA_FORMAT_R16G16_SNORM
;
623 /* Non ETC1 / ETC2 format */
628 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
630 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
631 unsigned long *pitch
)
633 uint32_t tile_width
, tile_height
;
634 unsigned long stride
, size
, aligned_y
;
636 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
637 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
638 &tile_width
, &tile_height
);
640 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
641 stride
= mt
->total_width
* mt
->cpp
;
642 stride
= ALIGN(stride
, tile_width
);
643 size
= stride
* aligned_y
;
645 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
646 assert(size
% 4096 == 0);
649 assert(size
% (64 * 1024) == 0);
650 *alignment
= 64 * 1024;
656 static struct intel_mipmap_tree
*
657 miptree_create(struct brw_context
*brw
,
666 uint32_t layout_flags
)
668 struct intel_mipmap_tree
*mt
;
669 mesa_format tex_format
= format
;
670 mesa_format etc_format
= MESA_FORMAT_NONE
;
671 uint32_t alloc_flags
= 0;
673 format
= intel_lower_compressed_format(brw
, format
);
675 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
677 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
678 mt
= intel_miptree_create_layout(brw
, target
, format
,
679 first_level
, last_level
, width0
,
680 height0
, depth0
, num_samples
,
683 * pitch == 0 || height == 0 indicates the null texture
685 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
686 intel_miptree_release(&mt
);
690 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
691 mt
->tiling
= I915_TILING_Y
;
693 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
694 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
697 mt
->etc_format
= etc_format
;
699 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
700 unsigned alignment
= 0;
702 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
704 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
707 if (format
== MESA_FORMAT_S_UINT8
) {
708 /* Align to size of W tile, 64x64. */
709 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
710 ALIGN(mt
->total_width
, 64),
711 ALIGN(mt
->total_height
, 64),
712 mt
->cpp
, &mt
->tiling
, &pitch
,
715 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
716 mt
->total_width
, mt
->total_height
,
717 mt
->cpp
, &mt
->tiling
, &pitch
,
727 struct intel_mipmap_tree
*
728 intel_miptree_create(struct brw_context
*brw
,
737 uint32_t layout_flags
)
739 struct intel_mipmap_tree
*mt
= miptree_create(
741 first_level
, last_level
,
742 width0
, height0
, depth0
, num_samples
,
745 /* If the BO is too large to fit in the aperture, we need to use the
746 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
747 * handle Y-tiling, so we need to fall back to X.
749 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
750 mt
->tiling
== I915_TILING_Y
) {
751 unsigned long pitch
= mt
->pitch
;
752 const uint32_t alloc_flags
=
753 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
754 BO_ALLOC_FOR_RENDER
: 0;
755 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
756 mt
->total_width
, mt
->total_height
);
758 mt
->tiling
= I915_TILING_X
;
759 drm_intel_bo_unreference(mt
->bo
);
760 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
761 mt
->total_width
, mt
->total_height
, mt
->cpp
,
762 &mt
->tiling
, &pitch
, alloc_flags
);
769 intel_miptree_release(&mt
);
774 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
775 assert(mt
->num_samples
> 1);
776 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
777 intel_miptree_release(&mt
);
782 /* If this miptree is capable of supporting fast color clears, set
783 * fast_clear_state appropriately to ensure that fast clears will occur.
784 * Allocation of the MCS miptree will be deferred until the first fast
785 * clear actually occurs or when compressed single sampled buffer is
786 * written by the GPU for the first time.
788 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
789 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
790 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
791 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
793 /* On Gen9+ clients are not currently capable of consuming compressed
794 * single-sampled buffers. Disabling compression allows us to skip
797 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
798 const bool is_lossless_compressed
=
799 unlikely(!lossless_compression_disabled
) &&
800 brw
->gen
>= 9 && !mt
->is_scanout
&&
801 intel_miptree_supports_lossless_compressed(brw
, mt
);
803 if (is_lossless_compressed
) {
804 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
811 struct intel_mipmap_tree
*
812 intel_miptree_create_for_bo(struct brw_context
*brw
,
820 uint32_t layout_flags
)
822 struct intel_mipmap_tree
*mt
;
823 uint32_t tiling
, swizzle
;
826 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
828 /* Nothing will be able to use this miptree with the BO if the offset isn't
831 if (tiling
!= I915_TILING_NONE
)
832 assert(offset
% 4096 == 0);
834 /* miptrees can't handle negative pitch. If you need flipping of images,
835 * that's outside of the scope of the mt.
839 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
841 /* The BO already has a tiling format and we shouldn't confuse the lower
842 * layers by making it try to find a tiling format again.
844 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
845 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
847 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
848 mt
= intel_miptree_create_layout(brw
, target
, format
,
850 width
, height
, depth
, 0,
855 drm_intel_bo_reference(bo
);
865 * For a singlesample renderbuffer, this simply wraps the given BO with a
868 * For a multisample renderbuffer, this wraps the window system's
869 * (singlesample) BO with a singlesample miptree attached to the
870 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
871 * that will contain the actual rendering (which is lazily resolved to
872 * irb->singlesample_mt).
875 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
876 struct intel_renderbuffer
*irb
,
878 uint32_t width
, uint32_t height
,
881 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
882 struct intel_mipmap_tree
*multisample_mt
= NULL
;
883 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
884 mesa_format format
= rb
->Format
;
885 int num_samples
= rb
->NumSamples
;
887 /* Only the front and back buffers, which are color buffers, are allocated
888 * through the image loader.
890 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
891 _mesa_get_format_base_format(format
) == GL_RGBA
);
893 singlesample_mt
= intel_miptree_create_for_bo(intel
,
901 MIPTREE_LAYOUT_FOR_SCANOUT
);
902 if (!singlesample_mt
)
905 /* If this miptree is capable of supporting fast color clears, set
906 * mcs_state appropriately to ensure that fast clears will occur.
907 * Allocation of the MCS miptree will be deferred until the first fast
908 * clear actually occurs.
910 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
911 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
912 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
915 if (num_samples
== 0) {
916 intel_miptree_release(&irb
->mt
);
917 irb
->mt
= singlesample_mt
;
919 assert(!irb
->singlesample_mt
);
921 intel_miptree_release(&irb
->singlesample_mt
);
922 irb
->singlesample_mt
= singlesample_mt
;
925 irb
->mt
->logical_width0
!= width
||
926 irb
->mt
->logical_height0
!= height
) {
927 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
935 irb
->need_downsample
= false;
936 intel_miptree_release(&irb
->mt
);
937 irb
->mt
= multisample_mt
;
943 intel_miptree_release(&irb
->singlesample_mt
);
944 intel_miptree_release(&irb
->mt
);
948 struct intel_mipmap_tree
*
949 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
953 uint32_t num_samples
)
955 struct intel_mipmap_tree
*mt
;
958 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
959 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
960 MIPTREE_LAYOUT_TILING_ANY
|
961 MIPTREE_LAYOUT_FOR_SCANOUT
;
963 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
964 width
, height
, depth
, num_samples
,
969 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
970 ok
= intel_miptree_alloc_hiz(brw
, mt
);
978 intel_miptree_release(&mt
);
983 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
984 struct intel_mipmap_tree
*src
)
989 intel_miptree_release(dst
);
993 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1001 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1006 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1007 if (--(*mt
)->refcount
<= 0) {
1010 DBG("%s deleting %p\n", __func__
, *mt
);
1012 drm_intel_bo_unreference((*mt
)->bo
);
1013 intel_miptree_release(&(*mt
)->stencil_mt
);
1014 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1015 if ((*mt
)->hiz_buf
) {
1016 if ((*mt
)->hiz_buf
->mt
)
1017 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1019 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1020 free((*mt
)->hiz_buf
);
1022 if ((*mt
)->mcs_buf
) {
1023 intel_miptree_release(&(*mt
)->mcs_buf
->mt
);
1024 free((*mt
)->mcs_buf
);
1026 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1028 intel_miptree_release(&(*mt
)->plane
[0]);
1029 intel_miptree_release(&(*mt
)->plane
[1]);
1031 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1032 free((*mt
)->level
[i
].slice
);
1042 intel_get_image_dims(struct gl_texture_image
*image
,
1043 int *width
, int *height
, int *depth
)
1045 switch (image
->TexObject
->Target
) {
1046 case GL_TEXTURE_1D_ARRAY
:
1047 /* For a 1D Array texture the OpenGL API will treat the image height as
1048 * the number of array slices. For Intel hardware, we treat the 1D array
1049 * as a 2D Array with a height of 1. So, here we want to swap image
1052 assert(image
->Depth
== 1);
1053 *width
= image
->Width
;
1055 *depth
= image
->Height
;
1057 case GL_TEXTURE_CUBE_MAP
:
1058 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1059 * though we really have 6 slices.
1061 assert(image
->Depth
== 1);
1062 *width
= image
->Width
;
1063 *height
= image
->Height
;
1067 *width
= image
->Width
;
1068 *height
= image
->Height
;
1069 *depth
= image
->Depth
;
1075 * Can the image be pulled into a unified mipmap tree? This mirrors
1076 * the completeness test in a lot of ways.
1078 * Not sure whether I want to pass gl_texture_image here.
1081 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1082 struct gl_texture_image
*image
)
1084 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1085 GLuint level
= intelImage
->base
.Base
.Level
;
1086 int width
, height
, depth
;
1088 /* glTexImage* choose the texture object based on the target passed in, and
1089 * objects can't change targets over their lifetimes, so this should be
1092 assert(image
->TexObject
->Target
== mt
->target
);
1094 mesa_format mt_format
= mt
->format
;
1095 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1096 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1097 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1098 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1099 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1100 mt_format
= mt
->etc_format
;
1102 if (image
->TexFormat
!= mt_format
)
1105 intel_get_image_dims(image
, &width
, &height
, &depth
);
1107 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1110 int level_depth
= mt
->level
[level
].depth
;
1111 if (mt
->num_samples
> 1) {
1112 switch (mt
->msaa_layout
) {
1113 case INTEL_MSAA_LAYOUT_NONE
:
1114 case INTEL_MSAA_LAYOUT_IMS
:
1116 case INTEL_MSAA_LAYOUT_UMS
:
1117 case INTEL_MSAA_LAYOUT_CMS
:
1118 level_depth
/= mt
->num_samples
;
1123 /* Test image dimensions against the base level image adjusted for
1124 * minification. This will also catch images not present in the
1125 * tree, changed targets, etc.
1127 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1128 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1129 depth
!= level_depth
) {
1133 if (image
->NumSamples
!= mt
->num_samples
)
1141 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1143 GLuint x
, GLuint y
, GLuint d
)
1145 mt
->level
[level
].depth
= d
;
1146 mt
->level
[level
].level_x
= x
;
1147 mt
->level
[level
].level_y
= y
;
1149 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1152 assert(mt
->level
[level
].slice
== NULL
);
1154 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1155 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1156 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1161 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1162 GLuint level
, GLuint img
,
1165 if (img
== 0 && level
== 0)
1166 assert(x
== 0 && y
== 0);
1168 assert(img
< mt
->level
[level
].depth
);
1170 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1171 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1173 DBG("%s level %d img %d pos %d,%d\n",
1174 __func__
, level
, img
,
1175 mt
->level
[level
].slice
[img
].x_offset
,
1176 mt
->level
[level
].slice
[img
].y_offset
);
1180 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1181 GLuint level
, GLuint slice
,
1182 GLuint
*x
, GLuint
*y
)
1184 assert(slice
< mt
->level
[level
].depth
);
1186 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1187 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1192 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1193 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1194 * and tile_h is set to 1.
1197 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1198 uint32_t *tile_w
, uint32_t *tile_h
)
1200 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1210 case I915_TILING_NONE
:
1215 unreachable("not reached");
1218 uint32_t aspect_ratio
= 1;
1219 assert(_mesa_is_pow_two(cpp
));
1234 unreachable("not reached");
1237 if (cpp
== 2 || cpp
== 8)
1240 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1243 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1249 * This function computes masks that may be used to select the bits of the X
1250 * and Y coordinates that indicate the offset within a tile. If the BO is
1251 * untiled, the masks are set to 0.
1254 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1255 uint32_t *mask_x
, uint32_t *mask_y
)
1257 uint32_t tile_w_bytes
, tile_h
;
1259 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1261 *mask_x
= tile_w_bytes
/ cpp
- 1;
1262 *mask_y
= tile_h
- 1;
1266 * Compute the offset (in bytes) from the start of the BO to the given x
1267 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1268 * multiples of the tile size.
1271 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1272 uint32_t x
, uint32_t y
)
1275 uint32_t pitch
= mt
->pitch
;
1276 uint32_t tiling
= mt
->tiling
;
1280 unreachable("not reached");
1281 case I915_TILING_NONE
:
1282 return y
* pitch
+ x
* cpp
;
1284 assert((x
% (512 / cpp
)) == 0);
1285 assert((y
% 8) == 0);
1286 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1288 assert((x
% (128 / cpp
)) == 0);
1289 assert((y
% 32) == 0);
1290 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1295 * Rendering with tiled buffers requires that the base address of the buffer
1296 * be aligned to a page boundary. For renderbuffers, and sometimes with
1297 * textures, we may want the surface to point at a texture image level that
1298 * isn't at a page boundary.
1300 * This function returns an appropriately-aligned base offset
1301 * according to the tiling restrictions, plus any required x/y offset
1305 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1306 GLuint level
, GLuint slice
,
1311 uint32_t mask_x
, mask_y
;
1313 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, &mask_x
, &mask_y
);
1314 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1316 *tile_x
= x
& mask_x
;
1317 *tile_y
= y
& mask_y
;
1319 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1323 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1324 struct intel_mipmap_tree
*dst_mt
,
1325 struct intel_mipmap_tree
*src_mt
,
1332 ptrdiff_t src_stride
, dst_stride
;
1333 int cpp
= dst_mt
->cpp
;
1335 intel_miptree_map(brw
, src_mt
,
1339 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1342 intel_miptree_map(brw
, dst_mt
,
1346 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1350 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1351 _mesa_get_format_name(src_mt
->format
),
1352 src_mt
, src
, src_stride
,
1353 _mesa_get_format_name(dst_mt
->format
),
1354 dst_mt
, dst
, dst_stride
,
1357 int row_size
= cpp
* width
;
1358 if (src_stride
== row_size
&&
1359 dst_stride
== row_size
) {
1360 memcpy(dst
, src
, row_size
* height
);
1362 for (int i
= 0; i
< height
; i
++) {
1363 memcpy(dst
, src
, row_size
);
1369 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1370 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1372 /* Don't forget to copy the stencil data over, too. We could have skipped
1373 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1374 * shuffling the two data sources in/out of temporary storage instead of
1375 * the direct mapping we get this way.
1377 if (dst_mt
->stencil_mt
) {
1378 assert(src_mt
->stencil_mt
);
1379 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1380 level
, slice
, width
, height
);
1385 intel_miptree_copy_slice(struct brw_context
*brw
,
1386 struct intel_mipmap_tree
*dst_mt
,
1387 struct intel_mipmap_tree
*src_mt
,
1393 mesa_format format
= src_mt
->format
;
1394 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1395 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1403 assert(depth
< src_mt
->level
[level
].depth
);
1404 assert(src_mt
->format
== dst_mt
->format
);
1406 if (dst_mt
->compressed
) {
1408 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1409 height
= ALIGN_NPOT(height
, j
) / j
;
1410 width
= ALIGN_NPOT(width
, i
) / i
;
1413 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1414 * below won't apply since we can't do the depth's Y tiling or the
1415 * stencil's W tiling in the blitter.
1417 if (src_mt
->stencil_mt
) {
1418 intel_miptree_copy_slice_sw(brw
,
1425 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1426 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1427 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1429 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1430 _mesa_get_format_name(src_mt
->format
),
1431 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1432 _mesa_get_format_name(dst_mt
->format
),
1433 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1436 if (!intel_miptree_blit(brw
,
1437 src_mt
, level
, slice
, 0, 0, false,
1438 dst_mt
, level
, slice
, 0, 0, false,
1439 width
, height
, GL_COPY
)) {
1440 perf_debug("miptree validate blit for %s failed\n",
1441 _mesa_get_format_name(format
));
1443 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1449 * Copies the image's current data to the given miptree, and associates that
1450 * miptree with the image.
1452 * If \c invalidate is true, then the actual image data does not need to be
1453 * copied, but the image still needs to be associated to the new miptree (this
1454 * is set to true if we're about to clear the image).
1457 intel_miptree_copy_teximage(struct brw_context
*brw
,
1458 struct intel_texture_image
*intelImage
,
1459 struct intel_mipmap_tree
*dst_mt
,
1462 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1463 struct intel_texture_object
*intel_obj
=
1464 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1465 int level
= intelImage
->base
.Base
.Level
;
1466 int face
= intelImage
->base
.Base
.Face
;
1469 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1470 depth
= intelImage
->base
.Base
.Height
;
1472 depth
= intelImage
->base
.Base
.Depth
;
1475 for (int slice
= 0; slice
< depth
; slice
++) {
1476 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1480 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1481 intel_obj
->needs_validate
= true;
1485 intel_miptree_init_mcs(struct brw_context
*brw
,
1486 struct intel_mipmap_tree
*mt
,
1489 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1491 * When MCS buffer is enabled and bound to MSRT, it is required that it
1492 * is cleared prior to any rendering.
1494 * Since we don't use the MCS buffer for any purpose other than rendering,
1495 * it makes sense to just clear it immediately upon allocation.
1497 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1499 const int ret
= brw_bo_map_gtt(brw
, mt
->mcs_buf
->bo
, "miptree");
1500 if (unlikely(ret
)) {
1501 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1502 intel_miptree_release(&mt
->mcs_buf
->mt
);
1506 void *data
= mt
->mcs_buf
->bo
->virtual;
1507 memset(data
, init_value
,
1508 mt
->mcs_buf
->mt
->total_height
* mt
->mcs_buf
->mt
->pitch
);
1509 drm_intel_bo_unmap(mt
->mcs_buf
->bo
);
1510 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1513 static struct intel_miptree_aux_buffer
*
1514 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1515 struct intel_mipmap_tree
*mt
,
1518 unsigned mcs_height
,
1519 uint32_t layout_flags
)
1521 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1526 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1528 * "The MCS surface must be stored as Tile Y."
1530 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1531 buf
->mt
= miptree_create(brw
,
1539 0 /* num_samples */,
1546 buf
->bo
= buf
->mt
->bo
;
1547 buf
->pitch
= buf
->mt
->pitch
;
1548 buf
->qpitch
= buf
->mt
->qpitch
;
1554 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1555 struct intel_mipmap_tree
*mt
,
1558 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1559 assert(mt
->mcs_buf
== NULL
);
1560 assert(!mt
->disable_aux_buffers
);
1562 /* Choose the correct format for the MCS buffer. All that really matters
1563 * is that we allocate the right buffer size, since we'll always be
1564 * accessing this miptree using MCS-specific hardware mechanisms, which
1565 * infer the correct format based on num_samples.
1568 switch (num_samples
) {
1571 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1574 format
= MESA_FORMAT_R_UNORM8
;
1577 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1578 * for each sample, plus 8 padding bits).
1580 format
= MESA_FORMAT_R_UINT32
;
1583 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1586 format
= MESA_FORMAT_RG_UINT32
;
1589 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1593 intel_mcs_miptree_buf_create(brw
, mt
,
1596 mt
->logical_height0
,
1597 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1599 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1601 return mt
->mcs_buf
!= NULL
;
1606 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1607 struct intel_mipmap_tree
*mt
,
1608 bool is_lossless_compressed
)
1610 assert(mt
->mcs_buf
== NULL
);
1611 assert(!mt
->disable_aux_buffers
);
1613 /* The format of the MCS buffer is opaque to the driver; all that matters
1614 * is that we get its size and pitch right. We'll pretend that the format
1615 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1616 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1617 * the block width and then a further factor of 4. Since an MCS tile
1618 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1619 * we'll need to scale the height down by the block height and then a
1620 * further factor of 8.
1622 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1623 unsigned block_width_px
;
1624 unsigned block_height
;
1625 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1626 unsigned width_divisor
= block_width_px
* 4;
1627 unsigned height_divisor
= block_height
* 8;
1629 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1631 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1632 * in the main surface. In Skylake, it's two bits. The extra bit
1633 * doubles the MCS height, not width, because in Skylake the MCS is always
1637 height_divisor
/= 2;
1639 unsigned mcs_width
=
1640 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1641 unsigned mcs_height
=
1642 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1643 assert(mt
->logical_depth0
== 1);
1645 uint32_t layout_flags
=
1646 (brw
->gen
>= 8) ? MIPTREE_LAYOUT_FORCE_HALIGN16
: 0;
1647 /* In case of compression mcs buffer needs to be initialised requiring the
1648 * buffer to be immediately mapped to cpu space for writing. Therefore do
1649 * not use the gpu access flag which can cause an unnecessary delay if the
1650 * backing pages happened to be just used by the GPU.
1652 if (!is_lossless_compressed
)
1653 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1655 mt
->mcs_buf
= intel_mcs_miptree_buf_create(brw
, mt
,
1661 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1662 * used for lossless compression which requires similar initialisation
1663 * as multi-sample compression.
1665 if (is_lossless_compressed
) {
1666 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1667 * resolve. Initialize it accordingly in case the first renderer is
1668 * cpu (or other none compression aware party).
1670 * This is also explicitly stated in the spec (MCS Buffer for Render
1672 * "If Software wants to enable Color Compression without Fast clear,
1673 * Software needs to initialize MCS with zeros."
1675 intel_miptree_init_mcs(brw
, mt
, 0);
1676 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1677 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1680 return mt
->mcs_buf
!= NULL
;
1684 * Helper for intel_miptree_alloc_hiz() that sets
1685 * \c mt->level[level].has_hiz. Return true if and only if
1686 * \c has_hiz was set.
1689 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1690 struct intel_mipmap_tree
*mt
,
1693 assert(mt
->hiz_buf
);
1695 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1696 uint32_t width
= minify(mt
->physical_width0
, level
);
1697 uint32_t height
= minify(mt
->physical_height0
, level
);
1699 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1700 * and the height is 4 aligned. This allows our HiZ support
1701 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1702 * we can grow the width & height to allow the HiZ op to
1703 * force the proper size alignments.
1705 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1706 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1711 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1712 mt
->level
[level
].has_hiz
= true;
1718 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1719 * buffer dimensions and allocates a bo for the hiz buffer.
1721 static struct intel_miptree_aux_buffer
*
1722 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1723 struct intel_mipmap_tree
*mt
)
1725 unsigned z_width
= mt
->logical_width0
;
1726 unsigned z_height
= mt
->logical_height0
;
1727 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1728 unsigned hz_width
, hz_height
;
1729 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1734 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1735 * adjustments required for Z_Height and Z_Width based on multisampling.
1737 switch (mt
->num_samples
) {
1751 unreachable("unsupported sample count");
1754 const unsigned vertical_align
= 8; /* 'j' in the docs */
1755 const unsigned H0
= z_height
;
1756 const unsigned h0
= ALIGN(H0
, vertical_align
);
1757 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1758 const unsigned Z0
= z_depth
;
1760 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1761 hz_width
= ALIGN(z_width
, 16);
1763 if (mt
->target
== GL_TEXTURE_3D
) {
1767 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1768 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1769 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1770 hz_height
+= h_i
* Z_i
;
1771 H_i
= minify(H_i
, 1);
1772 Z_i
= minify(Z_i
, 1);
1775 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1777 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1779 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1780 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1781 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1784 unsigned long pitch
;
1785 uint32_t tiling
= I915_TILING_Y
;
1786 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1787 hz_width
, hz_height
, 1,
1789 BO_ALLOC_FOR_RENDER
);
1793 } else if (tiling
!= I915_TILING_Y
) {
1794 drm_intel_bo_unreference(buf
->bo
);
1806 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1807 * buffer dimensions and allocates a bo for the hiz buffer.
1809 static struct intel_miptree_aux_buffer
*
1810 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1811 struct intel_mipmap_tree
*mt
)
1813 unsigned z_width
= mt
->logical_width0
;
1814 unsigned z_height
= mt
->logical_height0
;
1815 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1816 unsigned hz_width
, hz_height
;
1817 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1822 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1823 * adjustments required for Z_Height and Z_Width based on multisampling.
1826 switch (mt
->num_samples
) {
1840 unreachable("unsupported sample count");
1844 const unsigned vertical_align
= 8; /* 'j' in the docs */
1845 const unsigned H0
= z_height
;
1846 const unsigned h0
= ALIGN(H0
, vertical_align
);
1847 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1848 const unsigned Z0
= z_depth
;
1850 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1851 hz_width
= ALIGN(z_width
, 16);
1855 unsigned sum_h_i
= 0;
1856 unsigned hz_height_3d_sum
= 0;
1857 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1858 unsigned i
= level
- mt
->first_level
;
1859 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1860 /* sum(i=2 to m; h_i) */
1864 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1865 hz_height_3d_sum
+= h_i
* Z_i
;
1866 H_i
= minify(H_i
, 1);
1867 Z_i
= minify(Z_i
, 1);
1869 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1870 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1872 if (mt
->target
== GL_TEXTURE_3D
) {
1873 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1874 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1876 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1877 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1880 unsigned long pitch
;
1881 uint32_t tiling
= I915_TILING_Y
;
1882 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1883 hz_width
, hz_height
, 1,
1885 BO_ALLOC_FOR_RENDER
);
1889 } else if (tiling
!= I915_TILING_Y
) {
1890 drm_intel_bo_unreference(buf
->bo
);
1901 static struct intel_miptree_aux_buffer
*
1902 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1903 struct intel_mipmap_tree
*mt
)
1905 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1906 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1909 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1914 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1915 buf
->mt
= intel_miptree_create(brw
,
1921 mt
->logical_height0
,
1930 buf
->bo
= buf
->mt
->bo
;
1931 buf
->pitch
= buf
->mt
->pitch
;
1932 buf
->qpitch
= buf
->mt
->qpitch
;
1938 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1939 struct intel_mipmap_tree
*mt
)
1944 if (mt
->hiz_buf
!= NULL
)
1947 if (mt
->disable_aux_buffers
)
1950 switch (mt
->format
) {
1951 case MESA_FORMAT_Z_FLOAT32
:
1952 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1953 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1954 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1955 case MESA_FORMAT_Z_UNORM16
:
1963 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1964 struct intel_mipmap_tree
*mt
)
1966 assert(mt
->hiz_buf
== NULL
);
1967 assert(!mt
->disable_aux_buffers
);
1969 if (brw
->gen
== 7) {
1970 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1971 } else if (brw
->gen
>= 8) {
1972 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1974 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1980 /* Mark that all slices need a HiZ resolve. */
1981 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1982 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1985 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1986 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1987 exec_node_init(&m
->link
);
1990 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
1992 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
2000 * Does the miptree slice have hiz enabled?
2003 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2005 intel_miptree_check_level_layer(mt
, level
, 0);
2006 return mt
->level
[level
].has_hiz
;
2010 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2014 if (!intel_miptree_level_has_hiz(mt
, level
))
2017 intel_resolve_map_set(&mt
->hiz_map
,
2018 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2023 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2027 if (!intel_miptree_level_has_hiz(mt
, level
))
2030 intel_resolve_map_set(&mt
->hiz_map
,
2031 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2035 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2039 uint32_t end_layer
= mt
->level
[level
].depth
;
2041 for (layer
= 0; layer
< end_layer
; layer
++) {
2042 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2047 intel_miptree_slice_resolve(struct brw_context
*brw
,
2048 struct intel_mipmap_tree
*mt
,
2051 enum blorp_hiz_op need
)
2053 intel_miptree_check_level_layer(mt
, level
, layer
);
2055 struct intel_resolve_map
*item
=
2056 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2058 if (!item
|| item
->need
!= need
)
2061 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2062 intel_resolve_map_remove(item
);
2067 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2068 struct intel_mipmap_tree
*mt
,
2072 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2073 BLORP_HIZ_OP_HIZ_RESOLVE
);
2077 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2078 struct intel_mipmap_tree
*mt
,
2082 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2083 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2087 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2088 struct intel_mipmap_tree
*mt
,
2089 enum blorp_hiz_op need
)
2091 bool did_resolve
= false;
2093 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2094 if (map
->need
!= need
)
2097 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2098 intel_resolve_map_remove(map
);
2106 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2107 struct intel_mipmap_tree
*mt
)
2109 return intel_miptree_all_slices_resolve(brw
, mt
,
2110 BLORP_HIZ_OP_HIZ_RESOLVE
);
2114 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2115 struct intel_mipmap_tree
*mt
)
2117 return intel_miptree_all_slices_resolve(brw
, mt
,
2118 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2123 intel_miptree_resolve_color(struct brw_context
*brw
,
2124 struct intel_mipmap_tree
*mt
,
2127 /* From gen9 onwards there is new compression scheme for single sampled
2128 * surfaces called "lossless compressed". These don't need to be always
2131 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2132 intel_miptree_is_lossless_compressed(brw
, mt
))
2135 switch (mt
->fast_clear_state
) {
2136 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2137 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2138 /* No resolve needed */
2140 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2141 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2142 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2143 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2144 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2145 brw_blorp_resolve_color(brw
, mt
);
2151 unreachable("Invalid fast clear state");
2157 * Make it possible to share the BO backing the given miptree with another
2158 * process or another miptree.
2160 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2161 * then discard the MCS buffer, if present. We also set the fast_clear_state
2162 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2163 * allocated in the future.
2166 intel_miptree_make_shareable(struct brw_context
*brw
,
2167 struct intel_mipmap_tree
*mt
)
2169 /* MCS buffers are also used for multisample buffers, but we can't resolve
2170 * away a multisample MCS buffer because it's an integral part of how the
2171 * pixel data is stored. Fortunately this code path should never be
2172 * reached for multisample buffers.
2174 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2177 intel_miptree_resolve_color(brw
, mt
, 0);
2178 intel_miptree_release(&mt
->mcs_buf
->mt
);
2179 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2185 * \brief Get pointer offset into stencil buffer.
2187 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2188 * must decode the tile's layout in software.
2191 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2193 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2195 * Even though the returned offset is always positive, the return type is
2197 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2198 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2201 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2203 uint32_t tile_size
= 4096;
2204 uint32_t tile_width
= 64;
2205 uint32_t tile_height
= 64;
2206 uint32_t row_size
= 64 * stride
;
2208 uint32_t tile_x
= x
/ tile_width
;
2209 uint32_t tile_y
= y
/ tile_height
;
2211 /* The byte's address relative to the tile's base addres. */
2212 uint32_t byte_x
= x
% tile_width
;
2213 uint32_t byte_y
= y
% tile_height
;
2215 uintptr_t u
= tile_y
* row_size
2216 + tile_x
* tile_size
2217 + 512 * (byte_x
/ 8)
2219 + 32 * ((byte_y
/ 4) % 2)
2220 + 16 * ((byte_x
/ 4) % 2)
2221 + 8 * ((byte_y
/ 2) % 2)
2222 + 4 * ((byte_x
/ 2) % 2)
2227 /* adjust for bit6 swizzling */
2228 if (((byte_x
/ 8) % 2) == 1) {
2229 if (((byte_y
/ 8) % 2) == 0) {
2241 intel_miptree_updownsample(struct brw_context
*brw
,
2242 struct intel_mipmap_tree
*src
,
2243 struct intel_mipmap_tree
*dst
)
2245 brw_blorp_blit_miptrees(brw
,
2246 src
, 0 /* level */, 0 /* layer */,
2247 src
->format
, SWIZZLE_XYZW
,
2248 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2250 src
->logical_width0
, src
->logical_height0
,
2252 dst
->logical_width0
, dst
->logical_height0
,
2253 GL_NEAREST
, false, false /*mirror x, y*/,
2256 if (src
->stencil_mt
) {
2257 brw_blorp_blit_miptrees(brw
,
2258 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2259 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2260 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2261 dst
->stencil_mt
->format
,
2263 src
->logical_width0
, src
->logical_height0
,
2265 dst
->logical_width0
, dst
->logical_height0
,
2266 GL_NEAREST
, false, false /*mirror x, y*/,
2267 false, false /* decode/encode srgb */);
2272 intel_update_r8stencil(struct brw_context
*brw
,
2273 struct intel_mipmap_tree
*mt
)
2275 assert(brw
->gen
>= 7);
2276 struct intel_mipmap_tree
*src
=
2277 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2278 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2281 if (!mt
->r8stencil_mt
) {
2282 const uint32_t r8stencil_flags
=
2283 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2284 MIPTREE_LAYOUT_DISABLE_AUX
;
2285 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2286 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2288 MESA_FORMAT_R_UINT8
,
2291 src
->logical_width0
,
2292 src
->logical_height0
,
2293 src
->logical_depth0
,
2296 assert(mt
->r8stencil_mt
);
2299 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2301 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2302 const unsigned depth
= src
->level
[level
].depth
;
2303 const int layers_per_blit
=
2304 (dst
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
2305 dst
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
2306 dst
->num_samples
: 1;
2308 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2309 brw_blorp_blit_miptrees(brw
,
2311 src
->format
, SWIZZLE_X
,
2312 dst
, level
, layers_per_blit
* layer
,
2313 MESA_FORMAT_R_UNORM8
,
2315 src
->logical_width0
, src
->logical_height0
,
2317 dst
->logical_width0
, dst
->logical_height0
,
2318 GL_NEAREST
, false, false /*mirror x, y*/,
2319 false, false /* decode/encode srgb */);
2323 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2324 src
->r8stencil_needs_update
= false;
2328 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2330 /* CPU accesses to color buffers don't understand fast color clears, so
2331 * resolve any pending fast color clears before we map.
2333 intel_miptree_resolve_color(brw
, mt
, 0);
2335 drm_intel_bo
*bo
= mt
->bo
;
2337 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2338 intel_batchbuffer_flush(brw
);
2340 if (mt
->tiling
!= I915_TILING_NONE
)
2341 brw_bo_map_gtt(brw
, bo
, "miptree");
2343 brw_bo_map(brw
, bo
, true, "miptree");
2349 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2351 drm_intel_bo_unmap(mt
->bo
);
2355 intel_miptree_map_gtt(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 struct intel_miptree_map
*map
,
2358 unsigned int level
, unsigned int slice
)
2360 unsigned int bw
, bh
;
2362 unsigned int image_x
, image_y
;
2363 intptr_t x
= map
->x
;
2364 intptr_t y
= map
->y
;
2366 /* For compressed formats, the stride is the number of bytes per
2367 * row of blocks. intel_miptree_get_image_offset() already does
2370 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2371 assert(y
% bh
== 0);
2372 assert(x
% bw
== 0);
2376 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2381 /* Note that in the case of cube maps, the caller must have passed the
2382 * slice number referencing the face.
2384 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2388 map
->stride
= mt
->pitch
;
2389 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2392 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2393 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2394 map
->x
, map
->y
, map
->w
, map
->h
,
2395 mt
, _mesa_get_format_name(mt
->format
),
2396 x
, y
, map
->ptr
, map
->stride
);
2400 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2402 intel_miptree_unmap_raw(mt
);
2406 intel_miptree_map_blit(struct brw_context
*brw
,
2407 struct intel_mipmap_tree
*mt
,
2408 struct intel_miptree_map
*map
,
2409 unsigned int level
, unsigned int slice
)
2411 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2412 /* first_level */ 0,
2416 MIPTREE_LAYOUT_TILING_NONE
);
2418 if (!map
->linear_mt
) {
2419 fprintf(stderr
, "Failed to allocate blit temporary\n");
2422 map
->stride
= map
->linear_mt
->pitch
;
2424 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2425 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2426 * invalidate is set, since we'll be writing the whole rectangle from our
2427 * temporary buffer back out.
2429 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2430 if (!intel_miptree_blit(brw
,
2432 map
->x
, map
->y
, false,
2433 map
->linear_mt
, 0, 0,
2435 map
->w
, map
->h
, GL_COPY
)) {
2436 fprintf(stderr
, "Failed to blit\n");
2441 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2443 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2444 map
->x
, map
->y
, map
->w
, map
->h
,
2445 mt
, _mesa_get_format_name(mt
->format
),
2446 level
, slice
, map
->ptr
, map
->stride
);
2451 intel_miptree_release(&map
->linear_mt
);
2457 intel_miptree_unmap_blit(struct brw_context
*brw
,
2458 struct intel_mipmap_tree
*mt
,
2459 struct intel_miptree_map
*map
,
2463 struct gl_context
*ctx
= &brw
->ctx
;
2465 intel_miptree_unmap_raw(map
->linear_mt
);
2467 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2468 bool ok
= intel_miptree_blit(brw
,
2469 map
->linear_mt
, 0, 0,
2472 map
->x
, map
->y
, false,
2473 map
->w
, map
->h
, GL_COPY
);
2474 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2477 intel_miptree_release(&map
->linear_mt
);
2481 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2483 #if defined(USE_SSE41)
2485 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2486 struct intel_mipmap_tree
*mt
,
2487 struct intel_miptree_map
*map
,
2488 unsigned int level
, unsigned int slice
)
2490 assert(map
->mode
& GL_MAP_READ_BIT
);
2491 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2493 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2494 map
->x
, map
->y
, map
->w
, map
->h
,
2495 mt
, _mesa_get_format_name(mt
->format
),
2496 level
, slice
, map
->ptr
, map
->stride
);
2498 /* Map the original image */
2501 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2505 void *src
= intel_miptree_map_raw(brw
, mt
);
2511 src
+= image_y
* mt
->pitch
;
2512 src
+= image_x
* mt
->cpp
;
2514 /* Due to the pixel offsets for the particular image being mapped, our
2515 * src pointer may not be 16-byte aligned. However, if the pitch is
2516 * divisible by 16, then the amount by which it's misaligned will remain
2517 * consistent from row to row.
2519 assert((mt
->pitch
% 16) == 0);
2520 const int misalignment
= ((uintptr_t) src
) & 15;
2522 /* Create an untiled temporary buffer for the mapping. */
2523 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2525 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2527 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2528 /* Offset the destination so it has the same misalignment as src. */
2529 map
->ptr
= map
->buffer
+ misalignment
;
2531 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2533 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2534 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2535 void *src_ptr
= src
+ y
* mt
->pitch
;
2537 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2540 intel_miptree_unmap_raw(mt
);
2544 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2545 struct intel_mipmap_tree
*mt
,
2546 struct intel_miptree_map
*map
,
2550 _mesa_align_free(map
->buffer
);
2557 intel_miptree_map_s8(struct brw_context
*brw
,
2558 struct intel_mipmap_tree
*mt
,
2559 struct intel_miptree_map
*map
,
2560 unsigned int level
, unsigned int slice
)
2562 map
->stride
= map
->w
;
2563 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2567 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2568 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2569 * invalidate is set, since we'll be writing the whole rectangle from our
2570 * temporary buffer back out.
2572 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2573 uint8_t *untiled_s8_map
= map
->ptr
;
2574 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2575 unsigned int image_x
, image_y
;
2577 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2579 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2580 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2581 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2582 x
+ image_x
+ map
->x
,
2583 y
+ image_y
+ map
->y
,
2584 brw
->has_swizzling
);
2585 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2589 intel_miptree_unmap_raw(mt
);
2591 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2592 map
->x
, map
->y
, map
->w
, map
->h
,
2593 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2595 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2596 map
->x
, map
->y
, map
->w
, map
->h
,
2597 mt
, map
->ptr
, map
->stride
);
2602 intel_miptree_unmap_s8(struct brw_context
*brw
,
2603 struct intel_mipmap_tree
*mt
,
2604 struct intel_miptree_map
*map
,
2608 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2609 unsigned int image_x
, image_y
;
2610 uint8_t *untiled_s8_map
= map
->ptr
;
2611 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2613 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2615 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2616 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2617 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2618 image_x
+ x
+ map
->x
,
2619 image_y
+ y
+ map
->y
,
2620 brw
->has_swizzling
);
2621 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2625 intel_miptree_unmap_raw(mt
);
2632 intel_miptree_map_etc(struct brw_context
*brw
,
2633 struct intel_mipmap_tree
*mt
,
2634 struct intel_miptree_map
*map
,
2638 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2639 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2640 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2643 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2644 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2646 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2647 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2648 map
->w
, map
->h
, 1));
2649 map
->ptr
= map
->buffer
;
2653 intel_miptree_unmap_etc(struct brw_context
*brw
,
2654 struct intel_mipmap_tree
*mt
,
2655 struct intel_miptree_map
*map
,
2661 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2666 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2667 + image_y
* mt
->pitch
2668 + image_x
* mt
->cpp
;
2670 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2671 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2672 map
->ptr
, map
->stride
,
2675 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2676 map
->ptr
, map
->stride
,
2677 map
->w
, map
->h
, mt
->etc_format
);
2679 intel_miptree_unmap_raw(mt
);
2684 * Mapping function for packed depth/stencil miptrees backed by real separate
2685 * miptrees for depth and stencil.
2687 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2688 * separate from the depth buffer. Yet at the GL API level, we have to expose
2689 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2690 * be able to map that memory for texture storage and glReadPixels-type
2691 * operations. We give Mesa core that access by mallocing a temporary and
2692 * copying the data between the actual backing store and the temporary.
2695 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2696 struct intel_mipmap_tree
*mt
,
2697 struct intel_miptree_map
*map
,
2698 unsigned int level
, unsigned int slice
)
2700 struct intel_mipmap_tree
*z_mt
= mt
;
2701 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2702 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2703 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2705 map
->stride
= map
->w
* packed_bpp
;
2706 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2710 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2711 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2712 * invalidate is set, since we'll be writing the whole rectangle from our
2713 * temporary buffer back out.
2715 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2716 uint32_t *packed_map
= map
->ptr
;
2717 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2718 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2719 unsigned int s_image_x
, s_image_y
;
2720 unsigned int z_image_x
, z_image_y
;
2722 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2723 &s_image_x
, &s_image_y
);
2724 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2725 &z_image_x
, &z_image_y
);
2727 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2728 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2729 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2730 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2733 brw
->has_swizzling
);
2734 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2736 (map_x
+ z_image_x
));
2737 uint8_t s
= s_map
[s_offset
];
2738 uint32_t z
= z_map
[z_offset
];
2740 if (map_z32f_x24s8
) {
2741 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2742 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2744 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2749 intel_miptree_unmap_raw(s_mt
);
2750 intel_miptree_unmap_raw(z_mt
);
2752 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2754 map
->x
, map
->y
, map
->w
, map
->h
,
2755 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2756 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2757 map
->ptr
, map
->stride
);
2759 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2760 map
->x
, map
->y
, map
->w
, map
->h
,
2761 mt
, map
->ptr
, map
->stride
);
2766 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2767 struct intel_mipmap_tree
*mt
,
2768 struct intel_miptree_map
*map
,
2772 struct intel_mipmap_tree
*z_mt
= mt
;
2773 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2774 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2776 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2777 uint32_t *packed_map
= map
->ptr
;
2778 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2779 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2780 unsigned int s_image_x
, s_image_y
;
2781 unsigned int z_image_x
, z_image_y
;
2783 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2784 &s_image_x
, &s_image_y
);
2785 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2786 &z_image_x
, &z_image_y
);
2788 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2789 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2790 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2791 x
+ s_image_x
+ map
->x
,
2792 y
+ s_image_y
+ map
->y
,
2793 brw
->has_swizzling
);
2794 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2796 (x
+ z_image_x
+ map
->x
));
2798 if (map_z32f_x24s8
) {
2799 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2800 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2802 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2803 s_map
[s_offset
] = packed
>> 24;
2804 z_map
[z_offset
] = packed
;
2809 intel_miptree_unmap_raw(s_mt
);
2810 intel_miptree_unmap_raw(z_mt
);
2812 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2814 map
->x
, map
->y
, map
->w
, map
->h
,
2815 z_mt
, _mesa_get_format_name(z_mt
->format
),
2816 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2817 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2818 map
->ptr
, map
->stride
);
2825 * Create and attach a map to the miptree at (level, slice). Return the
2828 static struct intel_miptree_map
*
2829 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2838 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2843 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2844 mt
->level
[level
].slice
[slice
].map
= map
;
2856 * Release the map at (level, slice).
2859 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2863 struct intel_miptree_map
**map
;
2865 map
= &mt
->level
[level
].slice
[slice
].map
;
2871 can_blit_slice(struct intel_mipmap_tree
*mt
,
2872 unsigned int level
, unsigned int slice
)
2874 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2875 if (mt
->pitch
>= 32768)
2882 use_intel_mipree_map_blit(struct brw_context
*brw
,
2883 struct intel_mipmap_tree
*mt
,
2889 /* It's probably not worth swapping to the blit ring because of
2890 * all the overhead involved. But, we must use blitter for the
2891 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2893 (!(mode
& GL_MAP_WRITE_BIT
) ||
2894 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2896 (mt
->tiling
== I915_TILING_X
||
2897 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2898 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2899 /* Fast copy blit on skl+ supports all tiling formats. */
2901 can_blit_slice(mt
, level
, slice
))
2904 if (mt
->tiling
!= I915_TILING_NONE
&&
2905 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2906 assert(can_blit_slice(mt
, level
, slice
));
2914 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2915 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2916 * arithmetic overflow.
2918 * If you call this function and use \a out_stride, then you're doing pointer
2919 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2920 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2921 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2922 * which usually have type uint32_t or GLuint.
2925 intel_miptree_map(struct brw_context
*brw
,
2926 struct intel_mipmap_tree
*mt
,
2935 ptrdiff_t *out_stride
)
2937 struct intel_miptree_map
*map
;
2939 assert(mt
->num_samples
<= 1);
2941 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2948 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2949 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2950 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2953 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2954 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2955 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2956 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2957 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2958 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2959 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2960 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2961 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2962 #if defined(USE_SSE41)
2963 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2964 !mt
->compressed
&& cpu_has_sse4_1
&&
2965 (mt
->pitch
% 16 == 0)) {
2966 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2969 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2970 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2971 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2974 *out_ptr
= map
->ptr
;
2975 *out_stride
= map
->stride
;
2977 if (map
->ptr
== NULL
)
2978 intel_miptree_release_map(mt
, level
, slice
);
2982 intel_miptree_unmap(struct brw_context
*brw
,
2983 struct intel_mipmap_tree
*mt
,
2987 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2989 assert(mt
->num_samples
<= 1);
2994 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2995 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2997 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2998 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2999 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3000 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3001 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3002 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3003 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3004 } else if (map
->linear_mt
) {
3005 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3006 #if defined(USE_SSE41)
3007 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3008 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3011 intel_miptree_unmap_gtt(mt
);
3014 intel_miptree_release_map(mt
, level
, slice
);
3018 get_isl_surf_dim(GLenum target
)
3022 case GL_TEXTURE_1D_ARRAY
:
3023 return ISL_SURF_DIM_1D
;
3026 case GL_TEXTURE_2D_ARRAY
:
3027 case GL_TEXTURE_RECTANGLE
:
3028 case GL_TEXTURE_CUBE_MAP
:
3029 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3030 case GL_TEXTURE_2D_MULTISAMPLE
:
3031 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3032 case GL_TEXTURE_EXTERNAL_OES
:
3033 return ISL_SURF_DIM_2D
;
3036 return ISL_SURF_DIM_3D
;
3039 unreachable("Invalid texture target");
3043 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3048 case GL_TEXTURE_1D_ARRAY
:
3049 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3050 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3053 case GL_TEXTURE_2D_ARRAY
:
3054 case GL_TEXTURE_RECTANGLE
:
3055 case GL_TEXTURE_2D_MULTISAMPLE
:
3056 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3057 case GL_TEXTURE_EXTERNAL_OES
:
3058 return ISL_DIM_LAYOUT_GEN4_2D
;
3060 case GL_TEXTURE_CUBE_MAP
:
3061 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3062 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3063 ISL_DIM_LAYOUT_GEN4_2D
);
3066 return (devinfo
->gen
>= 9 ?
3067 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3070 unreachable("Invalid texture target");
3074 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3076 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3077 return ISL_TILING_W
;
3079 switch (mt
->tiling
) {
3080 case I915_TILING_NONE
:
3081 return ISL_TILING_LINEAR
;
3083 return ISL_TILING_X
;
3085 switch (mt
->tr_mode
) {
3086 case INTEL_MIPTREE_TRMODE_NONE
:
3087 return ISL_TILING_Y0
;
3088 case INTEL_MIPTREE_TRMODE_YF
:
3089 return ISL_TILING_Yf
;
3090 case INTEL_MIPTREE_TRMODE_YS
:
3091 return ISL_TILING_Ys
;
3093 unreachable("Invalid tiled resource mode");
3096 unreachable("Invalid tiling mode");
3102 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3103 const struct intel_mipmap_tree
*mt
,
3104 struct isl_surf
*surf
)
3106 surf
->dim
= get_isl_surf_dim(mt
->target
);
3107 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3108 mt
->tiling
, mt
->target
);
3110 if (mt
->num_samples
> 1) {
3111 switch (mt
->msaa_layout
) {
3112 case INTEL_MSAA_LAYOUT_IMS
:
3113 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3115 case INTEL_MSAA_LAYOUT_UMS
:
3116 case INTEL_MSAA_LAYOUT_CMS
:
3117 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3120 unreachable("Invalid MSAA layout");
3123 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3126 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3128 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3129 /* The ISL definition of row_pitch matches the surface state pitch field
3130 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3131 * the factor of 2 for W-tiling in row_pitch.
3133 surf
->row_pitch
= 2 * mt
->pitch
;
3135 surf
->row_pitch
= mt
->pitch
;
3138 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3140 if (brw
->gen
>= 9) {
3141 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3142 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3143 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3145 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3146 * alignment in terms of surface elements like we want.
3148 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3151 /* On earlier gens it's stored in pixels. */
3153 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3154 surf
->image_alignment_el
=
3155 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3158 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3159 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3160 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3161 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3162 surf
->logical_level0_px
.array_len
= 1;
3164 surf
->logical_level0_px
.depth
= 1;
3165 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3168 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3169 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3170 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3171 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3172 surf
->phys_level0_sa
.array_len
= 1;
3174 surf
->phys_level0_sa
.depth
= 1;
3175 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3178 surf
->levels
= mt
->last_level
+ 1;
3179 surf
->samples
= MAX2(mt
->num_samples
, 1);
3181 surf
->size
= 0; /* TODO */
3182 surf
->alignment
= 0; /* TODO */
3184 switch (surf
->dim_layout
) {
3185 case ISL_DIM_LAYOUT_GEN4_2D
:
3186 case ISL_DIM_LAYOUT_GEN4_3D
:
3187 if (brw
->gen
>= 9) {
3188 surf
->array_pitch_el_rows
= mt
->qpitch
;
3191 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3192 assert(mt
->qpitch
% bh
== 0);
3193 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3196 case ISL_DIM_LAYOUT_GEN9_1D
:
3197 surf
->array_pitch_el_rows
= 1;
3201 switch (mt
->array_layout
) {
3202 case ALL_LOD_IN_EACH_SLICE
:
3203 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3205 case ALL_SLICES_AT_EACH_LOD
:
3206 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3209 unreachable("Invalid array layout");
3212 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3213 switch (base_format
) {
3214 case GL_DEPTH_COMPONENT
:
3215 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3217 case GL_STENCIL_INDEX
:
3218 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3220 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3222 case GL_DEPTH_STENCIL
:
3223 /* In this case we only texture from the depth part */
3224 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3225 ISL_SURF_USAGE_TEXTURE_BIT
;
3228 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3229 if (brw
->format_supported_as_render_target
[mt
->format
])
3230 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3234 if (_mesa_is_cube_map_texture(mt
->target
))
3235 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3238 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3239 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3240 * PASS IT INTO isl_surf_fill_state.
3243 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3244 const struct intel_mipmap_tree
*mt
,
3245 struct isl_surf
*surf
,
3246 enum isl_aux_usage
*usage
)
3248 uint32_t aux_pitch
, aux_qpitch
;
3250 aux_pitch
= mt
->mcs_buf
->mt
->pitch
;
3251 aux_qpitch
= mt
->mcs_buf
->mt
->qpitch
;
3253 if (mt
->num_samples
> 1) {
3254 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3255 *usage
= ISL_AUX_USAGE_MCS
;
3256 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3257 assert(brw
->gen
>= 9);
3258 *usage
= ISL_AUX_USAGE_CCS_E
;
3259 } else if (mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_NO_MCS
) {
3260 *usage
= ISL_AUX_USAGE_CCS_D
;
3262 unreachable("Invalid MCS miptree");
3264 } else if (mt
->hiz_buf
) {
3265 if (mt
->hiz_buf
->mt
) {
3266 aux_pitch
= mt
->hiz_buf
->mt
->pitch
;
3267 aux_qpitch
= mt
->hiz_buf
->mt
->qpitch
;
3269 aux_pitch
= mt
->hiz_buf
->pitch
;
3270 aux_qpitch
= mt
->hiz_buf
->qpitch
;
3273 *usage
= ISL_AUX_USAGE_HIZ
;
3275 *usage
= ISL_AUX_USAGE_NONE
;
3279 /* Start with a copy of the original surface. */
3280 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3282 /* Figure out the format and tiling of the auxiliary surface */
3284 case ISL_AUX_USAGE_NONE
:
3285 unreachable("Invalid auxiliary usage");
3287 case ISL_AUX_USAGE_HIZ
:
3288 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3291 case ISL_AUX_USAGE_MCS
:
3294 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3295 * HALIGN 16 must be used."
3298 assert(mt
->halign
== 16);
3300 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3303 case ISL_AUX_USAGE_CCS_D
:
3304 case ISL_AUX_USAGE_CCS_E
:
3306 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3308 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3310 * From the hardware spec for GEN9:
3312 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3313 * HALIGN 16 must be used."
3315 assert(mt
->num_samples
<= 1);
3317 assert(mt
->halign
== 16);
3319 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3323 /* We want the pitch of the actual aux buffer. */
3324 surf
->row_pitch
= aux_pitch
;
3326 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3327 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3328 * in elements of the primary color surface so we have to divide by the
3329 * compression block height.
3331 surf
->array_pitch_el_rows
=
3332 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3335 union isl_color_value
3336 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3337 const struct intel_mipmap_tree
*mt
)
3339 union isl_color_value clear_color
;
3341 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3342 clear_color
.i32
[0] = mt
->depth_clear_value
;
3343 clear_color
.i32
[1] = 0;
3344 clear_color
.i32
[2] = 0;
3345 clear_color
.i32
[3] = 0;
3346 } else if (brw
->gen
>= 9) {
3347 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3348 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3349 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3350 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3351 } else if (_mesa_is_format_integer(mt
->format
)) {
3352 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3353 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3354 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3355 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3357 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3358 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3359 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3360 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;