1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 target_to_target(GLenum target
)
55 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
56 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
61 return GL_TEXTURE_CUBE_MAP_ARB
;
69 * Determine which MSAA layout should be used by the MSAA surface being
70 * created, based on the chip generation and the surface type.
72 static enum intel_msaa_layout
73 compute_msaa_layout(struct brw_context
*brw
, gl_format format
, GLenum target
)
75 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
84 return INTEL_MSAA_LAYOUT_IMS
;
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (_mesa_get_format_datatype(format
) == GL_INT
) {
98 /* TODO: is this workaround needed for future chipsets? */
99 assert(brw
->gen
== 7);
100 return INTEL_MSAA_LAYOUT_UMS
;
102 /* For now, if we're going to be texturing from this surface,
103 * force UMS, so that the shader doesn't have to do different things
104 * based on whether there's a multisample control surface needing sampled first.
105 * We can't just blindly read the MCS surface in all cases because:
107 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
109 * If this field is disabled and the sampling engine <ld_mcs> message
110 * is issued on this surface, the MCS surface may be accessed. Software
111 * must ensure that the surface is defined to avoid GTT errors.
113 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
114 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
115 return INTEL_MSAA_LAYOUT_UMS
;
117 return INTEL_MSAA_LAYOUT_CMS
;
125 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
126 * scaled-down bitfield representation of the color buffer which is capable of
127 * recording when blocks of the color buffer are equal to the clear value.
128 * This function returns the block size that will be used by the MCS buffer
129 * corresponding to a certain color miptree.
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p327):
134 * The following table describes the RT alignment
148 * This alignment has the following uses:
150 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
151 * buffer contains 128 blocks horizontally and 256 blocks vertically.
153 * - For figuring out alignment restrictions for a fast clear operation. Fast
154 * clear operations must always clear aligned multiples of 16 blocks
155 * horizontally and 32 blocks vertically.
157 * - For scaling down the coordinates sent through the render pipeline during
158 * a fast clear. X coordinates must be scaled down by 8 times the block
159 * width, and Y coordinates by 16 times the block height.
161 * - For scaling down the coordinates sent through the render pipeline during
162 * a "Render Target Resolve" operation. X coordinates must be scaled down
163 * by half the block width, and Y coordinates by half the block height.
166 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
167 struct intel_mipmap_tree
*mt
,
168 unsigned *width_px
, unsigned *height
)
170 switch (mt
->region
->tiling
) {
172 assert(!"Non-MSRT MCS requires X or Y tiling");
173 /* In release builds, fall through */
175 *width_px
= 32 / mt
->cpp
;
179 *width_px
= 64 / mt
->cpp
;
186 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
189 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
190 * beneath the "Fast Color Clear" bullet (p326):
192 * - Support is limited to tiled render targets.
193 * - Support is for non-mip-mapped and non-array surface types only.
195 * And then later, on p327:
197 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
201 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
202 struct intel_mipmap_tree
*mt
)
204 /* MCS support does not exist prior to Gen7 */
208 /* MCS is only supported for color buffers */
209 switch (_mesa_get_format_base_format(mt
->format
)) {
210 case GL_DEPTH_COMPONENT
:
211 case GL_DEPTH_STENCIL
:
212 case GL_STENCIL_INDEX
:
216 if (mt
->region
->tiling
!= I915_TILING_X
&&
217 mt
->region
->tiling
!= I915_TILING_Y
)
219 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
221 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
223 if (mt
->physical_depth0
!= 1)
226 /* There's no point in using an MCS buffer if the surface isn't in a
229 if (!brw
->format_supported_as_render_target
[mt
->format
])
237 * @param for_bo Indicates that the caller is
238 * intel_miptree_create_for_bo(). If true, then do not create
241 struct intel_mipmap_tree
*
242 intel_miptree_create_layout(struct brw_context
*brw
,
253 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
257 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
258 _mesa_lookup_enum_by_nr(target
),
259 _mesa_get_format_name(format
),
260 first_level
, last_level
, mt
);
262 mt
->target
= target_to_target(target
);
264 mt
->first_level
= first_level
;
265 mt
->last_level
= last_level
;
266 mt
->logical_width0
= width0
;
267 mt
->logical_height0
= height0
;
268 mt
->logical_depth0
= depth0
;
269 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
271 /* The cpp is bytes per (1, blockheight)-sized block for compressed
272 * textures. This is why you'll see divides by blockheight all over
275 _mesa_get_format_block_size(format
, &bw
, &bh
);
276 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
277 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
279 mt
->num_samples
= num_samples
;
280 mt
->compressed
= _mesa_is_format_compressed(format
);
281 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
284 if (num_samples
> 1) {
285 /* Adjust width/height/depth for MSAA */
286 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
287 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
288 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
290 * "Any of the other messages (sample*, LOD, load4) used with a
291 * (4x) multisampled surface will in-effect sample a surface with
292 * double the height and width as that indicated in the surface
293 * state. Each pixel position on the original-sized surface is
294 * replaced with a 2x2 of samples with the following arrangement:
299 * Thus, when sampling from a multisampled texture, it behaves as
300 * though the layout in memory for (x,y,sample) is:
302 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
303 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
305 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
306 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
308 * However, the actual layout of multisampled data in memory is:
310 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
311 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
313 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
314 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
316 * This pattern repeats for each 2x2 pixel block.
318 * As a result, when calculating the size of our 4-sample buffer for
319 * an odd width or height, we have to align before scaling up because
320 * sample 3 is in that bottom right 2x2 block.
322 switch (num_samples
) {
324 width0
= ALIGN(width0
, 2) * 2;
325 height0
= ALIGN(height0
, 2) * 2;
328 width0
= ALIGN(width0
, 2) * 4;
329 height0
= ALIGN(height0
, 2) * 2;
332 /* num_samples should already have been quantized to 0, 1, 4, or
338 /* Non-interleaved */
339 depth0
*= num_samples
;
343 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
346 switch (mt
->msaa_layout
) {
347 case INTEL_MSAA_LAYOUT_NONE
:
348 case INTEL_MSAA_LAYOUT_IMS
:
349 mt
->array_spacing_lod0
= false;
351 case INTEL_MSAA_LAYOUT_UMS
:
352 case INTEL_MSAA_LAYOUT_CMS
:
353 mt
->array_spacing_lod0
= true;
357 if (target
== GL_TEXTURE_CUBE_MAP
) {
362 mt
->physical_width0
= width0
;
363 mt
->physical_height0
= height0
;
364 mt
->physical_depth0
= depth0
;
367 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
368 (brw
->must_use_separate_stencil
||
369 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
370 mt
->stencil_mt
= intel_miptree_create(brw
,
380 INTEL_MIPTREE_TILING_ANY
);
381 if (!mt
->stencil_mt
) {
382 intel_miptree_release(&mt
);
386 /* Fix up the Z miptree format for how we're splitting out separate
387 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
389 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
390 mt
->format
= MESA_FORMAT_X8_Z24
;
391 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
392 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
395 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
396 _mesa_get_format_name(mt
->format
));
400 brw_miptree_layout(brw
, mt
);
406 * \brief Helper function for intel_miptree_create().
409 intel_miptree_choose_tiling(struct brw_context
*brw
,
412 uint32_t num_samples
,
413 enum intel_miptree_tiling_mode requested
,
414 struct intel_mipmap_tree
*mt
)
416 if (format
== MESA_FORMAT_S8
) {
417 /* The stencil buffer is W tiled. However, we request from the kernel a
418 * non-tiled buffer because the GTT is incapable of W fencing.
420 return I915_TILING_NONE
;
423 /* Some usages may want only one type of tiling, like depth miptrees (Y
424 * tiled), or temporary BOs for uploading data once (linear).
427 case INTEL_MIPTREE_TILING_ANY
:
429 case INTEL_MIPTREE_TILING_Y
:
430 return I915_TILING_Y
;
431 case INTEL_MIPTREE_TILING_NONE
:
432 return I915_TILING_NONE
;
435 if (num_samples
> 1) {
436 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
439 * [DevSNB+]: For multi-sample render targets, this field must be
440 * 1. MSRTs can only be tiled.
442 * Our usual reason for preferring X tiling (fast blits using the
443 * blitting engine) doesn't apply to MSAA, since we'll generally be
444 * downsampling or upsampling when blitting between the MSAA buffer
445 * and another buffer, and the blitting engine doesn't support that.
446 * So use Y tiling, since it makes better use of the cache.
448 return I915_TILING_Y
;
451 GLenum base_format
= _mesa_get_format_base_format(format
);
452 if (base_format
== GL_DEPTH_COMPONENT
||
453 base_format
== GL_DEPTH_STENCIL_EXT
)
454 return I915_TILING_Y
;
456 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
458 /* If the width is much smaller than a tile, don't bother tiling. */
459 if (minimum_pitch
< 64)
460 return I915_TILING_NONE
;
462 if (ALIGN(minimum_pitch
, 512) >= 32768) {
463 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
464 mt
->total_width
, mt
->total_height
);
465 return I915_TILING_NONE
;
468 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
470 return I915_TILING_X
;
472 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
473 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
475 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
476 * all the way back to 965, but is explicitly permitted on Gen7.
478 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
479 return I915_TILING_X
;
481 return I915_TILING_Y
| I915_TILING_X
;
484 struct intel_mipmap_tree
*
485 intel_miptree_create(struct brw_context
*brw
,
493 bool expect_accelerated_upload
,
495 enum intel_miptree_tiling_mode requested_tiling
)
497 struct intel_mipmap_tree
*mt
;
498 gl_format tex_format
= format
;
499 gl_format etc_format
= MESA_FORMAT_NONE
;
500 GLuint total_width
, total_height
;
502 if (!brw
->is_baytrail
) {
504 case MESA_FORMAT_ETC1_RGB8
:
505 format
= MESA_FORMAT_RGBX8888_REV
;
507 case MESA_FORMAT_ETC2_RGB8
:
508 format
= MESA_FORMAT_RGBX8888_REV
;
510 case MESA_FORMAT_ETC2_SRGB8
:
511 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
512 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
513 format
= MESA_FORMAT_SARGB8
;
515 case MESA_FORMAT_ETC2_RGBA8_EAC
:
516 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
517 format
= MESA_FORMAT_RGBA8888_REV
;
519 case MESA_FORMAT_ETC2_R11_EAC
:
520 format
= MESA_FORMAT_R16
;
522 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
523 format
= MESA_FORMAT_SIGNED_R16
;
525 case MESA_FORMAT_ETC2_RG11_EAC
:
526 format
= MESA_FORMAT_GR1616
;
528 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
529 format
= MESA_FORMAT_SIGNED_GR1616
;
532 /* Non ETC1 / ETC2 format */
537 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
539 mt
= intel_miptree_create_layout(brw
, target
, format
,
540 first_level
, last_level
, width0
,
544 * pitch == 0 || height == 0 indicates the null texture
546 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
547 intel_miptree_release(&mt
);
551 total_width
= mt
->total_width
;
552 total_height
= mt
->total_height
;
554 if (format
== MESA_FORMAT_S8
) {
555 /* Align to size of W tile, 64x64. */
556 total_width
= ALIGN(total_width
, 64);
557 total_height
= ALIGN(total_height
, 64);
560 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
561 num_samples
, requested_tiling
,
563 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
565 mt
->etc_format
= etc_format
;
566 mt
->region
= intel_region_alloc(brw
->intelScreen
,
567 y_or_x
? I915_TILING_Y
: tiling
,
571 expect_accelerated_upload
);
573 /* If the region is too large to fit in the aperture, we need to use the
574 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
575 * so we need to fall back to X.
577 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
578 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
579 mt
->total_width
, mt
->total_height
);
580 intel_region_release(&mt
->region
);
582 mt
->region
= intel_region_alloc(brw
->intelScreen
,
587 expect_accelerated_upload
);
593 intel_miptree_release(&mt
);
597 /* If this miptree is capable of supporting fast color clears, set
598 * mcs_state appropriately to ensure that fast clears will occur.
599 * Allocation of the MCS miptree will be deferred until the first fast
600 * clear actually occurs.
602 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
603 mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
608 struct intel_mipmap_tree
*
609 intel_miptree_create_for_bo(struct brw_context
*brw
,
618 struct intel_mipmap_tree
*mt
;
620 struct intel_region
*region
= calloc(1, sizeof(*region
));
624 /* Nothing will be able to use this miptree with the BO if the offset isn't
627 if (tiling
!= I915_TILING_NONE
)
628 assert(offset
% 4096 == 0);
630 /* miptrees can't handle negative pitch. If you need flipping of images,
631 * that's outside of the scope of the mt.
635 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
638 true, 0 /* num_samples */);
642 region
->cpp
= mt
->cpp
;
643 region
->width
= width
;
644 region
->height
= height
;
645 region
->pitch
= pitch
;
646 region
->refcount
= 1;
647 drm_intel_bo_reference(bo
);
649 region
->tiling
= tiling
;
659 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
661 * For a multisample DRI2 buffer, this wraps the given region with
662 * a singlesample miptree, then creates a multisample miptree into which the
663 * singlesample miptree is embedded as a child.
665 struct intel_mipmap_tree
*
666 intel_miptree_create_for_dri2_buffer(struct brw_context
*brw
,
667 unsigned dri_attachment
,
669 uint32_t num_samples
,
670 struct intel_region
*region
)
672 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
673 struct intel_mipmap_tree
*multisample_mt
= NULL
;
675 /* Only the front and back buffers, which are color buffers, are shared
678 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
679 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
680 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
681 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
682 _mesa_get_format_base_format(format
) == GL_RGBA
);
684 singlesample_mt
= intel_miptree_create_for_bo(brw
,
692 if (!singlesample_mt
)
694 singlesample_mt
->region
->name
= region
->name
;
696 /* If this miptree is capable of supporting fast color clears, set
697 * mcs_state appropriately to ensure that fast clears will occur.
698 * Allocation of the MCS miptree will be deferred until the first fast
699 * clear actually occurs.
701 if (intel_is_non_msrt_mcs_buffer_supported(brw
, singlesample_mt
))
702 singlesample_mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
704 if (num_samples
== 0)
705 return singlesample_mt
;
707 multisample_mt
= intel_miptree_create_for_renderbuffer(brw
,
712 if (!multisample_mt
) {
713 intel_miptree_release(&singlesample_mt
);
717 multisample_mt
->singlesample_mt
= singlesample_mt
;
718 multisample_mt
->need_downsample
= false;
720 if (brw
->is_front_buffer_rendering
&&
721 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
722 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
723 intel_miptree_upsample(brw
, multisample_mt
);
726 return multisample_mt
;
730 * For a singlesample image buffer, this simply wraps the given region with a miptree.
732 * For a multisample image buffer, this wraps the given region with
733 * a singlesample miptree, then creates a multisample miptree into which the
734 * singlesample miptree is embedded as a child.
736 struct intel_mipmap_tree
*
737 intel_miptree_create_for_image_buffer(struct brw_context
*intel
,
738 enum __DRIimageBufferMask buffer_type
,
740 uint32_t num_samples
,
741 struct intel_region
*region
)
743 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
744 struct intel_mipmap_tree
*multisample_mt
= NULL
;
746 /* Only the front and back buffers, which are color buffers, are allocated
747 * through the image loader.
749 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
750 _mesa_get_format_base_format(format
) == GL_RGBA
);
752 singlesample_mt
= intel_miptree_create_for_bo(intel
,
760 if (!singlesample_mt
)
763 intel_region_reference(&singlesample_mt
->region
, region
);
765 if (num_samples
== 0)
766 return singlesample_mt
;
768 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
773 if (!multisample_mt
) {
774 intel_miptree_release(&singlesample_mt
);
778 multisample_mt
->singlesample_mt
= singlesample_mt
;
779 multisample_mt
->need_downsample
= false;
781 intel_region_reference(&multisample_mt
->region
, region
);
783 if (intel
->is_front_buffer_rendering
&& buffer_type
== __DRI_IMAGE_BUFFER_FRONT
) {
784 intel_miptree_upsample(intel
, multisample_mt
);
787 return multisample_mt
;
790 struct intel_mipmap_tree
*
791 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
795 uint32_t num_samples
)
797 struct intel_mipmap_tree
*mt
;
801 mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, format
, 0, 0,
802 width
, height
, depth
, true, num_samples
,
803 INTEL_MIPTREE_TILING_ANY
);
807 if (brw_is_hiz_depth_format(brw
, format
)) {
808 ok
= intel_miptree_alloc_hiz(brw
, mt
);
813 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
814 ok
= intel_miptree_alloc_mcs(brw
, mt
, num_samples
);
822 intel_miptree_release(&mt
);
827 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
828 struct intel_mipmap_tree
*src
)
833 intel_miptree_release(dst
);
837 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
845 intel_miptree_release(struct intel_mipmap_tree
**mt
)
850 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
851 if (--(*mt
)->refcount
<= 0) {
854 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
856 intel_region_release(&((*mt
)->region
));
857 intel_miptree_release(&(*mt
)->stencil_mt
);
858 intel_miptree_release(&(*mt
)->hiz_mt
);
859 intel_miptree_release(&(*mt
)->mcs_mt
);
860 intel_miptree_release(&(*mt
)->singlesample_mt
);
861 intel_resolve_map_clear(&(*mt
)->hiz_map
);
863 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
864 free((*mt
)->level
[i
].slice
);
873 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
874 int *width
, int *height
, int *depth
)
876 switch (image
->TexObject
->Target
) {
877 case GL_TEXTURE_1D_ARRAY
:
878 *width
= image
->Width
;
880 *depth
= image
->Height
;
883 *width
= image
->Width
;
884 *height
= image
->Height
;
885 *depth
= image
->Depth
;
891 * Can the image be pulled into a unified mipmap tree? This mirrors
892 * the completeness test in a lot of ways.
894 * Not sure whether I want to pass gl_texture_image here.
897 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
898 struct gl_texture_image
*image
)
900 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
901 GLuint level
= intelImage
->base
.Base
.Level
;
902 int width
, height
, depth
;
904 /* glTexImage* choose the texture object based on the target passed in, and
905 * objects can't change targets over their lifetimes, so this should be
908 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
910 gl_format mt_format
= mt
->format
;
911 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
912 mt_format
= MESA_FORMAT_S8_Z24
;
913 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
914 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
915 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
916 mt_format
= mt
->etc_format
;
918 if (image
->TexFormat
!= mt_format
)
921 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
923 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
926 /* Test image dimensions against the base level image adjusted for
927 * minification. This will also catch images not present in the
928 * tree, changed targets, etc.
930 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
931 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
932 /* nonzero level here is always bogus */
935 if (width
!= mt
->logical_width0
||
936 height
!= mt
->logical_height0
||
937 depth
!= mt
->logical_depth0
) {
942 /* all normal textures, renderbuffers, etc */
943 if (width
!= mt
->level
[level
].width
||
944 height
!= mt
->level
[level
].height
||
945 depth
!= mt
->level
[level
].depth
) {
950 if (image
->NumSamples
!= mt
->num_samples
)
958 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
961 GLuint w
, GLuint h
, GLuint d
)
963 mt
->level
[level
].width
= w
;
964 mt
->level
[level
].height
= h
;
965 mt
->level
[level
].depth
= d
;
966 mt
->level
[level
].level_x
= x
;
967 mt
->level
[level
].level_y
= y
;
969 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
970 level
, w
, h
, d
, x
, y
);
972 assert(mt
->level
[level
].slice
== NULL
);
974 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
975 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
976 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
981 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
982 GLuint level
, GLuint img
,
985 if (img
== 0 && level
== 0)
986 assert(x
== 0 && y
== 0);
988 assert(img
< mt
->level
[level
].depth
);
990 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
991 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
993 DBG("%s level %d img %d pos %d,%d\n",
994 __FUNCTION__
, level
, img
,
995 mt
->level
[level
].slice
[img
].x_offset
,
996 mt
->level
[level
].slice
[img
].y_offset
);
1000 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
1001 GLuint level
, GLuint slice
,
1002 GLuint
*x
, GLuint
*y
)
1004 assert(slice
< mt
->level
[level
].depth
);
1006 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1007 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1011 * Rendering with tiled buffers requires that the base address of the buffer
1012 * be aligned to a page boundary. For renderbuffers, and sometimes with
1013 * textures, we may want the surface to point at a texture image level that
1014 * isn't at a page boundary.
1016 * This function returns an appropriately-aligned base offset
1017 * according to the tiling restrictions, plus any required x/y offset
1021 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
1022 GLuint level
, GLuint slice
,
1026 struct intel_region
*region
= mt
->region
;
1028 uint32_t mask_x
, mask_y
;
1030 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
1031 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1033 *tile_x
= x
& mask_x
;
1034 *tile_y
= y
& mask_y
;
1036 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
1041 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1042 struct intel_mipmap_tree
*dst_mt
,
1043 struct intel_mipmap_tree
*src_mt
,
1050 int src_stride
, dst_stride
;
1051 int cpp
= dst_mt
->cpp
;
1053 intel_miptree_map(brw
, src_mt
,
1057 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1060 intel_miptree_map(brw
, dst_mt
,
1064 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1068 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1069 _mesa_get_format_name(src_mt
->format
),
1070 src_mt
, src
, src_stride
,
1071 _mesa_get_format_name(dst_mt
->format
),
1072 dst_mt
, dst
, dst_stride
,
1075 int row_size
= cpp
* width
;
1076 if (src_stride
== row_size
&&
1077 dst_stride
== row_size
) {
1078 memcpy(dst
, src
, row_size
* height
);
1080 for (int i
= 0; i
< height
; i
++) {
1081 memcpy(dst
, src
, row_size
);
1087 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1088 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1090 /* Don't forget to copy the stencil data over, too. We could have skipped
1091 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1092 * shuffling the two data sources in/out of temporary storage instead of
1093 * the direct mapping we get this way.
1095 if (dst_mt
->stencil_mt
) {
1096 assert(src_mt
->stencil_mt
);
1097 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1098 level
, slice
, width
, height
);
1103 intel_miptree_copy_slice(struct brw_context
*brw
,
1104 struct intel_mipmap_tree
*dst_mt
,
1105 struct intel_mipmap_tree
*src_mt
,
1111 gl_format format
= src_mt
->format
;
1112 uint32_t width
= src_mt
->level
[level
].width
;
1113 uint32_t height
= src_mt
->level
[level
].height
;
1121 assert(depth
< src_mt
->level
[level
].depth
);
1122 assert(src_mt
->format
== dst_mt
->format
);
1124 if (dst_mt
->compressed
) {
1125 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1126 width
= ALIGN(width
, dst_mt
->align_w
);
1129 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1130 * below won't apply since we can't do the depth's Y tiling or the
1131 * stencil's W tiling in the blitter.
1133 if (src_mt
->stencil_mt
) {
1134 intel_miptree_copy_slice_sw(brw
,
1141 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1142 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1143 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1145 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1146 _mesa_get_format_name(src_mt
->format
),
1147 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1148 _mesa_get_format_name(dst_mt
->format
),
1149 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1152 if (!intel_miptree_blit(brw
,
1153 src_mt
, level
, slice
, 0, 0, false,
1154 dst_mt
, level
, slice
, 0, 0, false,
1155 width
, height
, GL_COPY
)) {
1156 perf_debug("miptree validate blit for %s failed\n",
1157 _mesa_get_format_name(format
));
1159 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1165 * Copies the image's current data to the given miptree, and associates that
1166 * miptree with the image.
1168 * If \c invalidate is true, then the actual image data does not need to be
1169 * copied, but the image still needs to be associated to the new miptree (this
1170 * is set to true if we're about to clear the image).
1173 intel_miptree_copy_teximage(struct brw_context
*brw
,
1174 struct intel_texture_image
*intelImage
,
1175 struct intel_mipmap_tree
*dst_mt
,
1178 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1179 struct intel_texture_object
*intel_obj
=
1180 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1181 int level
= intelImage
->base
.Base
.Level
;
1182 int face
= intelImage
->base
.Base
.Face
;
1183 GLuint depth
= intelImage
->base
.Base
.Depth
;
1186 for (int slice
= 0; slice
< depth
; slice
++) {
1187 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1191 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1192 intel_obj
->needs_validate
= true;
1196 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1197 struct intel_mipmap_tree
*mt
,
1200 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1201 assert(mt
->mcs_mt
== NULL
);
1203 /* Choose the correct format for the MCS buffer. All that really matters
1204 * is that we allocate the right buffer size, since we'll always be
1205 * accessing this miptree using MCS-specific hardware mechanisms, which
1206 * infer the correct format based on num_samples.
1209 switch (num_samples
) {
1211 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1214 format
= MESA_FORMAT_R8
;
1217 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1218 * for each sample, plus 8 padding bits).
1220 format
= MESA_FORMAT_R_UINT32
;
1223 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1227 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1229 * "The MCS surface must be stored as Tile Y."
1231 mt
->mcs_state
= INTEL_MCS_STATE_MSAA
;
1232 mt
->mcs_mt
= intel_miptree_create(brw
,
1238 mt
->logical_height0
,
1241 0 /* num_samples */,
1242 INTEL_MIPTREE_TILING_Y
);
1244 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1246 * When MCS buffer is enabled and bound to MSRT, it is required that it
1247 * is cleared prior to any rendering.
1249 * Since we don't use the MCS buffer for any purpose other than rendering,
1250 * it makes sense to just clear it immediately upon allocation.
1252 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1254 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1255 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1256 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1263 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1264 struct intel_mipmap_tree
*mt
)
1266 assert(mt
->mcs_mt
== NULL
);
1268 /* The format of the MCS buffer is opaque to the driver; all that matters
1269 * is that we get its size and pitch right. We'll pretend that the format
1270 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1271 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1272 * the block width and then a further factor of 4. Since an MCS tile
1273 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1274 * we'll need to scale the height down by the block height and then a
1275 * further factor of 8.
1277 const gl_format format
= MESA_FORMAT_R_UINT32
;
1278 unsigned block_width_px
;
1279 unsigned block_height
;
1280 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1281 unsigned width_divisor
= block_width_px
* 4;
1282 unsigned height_divisor
= block_height
* 8;
1283 unsigned mcs_width
=
1284 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1285 unsigned mcs_height
=
1286 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1287 assert(mt
->logical_depth0
== 1);
1288 mt
->mcs_mt
= intel_miptree_create(brw
,
1297 0 /* num_samples */,
1298 INTEL_MIPTREE_TILING_Y
);
1305 * Helper for intel_miptree_alloc_hiz() that sets
1306 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1307 * \c has_hiz was set.
1310 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1311 struct intel_mipmap_tree
*mt
,
1317 if (brw
->is_haswell
) {
1318 const struct intel_mipmap_level
*l
= &mt
->level
[level
];
1320 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1321 * and the height is 4 aligned. This allows our HiZ support
1322 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1323 * we can grow the width & height to allow the HiZ op to
1324 * force the proper size alignments.
1326 if (level
> 0 && ((l
->width
& 7) || (l
->height
& 3))) {
1331 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1338 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1339 struct intel_mipmap_tree
*mt
)
1341 assert(mt
->hiz_mt
== NULL
);
1342 mt
->hiz_mt
= intel_miptree_create(brw
,
1348 mt
->logical_height0
,
1352 INTEL_MIPTREE_TILING_ANY
);
1357 /* Mark that all slices need a HiZ resolve. */
1358 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1359 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1360 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1361 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1364 head
->next
= malloc(sizeof(*head
->next
));
1365 head
->next
->prev
= head
;
1366 head
->next
->next
= NULL
;
1369 head
->level
= level
;
1370 head
->layer
= layer
;
1371 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1379 * Does the miptree slice have hiz enabled?
1382 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1386 intel_miptree_check_level_layer(mt
, level
, layer
);
1387 return mt
->level
[level
].slice
[layer
].has_hiz
;
1391 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1395 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1398 intel_resolve_map_set(&mt
->hiz_map
,
1399 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1404 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1408 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1411 intel_resolve_map_set(&mt
->hiz_map
,
1412 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1416 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1420 uint32_t end_layer
= mt
->level
[level
].depth
;
1422 for (layer
= 0; layer
< end_layer
; layer
++) {
1423 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1428 intel_miptree_slice_resolve(struct brw_context
*brw
,
1429 struct intel_mipmap_tree
*mt
,
1432 enum gen6_hiz_op need
)
1434 intel_miptree_check_level_layer(mt
, level
, layer
);
1436 struct intel_resolve_map
*item
=
1437 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1439 if (!item
|| item
->need
!= need
)
1442 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1443 intel_resolve_map_remove(item
);
1448 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1449 struct intel_mipmap_tree
*mt
,
1453 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1454 GEN6_HIZ_OP_HIZ_RESOLVE
);
1458 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1459 struct intel_mipmap_tree
*mt
,
1463 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1464 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1468 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1469 struct intel_mipmap_tree
*mt
,
1470 enum gen6_hiz_op need
)
1472 bool did_resolve
= false;
1473 struct intel_resolve_map
*i
, *next
;
1475 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1477 if (i
->need
!= need
)
1480 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1481 intel_resolve_map_remove(i
);
1489 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1490 struct intel_mipmap_tree
*mt
)
1492 return intel_miptree_all_slices_resolve(brw
, mt
,
1493 GEN6_HIZ_OP_HIZ_RESOLVE
);
1497 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1498 struct intel_mipmap_tree
*mt
)
1500 return intel_miptree_all_slices_resolve(brw
, mt
,
1501 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1506 intel_miptree_resolve_color(struct brw_context
*brw
,
1507 struct intel_mipmap_tree
*mt
)
1509 switch (mt
->mcs_state
) {
1510 case INTEL_MCS_STATE_NONE
:
1511 case INTEL_MCS_STATE_MSAA
:
1512 case INTEL_MCS_STATE_RESOLVED
:
1513 /* No resolve needed */
1515 case INTEL_MCS_STATE_UNRESOLVED
:
1516 case INTEL_MCS_STATE_CLEAR
:
1517 brw_blorp_resolve_color(brw
, mt
);
1524 * Make it possible to share the region backing the given miptree with another
1525 * process or another miptree.
1527 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1528 * then discard the MCS buffer, if present. We also set the mcs_state to
1529 * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
1533 intel_miptree_make_shareable(struct brw_context
*brw
,
1534 struct intel_mipmap_tree
*mt
)
1536 /* MCS buffers are also used for multisample buffers, but we can't resolve
1537 * away a multisample MCS buffer because it's an integral part of how the
1538 * pixel data is stored. Fortunately this code path should never be
1539 * reached for multisample buffers.
1541 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1544 intel_miptree_resolve_color(brw
, mt
);
1545 intel_miptree_release(&mt
->mcs_mt
);
1546 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
1552 * \brief Get pointer offset into stencil buffer.
1554 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1555 * must decode the tile's layout in software.
1558 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1560 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1562 * Even though the returned offset is always positive, the return type is
1564 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1565 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1568 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1570 uint32_t tile_size
= 4096;
1571 uint32_t tile_width
= 64;
1572 uint32_t tile_height
= 64;
1573 uint32_t row_size
= 64 * stride
;
1575 uint32_t tile_x
= x
/ tile_width
;
1576 uint32_t tile_y
= y
/ tile_height
;
1578 /* The byte's address relative to the tile's base addres. */
1579 uint32_t byte_x
= x
% tile_width
;
1580 uint32_t byte_y
= y
% tile_height
;
1582 uintptr_t u
= tile_y
* row_size
1583 + tile_x
* tile_size
1584 + 512 * (byte_x
/ 8)
1586 + 32 * ((byte_y
/ 4) % 2)
1587 + 16 * ((byte_x
/ 4) % 2)
1588 + 8 * ((byte_y
/ 2) % 2)
1589 + 4 * ((byte_x
/ 2) % 2)
1594 /* adjust for bit6 swizzling */
1595 if (((byte_x
/ 8) % 2) == 1) {
1596 if (((byte_y
/ 8) % 2) == 0) {
1608 intel_miptree_updownsample(struct brw_context
*brw
,
1609 struct intel_mipmap_tree
*src
,
1610 struct intel_mipmap_tree
*dst
,
1619 brw_blorp_blit_miptrees(brw
,
1620 src
, 0 /* level */, 0 /* layer */,
1621 dst
, 0 /* level */, 0 /* layer */,
1626 GL_NEAREST
, false, false /*mirror x, y*/);
1628 if (src
->stencil_mt
) {
1629 brw_blorp_blit_miptrees(brw
,
1630 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1631 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1636 GL_NEAREST
, false, false /*mirror x, y*/);
1641 assert_is_flat(struct intel_mipmap_tree
*mt
)
1643 assert(mt
->target
== GL_TEXTURE_2D
);
1644 assert(mt
->first_level
== 0);
1645 assert(mt
->last_level
== 0);
1649 * \brief Downsample from mt to mt->singlesample_mt.
1651 * If the miptree needs no downsample, then skip.
1654 intel_miptree_downsample(struct brw_context
*brw
,
1655 struct intel_mipmap_tree
*mt
)
1657 /* Only flat, renderbuffer-like miptrees are supported. */
1660 if (!mt
->need_downsample
)
1662 intel_miptree_updownsample(brw
,
1663 mt
, mt
->singlesample_mt
,
1665 mt
->logical_height0
);
1666 mt
->need_downsample
= false;
1670 * \brief Upsample from mt->singlesample_mt to mt.
1672 * The upsample is done unconditionally.
1675 intel_miptree_upsample(struct brw_context
*brw
,
1676 struct intel_mipmap_tree
*mt
)
1678 /* Only flat, renderbuffer-like miptrees are supported. */
1680 assert(!mt
->need_downsample
);
1682 intel_miptree_updownsample(brw
,
1683 mt
->singlesample_mt
, mt
,
1685 mt
->logical_height0
);
1689 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1691 /* CPU accesses to color buffers don't understand fast color clears, so
1692 * resolve any pending fast color clears before we map.
1694 intel_miptree_resolve_color(brw
, mt
);
1696 drm_intel_bo
*bo
= mt
->region
->bo
;
1698 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1699 if (drm_intel_bo_busy(bo
)) {
1700 perf_debug("Mapping a busy miptree, causing a stall on the GPU.\n");
1704 intel_batchbuffer_flush(brw
);
1706 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1707 drm_intel_gem_bo_map_gtt(bo
);
1709 drm_intel_bo_map(bo
, true);
1715 intel_miptree_unmap_raw(struct brw_context
*brw
,
1716 struct intel_mipmap_tree
*mt
)
1718 drm_intel_bo_unmap(mt
->region
->bo
);
1722 intel_miptree_map_gtt(struct brw_context
*brw
,
1723 struct intel_mipmap_tree
*mt
,
1724 struct intel_miptree_map
*map
,
1725 unsigned int level
, unsigned int slice
)
1727 unsigned int bw
, bh
;
1729 unsigned int image_x
, image_y
;
1733 /* For compressed formats, the stride is the number of bytes per
1734 * row of blocks. intel_miptree_get_image_offset() already does
1737 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1738 assert(y
% bh
== 0);
1741 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1746 /* Note that in the case of cube maps, the caller must have passed the
1747 * slice number referencing the face.
1749 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1753 map
->stride
= mt
->region
->pitch
;
1754 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1757 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1758 map
->x
, map
->y
, map
->w
, map
->h
,
1759 mt
, _mesa_get_format_name(mt
->format
),
1760 x
, y
, map
->ptr
, map
->stride
);
1764 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1765 struct intel_mipmap_tree
*mt
,
1766 struct intel_miptree_map
*map
,
1770 intel_miptree_unmap_raw(brw
, mt
);
1774 intel_miptree_map_blit(struct brw_context
*brw
,
1775 struct intel_mipmap_tree
*mt
,
1776 struct intel_miptree_map
*map
,
1777 unsigned int level
, unsigned int slice
)
1779 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1783 INTEL_MIPTREE_TILING_NONE
);
1785 fprintf(stderr
, "Failed to allocate blit temporary\n");
1788 map
->stride
= map
->mt
->region
->pitch
;
1790 if (!intel_miptree_blit(brw
,
1792 map
->x
, map
->y
, false,
1795 map
->w
, map
->h
, GL_COPY
)) {
1796 fprintf(stderr
, "Failed to blit\n");
1800 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1802 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1803 map
->x
, map
->y
, map
->w
, map
->h
,
1804 mt
, _mesa_get_format_name(mt
->format
),
1805 level
, slice
, map
->ptr
, map
->stride
);
1810 intel_miptree_release(&map
->mt
);
1816 intel_miptree_unmap_blit(struct brw_context
*brw
,
1817 struct intel_mipmap_tree
*mt
,
1818 struct intel_miptree_map
*map
,
1822 struct gl_context
*ctx
= &brw
->ctx
;
1824 intel_miptree_unmap_raw(brw
, map
->mt
);
1826 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1827 bool ok
= intel_miptree_blit(brw
,
1831 map
->x
, map
->y
, false,
1832 map
->w
, map
->h
, GL_COPY
);
1833 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1836 intel_miptree_release(&map
->mt
);
1841 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1844 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1845 struct intel_mipmap_tree
*mt
,
1846 struct intel_miptree_map
*map
,
1847 unsigned int level
, unsigned int slice
)
1849 assert(map
->mode
& GL_MAP_READ_BIT
);
1850 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1852 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1853 map
->x
, map
->y
, map
->w
, map
->h
,
1854 mt
, _mesa_get_format_name(mt
->format
),
1855 level
, slice
, map
->ptr
, map
->stride
);
1857 /* Map the original image */
1860 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1864 void *src
= intel_miptree_map_raw(brw
, mt
);
1867 src
+= image_y
* mt
->region
->pitch
;
1868 src
+= image_x
* mt
->region
->cpp
;
1870 /* Due to the pixel offsets for the particular image being mapped, our
1871 * src pointer may not be 16-byte aligned. However, if the pitch is
1872 * divisible by 16, then the amount by which it's misaligned will remain
1873 * consistent from row to row.
1875 assert((mt
->region
->pitch
% 16) == 0);
1876 const int misalignment
= ((uintptr_t) src
) & 15;
1878 /* Create an untiled temporary buffer for the mapping. */
1879 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1881 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1883 map
->buffer
= malloc(map
->stride
* map
->h
);
1884 /* Offset the destination so it has the same misalignment as src. */
1885 map
->ptr
= map
->buffer
+ misalignment
;
1887 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1889 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1890 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1891 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1893 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1895 dst_ptr
+= width_bytes
;
1896 src_ptr
+= width_bytes
;
1899 intel_miptree_unmap_raw(brw
, mt
);
1903 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1904 struct intel_mipmap_tree
*mt
,
1905 struct intel_miptree_map
*map
,
1916 intel_miptree_map_s8(struct brw_context
*brw
,
1917 struct intel_mipmap_tree
*mt
,
1918 struct intel_miptree_map
*map
,
1919 unsigned int level
, unsigned int slice
)
1921 map
->stride
= map
->w
;
1922 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1926 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1927 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1928 * invalidate is set, since we'll be writing the whole rectangle from our
1929 * temporary buffer back out.
1931 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1932 uint8_t *untiled_s8_map
= map
->ptr
;
1933 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1934 unsigned int image_x
, image_y
;
1936 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1938 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1939 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1940 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1941 x
+ image_x
+ map
->x
,
1942 y
+ image_y
+ map
->y
,
1943 brw
->has_swizzling
);
1944 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1948 intel_miptree_unmap_raw(brw
, mt
);
1950 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1951 map
->x
, map
->y
, map
->w
, map
->h
,
1952 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1954 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1955 map
->x
, map
->y
, map
->w
, map
->h
,
1956 mt
, map
->ptr
, map
->stride
);
1961 intel_miptree_unmap_s8(struct brw_context
*brw
,
1962 struct intel_mipmap_tree
*mt
,
1963 struct intel_miptree_map
*map
,
1967 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1968 unsigned int image_x
, image_y
;
1969 uint8_t *untiled_s8_map
= map
->ptr
;
1970 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1972 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1974 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1975 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1976 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1979 brw
->has_swizzling
);
1980 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1984 intel_miptree_unmap_raw(brw
, mt
);
1991 intel_miptree_map_etc(struct brw_context
*brw
,
1992 struct intel_mipmap_tree
*mt
,
1993 struct intel_miptree_map
*map
,
1997 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1998 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1999 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
2002 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2003 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2005 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2006 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2007 map
->w
, map
->h
, 1));
2008 map
->ptr
= map
->buffer
;
2012 intel_miptree_unmap_etc(struct brw_context
*brw
,
2013 struct intel_mipmap_tree
*mt
,
2014 struct intel_miptree_map
*map
,
2020 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2025 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2026 + image_y
* mt
->region
->pitch
2027 + image_x
* mt
->region
->cpp
;
2029 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2030 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
2031 map
->ptr
, map
->stride
,
2034 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
2035 map
->ptr
, map
->stride
,
2036 map
->w
, map
->h
, mt
->etc_format
);
2038 intel_miptree_unmap_raw(brw
, mt
);
2043 * Mapping function for packed depth/stencil miptrees backed by real separate
2044 * miptrees for depth and stencil.
2046 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2047 * separate from the depth buffer. Yet at the GL API level, we have to expose
2048 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2049 * be able to map that memory for texture storage and glReadPixels-type
2050 * operations. We give Mesa core that access by mallocing a temporary and
2051 * copying the data between the actual backing store and the temporary.
2054 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2055 struct intel_mipmap_tree
*mt
,
2056 struct intel_miptree_map
*map
,
2057 unsigned int level
, unsigned int slice
)
2059 struct intel_mipmap_tree
*z_mt
= mt
;
2060 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2061 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
2062 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2064 map
->stride
= map
->w
* packed_bpp
;
2065 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2069 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2070 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2071 * invalidate is set, since we'll be writing the whole rectangle from our
2072 * temporary buffer back out.
2074 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2075 uint32_t *packed_map
= map
->ptr
;
2076 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2077 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2078 unsigned int s_image_x
, s_image_y
;
2079 unsigned int z_image_x
, z_image_y
;
2081 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2082 &s_image_x
, &s_image_y
);
2083 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2084 &z_image_x
, &z_image_y
);
2086 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2087 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2088 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2089 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2092 brw
->has_swizzling
);
2093 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2094 (z_mt
->region
->pitch
/ 4) +
2095 (map_x
+ z_image_x
));
2096 uint8_t s
= s_map
[s_offset
];
2097 uint32_t z
= z_map
[z_offset
];
2099 if (map_z32f_x24s8
) {
2100 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2101 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2103 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2108 intel_miptree_unmap_raw(brw
, s_mt
);
2109 intel_miptree_unmap_raw(brw
, z_mt
);
2111 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2113 map
->x
, map
->y
, map
->w
, map
->h
,
2114 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2115 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2116 map
->ptr
, map
->stride
);
2118 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2119 map
->x
, map
->y
, map
->w
, map
->h
,
2120 mt
, map
->ptr
, map
->stride
);
2125 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2126 struct intel_mipmap_tree
*mt
,
2127 struct intel_miptree_map
*map
,
2131 struct intel_mipmap_tree
*z_mt
= mt
;
2132 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2133 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
2135 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2136 uint32_t *packed_map
= map
->ptr
;
2137 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2138 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2139 unsigned int s_image_x
, s_image_y
;
2140 unsigned int z_image_x
, z_image_y
;
2142 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2143 &s_image_x
, &s_image_y
);
2144 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2145 &z_image_x
, &z_image_y
);
2147 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2148 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2149 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2150 x
+ s_image_x
+ map
->x
,
2151 y
+ s_image_y
+ map
->y
,
2152 brw
->has_swizzling
);
2153 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2154 (z_mt
->region
->pitch
/ 4) +
2157 if (map_z32f_x24s8
) {
2158 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2159 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2161 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2162 s_map
[s_offset
] = packed
>> 24;
2163 z_map
[z_offset
] = packed
;
2168 intel_miptree_unmap_raw(brw
, s_mt
);
2169 intel_miptree_unmap_raw(brw
, z_mt
);
2171 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2173 map
->x
, map
->y
, map
->w
, map
->h
,
2174 z_mt
, _mesa_get_format_name(z_mt
->format
),
2175 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2176 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2177 map
->ptr
, map
->stride
);
2184 * Create and attach a map to the miptree at (level, slice). Return the
2187 static struct intel_miptree_map
*
2188 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2197 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2202 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2203 mt
->level
[level
].slice
[slice
].map
= map
;
2215 * Release the map at (level, slice).
2218 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2222 struct intel_miptree_map
**map
;
2224 map
= &mt
->level
[level
].slice
[slice
].map
;
2230 intel_miptree_map_singlesample(struct brw_context
*brw
,
2231 struct intel_mipmap_tree
*mt
,
2242 struct intel_miptree_map
*map
;
2244 assert(mt
->num_samples
<= 1);
2246 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2253 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2254 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2255 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2258 if (mt
->format
== MESA_FORMAT_S8
) {
2259 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2260 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2261 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2262 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2263 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2264 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2266 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2267 else if (brw
->has_llc
&&
2268 !(mode
& GL_MAP_WRITE_BIT
) &&
2270 (mt
->region
->tiling
== I915_TILING_X
||
2271 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2272 mt
->region
->pitch
< 32768) {
2273 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2274 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2275 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2276 assert(mt
->region
->pitch
< 32768);
2277 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2279 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2280 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2283 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2286 *out_ptr
= map
->ptr
;
2287 *out_stride
= map
->stride
;
2289 if (map
->ptr
== NULL
)
2290 intel_miptree_release_map(mt
, level
, slice
);
2294 intel_miptree_unmap_singlesample(struct brw_context
*brw
,
2295 struct intel_mipmap_tree
*mt
,
2299 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2301 assert(mt
->num_samples
<= 1);
2306 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2307 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2309 if (mt
->format
== MESA_FORMAT_S8
) {
2310 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2311 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2312 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2313 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2314 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2315 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2316 } else if (map
->mt
) {
2317 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2319 } else if (map
->buffer
) {
2320 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2323 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2326 intel_miptree_release_map(mt
, level
, slice
);
2330 intel_miptree_map_multisample(struct brw_context
*brw
,
2331 struct intel_mipmap_tree
*mt
,
2342 struct gl_context
*ctx
= &brw
->ctx
;
2343 struct intel_miptree_map
*map
;
2345 assert(mt
->num_samples
> 1);
2347 /* Only flat, renderbuffer-like miptrees are supported. */
2348 if (mt
->target
!= GL_TEXTURE_2D
||
2349 mt
->first_level
!= 0 ||
2350 mt
->last_level
!= 0) {
2351 _mesa_problem(ctx
, "attempt to map a multisample miptree for "
2352 "which (target, first_level, last_level != "
2353 "(GL_TEXTURE_2D, 0, 0)");
2357 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2361 if (!mt
->singlesample_mt
) {
2362 mt
->singlesample_mt
=
2363 intel_miptree_create_for_renderbuffer(brw
,
2366 mt
->logical_height0
,
2368 if (!mt
->singlesample_mt
)
2371 map
->singlesample_mt_is_tmp
= true;
2372 mt
->need_downsample
= true;
2375 intel_miptree_downsample(brw
, mt
);
2376 intel_miptree_map_singlesample(brw
, mt
->singlesample_mt
,
2380 out_ptr
, out_stride
);
2384 intel_miptree_release_map(mt
, level
, slice
);
2390 intel_miptree_unmap_multisample(struct brw_context
*brw
,
2391 struct intel_mipmap_tree
*mt
,
2395 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2397 assert(mt
->num_samples
> 1);
2402 intel_miptree_unmap_singlesample(brw
, mt
->singlesample_mt
, level
, slice
);
2404 mt
->need_downsample
= false;
2405 if (map
->mode
& GL_MAP_WRITE_BIT
)
2406 intel_miptree_upsample(brw
, mt
);
2408 if (map
->singlesample_mt_is_tmp
)
2409 intel_miptree_release(&mt
->singlesample_mt
);
2411 intel_miptree_release_map(mt
, level
, slice
);
2415 intel_miptree_map(struct brw_context
*brw
,
2416 struct intel_mipmap_tree
*mt
,
2427 if (mt
->num_samples
<= 1)
2428 intel_miptree_map_singlesample(brw
, mt
,
2432 out_ptr
, out_stride
);
2434 intel_miptree_map_multisample(brw
, mt
,
2438 out_ptr
, out_stride
);
2442 intel_miptree_unmap(struct brw_context
*brw
,
2443 struct intel_mipmap_tree
*mt
,
2447 if (mt
->num_samples
<= 1)
2448 intel_miptree_unmap_singlesample(brw
, mt
, level
, slice
);
2450 intel_miptree_unmap_multisample(brw
, mt
, level
, slice
);