1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_context.h"
34 #include "intel_mipmap_tree.h"
35 #include "intel_regions.h"
36 #include "intel_resolve_map.h"
37 #include "intel_tex_layout.h"
38 #include "intel_tex.h"
39 #include "intel_blit.h"
41 #include "brw_blorp.h"
43 #include "main/enums.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 target_to_target(GLenum target
)
55 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
56 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
61 return GL_TEXTURE_CUBE_MAP_ARB
;
69 * Determine which MSAA layout should be used by the MSAA surface being
70 * created, based on the chip generation and the surface type.
72 static enum intel_msaa_layout
73 compute_msaa_layout(struct intel_context
*intel
, gl_format format
, GLenum target
)
75 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
84 return INTEL_MSAA_LAYOUT_IMS
;
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (_mesa_get_format_datatype(format
) == GL_INT
) {
98 /* TODO: is this workaround needed for future chipsets? */
99 assert(intel
->gen
== 7);
100 return INTEL_MSAA_LAYOUT_UMS
;
102 /* For now, if we're going to be texturing from this surface,
103 * force UMS, so that the shader doesn't have to do different things
104 * based on whether there's a multisample control surface needing sampled first.
105 * We can't just blindly read the MCS surface in all cases because:
107 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
109 * If this field is disabled and the sampling engine <ld_mcs> message
110 * is issued on this surface, the MCS surface may be accessed. Software
111 * must ensure that the surface is defined to avoid GTT errors.
113 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
114 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
115 return INTEL_MSAA_LAYOUT_UMS
;
117 return INTEL_MSAA_LAYOUT_CMS
;
125 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
126 * scaled-down bitfield representation of the color buffer which is capable of
127 * recording when blocks of the color buffer are equal to the clear value.
128 * This function returns the block size that will be used by the MCS buffer
129 * corresponding to a certain color miptree.
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p327):
134 * The following table describes the RT alignment
148 * This alignment has the following uses:
150 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
151 * buffer contains 128 blocks horizontally and 256 blocks vertically.
153 * - For figuring out alignment restrictions for a fast clear operation. Fast
154 * clear operations must always clear aligned multiples of 16 blocks
155 * horizontally and 32 blocks vertically.
157 * - For scaling down the coordinates sent through the render pipeline during
158 * a fast clear. X coordinates must be scaled down by 8 times the block
159 * width, and Y coordinates by 16 times the block height.
161 * - For scaling down the coordinates sent through the render pipeline during
162 * a "Render Target Resolve" operation. X coordinates must be scaled down
163 * by half the block width, and Y coordinates by half the block height.
166 intel_get_non_msrt_mcs_alignment(struct intel_context
*intel
,
167 struct intel_mipmap_tree
*mt
,
168 unsigned *width_px
, unsigned *height
)
170 switch (mt
->region
->tiling
) {
172 assert(!"Non-MSRT MCS requires X or Y tiling");
173 /* In release builds, fall through */
175 *width_px
= 32 / mt
->cpp
;
179 *width_px
= 64 / mt
->cpp
;
186 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
189 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
190 * beneath the "Fast Color Clear" bullet (p326):
192 * - Support is limited to tiled render targets.
193 * - Support is for non-mip-mapped and non-array surface types only.
195 * And then later, on p327:
197 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
201 intel_is_non_msrt_mcs_buffer_supported(struct intel_context
*intel
,
202 struct intel_mipmap_tree
*mt
)
204 struct brw_context
*brw
= brw_context(&intel
->ctx
);
206 /* MCS support does not exist prior to Gen7 */
210 /* MCS is only supported for color buffers */
211 switch (_mesa_get_format_base_format(mt
->format
)) {
212 case GL_DEPTH_COMPONENT
:
213 case GL_DEPTH_STENCIL
:
214 case GL_STENCIL_INDEX
:
218 if (mt
->region
->tiling
!= I915_TILING_X
&&
219 mt
->region
->tiling
!= I915_TILING_Y
)
221 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
223 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
225 if (mt
->physical_depth0
!= 1)
228 /* There's no point in using an MCS buffer if the surface isn't in a
231 if (!brw
->format_supported_as_render_target
[mt
->format
])
239 * @param for_bo Indicates that the caller is
240 * intel_miptree_create_for_bo(). If true, then do not create
243 struct intel_mipmap_tree
*
244 intel_miptree_create_layout(struct intel_context
*intel
,
255 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
259 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
260 _mesa_lookup_enum_by_nr(target
),
261 _mesa_get_format_name(format
),
262 first_level
, last_level
, mt
);
264 mt
->target
= target_to_target(target
);
266 mt
->first_level
= first_level
;
267 mt
->last_level
= last_level
;
268 mt
->logical_width0
= width0
;
269 mt
->logical_height0
= height0
;
270 mt
->logical_depth0
= depth0
;
271 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
273 /* The cpp is bytes per (1, blockheight)-sized block for compressed
274 * textures. This is why you'll see divides by blockheight all over
277 _mesa_get_format_block_size(format
, &bw
, &bh
);
278 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
279 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
281 mt
->num_samples
= num_samples
;
282 mt
->compressed
= _mesa_is_format_compressed(format
);
283 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
286 if (num_samples
> 1) {
287 /* Adjust width/height/depth for MSAA */
288 mt
->msaa_layout
= compute_msaa_layout(intel
, format
, mt
->target
);
289 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
290 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
292 * "Any of the other messages (sample*, LOD, load4) used with a
293 * (4x) multisampled surface will in-effect sample a surface with
294 * double the height and width as that indicated in the surface
295 * state. Each pixel position on the original-sized surface is
296 * replaced with a 2x2 of samples with the following arrangement:
301 * Thus, when sampling from a multisampled texture, it behaves as
302 * though the layout in memory for (x,y,sample) is:
304 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
305 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
307 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
308 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
310 * However, the actual layout of multisampled data in memory is:
312 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
313 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
315 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
316 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
318 * This pattern repeats for each 2x2 pixel block.
320 * As a result, when calculating the size of our 4-sample buffer for
321 * an odd width or height, we have to align before scaling up because
322 * sample 3 is in that bottom right 2x2 block.
324 switch (num_samples
) {
326 width0
= ALIGN(width0
, 2) * 2;
327 height0
= ALIGN(height0
, 2) * 2;
330 width0
= ALIGN(width0
, 2) * 4;
331 height0
= ALIGN(height0
, 2) * 2;
334 /* num_samples should already have been quantized to 0, 1, 4, or
340 /* Non-interleaved */
341 depth0
*= num_samples
;
345 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
348 switch (mt
->msaa_layout
) {
349 case INTEL_MSAA_LAYOUT_NONE
:
350 case INTEL_MSAA_LAYOUT_IMS
:
351 mt
->array_spacing_lod0
= false;
353 case INTEL_MSAA_LAYOUT_UMS
:
354 case INTEL_MSAA_LAYOUT_CMS
:
355 mt
->array_spacing_lod0
= true;
359 if (target
== GL_TEXTURE_CUBE_MAP
) {
364 mt
->physical_width0
= width0
;
365 mt
->physical_height0
= height0
;
366 mt
->physical_depth0
= depth0
;
369 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
370 (intel
->must_use_separate_stencil
||
371 (intel
->has_separate_stencil
&&
372 intel
->vtbl
.is_hiz_depth_format(intel
, format
)))) {
373 mt
->stencil_mt
= intel_miptree_create(intel
,
383 INTEL_MIPTREE_TILING_ANY
);
384 if (!mt
->stencil_mt
) {
385 intel_miptree_release(&mt
);
389 /* Fix up the Z miptree format for how we're splitting out separate
390 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
392 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
393 mt
->format
= MESA_FORMAT_X8_Z24
;
394 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
395 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
398 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
399 _mesa_get_format_name(mt
->format
));
403 intel_get_texture_alignment_unit(intel
, mt
->format
,
404 &mt
->align_w
, &mt
->align_h
);
406 brw_miptree_layout(intel
, mt
);
412 * \brief Helper function for intel_miptree_create().
415 intel_miptree_choose_tiling(struct intel_context
*intel
,
418 uint32_t num_samples
,
419 enum intel_miptree_tiling_mode requested
,
420 struct intel_mipmap_tree
*mt
)
423 if (format
== MESA_FORMAT_S8
) {
424 /* The stencil buffer is W tiled. However, we request from the kernel a
425 * non-tiled buffer because the GTT is incapable of W fencing.
427 return I915_TILING_NONE
;
430 /* Some usages may want only one type of tiling, like depth miptrees (Y
431 * tiled), or temporary BOs for uploading data once (linear).
434 case INTEL_MIPTREE_TILING_ANY
:
436 case INTEL_MIPTREE_TILING_Y
:
437 return I915_TILING_Y
;
438 case INTEL_MIPTREE_TILING_NONE
:
439 return I915_TILING_NONE
;
442 if (num_samples
> 1) {
443 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
446 * [DevSNB+]: For multi-sample render targets, this field must be
447 * 1. MSRTs can only be tiled.
449 * Our usual reason for preferring X tiling (fast blits using the
450 * blitting engine) doesn't apply to MSAA, since we'll generally be
451 * downsampling or upsampling when blitting between the MSAA buffer
452 * and another buffer, and the blitting engine doesn't support that.
453 * So use Y tiling, since it makes better use of the cache.
455 return I915_TILING_Y
;
458 GLenum base_format
= _mesa_get_format_base_format(format
);
459 if (base_format
== GL_DEPTH_COMPONENT
||
460 base_format
== GL_DEPTH_STENCIL_EXT
)
461 return I915_TILING_Y
;
463 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
465 /* If the width is much smaller than a tile, don't bother tiling. */
466 if (minimum_pitch
< 64)
467 return I915_TILING_NONE
;
469 if (ALIGN(minimum_pitch
, 512) >= 32768) {
470 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
471 mt
->total_width
, mt
->total_height
);
472 return I915_TILING_NONE
;
475 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
477 return I915_TILING_X
;
479 return I915_TILING_Y
| I915_TILING_X
;
482 struct intel_mipmap_tree
*
483 intel_miptree_create(struct intel_context
*intel
,
491 bool expect_accelerated_upload
,
493 enum intel_miptree_tiling_mode requested_tiling
)
495 struct intel_mipmap_tree
*mt
;
496 gl_format tex_format
= format
;
497 gl_format etc_format
= MESA_FORMAT_NONE
;
498 GLuint total_width
, total_height
;
500 if (!intel
->is_baytrail
) {
502 case MESA_FORMAT_ETC1_RGB8
:
503 format
= MESA_FORMAT_RGBX8888_REV
;
505 case MESA_FORMAT_ETC2_RGB8
:
506 format
= MESA_FORMAT_RGBX8888_REV
;
508 case MESA_FORMAT_ETC2_SRGB8
:
509 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
510 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
511 format
= MESA_FORMAT_SARGB8
;
513 case MESA_FORMAT_ETC2_RGBA8_EAC
:
514 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
515 format
= MESA_FORMAT_RGBA8888_REV
;
517 case MESA_FORMAT_ETC2_R11_EAC
:
518 format
= MESA_FORMAT_R16
;
520 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
521 format
= MESA_FORMAT_SIGNED_R16
;
523 case MESA_FORMAT_ETC2_RG11_EAC
:
524 format
= MESA_FORMAT_GR1616
;
526 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
527 format
= MESA_FORMAT_SIGNED_GR1616
;
530 /* Non ETC1 / ETC2 format */
535 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
537 mt
= intel_miptree_create_layout(intel
, target
, format
,
538 first_level
, last_level
, width0
,
542 * pitch == 0 || height == 0 indicates the null texture
544 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
545 intel_miptree_release(&mt
);
549 total_width
= mt
->total_width
;
550 total_height
= mt
->total_height
;
552 if (format
== MESA_FORMAT_S8
) {
553 /* Align to size of W tile, 64x64. */
554 total_width
= ALIGN(total_width
, 64);
555 total_height
= ALIGN(total_height
, 64);
558 uint32_t tiling
= intel_miptree_choose_tiling(intel
, format
, width0
,
559 num_samples
, requested_tiling
,
561 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
563 mt
->etc_format
= etc_format
;
564 mt
->region
= intel_region_alloc(intel
->intelScreen
,
565 y_or_x
? I915_TILING_Y
: tiling
,
569 expect_accelerated_upload
);
571 /* If the region is too large to fit in the aperture, we need to use the
572 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
573 * so we need to fall back to X.
575 if (y_or_x
&& mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
576 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
577 mt
->total_width
, mt
->total_height
);
578 intel_region_release(&mt
->region
);
580 mt
->region
= intel_region_alloc(intel
->intelScreen
,
585 expect_accelerated_upload
);
591 intel_miptree_release(&mt
);
595 /* If this miptree is capable of supporting fast color clears, set
596 * mcs_state appropriately to ensure that fast clears will occur.
597 * Allocation of the MCS miptree will be deferred until the first fast
598 * clear actually occurs.
600 if (intel_is_non_msrt_mcs_buffer_supported(intel
, mt
))
601 mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
606 struct intel_mipmap_tree
*
607 intel_miptree_create_for_bo(struct intel_context
*intel
,
616 struct intel_mipmap_tree
*mt
;
618 struct intel_region
*region
= calloc(1, sizeof(*region
));
622 /* Nothing will be able to use this miptree with the BO if the offset isn't
625 if (tiling
!= I915_TILING_NONE
)
626 assert(offset
% 4096 == 0);
628 /* miptrees can't handle negative pitch. If you need flipping of images,
629 * that's outside of the scope of the mt.
633 mt
= intel_miptree_create_layout(intel
, GL_TEXTURE_2D
, format
,
636 true, 0 /* num_samples */);
640 region
->cpp
= mt
->cpp
;
641 region
->width
= width
;
642 region
->height
= height
;
643 region
->pitch
= pitch
;
644 region
->refcount
= 1;
645 drm_intel_bo_reference(bo
);
647 region
->tiling
= tiling
;
657 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
659 * For a multisample DRI2 buffer, this wraps the given region with
660 * a singlesample miptree, then creates a multisample miptree into which the
661 * singlesample miptree is embedded as a child.
663 struct intel_mipmap_tree
*
664 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
665 unsigned dri_attachment
,
667 uint32_t num_samples
,
668 struct intel_region
*region
)
670 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
671 struct intel_mipmap_tree
*multisample_mt
= NULL
;
673 /* Only the front and back buffers, which are color buffers, are shared
676 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
677 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
678 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
679 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
680 _mesa_get_format_base_format(format
) == GL_RGBA
);
682 singlesample_mt
= intel_miptree_create_for_bo(intel
,
690 if (!singlesample_mt
)
692 singlesample_mt
->region
->name
= region
->name
;
694 /* If this miptree is capable of supporting fast color clears, set
695 * mcs_state appropriately to ensure that fast clears will occur.
696 * Allocation of the MCS miptree will be deferred until the first fast
697 * clear actually occurs.
699 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
700 singlesample_mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
702 if (num_samples
== 0)
703 return singlesample_mt
;
705 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
710 if (!multisample_mt
) {
711 intel_miptree_release(&singlesample_mt
);
715 multisample_mt
->singlesample_mt
= singlesample_mt
;
716 multisample_mt
->need_downsample
= false;
718 if (intel
->is_front_buffer_rendering
&&
719 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
720 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
721 intel_miptree_upsample(intel
, multisample_mt
);
724 return multisample_mt
;
727 struct intel_mipmap_tree
*
728 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
732 uint32_t num_samples
)
734 struct intel_mipmap_tree
*mt
;
738 mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, format
, 0, 0,
739 width
, height
, depth
, true, num_samples
,
740 INTEL_MIPTREE_TILING_ANY
);
744 if (intel
->vtbl
.is_hiz_depth_format(intel
, format
)) {
745 ok
= intel_miptree_alloc_hiz(intel
, mt
);
750 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
751 ok
= intel_miptree_alloc_mcs(intel
, mt
, num_samples
);
759 intel_miptree_release(&mt
);
764 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
765 struct intel_mipmap_tree
*src
)
770 intel_miptree_release(dst
);
774 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
782 intel_miptree_release(struct intel_mipmap_tree
**mt
)
787 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
788 if (--(*mt
)->refcount
<= 0) {
791 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
793 intel_region_release(&((*mt
)->region
));
794 intel_miptree_release(&(*mt
)->stencil_mt
);
795 intel_miptree_release(&(*mt
)->hiz_mt
);
796 intel_miptree_release(&(*mt
)->mcs_mt
);
797 intel_miptree_release(&(*mt
)->singlesample_mt
);
798 intel_resolve_map_clear(&(*mt
)->hiz_map
);
800 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
801 free((*mt
)->level
[i
].slice
);
810 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
811 int *width
, int *height
, int *depth
)
813 switch (image
->TexObject
->Target
) {
814 case GL_TEXTURE_1D_ARRAY
:
815 *width
= image
->Width
;
817 *depth
= image
->Height
;
820 *width
= image
->Width
;
821 *height
= image
->Height
;
822 *depth
= image
->Depth
;
828 * Can the image be pulled into a unified mipmap tree? This mirrors
829 * the completeness test in a lot of ways.
831 * Not sure whether I want to pass gl_texture_image here.
834 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
835 struct gl_texture_image
*image
)
837 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
838 GLuint level
= intelImage
->base
.Base
.Level
;
839 int width
, height
, depth
;
841 /* glTexImage* choose the texture object based on the target passed in, and
842 * objects can't change targets over their lifetimes, so this should be
845 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
847 gl_format mt_format
= mt
->format
;
848 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
849 mt_format
= MESA_FORMAT_S8_Z24
;
850 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
851 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
852 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
853 mt_format
= mt
->etc_format
;
855 if (image
->TexFormat
!= mt_format
)
858 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
860 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
863 /* Test image dimensions against the base level image adjusted for
864 * minification. This will also catch images not present in the
865 * tree, changed targets, etc.
867 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
868 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
869 /* nonzero level here is always bogus */
872 if (width
!= mt
->logical_width0
||
873 height
!= mt
->logical_height0
||
874 depth
!= mt
->logical_depth0
) {
879 /* all normal textures, renderbuffers, etc */
880 if (width
!= mt
->level
[level
].width
||
881 height
!= mt
->level
[level
].height
||
882 depth
!= mt
->level
[level
].depth
) {
887 if (image
->NumSamples
!= mt
->num_samples
)
895 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
898 GLuint w
, GLuint h
, GLuint d
)
900 mt
->level
[level
].width
= w
;
901 mt
->level
[level
].height
= h
;
902 mt
->level
[level
].depth
= d
;
903 mt
->level
[level
].level_x
= x
;
904 mt
->level
[level
].level_y
= y
;
906 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
907 level
, w
, h
, d
, x
, y
);
909 assert(mt
->level
[level
].slice
== NULL
);
911 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
912 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
913 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
918 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
919 GLuint level
, GLuint img
,
922 if (img
== 0 && level
== 0)
923 assert(x
== 0 && y
== 0);
925 assert(img
< mt
->level
[level
].depth
);
927 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
928 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
930 DBG("%s level %d img %d pos %d,%d\n",
931 __FUNCTION__
, level
, img
,
932 mt
->level
[level
].slice
[img
].x_offset
,
933 mt
->level
[level
].slice
[img
].y_offset
);
937 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
938 GLuint level
, GLuint slice
,
939 GLuint
*x
, GLuint
*y
)
941 assert(slice
< mt
->level
[level
].depth
);
943 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
944 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
948 * Rendering with tiled buffers requires that the base address of the buffer
949 * be aligned to a page boundary. For renderbuffers, and sometimes with
950 * textures, we may want the surface to point at a texture image level that
951 * isn't at a page boundary.
953 * This function returns an appropriately-aligned base offset
954 * according to the tiling restrictions, plus any required x/y offset
958 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
959 GLuint level
, GLuint slice
,
963 struct intel_region
*region
= mt
->region
;
965 uint32_t mask_x
, mask_y
;
967 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
968 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
970 *tile_x
= x
& mask_x
;
971 *tile_y
= y
& mask_y
;
973 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
978 intel_miptree_copy_slice_sw(struct intel_context
*intel
,
979 struct intel_mipmap_tree
*dst_mt
,
980 struct intel_mipmap_tree
*src_mt
,
987 int src_stride
, dst_stride
;
988 int cpp
= dst_mt
->cpp
;
990 intel_miptree_map(intel
, src_mt
,
994 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
997 intel_miptree_map(intel
, dst_mt
,
1001 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1005 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1006 _mesa_get_format_name(src_mt
->format
),
1007 src_mt
, src
, src_stride
,
1008 _mesa_get_format_name(dst_mt
->format
),
1009 dst_mt
, dst
, dst_stride
,
1012 int row_size
= cpp
* width
;
1013 if (src_stride
== row_size
&&
1014 dst_stride
== row_size
) {
1015 memcpy(dst
, src
, row_size
* height
);
1017 for (int i
= 0; i
< height
; i
++) {
1018 memcpy(dst
, src
, row_size
);
1024 intel_miptree_unmap(intel
, dst_mt
, level
, slice
);
1025 intel_miptree_unmap(intel
, src_mt
, level
, slice
);
1027 /* Don't forget to copy the stencil data over, too. We could have skipped
1028 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1029 * shuffling the two data sources in/out of temporary storage instead of
1030 * the direct mapping we get this way.
1032 if (dst_mt
->stencil_mt
) {
1033 assert(src_mt
->stencil_mt
);
1034 intel_miptree_copy_slice_sw(intel
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1035 level
, slice
, width
, height
);
1040 intel_miptree_copy_slice(struct intel_context
*intel
,
1041 struct intel_mipmap_tree
*dst_mt
,
1042 struct intel_mipmap_tree
*src_mt
,
1048 gl_format format
= src_mt
->format
;
1049 uint32_t width
= src_mt
->level
[level
].width
;
1050 uint32_t height
= src_mt
->level
[level
].height
;
1058 assert(depth
< src_mt
->level
[level
].depth
);
1059 assert(src_mt
->format
== dst_mt
->format
);
1061 if (dst_mt
->compressed
) {
1062 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1063 width
= ALIGN(width
, dst_mt
->align_w
);
1066 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1067 * below won't apply since we can't do the depth's Y tiling or the
1068 * stencil's W tiling in the blitter.
1070 if (src_mt
->stencil_mt
) {
1071 intel_miptree_copy_slice_sw(intel
,
1078 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1079 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1080 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1082 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1083 _mesa_get_format_name(src_mt
->format
),
1084 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1085 _mesa_get_format_name(dst_mt
->format
),
1086 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1089 if (!intel_miptree_blit(intel
,
1090 src_mt
, level
, slice
, 0, 0, false,
1091 dst_mt
, level
, slice
, 0, 0, false,
1092 width
, height
, GL_COPY
)) {
1093 perf_debug("miptree validate blit for %s failed\n",
1094 _mesa_get_format_name(format
));
1096 intel_miptree_copy_slice_sw(intel
, dst_mt
, src_mt
, level
, slice
,
1102 * Copies the image's current data to the given miptree, and associates that
1103 * miptree with the image.
1105 * If \c invalidate is true, then the actual image data does not need to be
1106 * copied, but the image still needs to be associated to the new miptree (this
1107 * is set to true if we're about to clear the image).
1110 intel_miptree_copy_teximage(struct intel_context
*intel
,
1111 struct intel_texture_image
*intelImage
,
1112 struct intel_mipmap_tree
*dst_mt
,
1115 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1116 struct intel_texture_object
*intel_obj
=
1117 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1118 int level
= intelImage
->base
.Base
.Level
;
1119 int face
= intelImage
->base
.Base
.Face
;
1120 GLuint depth
= intelImage
->base
.Base
.Depth
;
1123 for (int slice
= 0; slice
< depth
; slice
++) {
1124 intel_miptree_copy_slice(intel
, dst_mt
, src_mt
, level
, face
, slice
);
1128 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1129 intel_obj
->needs_validate
= true;
1133 intel_miptree_alloc_mcs(struct intel_context
*intel
,
1134 struct intel_mipmap_tree
*mt
,
1137 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
1138 assert(mt
->mcs_mt
== NULL
);
1140 /* Choose the correct format for the MCS buffer. All that really matters
1141 * is that we allocate the right buffer size, since we'll always be
1142 * accessing this miptree using MCS-specific hardware mechanisms, which
1143 * infer the correct format based on num_samples.
1146 switch (num_samples
) {
1148 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1151 format
= MESA_FORMAT_R8
;
1154 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1155 * for each sample, plus 8 padding bits).
1157 format
= MESA_FORMAT_R_UINT32
;
1160 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1164 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1166 * "The MCS surface must be stored as Tile Y."
1168 mt
->mcs_state
= INTEL_MCS_STATE_MSAA
;
1169 mt
->mcs_mt
= intel_miptree_create(intel
,
1175 mt
->logical_height0
,
1178 0 /* num_samples */,
1179 INTEL_MIPTREE_TILING_Y
);
1181 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1183 * When MCS buffer is enabled and bound to MSRT, it is required that it
1184 * is cleared prior to any rendering.
1186 * Since we don't use the MCS buffer for any purpose other than rendering,
1187 * it makes sense to just clear it immediately upon allocation.
1189 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1191 void *data
= intel_miptree_map_raw(intel
, mt
->mcs_mt
);
1192 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1193 intel_miptree_unmap_raw(intel
, mt
->mcs_mt
);
1200 intel_miptree_alloc_non_msrt_mcs(struct intel_context
*intel
,
1201 struct intel_mipmap_tree
*mt
)
1203 assert(mt
->mcs_mt
== NULL
);
1205 /* The format of the MCS buffer is opaque to the driver; all that matters
1206 * is that we get its size and pitch right. We'll pretend that the format
1207 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1208 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1209 * the block width and then a further factor of 4. Since an MCS tile
1210 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1211 * we'll need to scale the height down by the block height and then a
1212 * further factor of 8.
1214 const gl_format format
= MESA_FORMAT_R_UINT32
;
1215 unsigned block_width_px
;
1216 unsigned block_height
;
1217 intel_get_non_msrt_mcs_alignment(intel
, mt
, &block_width_px
, &block_height
);
1218 unsigned width_divisor
= block_width_px
* 4;
1219 unsigned height_divisor
= block_height
* 8;
1220 unsigned mcs_width
=
1221 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1222 unsigned mcs_height
=
1223 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1224 assert(mt
->logical_depth0
== 1);
1225 mt
->mcs_mt
= intel_miptree_create(intel
,
1234 0 /* num_samples */,
1235 INTEL_MIPTREE_TILING_Y
);
1242 * Helper for intel_miptree_alloc_hiz() that sets
1243 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1244 * \c has_hiz was set.
1247 intel_miptree_slice_enable_hiz(struct intel_context
*intel
,
1248 struct intel_mipmap_tree
*mt
,
1254 if (intel
->is_haswell
) {
1255 /* Disable HiZ for some slices to work around a hardware bug.
1257 * Haswell hardware fails to respect
1258 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y when during HiZ
1259 * ambiguate operations. The failure is inconsistent and affected by
1260 * other GPU contexts. Running a heavy GPU workload in a separate
1261 * process causes the failure rate to drop to nearly 0.
1263 * To workaround the bug, we enable HiZ only when we can guarantee that
1264 * the Depth Coordinate Offset fields will be set to 0. The function
1265 * brw_get_depthstencil_tile_masks() is used to calculate the fields,
1266 * and the function is sometimes called in such a way that the presence
1267 * of an attached stencil buffer changes the fuction's return value.
1269 * The largest tile size considered by brw_get_depthstencil_tile_masks()
1270 * is that of the stencil buffer. Therefore, if this hiz slice's
1271 * corresponding depth slice has an offset that is aligned to the
1272 * stencil buffer tile size, 64x64 pixels, then
1273 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y is set to 0.
1275 uint32_t depth_x_offset
= mt
->level
[level
].slice
[layer
].x_offset
;
1276 uint32_t depth_y_offset
= mt
->level
[level
].slice
[layer
].y_offset
;
1277 if ((depth_x_offset
& 63) || (depth_y_offset
& 63)) {
1282 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1289 intel_miptree_alloc_hiz(struct intel_context
*intel
,
1290 struct intel_mipmap_tree
*mt
)
1292 assert(mt
->hiz_mt
== NULL
);
1293 mt
->hiz_mt
= intel_miptree_create(intel
,
1299 mt
->logical_height0
,
1303 INTEL_MIPTREE_TILING_ANY
);
1308 /* Mark that all slices need a HiZ resolve. */
1309 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1310 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1311 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1312 if (!intel_miptree_slice_enable_hiz(intel
, mt
, level
, layer
))
1315 head
->next
= malloc(sizeof(*head
->next
));
1316 head
->next
->prev
= head
;
1317 head
->next
->next
= NULL
;
1320 head
->level
= level
;
1321 head
->layer
= layer
;
1322 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1330 * Does the miptree slice have hiz enabled?
1333 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1337 intel_miptree_check_level_layer(mt
, level
, layer
);
1338 return mt
->level
[level
].slice
[layer
].has_hiz
;
1342 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1346 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1349 intel_resolve_map_set(&mt
->hiz_map
,
1350 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1355 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1359 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1362 intel_resolve_map_set(&mt
->hiz_map
,
1363 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1367 intel_miptree_slice_resolve(struct intel_context
*intel
,
1368 struct intel_mipmap_tree
*mt
,
1371 enum gen6_hiz_op need
)
1373 intel_miptree_check_level_layer(mt
, level
, layer
);
1375 struct intel_resolve_map
*item
=
1376 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1378 if (!item
|| item
->need
!= need
)
1381 intel_hiz_exec(intel
, mt
, level
, layer
, need
);
1382 intel_resolve_map_remove(item
);
1387 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
1388 struct intel_mipmap_tree
*mt
,
1392 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
1393 GEN6_HIZ_OP_HIZ_RESOLVE
);
1397 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
1398 struct intel_mipmap_tree
*mt
,
1402 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
1403 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1407 intel_miptree_all_slices_resolve(struct intel_context
*intel
,
1408 struct intel_mipmap_tree
*mt
,
1409 enum gen6_hiz_op need
)
1411 bool did_resolve
= false;
1412 struct intel_resolve_map
*i
, *next
;
1414 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1416 if (i
->need
!= need
)
1419 intel_hiz_exec(intel
, mt
, i
->level
, i
->layer
, need
);
1420 intel_resolve_map_remove(i
);
1428 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
1429 struct intel_mipmap_tree
*mt
)
1431 return intel_miptree_all_slices_resolve(intel
, mt
,
1432 GEN6_HIZ_OP_HIZ_RESOLVE
);
1436 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
1437 struct intel_mipmap_tree
*mt
)
1439 return intel_miptree_all_slices_resolve(intel
, mt
,
1440 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1445 intel_miptree_resolve_color(struct intel_context
*intel
,
1446 struct intel_mipmap_tree
*mt
)
1448 switch (mt
->mcs_state
) {
1449 case INTEL_MCS_STATE_NONE
:
1450 case INTEL_MCS_STATE_MSAA
:
1451 case INTEL_MCS_STATE_RESOLVED
:
1452 /* No resolve needed */
1454 case INTEL_MCS_STATE_UNRESOLVED
:
1455 case INTEL_MCS_STATE_CLEAR
:
1456 brw_blorp_resolve_color(intel
, mt
);
1463 * Make it possible to share the region backing the given miptree with another
1464 * process or another miptree.
1466 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1467 * then discard the MCS buffer, if present. We also set the mcs_state to
1468 * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
1472 intel_miptree_make_shareable(struct intel_context
*intel
,
1473 struct intel_mipmap_tree
*mt
)
1475 /* MCS buffers are also used for multisample buffers, but we can't resolve
1476 * away a multisample MCS buffer because it's an integral part of how the
1477 * pixel data is stored. Fortunately this code path should never be
1478 * reached for multisample buffers.
1480 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1483 intel_miptree_resolve_color(intel
, mt
);
1484 intel_miptree_release(&mt
->mcs_mt
);
1485 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
1491 * \brief Get pointer offset into stencil buffer.
1493 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1494 * must decode the tile's layout in software.
1497 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1499 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1501 * Even though the returned offset is always positive, the return type is
1503 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1504 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1507 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1509 uint32_t tile_size
= 4096;
1510 uint32_t tile_width
= 64;
1511 uint32_t tile_height
= 64;
1512 uint32_t row_size
= 64 * stride
;
1514 uint32_t tile_x
= x
/ tile_width
;
1515 uint32_t tile_y
= y
/ tile_height
;
1517 /* The byte's address relative to the tile's base addres. */
1518 uint32_t byte_x
= x
% tile_width
;
1519 uint32_t byte_y
= y
% tile_height
;
1521 uintptr_t u
= tile_y
* row_size
1522 + tile_x
* tile_size
1523 + 512 * (byte_x
/ 8)
1525 + 32 * ((byte_y
/ 4) % 2)
1526 + 16 * ((byte_x
/ 4) % 2)
1527 + 8 * ((byte_y
/ 2) % 2)
1528 + 4 * ((byte_x
/ 2) % 2)
1533 /* adjust for bit6 swizzling */
1534 if (((byte_x
/ 8) % 2) == 1) {
1535 if (((byte_y
/ 8) % 2) == 0) {
1547 intel_miptree_updownsample(struct intel_context
*intel
,
1548 struct intel_mipmap_tree
*src
,
1549 struct intel_mipmap_tree
*dst
,
1558 brw_blorp_blit_miptrees(intel
,
1559 src
, 0 /* level */, 0 /* layer */,
1560 dst
, 0 /* level */, 0 /* layer */,
1565 false, false /*mirror x, y*/);
1567 if (src
->stencil_mt
) {
1568 brw_blorp_blit_miptrees(intel
,
1569 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1570 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1575 false, false /*mirror x, y*/);
1580 assert_is_flat(struct intel_mipmap_tree
*mt
)
1582 assert(mt
->target
== GL_TEXTURE_2D
);
1583 assert(mt
->first_level
== 0);
1584 assert(mt
->last_level
== 0);
1588 * \brief Downsample from mt to mt->singlesample_mt.
1590 * If the miptree needs no downsample, then skip.
1593 intel_miptree_downsample(struct intel_context
*intel
,
1594 struct intel_mipmap_tree
*mt
)
1596 /* Only flat, renderbuffer-like miptrees are supported. */
1599 if (!mt
->need_downsample
)
1601 intel_miptree_updownsample(intel
,
1602 mt
, mt
->singlesample_mt
,
1604 mt
->logical_height0
);
1605 mt
->need_downsample
= false;
1609 * \brief Upsample from mt->singlesample_mt to mt.
1611 * The upsample is done unconditionally.
1614 intel_miptree_upsample(struct intel_context
*intel
,
1615 struct intel_mipmap_tree
*mt
)
1617 /* Only flat, renderbuffer-like miptrees are supported. */
1619 assert(!mt
->need_downsample
);
1621 intel_miptree_updownsample(intel
,
1622 mt
->singlesample_mt
, mt
,
1624 mt
->logical_height0
);
1628 intel_miptree_map_raw(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
)
1630 /* CPU accesses to color buffers don't understand fast color clears, so
1631 * resolve any pending fast color clears before we map.
1633 intel_miptree_resolve_color(intel
, mt
);
1635 drm_intel_bo
*bo
= mt
->region
->bo
;
1637 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1638 if (drm_intel_bo_busy(bo
)) {
1639 perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
1643 intel_flush(&intel
->ctx
);
1645 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1646 drm_intel_gem_bo_map_gtt(bo
);
1648 drm_intel_bo_map(bo
, true);
1654 intel_miptree_unmap_raw(struct intel_context
*intel
,
1655 struct intel_mipmap_tree
*mt
)
1657 drm_intel_bo_unmap(mt
->region
->bo
);
1661 intel_miptree_map_gtt(struct intel_context
*intel
,
1662 struct intel_mipmap_tree
*mt
,
1663 struct intel_miptree_map
*map
,
1664 unsigned int level
, unsigned int slice
)
1666 unsigned int bw
, bh
;
1668 unsigned int image_x
, image_y
;
1672 /* For compressed formats, the stride is the number of bytes per
1673 * row of blocks. intel_miptree_get_image_offset() already does
1676 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1677 assert(y
% bh
== 0);
1680 base
= intel_miptree_map_raw(intel
, mt
) + mt
->offset
;
1685 /* Note that in the case of cube maps, the caller must have passed the
1686 * slice number referencing the face.
1688 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1692 map
->stride
= mt
->region
->pitch
;
1693 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1696 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1697 map
->x
, map
->y
, map
->w
, map
->h
,
1698 mt
, _mesa_get_format_name(mt
->format
),
1699 x
, y
, map
->ptr
, map
->stride
);
1703 intel_miptree_unmap_gtt(struct intel_context
*intel
,
1704 struct intel_mipmap_tree
*mt
,
1705 struct intel_miptree_map
*map
,
1709 intel_miptree_unmap_raw(intel
, mt
);
1713 intel_miptree_map_blit(struct intel_context
*intel
,
1714 struct intel_mipmap_tree
*mt
,
1715 struct intel_miptree_map
*map
,
1716 unsigned int level
, unsigned int slice
)
1718 map
->mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, mt
->format
,
1722 INTEL_MIPTREE_TILING_NONE
);
1724 fprintf(stderr
, "Failed to allocate blit temporary\n");
1727 map
->stride
= map
->mt
->region
->pitch
;
1729 if (!intel_miptree_blit(intel
,
1731 map
->x
, map
->y
, false,
1734 map
->w
, map
->h
, GL_COPY
)) {
1735 fprintf(stderr
, "Failed to blit\n");
1739 intel_batchbuffer_flush(intel
);
1740 map
->ptr
= intel_miptree_map_raw(intel
, map
->mt
);
1742 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1743 map
->x
, map
->y
, map
->w
, map
->h
,
1744 mt
, _mesa_get_format_name(mt
->format
),
1745 level
, slice
, map
->ptr
, map
->stride
);
1750 intel_miptree_release(&map
->mt
);
1756 intel_miptree_unmap_blit(struct intel_context
*intel
,
1757 struct intel_mipmap_tree
*mt
,
1758 struct intel_miptree_map
*map
,
1762 struct gl_context
*ctx
= &intel
->ctx
;
1764 intel_miptree_unmap_raw(intel
, map
->mt
);
1766 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1767 bool ok
= intel_miptree_blit(intel
,
1771 map
->x
, map
->y
, false,
1772 map
->w
, map
->h
, GL_COPY
);
1773 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1776 intel_miptree_release(&map
->mt
);
1780 intel_miptree_map_s8(struct intel_context
*intel
,
1781 struct intel_mipmap_tree
*mt
,
1782 struct intel_miptree_map
*map
,
1783 unsigned int level
, unsigned int slice
)
1785 map
->stride
= map
->w
;
1786 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1790 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1791 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1792 * invalidate is set, since we'll be writing the whole rectangle from our
1793 * temporary buffer back out.
1795 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1796 uint8_t *untiled_s8_map
= map
->ptr
;
1797 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1798 unsigned int image_x
, image_y
;
1800 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1802 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1803 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1804 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1805 x
+ image_x
+ map
->x
,
1806 y
+ image_y
+ map
->y
,
1807 intel
->has_swizzling
);
1808 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1812 intel_miptree_unmap_raw(intel
, mt
);
1814 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1815 map
->x
, map
->y
, map
->w
, map
->h
,
1816 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1818 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1819 map
->x
, map
->y
, map
->w
, map
->h
,
1820 mt
, map
->ptr
, map
->stride
);
1825 intel_miptree_unmap_s8(struct intel_context
*intel
,
1826 struct intel_mipmap_tree
*mt
,
1827 struct intel_miptree_map
*map
,
1831 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1832 unsigned int image_x
, image_y
;
1833 uint8_t *untiled_s8_map
= map
->ptr
;
1834 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1836 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1838 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1839 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1840 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1843 intel
->has_swizzling
);
1844 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1848 intel_miptree_unmap_raw(intel
, mt
);
1855 intel_miptree_map_etc(struct intel_context
*intel
,
1856 struct intel_mipmap_tree
*mt
,
1857 struct intel_miptree_map
*map
,
1861 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1862 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1863 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1866 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1867 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1869 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1870 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1871 map
->w
, map
->h
, 1));
1872 map
->ptr
= map
->buffer
;
1876 intel_miptree_unmap_etc(struct intel_context
*intel
,
1877 struct intel_mipmap_tree
*mt
,
1878 struct intel_miptree_map
*map
,
1884 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1889 uint8_t *dst
= intel_miptree_map_raw(intel
, mt
)
1890 + image_y
* mt
->region
->pitch
1891 + image_x
* mt
->region
->cpp
;
1893 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1894 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1895 map
->ptr
, map
->stride
,
1898 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1899 map
->ptr
, map
->stride
,
1900 map
->w
, map
->h
, mt
->etc_format
);
1902 intel_miptree_unmap_raw(intel
, mt
);
1907 * Mapping function for packed depth/stencil miptrees backed by real separate
1908 * miptrees for depth and stencil.
1910 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1911 * separate from the depth buffer. Yet at the GL API level, we have to expose
1912 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1913 * be able to map that memory for texture storage and glReadPixels-type
1914 * operations. We give Mesa core that access by mallocing a temporary and
1915 * copying the data between the actual backing store and the temporary.
1918 intel_miptree_map_depthstencil(struct intel_context
*intel
,
1919 struct intel_mipmap_tree
*mt
,
1920 struct intel_miptree_map
*map
,
1921 unsigned int level
, unsigned int slice
)
1923 struct intel_mipmap_tree
*z_mt
= mt
;
1924 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1925 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1926 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1928 map
->stride
= map
->w
* packed_bpp
;
1929 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1933 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1934 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1935 * invalidate is set, since we'll be writing the whole rectangle from our
1936 * temporary buffer back out.
1938 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1939 uint32_t *packed_map
= map
->ptr
;
1940 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
1941 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
1942 unsigned int s_image_x
, s_image_y
;
1943 unsigned int z_image_x
, z_image_y
;
1945 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1946 &s_image_x
, &s_image_y
);
1947 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1948 &z_image_x
, &z_image_y
);
1950 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1951 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1952 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1953 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1956 intel
->has_swizzling
);
1957 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1958 (z_mt
->region
->pitch
/ 4) +
1959 (map_x
+ z_image_x
));
1960 uint8_t s
= s_map
[s_offset
];
1961 uint32_t z
= z_map
[z_offset
];
1963 if (map_z32f_x24s8
) {
1964 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1965 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1967 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1972 intel_miptree_unmap_raw(intel
, s_mt
);
1973 intel_miptree_unmap_raw(intel
, z_mt
);
1975 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1977 map
->x
, map
->y
, map
->w
, map
->h
,
1978 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1979 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1980 map
->ptr
, map
->stride
);
1982 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1983 map
->x
, map
->y
, map
->w
, map
->h
,
1984 mt
, map
->ptr
, map
->stride
);
1989 intel_miptree_unmap_depthstencil(struct intel_context
*intel
,
1990 struct intel_mipmap_tree
*mt
,
1991 struct intel_miptree_map
*map
,
1995 struct intel_mipmap_tree
*z_mt
= mt
;
1996 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1997 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1999 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2000 uint32_t *packed_map
= map
->ptr
;
2001 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
2002 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
2003 unsigned int s_image_x
, s_image_y
;
2004 unsigned int z_image_x
, z_image_y
;
2006 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2007 &s_image_x
, &s_image_y
);
2008 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2009 &z_image_x
, &z_image_y
);
2011 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2012 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2013 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2014 x
+ s_image_x
+ map
->x
,
2015 y
+ s_image_y
+ map
->y
,
2016 intel
->has_swizzling
);
2017 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2018 (z_mt
->region
->pitch
/ 4) +
2021 if (map_z32f_x24s8
) {
2022 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2023 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2025 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2026 s_map
[s_offset
] = packed
>> 24;
2027 z_map
[z_offset
] = packed
;
2032 intel_miptree_unmap_raw(intel
, s_mt
);
2033 intel_miptree_unmap_raw(intel
, z_mt
);
2035 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2037 map
->x
, map
->y
, map
->w
, map
->h
,
2038 z_mt
, _mesa_get_format_name(z_mt
->format
),
2039 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2040 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2041 map
->ptr
, map
->stride
);
2048 * Create and attach a map to the miptree at (level, slice). Return the
2051 static struct intel_miptree_map
*
2052 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2061 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2066 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2067 mt
->level
[level
].slice
[slice
].map
= map
;
2079 * Release the map at (level, slice).
2082 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2086 struct intel_miptree_map
**map
;
2088 map
= &mt
->level
[level
].slice
[slice
].map
;
2094 intel_miptree_map_singlesample(struct intel_context
*intel
,
2095 struct intel_mipmap_tree
*mt
,
2106 struct intel_miptree_map
*map
;
2108 assert(mt
->num_samples
<= 1);
2110 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2117 intel_miptree_slice_resolve_depth(intel
, mt
, level
, slice
);
2118 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2119 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2122 if (mt
->format
== MESA_FORMAT_S8
) {
2123 intel_miptree_map_s8(intel
, mt
, map
, level
, slice
);
2124 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2125 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2126 intel_miptree_map_etc(intel
, mt
, map
, level
, slice
);
2127 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2128 intel_miptree_map_depthstencil(intel
, mt
, map
, level
, slice
);
2130 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2131 else if (intel
->has_llc
&&
2132 !(mode
& GL_MAP_WRITE_BIT
) &&
2134 (mt
->region
->tiling
== I915_TILING_X
||
2135 (intel
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2136 mt
->region
->pitch
< 32768) {
2137 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
2138 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2139 mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
2140 assert(mt
->region
->pitch
< 32768);
2141 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
2143 intel_miptree_map_gtt(intel
, mt
, map
, level
, slice
);
2146 *out_ptr
= map
->ptr
;
2147 *out_stride
= map
->stride
;
2149 if (map
->ptr
== NULL
)
2150 intel_miptree_release_map(mt
, level
, slice
);
2154 intel_miptree_unmap_singlesample(struct intel_context
*intel
,
2155 struct intel_mipmap_tree
*mt
,
2159 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2161 assert(mt
->num_samples
<= 1);
2166 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2167 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2169 if (mt
->format
== MESA_FORMAT_S8
) {
2170 intel_miptree_unmap_s8(intel
, mt
, map
, level
, slice
);
2171 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2172 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2173 intel_miptree_unmap_etc(intel
, mt
, map
, level
, slice
);
2174 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2175 intel_miptree_unmap_depthstencil(intel
, mt
, map
, level
, slice
);
2176 } else if (map
->mt
) {
2177 intel_miptree_unmap_blit(intel
, mt
, map
, level
, slice
);
2179 intel_miptree_unmap_gtt(intel
, mt
, map
, level
, slice
);
2182 intel_miptree_release_map(mt
, level
, slice
);
2186 intel_miptree_map_multisample(struct intel_context
*intel
,
2187 struct intel_mipmap_tree
*mt
,
2198 struct intel_miptree_map
*map
;
2200 assert(mt
->num_samples
> 1);
2202 /* Only flat, renderbuffer-like miptrees are supported. */
2203 if (mt
->target
!= GL_TEXTURE_2D
||
2204 mt
->first_level
!= 0 ||
2205 mt
->last_level
!= 0) {
2206 _mesa_problem(&intel
->ctx
, "attempt to map a multisample miptree for "
2207 "which (target, first_level, last_level != "
2208 "(GL_TEXTURE_2D, 0, 0)");
2212 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2216 if (!mt
->singlesample_mt
) {
2217 mt
->singlesample_mt
=
2218 intel_miptree_create_for_renderbuffer(intel
,
2221 mt
->logical_height0
,
2223 if (!mt
->singlesample_mt
)
2226 map
->singlesample_mt_is_tmp
= true;
2227 mt
->need_downsample
= true;
2230 intel_miptree_downsample(intel
, mt
);
2231 intel_miptree_map_singlesample(intel
, mt
->singlesample_mt
,
2235 out_ptr
, out_stride
);
2239 intel_miptree_release_map(mt
, level
, slice
);
2245 intel_miptree_unmap_multisample(struct intel_context
*intel
,
2246 struct intel_mipmap_tree
*mt
,
2250 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2252 assert(mt
->num_samples
> 1);
2257 intel_miptree_unmap_singlesample(intel
, mt
->singlesample_mt
, level
, slice
);
2259 mt
->need_downsample
= false;
2260 if (map
->mode
& GL_MAP_WRITE_BIT
)
2261 intel_miptree_upsample(intel
, mt
);
2263 if (map
->singlesample_mt_is_tmp
)
2264 intel_miptree_release(&mt
->singlesample_mt
);
2266 intel_miptree_release_map(mt
, level
, slice
);
2270 intel_miptree_map(struct intel_context
*intel
,
2271 struct intel_mipmap_tree
*mt
,
2282 if (mt
->num_samples
<= 1)
2283 intel_miptree_map_singlesample(intel
, mt
,
2287 out_ptr
, out_stride
);
2289 intel_miptree_map_multisample(intel
, mt
,
2293 out_ptr
, out_stride
);
2297 intel_miptree_unmap(struct intel_context
*intel
,
2298 struct intel_mipmap_tree
*mt
,
2302 if (mt
->num_samples
<= 1)
2303 intel_miptree_unmap_singlesample(intel
, mt
, level
, slice
);
2305 intel_miptree_unmap_multisample(intel
, mt
, level
, slice
);