2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return isl_format_supports_lossless_compression(brw
->intelScreen
->devinfo
,
271 /* On Gen9 support for color buffer compression was extended to single
272 * sampled surfaces. This is a helper considering both auxiliary buffer
273 * type and number of samples telling if the given miptree represents
274 * the new single sampled case - also called lossless compression.
277 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
278 const struct intel_mipmap_tree
*mt
)
280 /* Only available from Gen9 onwards. */
284 /* Compression always requires auxiliary buffer. */
288 /* Single sample compression is represented re-using msaa compression
289 * layout type: "Compressed Multisampled Surfaces".
291 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
294 /* And finally distinguish between msaa and single sample case. */
295 return mt
->num_samples
<= 1;
299 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
300 const struct intel_mipmap_tree
*mt
)
302 /* For now compression is only enabled for integer formats even though
303 * there exist supported floating point formats also. This is a heuristic
304 * decision based on current public benchmarks. In none of the cases these
305 * formats provided any improvement but a few cases were seen to regress.
306 * Hence these are left to to be enabled in the future when they are known
309 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
312 /* Fast clear mechanism and lossless compression go hand in hand. */
313 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
316 /* Fast clear can be also used to clear srgb surfaces by using equivalent
317 * linear format. This trick, however, can't be extended to be used with
318 * lossless compression and therefore a check is needed to see if the format
321 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
325 * Determine depth format corresponding to a depth+stencil format,
326 * for separate stencil.
329 intel_depth_format_for_depthstencil_format(mesa_format format
) {
331 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
332 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
333 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
334 return MESA_FORMAT_Z_FLOAT32
;
342 * @param for_bo Indicates that the caller is
343 * intel_miptree_create_for_bo(). If true, then do not create
346 static struct intel_mipmap_tree
*
347 intel_miptree_create_layout(struct brw_context
*brw
,
356 uint32_t layout_flags
)
358 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
362 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
363 _mesa_enum_to_string(target
),
364 _mesa_get_format_name(format
),
365 first_level
, last_level
, depth0
, mt
);
367 if (target
== GL_TEXTURE_1D_ARRAY
)
368 assert(height0
== 1);
372 mt
->first_level
= first_level
;
373 mt
->last_level
= last_level
;
374 mt
->logical_width0
= width0
;
375 mt
->logical_height0
= height0
;
376 mt
->logical_depth0
= depth0
;
377 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
378 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
379 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
380 exec_list_make_empty(&mt
->hiz_map
);
381 mt
->cpp
= _mesa_get_format_bytes(format
);
382 mt
->num_samples
= num_samples
;
383 mt
->compressed
= _mesa_is_format_compressed(format
);
384 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
387 if (num_samples
> 1) {
388 /* Adjust width/height/depth for MSAA */
389 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
390 mt
->disable_aux_buffers
);
391 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
392 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
393 * "If the surface is multisampled and it is a depth or stencil
394 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
395 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
398 * +----------------------------------------------------------------+
399 * | Num Multisamples | W_l = | H_l = |
400 * +----------------------------------------------------------------+
401 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
402 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
403 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
404 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
405 * +----------------------------------------------------------------+
408 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
409 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
410 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
412 * Another more complicated explanation for these adjustments comes
413 * from the Sandybridge PRM, volume 4, part 1, page 31:
415 * "Any of the other messages (sample*, LOD, load4) used with a
416 * (4x) multisampled surface will in-effect sample a surface with
417 * double the height and width as that indicated in the surface
418 * state. Each pixel position on the original-sized surface is
419 * replaced with a 2x2 of samples with the following arrangement:
424 * Thus, when sampling from a multisampled texture, it behaves as
425 * though the layout in memory for (x,y,sample) is:
427 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
428 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
430 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
431 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
433 * However, the actual layout of multisampled data in memory is:
435 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
436 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
438 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
439 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
441 * This pattern repeats for each 2x2 pixel block.
443 * As a result, when calculating the size of our 4-sample buffer for
444 * an odd width or height, we have to align before scaling up because
445 * sample 3 is in that bottom right 2x2 block.
447 switch (num_samples
) {
449 assert(brw
->gen
>= 8);
450 width0
= ALIGN(width0
, 2) * 2;
451 height0
= ALIGN(height0
, 2);
454 width0
= ALIGN(width0
, 2) * 2;
455 height0
= ALIGN(height0
, 2) * 2;
458 width0
= ALIGN(width0
, 2) * 4;
459 height0
= ALIGN(height0
, 2) * 2;
462 width0
= ALIGN(width0
, 2) * 4;
463 height0
= ALIGN(height0
, 2) * 4;
466 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
469 unreachable("not reached");
472 /* Non-interleaved */
473 depth0
*= num_samples
;
477 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
478 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
479 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
480 * used on Gen8 to make it pick a qpitch value which doesn't include space
481 * for the mipmaps. On Gen9 this is not necessary because it will
482 * automatically pick a packed qpitch value whenever mt->first_level ==
484 * TODO: can we use it elsewhere?
485 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
488 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
490 switch (mt
->msaa_layout
) {
491 case INTEL_MSAA_LAYOUT_NONE
:
492 case INTEL_MSAA_LAYOUT_IMS
:
493 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
495 case INTEL_MSAA_LAYOUT_UMS
:
496 case INTEL_MSAA_LAYOUT_CMS
:
497 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
502 if (target
== GL_TEXTURE_CUBE_MAP
)
505 mt
->physical_width0
= width0
;
506 mt
->physical_height0
= height0
;
507 mt
->physical_depth0
= depth0
;
509 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
510 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
511 (brw
->must_use_separate_stencil
||
512 (brw
->has_separate_stencil
&&
513 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
514 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
516 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
517 MIPTREE_LAYOUT_TILING_ANY
;
520 mt
->stencil_mt
= intel_miptree_create(brw
,
531 if (!mt
->stencil_mt
) {
532 intel_miptree_release(&mt
);
536 /* Fix up the Z miptree format for how we're splitting out separate
537 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
539 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
542 if (format
== mt
->format
) {
543 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
544 _mesa_get_format_name(mt
->format
));
548 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
549 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
552 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
553 * multisampled or have an AUX buffer attached to it.
555 * GEN | MSRT | AUX_CCS_* or AUX_MCS
556 * -------------------------------------------
557 * 9 | HALIGN_16 | HALIGN_16
558 * 8 | HALIGN_ANY | HALIGN_16
562 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
563 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
564 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
565 } else if (brw
->gen
>= 9 && num_samples
> 1) {
566 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
568 const UNUSED
bool is_lossless_compressed_aux
=
569 brw
->gen
>= 9 && num_samples
== 1 &&
570 mt
->format
== MESA_FORMAT_R_UINT32
;
572 /* For now, nothing else has this requirement */
573 assert(is_lossless_compressed_aux
||
574 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
577 brw_miptree_layout(brw
, mt
, layout_flags
);
579 if (mt
->disable_aux_buffers
)
580 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
587 * Choose an appropriate uncompressed format for a requested
588 * compressed format, if unsupported.
591 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
593 /* No need to lower ETC formats on these platforms,
594 * they are supported natively.
596 if (brw
->gen
>= 8 || brw
->is_baytrail
)
600 case MESA_FORMAT_ETC1_RGB8
:
601 return MESA_FORMAT_R8G8B8X8_UNORM
;
602 case MESA_FORMAT_ETC2_RGB8
:
603 return MESA_FORMAT_R8G8B8X8_UNORM
;
604 case MESA_FORMAT_ETC2_SRGB8
:
605 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
606 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
607 return MESA_FORMAT_B8G8R8A8_SRGB
;
608 case MESA_FORMAT_ETC2_RGBA8_EAC
:
609 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
610 return MESA_FORMAT_R8G8B8A8_UNORM
;
611 case MESA_FORMAT_ETC2_R11_EAC
:
612 return MESA_FORMAT_R_UNORM16
;
613 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
614 return MESA_FORMAT_R_SNORM16
;
615 case MESA_FORMAT_ETC2_RG11_EAC
:
616 return MESA_FORMAT_R16G16_UNORM
;
617 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
618 return MESA_FORMAT_R16G16_SNORM
;
620 /* Non ETC1 / ETC2 format */
625 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
627 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
628 unsigned long *pitch
)
630 uint32_t tile_width
, tile_height
;
631 unsigned long stride
, size
, aligned_y
;
633 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
634 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
635 &tile_width
, &tile_height
);
637 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
638 stride
= mt
->total_width
* mt
->cpp
;
639 stride
= ALIGN(stride
, tile_width
);
640 size
= stride
* aligned_y
;
642 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
643 assert(size
% 4096 == 0);
646 assert(size
% (64 * 1024) == 0);
647 *alignment
= 64 * 1024;
653 static struct intel_mipmap_tree
*
654 miptree_create(struct brw_context
*brw
,
663 uint32_t layout_flags
)
665 struct intel_mipmap_tree
*mt
;
666 mesa_format tex_format
= format
;
667 mesa_format etc_format
= MESA_FORMAT_NONE
;
668 uint32_t alloc_flags
= 0;
670 format
= intel_lower_compressed_format(brw
, format
);
672 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
674 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
675 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
676 mt
= intel_miptree_create_layout(brw
, target
, format
,
677 first_level
, last_level
, width0
,
678 height0
, depth0
, num_samples
,
681 * pitch == 0 || height == 0 indicates the null texture
683 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
684 intel_miptree_release(&mt
);
688 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
689 mt
->tiling
= I915_TILING_Y
;
691 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
692 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
695 mt
->etc_format
= etc_format
;
697 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
698 unsigned alignment
= 0;
700 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
702 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
705 if (format
== MESA_FORMAT_S_UINT8
) {
706 /* Align to size of W tile, 64x64. */
707 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
708 ALIGN(mt
->total_width
, 64),
709 ALIGN(mt
->total_height
, 64),
710 mt
->cpp
, &mt
->tiling
, &pitch
,
713 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
714 mt
->total_width
, mt
->total_height
,
715 mt
->cpp
, &mt
->tiling
, &pitch
,
725 struct intel_mipmap_tree
*
726 intel_miptree_create(struct brw_context
*brw
,
735 uint32_t layout_flags
)
737 struct intel_mipmap_tree
*mt
= miptree_create(
739 first_level
, last_level
,
740 width0
, height0
, depth0
, num_samples
,
743 /* If the BO is too large to fit in the aperture, we need to use the
744 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
745 * handle Y-tiling, so we need to fall back to X.
747 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
748 mt
->tiling
== I915_TILING_Y
) {
749 unsigned long pitch
= mt
->pitch
;
750 const uint32_t alloc_flags
=
751 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
752 BO_ALLOC_FOR_RENDER
: 0;
753 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
754 mt
->total_width
, mt
->total_height
);
756 mt
->tiling
= I915_TILING_X
;
757 drm_intel_bo_unreference(mt
->bo
);
758 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
759 mt
->total_width
, mt
->total_height
, mt
->cpp
,
760 &mt
->tiling
, &pitch
, alloc_flags
);
767 intel_miptree_release(&mt
);
772 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
773 assert(mt
->num_samples
> 1);
774 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
775 intel_miptree_release(&mt
);
780 /* If this miptree is capable of supporting fast color clears, set
781 * fast_clear_state appropriately to ensure that fast clears will occur.
782 * Allocation of the MCS miptree will be deferred until the first fast
783 * clear actually occurs or when compressed single sampled buffer is
784 * written by the GPU for the first time.
786 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
787 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
788 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
789 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
795 struct intel_mipmap_tree
*
796 intel_miptree_create_for_bo(struct brw_context
*brw
,
804 uint32_t layout_flags
)
806 struct intel_mipmap_tree
*mt
;
807 uint32_t tiling
, swizzle
;
810 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
812 /* Nothing will be able to use this miptree with the BO if the offset isn't
815 if (tiling
!= I915_TILING_NONE
)
816 assert(offset
% 4096 == 0);
818 /* miptrees can't handle negative pitch. If you need flipping of images,
819 * that's outside of the scope of the mt.
823 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
825 /* The BO already has a tiling format and we shouldn't confuse the lower
826 * layers by making it try to find a tiling format again.
828 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
829 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
831 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
832 mt
= intel_miptree_create_layout(brw
, target
, format
,
834 width
, height
, depth
, 0,
839 drm_intel_bo_reference(bo
);
849 * For a singlesample renderbuffer, this simply wraps the given BO with a
852 * For a multisample renderbuffer, this wraps the window system's
853 * (singlesample) BO with a singlesample miptree attached to the
854 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
855 * that will contain the actual rendering (which is lazily resolved to
856 * irb->singlesample_mt).
859 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
860 struct intel_renderbuffer
*irb
,
862 uint32_t width
, uint32_t height
,
865 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
866 struct intel_mipmap_tree
*multisample_mt
= NULL
;
867 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
868 mesa_format format
= rb
->Format
;
869 int num_samples
= rb
->NumSamples
;
871 /* Only the front and back buffers, which are color buffers, are allocated
872 * through the image loader.
874 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
875 _mesa_get_format_base_format(format
) == GL_RGBA
);
877 singlesample_mt
= intel_miptree_create_for_bo(intel
,
885 MIPTREE_LAYOUT_FOR_SCANOUT
);
886 if (!singlesample_mt
)
889 /* If this miptree is capable of supporting fast color clears, set
890 * mcs_state appropriately to ensure that fast clears will occur.
891 * Allocation of the MCS miptree will be deferred until the first fast
892 * clear actually occurs.
894 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
895 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
896 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
899 if (num_samples
== 0) {
900 intel_miptree_release(&irb
->mt
);
901 irb
->mt
= singlesample_mt
;
903 assert(!irb
->singlesample_mt
);
905 intel_miptree_release(&irb
->singlesample_mt
);
906 irb
->singlesample_mt
= singlesample_mt
;
909 irb
->mt
->logical_width0
!= width
||
910 irb
->mt
->logical_height0
!= height
) {
911 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
919 irb
->need_downsample
= false;
920 intel_miptree_release(&irb
->mt
);
921 irb
->mt
= multisample_mt
;
927 intel_miptree_release(&irb
->singlesample_mt
);
928 intel_miptree_release(&irb
->mt
);
932 struct intel_mipmap_tree
*
933 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
937 uint32_t num_samples
)
939 struct intel_mipmap_tree
*mt
;
942 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
943 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
944 MIPTREE_LAYOUT_TILING_ANY
|
945 MIPTREE_LAYOUT_FOR_SCANOUT
;
947 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
948 width
, height
, depth
, num_samples
,
953 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
954 ok
= intel_miptree_alloc_hiz(brw
, mt
);
962 intel_miptree_release(&mt
);
967 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
968 struct intel_mipmap_tree
*src
)
973 intel_miptree_release(dst
);
977 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
985 intel_miptree_release(struct intel_mipmap_tree
**mt
)
990 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
991 if (--(*mt
)->refcount
<= 0) {
994 DBG("%s deleting %p\n", __func__
, *mt
);
996 drm_intel_bo_unreference((*mt
)->bo
);
997 intel_miptree_release(&(*mt
)->stencil_mt
);
998 if ((*mt
)->hiz_buf
) {
999 if ((*mt
)->hiz_buf
->mt
)
1000 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1002 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1003 free((*mt
)->hiz_buf
);
1005 intel_miptree_release(&(*mt
)->mcs_mt
);
1006 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1008 intel_miptree_release(&(*mt
)->plane
[0]);
1009 intel_miptree_release(&(*mt
)->plane
[1]);
1011 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1012 free((*mt
)->level
[i
].slice
);
1022 intel_get_image_dims(struct gl_texture_image
*image
,
1023 int *width
, int *height
, int *depth
)
1025 switch (image
->TexObject
->Target
) {
1026 case GL_TEXTURE_1D_ARRAY
:
1027 /* For a 1D Array texture the OpenGL API will treat the image height as
1028 * the number of array slices. For Intel hardware, we treat the 1D array
1029 * as a 2D Array with a height of 1. So, here we want to swap image
1032 assert(image
->Depth
== 1);
1033 *width
= image
->Width
;
1035 *depth
= image
->Height
;
1037 case GL_TEXTURE_CUBE_MAP
:
1038 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1039 * though we really have 6 slices.
1041 assert(image
->Depth
== 1);
1042 *width
= image
->Width
;
1043 *height
= image
->Height
;
1047 *width
= image
->Width
;
1048 *height
= image
->Height
;
1049 *depth
= image
->Depth
;
1055 * Can the image be pulled into a unified mipmap tree? This mirrors
1056 * the completeness test in a lot of ways.
1058 * Not sure whether I want to pass gl_texture_image here.
1061 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1062 struct gl_texture_image
*image
)
1064 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1065 GLuint level
= intelImage
->base
.Base
.Level
;
1066 int width
, height
, depth
;
1068 /* glTexImage* choose the texture object based on the target passed in, and
1069 * objects can't change targets over their lifetimes, so this should be
1072 assert(image
->TexObject
->Target
== mt
->target
);
1074 mesa_format mt_format
= mt
->format
;
1075 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1076 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1077 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1078 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1079 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1080 mt_format
= mt
->etc_format
;
1082 if (image
->TexFormat
!= mt_format
)
1085 intel_get_image_dims(image
, &width
, &height
, &depth
);
1087 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1090 int level_depth
= mt
->level
[level
].depth
;
1091 if (mt
->num_samples
> 1) {
1092 switch (mt
->msaa_layout
) {
1093 case INTEL_MSAA_LAYOUT_NONE
:
1094 case INTEL_MSAA_LAYOUT_IMS
:
1096 case INTEL_MSAA_LAYOUT_UMS
:
1097 case INTEL_MSAA_LAYOUT_CMS
:
1098 level_depth
/= mt
->num_samples
;
1103 /* Test image dimensions against the base level image adjusted for
1104 * minification. This will also catch images not present in the
1105 * tree, changed targets, etc.
1107 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1108 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1109 depth
!= level_depth
) {
1113 if (image
->NumSamples
!= mt
->num_samples
)
1121 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1123 GLuint x
, GLuint y
, GLuint d
)
1125 mt
->level
[level
].depth
= d
;
1126 mt
->level
[level
].level_x
= x
;
1127 mt
->level
[level
].level_y
= y
;
1129 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1132 assert(mt
->level
[level
].slice
== NULL
);
1134 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1135 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1136 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1141 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1142 GLuint level
, GLuint img
,
1145 if (img
== 0 && level
== 0)
1146 assert(x
== 0 && y
== 0);
1148 assert(img
< mt
->level
[level
].depth
);
1150 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1151 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1153 DBG("%s level %d img %d pos %d,%d\n",
1154 __func__
, level
, img
,
1155 mt
->level
[level
].slice
[img
].x_offset
,
1156 mt
->level
[level
].slice
[img
].y_offset
);
1160 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1161 GLuint level
, GLuint slice
,
1162 GLuint
*x
, GLuint
*y
)
1164 assert(slice
< mt
->level
[level
].depth
);
1166 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1167 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1172 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1173 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1174 * and tile_h is set to 1.
1177 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1178 uint32_t *tile_w
, uint32_t *tile_h
)
1180 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1190 case I915_TILING_NONE
:
1195 unreachable("not reached");
1198 uint32_t aspect_ratio
= 1;
1199 assert(_mesa_is_pow_two(cpp
));
1214 unreachable("not reached");
1217 if (cpp
== 2 || cpp
== 8)
1220 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1223 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1229 * This function computes masks that may be used to select the bits of the X
1230 * and Y coordinates that indicate the offset within a tile. If the BO is
1231 * untiled, the masks are set to 0.
1234 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1235 bool map_stencil_as_y_tiled
,
1236 uint32_t *mask_x
, uint32_t *mask_y
)
1238 uint32_t tile_w_bytes
, tile_h
;
1239 if (map_stencil_as_y_tiled
)
1240 tiling
= I915_TILING_Y
;
1242 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1244 *mask_x
= tile_w_bytes
/ cpp
- 1;
1245 *mask_y
= tile_h
- 1;
1249 * Compute the offset (in bytes) from the start of the BO to the given x
1250 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1251 * multiples of the tile size.
1254 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1255 uint32_t x
, uint32_t y
,
1256 bool map_stencil_as_y_tiled
)
1259 uint32_t pitch
= mt
->pitch
;
1260 uint32_t tiling
= mt
->tiling
;
1262 if (map_stencil_as_y_tiled
) {
1263 tiling
= I915_TILING_Y
;
1265 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1266 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1267 * the resulting surface is twice the pitch of the original miptree,
1268 * since each row in the Y-tiled view corresponds to two rows in the
1269 * actual W-tiled surface. So we need to correct the pitch before
1270 * computing the offsets.
1277 unreachable("not reached");
1278 case I915_TILING_NONE
:
1279 return y
* pitch
+ x
* cpp
;
1281 assert((x
% (512 / cpp
)) == 0);
1282 assert((y
% 8) == 0);
1283 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1285 assert((x
% (128 / cpp
)) == 0);
1286 assert((y
% 32) == 0);
1287 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1292 * Rendering with tiled buffers requires that the base address of the buffer
1293 * be aligned to a page boundary. For renderbuffers, and sometimes with
1294 * textures, we may want the surface to point at a texture image level that
1295 * isn't at a page boundary.
1297 * This function returns an appropriately-aligned base offset
1298 * according to the tiling restrictions, plus any required x/y offset
1302 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1303 GLuint level
, GLuint slice
,
1308 uint32_t mask_x
, mask_y
;
1310 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1311 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1313 *tile_x
= x
& mask_x
;
1314 *tile_y
= y
& mask_y
;
1316 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1320 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1321 struct intel_mipmap_tree
*dst_mt
,
1322 struct intel_mipmap_tree
*src_mt
,
1329 ptrdiff_t src_stride
, dst_stride
;
1330 int cpp
= dst_mt
->cpp
;
1332 intel_miptree_map(brw
, src_mt
,
1336 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1339 intel_miptree_map(brw
, dst_mt
,
1343 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1347 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1348 _mesa_get_format_name(src_mt
->format
),
1349 src_mt
, src
, src_stride
,
1350 _mesa_get_format_name(dst_mt
->format
),
1351 dst_mt
, dst
, dst_stride
,
1354 int row_size
= cpp
* width
;
1355 if (src_stride
== row_size
&&
1356 dst_stride
== row_size
) {
1357 memcpy(dst
, src
, row_size
* height
);
1359 for (int i
= 0; i
< height
; i
++) {
1360 memcpy(dst
, src
, row_size
);
1366 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1367 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1369 /* Don't forget to copy the stencil data over, too. We could have skipped
1370 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1371 * shuffling the two data sources in/out of temporary storage instead of
1372 * the direct mapping we get this way.
1374 if (dst_mt
->stencil_mt
) {
1375 assert(src_mt
->stencil_mt
);
1376 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1377 level
, slice
, width
, height
);
1382 intel_miptree_copy_slice(struct brw_context
*brw
,
1383 struct intel_mipmap_tree
*dst_mt
,
1384 struct intel_mipmap_tree
*src_mt
,
1390 mesa_format format
= src_mt
->format
;
1391 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1392 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1400 assert(depth
< src_mt
->level
[level
].depth
);
1401 assert(src_mt
->format
== dst_mt
->format
);
1403 if (dst_mt
->compressed
) {
1405 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1406 height
= ALIGN_NPOT(height
, j
) / j
;
1407 width
= ALIGN_NPOT(width
, i
) / i
;
1410 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1411 * below won't apply since we can't do the depth's Y tiling or the
1412 * stencil's W tiling in the blitter.
1414 if (src_mt
->stencil_mt
) {
1415 intel_miptree_copy_slice_sw(brw
,
1422 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1423 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1424 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1426 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1427 _mesa_get_format_name(src_mt
->format
),
1428 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1429 _mesa_get_format_name(dst_mt
->format
),
1430 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1433 if (!intel_miptree_blit(brw
,
1434 src_mt
, level
, slice
, 0, 0, false,
1435 dst_mt
, level
, slice
, 0, 0, false,
1436 width
, height
, GL_COPY
)) {
1437 perf_debug("miptree validate blit for %s failed\n",
1438 _mesa_get_format_name(format
));
1440 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1446 * Copies the image's current data to the given miptree, and associates that
1447 * miptree with the image.
1449 * If \c invalidate is true, then the actual image data does not need to be
1450 * copied, but the image still needs to be associated to the new miptree (this
1451 * is set to true if we're about to clear the image).
1454 intel_miptree_copy_teximage(struct brw_context
*brw
,
1455 struct intel_texture_image
*intelImage
,
1456 struct intel_mipmap_tree
*dst_mt
,
1459 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1460 struct intel_texture_object
*intel_obj
=
1461 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1462 int level
= intelImage
->base
.Base
.Level
;
1463 int face
= intelImage
->base
.Base
.Face
;
1466 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1467 depth
= intelImage
->base
.Base
.Height
;
1469 depth
= intelImage
->base
.Base
.Depth
;
1472 for (int slice
= 0; slice
< depth
; slice
++) {
1473 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1477 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1478 intel_obj
->needs_validate
= true;
1482 intel_miptree_init_mcs(struct brw_context
*brw
,
1483 struct intel_mipmap_tree
*mt
,
1486 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1488 * When MCS buffer is enabled and bound to MSRT, it is required that it
1489 * is cleared prior to any rendering.
1491 * Since we don't use the MCS buffer for any purpose other than rendering,
1492 * it makes sense to just clear it immediately upon allocation.
1494 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1496 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1497 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1498 intel_miptree_unmap_raw(mt
->mcs_mt
);
1499 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1503 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1504 struct intel_mipmap_tree
*mt
,
1507 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1508 assert(mt
->mcs_mt
== NULL
);
1509 assert(!mt
->disable_aux_buffers
);
1511 /* Choose the correct format for the MCS buffer. All that really matters
1512 * is that we allocate the right buffer size, since we'll always be
1513 * accessing this miptree using MCS-specific hardware mechanisms, which
1514 * infer the correct format based on num_samples.
1517 switch (num_samples
) {
1520 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1523 format
= MESA_FORMAT_R_UNORM8
;
1526 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1527 * for each sample, plus 8 padding bits).
1529 format
= MESA_FORMAT_R_UINT32
;
1532 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1535 format
= MESA_FORMAT_RG_UINT32
;
1538 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1541 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1543 * "The MCS surface must be stored as Tile Y."
1545 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1546 MIPTREE_LAYOUT_TILING_Y
;
1547 mt
->mcs_mt
= miptree_create(brw
,
1553 mt
->logical_height0
,
1555 0 /* num_samples */,
1558 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1565 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1566 struct intel_mipmap_tree
*mt
)
1568 assert(mt
->mcs_mt
== NULL
);
1569 assert(!mt
->disable_aux_buffers
);
1571 /* The format of the MCS buffer is opaque to the driver; all that matters
1572 * is that we get its size and pitch right. We'll pretend that the format
1573 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1574 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1575 * the block width and then a further factor of 4. Since an MCS tile
1576 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1577 * we'll need to scale the height down by the block height and then a
1578 * further factor of 8.
1580 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1581 unsigned block_width_px
;
1582 unsigned block_height
;
1583 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1584 unsigned width_divisor
= block_width_px
* 4;
1585 unsigned height_divisor
= block_height
* 8;
1587 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1589 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1590 * in the main surface. In Skylake, it's two bits. The extra bit
1591 * doubles the MCS height, not width, because in Skylake the MCS is always
1595 height_divisor
/= 2;
1597 unsigned mcs_width
=
1598 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1599 unsigned mcs_height
=
1600 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1601 assert(mt
->logical_depth0
== 1);
1602 uint32_t layout_flags
= MIPTREE_LAYOUT_TILING_Y
;
1604 if (brw
->gen
>= 8) {
1605 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1608 /* On Gen9+ clients are not currently capable of consuming compressed
1609 * single-sampled buffers. Disabling compression allows us to skip
1612 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
1613 const bool is_lossless_compressed
=
1614 unlikely(!lossless_compression_disabled
) &&
1615 brw
->gen
>= 9 && !mt
->is_scanout
&&
1616 intel_miptree_supports_lossless_compressed(brw
, mt
);
1618 /* In case of compression mcs buffer needs to be initialised requiring the
1619 * buffer to be immediately mapped to cpu space for writing. Therefore do
1620 * not use the gpu access flag which can cause an unnecessary delay if the
1621 * backing pages happened to be just used by the GPU.
1623 if (!is_lossless_compressed
)
1624 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1626 mt
->mcs_mt
= miptree_create(brw
,
1634 0 /* num_samples */,
1637 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1638 * used for lossless compression which requires similar initialisation
1639 * as multi-sample compression.
1641 if (is_lossless_compressed
) {
1642 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1643 * resolve. Initialize it accordingly in case the first renderer is
1644 * cpu (or other none compression aware party).
1646 * This is also explicitly stated in the spec (MCS Buffer for Render
1648 * "If Software wants to enable Color Compression without Fast clear,
1649 * Software needs to initialize MCS with zeros."
1651 intel_miptree_init_mcs(brw
, mt
, 0);
1652 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1653 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1660 intel_miptree_prepare_mcs(struct brw_context
*brw
,
1661 struct intel_mipmap_tree
*mt
)
1669 /* Single sample compression is represented re-using msaa compression
1670 * layout type: "Compressed Multisampled Surfaces".
1672 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
|| mt
->num_samples
> 1)
1675 /* Clients are not currently capable of consuming compressed
1676 * single-sampled buffers.
1681 assert(intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) ||
1682 intel_miptree_supports_lossless_compressed(brw
, mt
));
1684 /* Consider if lossless compression is supported but the needed
1685 * auxiliary buffer doesn't exist yet.
1687 * Failing to allocate the auxiliary buffer means running out of
1688 * memory. The pointer to the aux miptree is left NULL which should
1689 * signal non-compressed behavior.
1691 if (!intel_miptree_alloc_non_msrt_mcs(brw
, mt
)) {
1693 "Failed to allocated aux buffer for lossless"
1694 " compressed %p %u:%u %s\n",
1695 mt
, mt
->logical_width0
, mt
->logical_height0
,
1696 _mesa_get_format_name(mt
->format
));
1701 * Helper for intel_miptree_alloc_hiz() that sets
1702 * \c mt->level[level].has_hiz. Return true if and only if
1703 * \c has_hiz was set.
1706 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1707 struct intel_mipmap_tree
*mt
,
1710 assert(mt
->hiz_buf
);
1712 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1713 uint32_t width
= minify(mt
->physical_width0
, level
);
1714 uint32_t height
= minify(mt
->physical_height0
, level
);
1716 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1717 * and the height is 4 aligned. This allows our HiZ support
1718 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1719 * we can grow the width & height to allow the HiZ op to
1720 * force the proper size alignments.
1722 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1723 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1728 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1729 mt
->level
[level
].has_hiz
= true;
1735 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1736 * buffer dimensions and allocates a bo for the hiz buffer.
1738 static struct intel_miptree_aux_buffer
*
1739 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1740 struct intel_mipmap_tree
*mt
)
1742 unsigned z_width
= mt
->logical_width0
;
1743 unsigned z_height
= mt
->logical_height0
;
1744 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1745 unsigned hz_width
, hz_height
;
1746 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1751 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1752 * adjustments required for Z_Height and Z_Width based on multisampling.
1754 switch (mt
->num_samples
) {
1768 unreachable("unsupported sample count");
1771 const unsigned vertical_align
= 8; /* 'j' in the docs */
1772 const unsigned H0
= z_height
;
1773 const unsigned h0
= ALIGN(H0
, vertical_align
);
1774 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1775 const unsigned Z0
= z_depth
;
1777 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1778 hz_width
= ALIGN(z_width
, 16);
1780 if (mt
->target
== GL_TEXTURE_3D
) {
1784 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1785 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1786 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1787 hz_height
+= h_i
* Z_i
;
1788 H_i
= minify(H_i
, 1);
1789 Z_i
= minify(Z_i
, 1);
1792 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1794 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1796 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1797 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1798 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1801 unsigned long pitch
;
1802 uint32_t tiling
= I915_TILING_Y
;
1803 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1804 hz_width
, hz_height
, 1,
1806 BO_ALLOC_FOR_RENDER
);
1810 } else if (tiling
!= I915_TILING_Y
) {
1811 drm_intel_bo_unreference(buf
->bo
);
1823 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1824 * buffer dimensions and allocates a bo for the hiz buffer.
1826 static struct intel_miptree_aux_buffer
*
1827 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1828 struct intel_mipmap_tree
*mt
)
1830 unsigned z_width
= mt
->logical_width0
;
1831 unsigned z_height
= mt
->logical_height0
;
1832 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1833 unsigned hz_width
, hz_height
;
1834 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1839 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1840 * adjustments required for Z_Height and Z_Width based on multisampling.
1843 switch (mt
->num_samples
) {
1857 unreachable("unsupported sample count");
1861 const unsigned vertical_align
= 8; /* 'j' in the docs */
1862 const unsigned H0
= z_height
;
1863 const unsigned h0
= ALIGN(H0
, vertical_align
);
1864 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1865 const unsigned Z0
= z_depth
;
1867 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1868 hz_width
= ALIGN(z_width
, 16);
1872 unsigned sum_h_i
= 0;
1873 unsigned hz_height_3d_sum
= 0;
1874 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1875 unsigned i
= level
- mt
->first_level
;
1876 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1877 /* sum(i=2 to m; h_i) */
1881 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1882 hz_height_3d_sum
+= h_i
* Z_i
;
1883 H_i
= minify(H_i
, 1);
1884 Z_i
= minify(Z_i
, 1);
1886 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1887 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1889 if (mt
->target
== GL_TEXTURE_3D
) {
1890 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1891 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1893 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1894 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1897 unsigned long pitch
;
1898 uint32_t tiling
= I915_TILING_Y
;
1899 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1900 hz_width
, hz_height
, 1,
1902 BO_ALLOC_FOR_RENDER
);
1906 } else if (tiling
!= I915_TILING_Y
) {
1907 drm_intel_bo_unreference(buf
->bo
);
1918 static struct intel_miptree_aux_buffer
*
1919 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1920 struct intel_mipmap_tree
*mt
)
1922 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1923 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1926 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1931 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1932 buf
->mt
= intel_miptree_create(brw
,
1938 mt
->logical_height0
,
1947 buf
->bo
= buf
->mt
->bo
;
1948 buf
->pitch
= buf
->mt
->pitch
;
1949 buf
->qpitch
= buf
->mt
->qpitch
;
1955 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1956 struct intel_mipmap_tree
*mt
)
1961 if (mt
->hiz_buf
!= NULL
)
1964 if (mt
->disable_aux_buffers
)
1967 switch (mt
->format
) {
1968 case MESA_FORMAT_Z_FLOAT32
:
1969 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1970 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1971 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1972 case MESA_FORMAT_Z_UNORM16
:
1980 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1981 struct intel_mipmap_tree
*mt
)
1983 assert(mt
->hiz_buf
== NULL
);
1984 assert(!mt
->disable_aux_buffers
);
1986 if (brw
->gen
== 7) {
1987 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1988 } else if (brw
->gen
>= 8) {
1989 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1991 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1997 /* Mark that all slices need a HiZ resolve. */
1998 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1999 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
2002 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
2003 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
2004 exec_node_init(&m
->link
);
2007 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
2009 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
2017 * Does the miptree slice have hiz enabled?
2020 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2022 intel_miptree_check_level_layer(mt
, level
, 0);
2023 return mt
->level
[level
].has_hiz
;
2027 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2031 if (!intel_miptree_level_has_hiz(mt
, level
))
2034 intel_resolve_map_set(&mt
->hiz_map
,
2035 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
2040 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2044 if (!intel_miptree_level_has_hiz(mt
, level
))
2047 intel_resolve_map_set(&mt
->hiz_map
,
2048 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
2052 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2056 uint32_t end_layer
= mt
->level
[level
].depth
;
2058 for (layer
= 0; layer
< end_layer
; layer
++) {
2059 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2064 intel_miptree_slice_resolve(struct brw_context
*brw
,
2065 struct intel_mipmap_tree
*mt
,
2068 enum gen6_hiz_op need
)
2070 intel_miptree_check_level_layer(mt
, level
, layer
);
2072 struct intel_resolve_map
*item
=
2073 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2075 if (!item
|| item
->need
!= need
)
2078 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2079 intel_resolve_map_remove(item
);
2084 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2085 struct intel_mipmap_tree
*mt
,
2089 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2090 GEN6_HIZ_OP_HIZ_RESOLVE
);
2094 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2095 struct intel_mipmap_tree
*mt
,
2099 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2100 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2104 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2105 struct intel_mipmap_tree
*mt
,
2106 enum gen6_hiz_op need
)
2108 bool did_resolve
= false;
2110 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2111 if (map
->need
!= need
)
2114 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2115 intel_resolve_map_remove(map
);
2123 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2124 struct intel_mipmap_tree
*mt
)
2126 return intel_miptree_all_slices_resolve(brw
, mt
,
2127 GEN6_HIZ_OP_HIZ_RESOLVE
);
2131 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2132 struct intel_mipmap_tree
*mt
)
2134 return intel_miptree_all_slices_resolve(brw
, mt
,
2135 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2140 intel_miptree_resolve_color(struct brw_context
*brw
,
2141 struct intel_mipmap_tree
*mt
,
2144 /* From gen9 onwards there is new compression scheme for single sampled
2145 * surfaces called "lossless compressed". These don't need to be always
2148 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2149 intel_miptree_is_lossless_compressed(brw
, mt
))
2152 switch (mt
->fast_clear_state
) {
2153 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2154 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2155 /* No resolve needed */
2157 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2158 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2159 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2160 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2161 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2162 brw_blorp_resolve_color(brw
, mt
);
2170 * Make it possible to share the BO backing the given miptree with another
2171 * process or another miptree.
2173 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2174 * then discard the MCS buffer, if present. We also set the fast_clear_state
2175 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2176 * allocated in the future.
2179 intel_miptree_make_shareable(struct brw_context
*brw
,
2180 struct intel_mipmap_tree
*mt
)
2182 /* MCS buffers are also used for multisample buffers, but we can't resolve
2183 * away a multisample MCS buffer because it's an integral part of how the
2184 * pixel data is stored. Fortunately this code path should never be
2185 * reached for multisample buffers.
2187 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2190 intel_miptree_resolve_color(brw
, mt
, 0);
2191 intel_miptree_release(&mt
->mcs_mt
);
2192 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2198 * \brief Get pointer offset into stencil buffer.
2200 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2201 * must decode the tile's layout in software.
2204 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2206 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2208 * Even though the returned offset is always positive, the return type is
2210 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2211 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2214 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2216 uint32_t tile_size
= 4096;
2217 uint32_t tile_width
= 64;
2218 uint32_t tile_height
= 64;
2219 uint32_t row_size
= 64 * stride
;
2221 uint32_t tile_x
= x
/ tile_width
;
2222 uint32_t tile_y
= y
/ tile_height
;
2224 /* The byte's address relative to the tile's base addres. */
2225 uint32_t byte_x
= x
% tile_width
;
2226 uint32_t byte_y
= y
% tile_height
;
2228 uintptr_t u
= tile_y
* row_size
2229 + tile_x
* tile_size
2230 + 512 * (byte_x
/ 8)
2232 + 32 * ((byte_y
/ 4) % 2)
2233 + 16 * ((byte_x
/ 4) % 2)
2234 + 8 * ((byte_y
/ 2) % 2)
2235 + 4 * ((byte_x
/ 2) % 2)
2240 /* adjust for bit6 swizzling */
2241 if (((byte_x
/ 8) % 2) == 1) {
2242 if (((byte_y
/ 8) % 2) == 0) {
2254 intel_miptree_updownsample(struct brw_context
*brw
,
2255 struct intel_mipmap_tree
*src
,
2256 struct intel_mipmap_tree
*dst
)
2258 brw_blorp_blit_miptrees(brw
,
2259 src
, 0 /* level */, 0 /* layer */,
2260 src
->format
, SWIZZLE_XYZW
,
2261 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2263 src
->logical_width0
, src
->logical_height0
,
2265 dst
->logical_width0
, dst
->logical_height0
,
2266 GL_NEAREST
, false, false /*mirror x, y*/,
2269 if (src
->stencil_mt
) {
2270 brw_blorp_blit_miptrees(brw
,
2271 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2272 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2273 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2274 dst
->stencil_mt
->format
,
2276 src
->logical_width0
, src
->logical_height0
,
2278 dst
->logical_width0
, dst
->logical_height0
,
2279 GL_NEAREST
, false, false /*mirror x, y*/,
2280 false, false /* decode/encode srgb */);
2285 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2287 /* CPU accesses to color buffers don't understand fast color clears, so
2288 * resolve any pending fast color clears before we map.
2290 intel_miptree_resolve_color(brw
, mt
, 0);
2292 drm_intel_bo
*bo
= mt
->bo
;
2294 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2295 intel_batchbuffer_flush(brw
);
2297 if (mt
->tiling
!= I915_TILING_NONE
)
2298 brw_bo_map_gtt(brw
, bo
, "miptree");
2300 brw_bo_map(brw
, bo
, true, "miptree");
2306 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2308 drm_intel_bo_unmap(mt
->bo
);
2312 intel_miptree_map_gtt(struct brw_context
*brw
,
2313 struct intel_mipmap_tree
*mt
,
2314 struct intel_miptree_map
*map
,
2315 unsigned int level
, unsigned int slice
)
2317 unsigned int bw
, bh
;
2319 unsigned int image_x
, image_y
;
2320 intptr_t x
= map
->x
;
2321 intptr_t y
= map
->y
;
2323 /* For compressed formats, the stride is the number of bytes per
2324 * row of blocks. intel_miptree_get_image_offset() already does
2327 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2328 assert(y
% bh
== 0);
2329 assert(x
% bw
== 0);
2333 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2338 /* Note that in the case of cube maps, the caller must have passed the
2339 * slice number referencing the face.
2341 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2345 map
->stride
= mt
->pitch
;
2346 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2349 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2350 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2351 map
->x
, map
->y
, map
->w
, map
->h
,
2352 mt
, _mesa_get_format_name(mt
->format
),
2353 x
, y
, map
->ptr
, map
->stride
);
2357 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2359 intel_miptree_unmap_raw(mt
);
2363 intel_miptree_map_blit(struct brw_context
*brw
,
2364 struct intel_mipmap_tree
*mt
,
2365 struct intel_miptree_map
*map
,
2366 unsigned int level
, unsigned int slice
)
2368 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2369 /* first_level */ 0,
2373 MIPTREE_LAYOUT_TILING_NONE
);
2375 if (!map
->linear_mt
) {
2376 fprintf(stderr
, "Failed to allocate blit temporary\n");
2379 map
->stride
= map
->linear_mt
->pitch
;
2381 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2382 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2383 * invalidate is set, since we'll be writing the whole rectangle from our
2384 * temporary buffer back out.
2386 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2387 if (!intel_miptree_blit(brw
,
2389 map
->x
, map
->y
, false,
2390 map
->linear_mt
, 0, 0,
2392 map
->w
, map
->h
, GL_COPY
)) {
2393 fprintf(stderr
, "Failed to blit\n");
2398 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2400 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2401 map
->x
, map
->y
, map
->w
, map
->h
,
2402 mt
, _mesa_get_format_name(mt
->format
),
2403 level
, slice
, map
->ptr
, map
->stride
);
2408 intel_miptree_release(&map
->linear_mt
);
2414 intel_miptree_unmap_blit(struct brw_context
*brw
,
2415 struct intel_mipmap_tree
*mt
,
2416 struct intel_miptree_map
*map
,
2420 struct gl_context
*ctx
= &brw
->ctx
;
2422 intel_miptree_unmap_raw(map
->linear_mt
);
2424 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2425 bool ok
= intel_miptree_blit(brw
,
2426 map
->linear_mt
, 0, 0,
2429 map
->x
, map
->y
, false,
2430 map
->w
, map
->h
, GL_COPY
);
2431 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2434 intel_miptree_release(&map
->linear_mt
);
2438 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2440 #if defined(USE_SSE41)
2442 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2443 struct intel_mipmap_tree
*mt
,
2444 struct intel_miptree_map
*map
,
2445 unsigned int level
, unsigned int slice
)
2447 assert(map
->mode
& GL_MAP_READ_BIT
);
2448 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2450 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2451 map
->x
, map
->y
, map
->w
, map
->h
,
2452 mt
, _mesa_get_format_name(mt
->format
),
2453 level
, slice
, map
->ptr
, map
->stride
);
2455 /* Map the original image */
2458 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2462 void *src
= intel_miptree_map_raw(brw
, mt
);
2468 src
+= image_y
* mt
->pitch
;
2469 src
+= image_x
* mt
->cpp
;
2471 /* Due to the pixel offsets for the particular image being mapped, our
2472 * src pointer may not be 16-byte aligned. However, if the pitch is
2473 * divisible by 16, then the amount by which it's misaligned will remain
2474 * consistent from row to row.
2476 assert((mt
->pitch
% 16) == 0);
2477 const int misalignment
= ((uintptr_t) src
) & 15;
2479 /* Create an untiled temporary buffer for the mapping. */
2480 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2482 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2484 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2485 /* Offset the destination so it has the same misalignment as src. */
2486 map
->ptr
= map
->buffer
+ misalignment
;
2488 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2490 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2491 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2492 void *src_ptr
= src
+ y
* mt
->pitch
;
2494 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2497 intel_miptree_unmap_raw(mt
);
2501 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2502 struct intel_mipmap_tree
*mt
,
2503 struct intel_miptree_map
*map
,
2507 _mesa_align_free(map
->buffer
);
2514 intel_miptree_map_s8(struct brw_context
*brw
,
2515 struct intel_mipmap_tree
*mt
,
2516 struct intel_miptree_map
*map
,
2517 unsigned int level
, unsigned int slice
)
2519 map
->stride
= map
->w
;
2520 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2524 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2525 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2526 * invalidate is set, since we'll be writing the whole rectangle from our
2527 * temporary buffer back out.
2529 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2530 uint8_t *untiled_s8_map
= map
->ptr
;
2531 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2532 unsigned int image_x
, image_y
;
2534 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2536 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2537 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2538 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2539 x
+ image_x
+ map
->x
,
2540 y
+ image_y
+ map
->y
,
2541 brw
->has_swizzling
);
2542 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2546 intel_miptree_unmap_raw(mt
);
2548 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2549 map
->x
, map
->y
, map
->w
, map
->h
,
2550 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2552 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2553 map
->x
, map
->y
, map
->w
, map
->h
,
2554 mt
, map
->ptr
, map
->stride
);
2559 intel_miptree_unmap_s8(struct brw_context
*brw
,
2560 struct intel_mipmap_tree
*mt
,
2561 struct intel_miptree_map
*map
,
2565 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2566 unsigned int image_x
, image_y
;
2567 uint8_t *untiled_s8_map
= map
->ptr
;
2568 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2570 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2572 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2573 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2574 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2575 image_x
+ x
+ map
->x
,
2576 image_y
+ y
+ map
->y
,
2577 brw
->has_swizzling
);
2578 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2582 intel_miptree_unmap_raw(mt
);
2589 intel_miptree_map_etc(struct brw_context
*brw
,
2590 struct intel_mipmap_tree
*mt
,
2591 struct intel_miptree_map
*map
,
2595 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2596 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2597 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2600 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2601 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2603 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2604 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2605 map
->w
, map
->h
, 1));
2606 map
->ptr
= map
->buffer
;
2610 intel_miptree_unmap_etc(struct brw_context
*brw
,
2611 struct intel_mipmap_tree
*mt
,
2612 struct intel_miptree_map
*map
,
2618 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2623 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2624 + image_y
* mt
->pitch
2625 + image_x
* mt
->cpp
;
2627 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2628 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2629 map
->ptr
, map
->stride
,
2632 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2633 map
->ptr
, map
->stride
,
2634 map
->w
, map
->h
, mt
->etc_format
);
2636 intel_miptree_unmap_raw(mt
);
2641 * Mapping function for packed depth/stencil miptrees backed by real separate
2642 * miptrees for depth and stencil.
2644 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2645 * separate from the depth buffer. Yet at the GL API level, we have to expose
2646 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2647 * be able to map that memory for texture storage and glReadPixels-type
2648 * operations. We give Mesa core that access by mallocing a temporary and
2649 * copying the data between the actual backing store and the temporary.
2652 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2653 struct intel_mipmap_tree
*mt
,
2654 struct intel_miptree_map
*map
,
2655 unsigned int level
, unsigned int slice
)
2657 struct intel_mipmap_tree
*z_mt
= mt
;
2658 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2659 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2660 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2662 map
->stride
= map
->w
* packed_bpp
;
2663 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2667 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2668 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2669 * invalidate is set, since we'll be writing the whole rectangle from our
2670 * temporary buffer back out.
2672 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2673 uint32_t *packed_map
= map
->ptr
;
2674 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2675 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2676 unsigned int s_image_x
, s_image_y
;
2677 unsigned int z_image_x
, z_image_y
;
2679 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2680 &s_image_x
, &s_image_y
);
2681 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2682 &z_image_x
, &z_image_y
);
2684 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2685 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2686 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2687 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2690 brw
->has_swizzling
);
2691 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2693 (map_x
+ z_image_x
));
2694 uint8_t s
= s_map
[s_offset
];
2695 uint32_t z
= z_map
[z_offset
];
2697 if (map_z32f_x24s8
) {
2698 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2699 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2701 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2706 intel_miptree_unmap_raw(s_mt
);
2707 intel_miptree_unmap_raw(z_mt
);
2709 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2711 map
->x
, map
->y
, map
->w
, map
->h
,
2712 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2713 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2714 map
->ptr
, map
->stride
);
2716 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2717 map
->x
, map
->y
, map
->w
, map
->h
,
2718 mt
, map
->ptr
, map
->stride
);
2723 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2724 struct intel_mipmap_tree
*mt
,
2725 struct intel_miptree_map
*map
,
2729 struct intel_mipmap_tree
*z_mt
= mt
;
2730 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2731 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2733 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2734 uint32_t *packed_map
= map
->ptr
;
2735 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2736 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2737 unsigned int s_image_x
, s_image_y
;
2738 unsigned int z_image_x
, z_image_y
;
2740 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2741 &s_image_x
, &s_image_y
);
2742 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2743 &z_image_x
, &z_image_y
);
2745 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2746 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2747 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2748 x
+ s_image_x
+ map
->x
,
2749 y
+ s_image_y
+ map
->y
,
2750 brw
->has_swizzling
);
2751 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2753 (x
+ z_image_x
+ map
->x
));
2755 if (map_z32f_x24s8
) {
2756 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2757 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2759 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2760 s_map
[s_offset
] = packed
>> 24;
2761 z_map
[z_offset
] = packed
;
2766 intel_miptree_unmap_raw(s_mt
);
2767 intel_miptree_unmap_raw(z_mt
);
2769 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2771 map
->x
, map
->y
, map
->w
, map
->h
,
2772 z_mt
, _mesa_get_format_name(z_mt
->format
),
2773 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2774 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2775 map
->ptr
, map
->stride
);
2782 * Create and attach a map to the miptree at (level, slice). Return the
2785 static struct intel_miptree_map
*
2786 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2795 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2800 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2801 mt
->level
[level
].slice
[slice
].map
= map
;
2813 * Release the map at (level, slice).
2816 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2820 struct intel_miptree_map
**map
;
2822 map
= &mt
->level
[level
].slice
[slice
].map
;
2828 can_blit_slice(struct intel_mipmap_tree
*mt
,
2829 unsigned int level
, unsigned int slice
)
2833 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2834 if (image_x
>= 32768 || image_y
>= 32768)
2837 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2838 if (mt
->pitch
>= 32768)
2845 use_intel_mipree_map_blit(struct brw_context
*brw
,
2846 struct intel_mipmap_tree
*mt
,
2852 /* It's probably not worth swapping to the blit ring because of
2853 * all the overhead involved. But, we must use blitter for the
2854 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2856 (!(mode
& GL_MAP_WRITE_BIT
) ||
2857 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2859 (mt
->tiling
== I915_TILING_X
||
2860 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2861 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2862 /* Fast copy blit on skl+ supports all tiling formats. */
2864 can_blit_slice(mt
, level
, slice
))
2867 if (mt
->tiling
!= I915_TILING_NONE
&&
2868 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2869 assert(can_blit_slice(mt
, level
, slice
));
2877 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2878 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2879 * arithmetic overflow.
2881 * If you call this function and use \a out_stride, then you're doing pointer
2882 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2883 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2884 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2885 * which usually have type uint32_t or GLuint.
2888 intel_miptree_map(struct brw_context
*brw
,
2889 struct intel_mipmap_tree
*mt
,
2898 ptrdiff_t *out_stride
)
2900 struct intel_miptree_map
*map
;
2902 assert(mt
->num_samples
<= 1);
2904 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2911 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2912 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2913 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2916 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2917 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2918 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2919 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2920 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2921 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2922 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2923 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2924 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2925 #if defined(USE_SSE41)
2926 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2927 !mt
->compressed
&& cpu_has_sse4_1
&&
2928 (mt
->pitch
% 16 == 0)) {
2929 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2932 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2933 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2934 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2937 *out_ptr
= map
->ptr
;
2938 *out_stride
= map
->stride
;
2940 if (map
->ptr
== NULL
)
2941 intel_miptree_release_map(mt
, level
, slice
);
2945 intel_miptree_unmap(struct brw_context
*brw
,
2946 struct intel_mipmap_tree
*mt
,
2950 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2952 assert(mt
->num_samples
<= 1);
2957 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2958 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2960 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2961 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2962 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2963 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2964 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2965 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2966 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2967 } else if (map
->linear_mt
) {
2968 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2969 #if defined(USE_SSE41)
2970 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2971 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2974 intel_miptree_unmap_gtt(mt
);
2977 intel_miptree_release_map(mt
, level
, slice
);
2981 intel_miptree_get_isl_surf(struct brw_context
*brw
,
2982 const struct intel_mipmap_tree
*mt
,
2983 struct isl_surf
*surf
)
2985 switch (mt
->target
) {
2987 case GL_TEXTURE_1D_ARRAY
: {
2988 surf
->dim
= ISL_SURF_DIM_1D
;
2989 if (brw
->gen
>= 9 && mt
->tiling
== I915_TILING_NONE
)
2990 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN9_1D
;
2992 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
2996 case GL_TEXTURE_2D_ARRAY
:
2997 case GL_TEXTURE_RECTANGLE
:
2998 case GL_TEXTURE_CUBE_MAP
:
2999 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3000 case GL_TEXTURE_2D_MULTISAMPLE
:
3001 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3002 case GL_TEXTURE_EXTERNAL_OES
:
3003 surf
->dim
= ISL_SURF_DIM_2D
;
3004 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3007 surf
->dim
= ISL_SURF_DIM_3D
;
3009 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3011 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_3D
;
3014 unreachable("Invalid texture target");
3017 if (mt
->num_samples
> 1) {
3018 switch (mt
->msaa_layout
) {
3019 case INTEL_MSAA_LAYOUT_IMS
:
3020 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3022 case INTEL_MSAA_LAYOUT_UMS
:
3023 case INTEL_MSAA_LAYOUT_CMS
:
3024 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3027 unreachable("Invalid MSAA layout");
3030 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3033 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3034 surf
->tiling
= ISL_TILING_W
;
3035 /* The ISL definition of row_pitch matches the surface state pitch field
3036 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3037 * the factor of 2 for W-tiling in row_pitch.
3039 surf
->row_pitch
= 2 * mt
->pitch
;
3041 switch (mt
->tiling
) {
3042 case I915_TILING_NONE
:
3043 surf
->tiling
= ISL_TILING_LINEAR
;
3046 surf
->tiling
= ISL_TILING_X
;
3049 switch (mt
->tr_mode
) {
3050 case INTEL_MIPTREE_TRMODE_NONE
:
3051 surf
->tiling
= ISL_TILING_Y0
;
3053 case INTEL_MIPTREE_TRMODE_YF
:
3054 surf
->tiling
= ISL_TILING_Yf
;
3056 case INTEL_MIPTREE_TRMODE_YS
:
3057 surf
->tiling
= ISL_TILING_Ys
;
3062 unreachable("Invalid tiling mode");
3065 surf
->row_pitch
= mt
->pitch
;
3068 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3070 if (brw
->gen
>= 9) {
3071 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3072 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3073 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3075 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3076 * alignment in terms of surface elements like we want.
3078 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3081 /* On earlier gens it's stored in pixels. */
3083 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3084 surf
->image_alignment_el
=
3085 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3088 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3089 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3090 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3091 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3092 surf
->logical_level0_px
.array_len
= 1;
3094 surf
->logical_level0_px
.depth
= 1;
3095 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3098 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3099 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3100 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3101 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3102 surf
->phys_level0_sa
.array_len
= 1;
3104 surf
->phys_level0_sa
.depth
= 1;
3105 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3108 surf
->levels
= mt
->last_level
+ 1;
3109 surf
->samples
= MAX2(mt
->num_samples
, 1);
3111 surf
->size
= 0; /* TODO */
3112 surf
->alignment
= 0; /* TODO */
3114 switch (surf
->dim_layout
) {
3115 case ISL_DIM_LAYOUT_GEN4_2D
:
3116 case ISL_DIM_LAYOUT_GEN4_3D
:
3117 if (brw
->gen
>= 9) {
3118 surf
->array_pitch_el_rows
= mt
->qpitch
;
3121 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3122 assert(mt
->qpitch
% bh
== 0);
3123 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3126 case ISL_DIM_LAYOUT_GEN9_1D
:
3127 surf
->array_pitch_el_rows
= 1;
3131 switch (mt
->array_layout
) {
3132 case ALL_LOD_IN_EACH_SLICE
:
3133 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3135 case ALL_SLICES_AT_EACH_LOD
:
3136 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3139 unreachable("Invalid array layout");
3142 surf
->usage
= 0; /* TODO */
3145 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3146 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3147 * PASS IT INTO isl_surf_fill_state.
3150 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3151 const struct intel_mipmap_tree
*mt
,
3152 struct isl_surf
*surf
,
3153 enum isl_aux_usage
*usage
)
3155 /* Much is the same as the regular surface */
3156 intel_miptree_get_isl_surf(brw
, mt
->mcs_mt
, surf
);
3158 /* Figure out the layout */
3159 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3160 *usage
= ISL_AUX_USAGE_HIZ
;
3161 } else if (mt
->num_samples
> 1) {
3162 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3163 *usage
= ISL_AUX_USAGE_MCS
;
3164 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3165 assert(brw
->gen
>= 9);
3166 *usage
= ISL_AUX_USAGE_CCS_E
;
3167 } else if (mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_NO_MCS
) {
3168 *usage
= ISL_AUX_USAGE_CCS_D
;
3170 unreachable("Invalid MCS miptree");
3173 /* Figure out the format and tiling of the auxiliary surface */
3175 case ISL_AUX_USAGE_NONE
:
3176 unreachable("Invalid MCS miptree");
3178 case ISL_AUX_USAGE_HIZ
:
3179 surf
->format
= ISL_FORMAT_HIZ
;
3180 surf
->tiling
= ISL_TILING_HIZ
;
3181 surf
->usage
= ISL_SURF_USAGE_HIZ_BIT
;
3184 case ISL_AUX_USAGE_MCS
:
3187 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3188 * HALIGN 16 must be used."
3191 assert(mt
->halign
== 16);
3193 surf
->usage
= ISL_SURF_USAGE_MCS_BIT
;
3195 switch (mt
->num_samples
) {
3196 case 2: surf
->format
= ISL_FORMAT_MCS_2X
; break;
3197 case 4: surf
->format
= ISL_FORMAT_MCS_4X
; break;
3198 case 8: surf
->format
= ISL_FORMAT_MCS_8X
; break;
3199 case 16: surf
->format
= ISL_FORMAT_MCS_16X
; break;
3201 unreachable("Invalid number of samples");
3205 case ISL_AUX_USAGE_CCS_D
:
3206 case ISL_AUX_USAGE_CCS_E
:
3208 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3210 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3212 * From the hardware spec for GEN9:
3214 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3215 * HALIGN 16 must be used."
3217 assert(mt
->num_samples
<= 1);
3219 assert(mt
->halign
== 16);
3221 surf
->tiling
= ISL_TILING_CCS
;
3222 surf
->usage
= ISL_SURF_USAGE_CCS_BIT
;
3224 if (brw
->gen
>= 9) {
3225 assert(mt
->tiling
== I915_TILING_Y
);
3226 switch (_mesa_get_format_bytes(mt
->format
)) {
3227 case 4: surf
->format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
3228 case 8: surf
->format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
3229 case 16: surf
->format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
3231 unreachable("Invalid format size for color compression");
3233 } else if (mt
->tiling
== I915_TILING_Y
) {
3234 switch (_mesa_get_format_bytes(mt
->format
)) {
3235 case 4: surf
->format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
3236 case 8: surf
->format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
3237 case 16: surf
->format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
3239 unreachable("Invalid format size for color compression");
3242 assert(mt
->tiling
== I915_TILING_X
);
3243 switch (_mesa_get_format_bytes(mt
->format
)) {
3244 case 4: surf
->format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
3245 case 8: surf
->format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
3246 case 16: surf
->format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
3248 unreachable("Invalid format size for color compression");
3254 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3255 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3256 * in elements of the primary color surface so we have to divide by the
3257 * compression block height.
3259 surf
->array_pitch_el_rows
= mt
->qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3262 union isl_color_value
3263 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3264 const struct intel_mipmap_tree
*mt
)
3266 union isl_color_value clear_color
;
3268 if (brw
->gen
>= 9) {
3269 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3270 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3271 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3272 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3273 } else if (_mesa_is_format_integer(mt
->format
)) {
3274 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3275 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3276 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3277 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3279 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3280 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3281 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3282 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;