2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
,
125 enum isl_tiling tiling
)
127 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
128 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
130 * - Support is limited to tiled render targets.
132 * Gen9 changes the restriction to Y-tile only.
135 return tiling
== ISL_TILING_Y0
;
136 else if (brw
->gen
>= 7)
137 return tiling
!= ISL_TILING_LINEAR
;
143 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
144 * can be used. This doesn't (and should not) inspect any of the properties of
147 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
148 * beneath the "Fast Color Clear" bullet (p326):
150 * - Support is for non-mip-mapped and non-array surface types only.
152 * And then later, on p327:
154 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
157 * From the Skylake documentation, it is made clear that X-tiling is no longer
160 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
164 intel_miptree_supports_ccs(struct brw_context
*brw
,
165 const struct intel_mipmap_tree
*mt
)
167 /* MCS support does not exist prior to Gen7 */
171 /* This function applies only to non-multisampled render targets. */
172 if (mt
->surf
.samples
> 1)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
186 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
187 const bool arrayed
= mt
->physical_depth0
!= 1;
190 /* Multisample surfaces with the CMS layout are not layered surfaces,
191 * yet still have physical_depth0 > 1. Assert that we don't
192 * accidentally reject a multisampled surface here. We should have
193 * rejected it earlier by explicitly checking the sample count.
195 assert(mt
->surf
.samples
== 1);
198 /* Handle the hardware restrictions...
200 * All GENs have the following restriction: "MCS buffer for non-MSRT is
201 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
203 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
204 * Non-MultiSampler Render Target Restrictions) Support is for
205 * non-mip-mapped and non-array surface types only.
207 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
208 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
209 * surfaces are supported with MCS buffer layout with these alignments in
210 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
212 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
213 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
214 * surfaces are supported with MCS buffer layout with these alignments in
215 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
217 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
220 /* There's no point in using an MCS buffer if the surface isn't in a
223 if (!brw
->mesa_format_supports_render
[mt
->format
])
227 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
228 const enum isl_format isl_format
=
229 brw_isl_format_for_mesa_format(linear_format
);
230 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
236 intel_tiling_supports_hiz(const struct brw_context
*brw
,
237 enum isl_tiling tiling
)
242 return tiling
== ISL_TILING_Y0
;
246 intel_miptree_supports_hiz(const struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
252 switch (mt
->format
) {
253 case MESA_FORMAT_Z_FLOAT32
:
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
256 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
257 case MESA_FORMAT_Z_UNORM16
:
265 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
266 const struct intel_mipmap_tree
*mt
)
268 /* For now compression is only enabled for integer formats even though
269 * there exist supported floating point formats also. This is a heuristic
270 * decision based on current public benchmarks. In none of the cases these
271 * formats provided any improvement but a few cases were seen to regress.
272 * Hence these are left to to be enabled in the future when they are known
275 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
278 if (!intel_miptree_supports_ccs(brw
, mt
))
281 /* Fast clear can be also used to clear srgb surfaces by using equivalent
282 * linear format. This trick, however, can't be extended to be used with
283 * lossless compression and therefore a check is needed to see if the format
286 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
290 * Determine depth format corresponding to a depth+stencil format,
291 * for separate stencil.
294 intel_depth_format_for_depthstencil_format(mesa_format format
) {
296 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
297 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
298 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
299 return MESA_FORMAT_Z_FLOAT32
;
306 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
307 unsigned depth0
, struct intel_mipmap_level
*table
)
309 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
311 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
313 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
314 if (!table
[level
].slice
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++)
322 free(table
[level
].slice
);
328 needs_separate_stencil(const struct brw_context
*brw
,
329 struct intel_mipmap_tree
*mt
,
330 mesa_format format
, uint32_t layout_flags
)
333 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
336 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
339 if (brw
->must_use_separate_stencil
)
342 return brw
->has_separate_stencil
&&
343 intel_miptree_supports_hiz(brw
, mt
);
347 * @param for_bo Indicates that the caller is
348 * intel_miptree_create_for_bo(). If true, then do not create
351 static struct intel_mipmap_tree
*
352 intel_miptree_create_layout(struct brw_context
*brw
,
361 uint32_t layout_flags
)
363 assert(num_samples
> 0);
365 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
369 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
370 _mesa_enum_to_string(target
),
371 _mesa_get_format_name(format
),
372 first_level
, last_level
, depth0
, mt
);
374 if (target
== GL_TEXTURE_1D_ARRAY
)
375 assert(height0
== 1);
379 mt
->first_level
= first_level
;
380 mt
->last_level
= last_level
;
381 mt
->logical_width0
= width0
;
382 mt
->logical_height0
= height0
;
383 mt
->logical_depth0
= depth0
;
384 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
385 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
386 mt
->supports_fast_clear
= false;
387 mt
->aux_state
= NULL
;
388 mt
->cpp
= _mesa_get_format_bytes(format
);
389 mt
->surf
.samples
= num_samples
;
390 mt
->compressed
= _mesa_is_format_compressed(format
);
391 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
394 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
395 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
397 int depth_multiply
= 1;
398 if (num_samples
> 1) {
399 /* Adjust width/height/depth for MSAA */
400 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
401 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
402 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
403 * "If the surface is multisampled and it is a depth or stencil
404 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
405 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
408 * +----------------------------------------------------------------+
409 * | Num Multisamples | W_l = | H_l = |
410 * +----------------------------------------------------------------+
411 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
412 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
413 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
414 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
415 * +----------------------------------------------------------------+
418 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
419 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
420 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
422 * Another more complicated explanation for these adjustments comes
423 * from the Sandybridge PRM, volume 4, part 1, page 31:
425 * "Any of the other messages (sample*, LOD, load4) used with a
426 * (4x) multisampled surface will in-effect sample a surface with
427 * double the height and width as that indicated in the surface
428 * state. Each pixel position on the original-sized surface is
429 * replaced with a 2x2 of samples with the following arrangement:
434 * Thus, when sampling from a multisampled texture, it behaves as
435 * though the layout in memory for (x,y,sample) is:
437 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
438 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
440 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
441 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
443 * However, the actual layout of multisampled data in memory is:
445 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
446 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
448 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
449 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
451 * This pattern repeats for each 2x2 pixel block.
453 * As a result, when calculating the size of our 4-sample buffer for
454 * an odd width or height, we have to align before scaling up because
455 * sample 3 is in that bottom right 2x2 block.
457 switch (num_samples
) {
459 assert(brw
->gen
>= 8);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2);
464 width0
= ALIGN(width0
, 2) * 2;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 2;
472 width0
= ALIGN(width0
, 2) * 4;
473 height0
= ALIGN(height0
, 2) * 4;
476 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
479 unreachable("not reached");
482 /* Non-interleaved */
483 depth_multiply
= num_samples
;
484 depth0
*= depth_multiply
;
488 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->surf
.msaa_layout
) {
508 case ISL_MSAA_LAYOUT_NONE
:
509 case ISL_MSAA_LAYOUT_INTERLEAVED
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case ISL_MSAA_LAYOUT_ARRAY
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
519 assert(depth0
== 6 * depth_multiply
);
521 mt
->physical_width0
= width0
;
522 mt
->physical_height0
= height0
;
523 mt
->physical_depth0
= depth0
;
525 assert(!needs_separate_stencil(brw
, mt
, format
, layout_flags
));
528 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
529 * multisampled or have an AUX buffer attached to it.
531 * GEN | MSRT | AUX_CCS_* or AUX_MCS
532 * -------------------------------------------
533 * 9 | HALIGN_16 | HALIGN_16
534 * 8 | HALIGN_ANY | HALIGN_16
538 if (intel_miptree_supports_ccs(brw
, mt
)) {
539 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
540 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
541 } else if (brw
->gen
>= 9 && num_samples
> 1) {
542 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
544 const UNUSED
bool is_lossless_compressed_aux
=
545 brw
->gen
>= 9 && num_samples
== 1 &&
546 mt
->format
== MESA_FORMAT_R_UINT32
;
548 /* For now, nothing else has this requirement */
549 assert(is_lossless_compressed_aux
||
550 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
553 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
554 intel_miptree_release(&mt
);
563 * Choose the aux usage for this miptree. This function must be called fairly
564 * late in the miptree create process after we have a tiling.
567 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
568 struct intel_mipmap_tree
*mt
)
570 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
572 const unsigned no_flags
= 0;
573 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
574 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
575 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
576 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
577 intel_miptree_supports_ccs(brw
, mt
)) {
578 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
579 brw
->gen
>= 9 && !mt
->is_scanout
&&
580 intel_miptree_supports_ccs_e(brw
, mt
)) {
581 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
583 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
585 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
586 intel_miptree_supports_hiz(brw
, mt
)) {
587 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
590 /* We can do fast-clear on all auxiliary surface types that are
591 * allocated through the normal texture creation paths.
593 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
594 mt
->supports_fast_clear
= true;
599 * Choose an appropriate uncompressed format for a requested
600 * compressed format, if unsupported.
603 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
605 /* No need to lower ETC formats on these platforms,
606 * they are supported natively.
608 if (brw
->gen
>= 8 || brw
->is_baytrail
)
612 case MESA_FORMAT_ETC1_RGB8
:
613 return MESA_FORMAT_R8G8B8X8_UNORM
;
614 case MESA_FORMAT_ETC2_RGB8
:
615 return MESA_FORMAT_R8G8B8X8_UNORM
;
616 case MESA_FORMAT_ETC2_SRGB8
:
617 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
618 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
619 return MESA_FORMAT_B8G8R8A8_SRGB
;
620 case MESA_FORMAT_ETC2_RGBA8_EAC
:
621 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
622 return MESA_FORMAT_R8G8B8A8_UNORM
;
623 case MESA_FORMAT_ETC2_R11_EAC
:
624 return MESA_FORMAT_R_UNORM16
;
625 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
626 return MESA_FORMAT_R_SNORM16
;
627 case MESA_FORMAT_ETC2_RG11_EAC
:
628 return MESA_FORMAT_R16G16_UNORM
;
629 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
630 return MESA_FORMAT_R16G16_SNORM
;
632 /* Non ETC1 / ETC2 format */
638 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
640 /* In case of physical dimensions one needs to consider also the layout.
641 * See isl_calc_phys_level0_extent_sa().
643 if (surf
->dim
!= ISL_SURF_DIM_3D
)
644 return surf
->phys_level0_sa
.array_len
;
646 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
647 return minify(surf
->phys_level0_sa
.array_len
, level
);
649 return minify(surf
->phys_level0_sa
.depth
, level
);
652 /** \brief Assert that the level and layer are valid for the miptree. */
654 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
662 assert(level
>= mt
->first_level
);
663 assert(level
<= mt
->last_level
);
665 if (mt
->surf
.size
> 0)
666 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
668 assert(layer
< mt
->level
[level
].depth
);
671 static enum isl_aux_state
**
672 create_aux_state_map(struct intel_mipmap_tree
*mt
,
673 enum isl_aux_state initial
)
675 const uint32_t levels
= mt
->last_level
+ 1;
677 uint32_t total_slices
= 0;
678 for (uint32_t level
= 0; level
< levels
; level
++) {
679 if (mt
->surf
.size
> 0)
680 total_slices
+= get_num_phys_layers(&mt
->surf
, level
);
682 total_slices
+= mt
->level
[level
].depth
;
685 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
687 /* We're going to allocate a single chunk of data for both the per-level
688 * reference array and the arrays of aux_state. This makes cleanup
689 * significantly easier.
691 const size_t total_size
= per_level_array_size
+
692 total_slices
* sizeof(enum isl_aux_state
);
693 void *data
= malloc(total_size
);
697 enum isl_aux_state
**per_level_arr
= data
;
698 enum isl_aux_state
*s
= data
+ per_level_array_size
;
699 for (uint32_t level
= 0; level
< levels
; level
++) {
700 per_level_arr
[level
] = s
;
702 unsigned level_depth
;
703 if (mt
->surf
.size
> 0)
704 level_depth
= get_num_phys_layers(&mt
->surf
, level
);
706 level_depth
= mt
->level
[level
].depth
;
708 for (uint32_t a
= 0; a
< level_depth
; a
++)
711 assert((void *)s
== data
+ total_size
);
713 return per_level_arr
;
717 free_aux_state_map(enum isl_aux_state
**state
)
723 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
724 enum isl_tiling tiling
, unsigned samples
)
729 if (tiling
== ISL_TILING_LINEAR
)
732 /* If the width is much smaller than a tile, don't bother tiling. */
736 if (ALIGN(row_pitch
, 512) >= 32768) {
737 perf_debug("row pitch %u too large to blit, falling back to untiled",
745 static struct intel_mipmap_tree
*
746 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
747 unsigned first_level
, unsigned last_level
,
748 unsigned width0
, unsigned height0
, unsigned depth0
,
749 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
750 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
751 unsigned row_pitch
, struct brw_bo
*bo
)
753 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
757 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
765 if (target
== GL_TEXTURE_CUBE_MAP
||
766 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
767 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
769 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
771 _mesa_enum_to_string(target
),
772 _mesa_get_format_name(format
),
773 num_samples
, width0
, height0
, depth0
,
774 first_level
, last_level
, mt
);
776 struct isl_surf_init_info init_info
= {
777 .dim
= get_isl_surf_dim(target
),
778 .format
= translate_tex_format(brw
, format
, false),
781 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
782 .levels
= last_level
- first_level
+ 1,
783 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
784 .samples
= num_samples
,
785 .row_pitch
= row_pitch
,
786 .usage
= isl_usage_flags
,
787 .tiling_flags
= tiling_flags
,
790 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
793 /* In case caller doesn't specifically request Y-tiling (needed
794 * unconditionally for depth), check for corner cases needing special
797 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
798 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
799 mt
->surf
.tiling
, mt
->surf
.samples
)) {
800 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
801 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
806 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
809 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
811 isl_tiling_to_i915_tiling(
813 mt
->surf
.row_pitch
, alloc_flags
);
820 mt
->first_level
= first_level
;
821 mt
->last_level
= last_level
;
824 mt
->aux_state
= NULL
;
825 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
830 intel_miptree_release(&mt
);
835 make_separate_stencil_surface(struct brw_context
*brw
,
836 struct intel_mipmap_tree
*mt
)
838 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
839 0, mt
->surf
.levels
- 1,
840 mt
->surf
.logical_level0_px
.width
,
841 mt
->surf
.logical_level0_px
.height
,
842 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
843 mt
->surf
.logical_level0_px
.depth
:
844 mt
->surf
.logical_level0_px
.array_len
,
845 mt
->surf
.samples
, ISL_TILING_W_BIT
,
846 ISL_SURF_USAGE_STENCIL_BIT
|
847 ISL_SURF_USAGE_TEXTURE_BIT
,
848 BO_ALLOC_FOR_RENDER
, 0, NULL
);
853 mt
->stencil_mt
->r8stencil_needs_update
= true;
859 force_linear_tiling(uint32_t layout_flags
)
861 /* ANY includes NONE and Y bit. */
862 if (layout_flags
& MIPTREE_LAYOUT_TILING_Y
)
865 return layout_flags
& MIPTREE_LAYOUT_TILING_NONE
;
868 static struct intel_mipmap_tree
*
869 miptree_create(struct brw_context
*brw
,
878 uint32_t layout_flags
)
880 if (format
== MESA_FORMAT_S_UINT8
)
881 return make_surface(brw
, target
, format
, first_level
, last_level
,
882 width0
, height0
, depth0
, num_samples
,
884 ISL_SURF_USAGE_STENCIL_BIT
|
885 ISL_SURF_USAGE_TEXTURE_BIT
,
890 const GLenum base_format
= _mesa_get_format_base_format(format
);
891 if ((base_format
== GL_DEPTH_COMPONENT
||
892 base_format
== GL_DEPTH_STENCIL
) &&
893 !force_linear_tiling(layout_flags
)) {
894 /* Fix up the Z miptree format for how we're splitting out separate
895 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
897 const mesa_format depth_only_format
=
898 intel_depth_format_for_depthstencil_format(format
);
899 struct intel_mipmap_tree
*mt
= make_surface(
900 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
901 first_level
, last_level
,
902 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
903 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
904 BO_ALLOC_FOR_RENDER
, 0, NULL
);
906 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
) &&
907 !make_separate_stencil_surface(brw
, mt
)) {
908 intel_miptree_release(&mt
);
912 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
913 intel_miptree_choose_aux_usage(brw
, mt
);
918 struct intel_mipmap_tree
*mt
;
919 mesa_format tex_format
= format
;
920 mesa_format etc_format
= MESA_FORMAT_NONE
;
921 uint32_t alloc_flags
= 0;
923 format
= intel_lower_compressed_format(brw
, format
);
925 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
927 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
928 mt
= intel_miptree_create_layout(brw
, target
, format
,
929 first_level
, last_level
, width0
,
930 height0
, depth0
, num_samples
,
935 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
936 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
938 mt
->etc_format
= etc_format
;
940 if (format
== MESA_FORMAT_S_UINT8
) {
941 /* Align to size of W tile, 64x64. */
942 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
943 ALIGN(mt
->total_width
, 64),
944 ALIGN(mt
->total_height
, 64),
946 isl_tiling_to_i915_tiling(
951 /* The stencil buffer has quirky pitch requirements. From the
952 * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
953 * dword 1 bits 16:0 - Surface Pitch):
955 * The pitch must be set to 2x the value computed based on width, as
956 * the stencil buffer is stored with two rows interleaved.
958 * While the Ivybridge PRM lacks this comment, the BSpec contains the
959 * same text, and experiments indicate that this is necessary.
961 mt
->surf
.row_pitch
*= 2;
963 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
964 mt
->total_width
, mt
->total_height
,
966 isl_tiling_to_i915_tiling(
972 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
973 mt
->bo
->cache_coherent
= false;
975 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
976 intel_miptree_choose_aux_usage(brw
, mt
);
981 struct intel_mipmap_tree
*
982 intel_miptree_create(struct brw_context
*brw
,
991 uint32_t layout_flags
)
993 assert(num_samples
> 0);
995 struct intel_mipmap_tree
*mt
= miptree_create(
997 first_level
, last_level
,
998 width0
, height0
, depth0
, num_samples
,
1003 /* If the BO is too large to fit in the aperture, we need to use the
1004 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
1005 * handle Y-tiling, so we need to fall back to X.
1007 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
1008 mt
->surf
.tiling
== ISL_TILING_Y0
) {
1009 const uint32_t alloc_flags
=
1010 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
1011 BO_ALLOC_FOR_RENDER
: 0;
1012 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
1013 mt
->total_width
, mt
->total_height
);
1015 mt
->surf
.tiling
= ISL_TILING_X
;
1016 brw_bo_unreference(mt
->bo
);
1017 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
1018 mt
->total_width
, mt
->total_height
, mt
->cpp
,
1019 isl_tiling_to_i915_tiling(
1021 &mt
->surf
.row_pitch
, alloc_flags
);
1027 intel_miptree_release(&mt
);
1031 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1032 intel_miptree_release(&mt
);
1039 struct intel_mipmap_tree
*
1040 intel_miptree_create_for_bo(struct brw_context
*brw
,
1048 uint32_t layout_flags
)
1050 struct intel_mipmap_tree
*mt
;
1051 uint32_t tiling
, swizzle
;
1052 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
1053 const GLenum base_format
= _mesa_get_format_base_format(format
);
1055 if ((base_format
== GL_DEPTH_COMPONENT
||
1056 base_format
== GL_DEPTH_STENCIL
)) {
1057 const mesa_format depth_only_format
=
1058 intel_depth_format_for_depthstencil_format(format
);
1059 mt
= make_surface(brw
, target
,
1060 brw
->gen
>= 6 ? depth_only_format
: format
,
1061 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
1062 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
1063 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1065 brw_bo_reference(bo
);
1067 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1068 intel_miptree_choose_aux_usage(brw
, mt
);
1071 } else if (format
== MESA_FORMAT_S_UINT8
) {
1072 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
1073 0, 0, width
, height
, depth
, 1,
1075 ISL_SURF_USAGE_STENCIL_BIT
|
1076 ISL_SURF_USAGE_TEXTURE_BIT
,
1077 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1081 assert(bo
->size
>= mt
->surf
.size
);
1083 brw_bo_reference(bo
);
1087 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
1089 /* Nothing will be able to use this miptree with the BO if the offset isn't
1092 if (tiling
!= I915_TILING_NONE
)
1093 assert(offset
% 4096 == 0);
1095 /* miptrees can't handle negative pitch. If you need flipping of images,
1096 * that's outside of the scope of the mt.
1100 /* The BO already has a tiling format and we shouldn't confuse the lower
1101 * layers by making it try to find a tiling format again.
1103 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
1104 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
1106 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
1107 mt
= intel_miptree_create_layout(brw
, target
, format
,
1109 width
, height
, depth
,
1110 1 /* num_samples */,
1115 brw_bo_reference(bo
);
1117 mt
->surf
.row_pitch
= pitch
;
1118 mt
->offset
= offset
;
1119 mt
->surf
.tiling
= isl_tiling_from_i915_tiling(tiling
);
1121 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1122 intel_miptree_choose_aux_usage(brw
, mt
);
1127 static struct intel_mipmap_tree
*
1128 miptree_create_for_planar_image(struct brw_context
*brw
,
1129 __DRIimage
*image
, GLenum target
)
1131 struct intel_image_format
*f
= image
->planar_format
;
1132 struct intel_mipmap_tree
*planar_mt
= NULL
;
1134 for (int i
= 0; i
< f
->nplanes
; i
++) {
1135 const int index
= f
->planes
[i
].buffer_index
;
1136 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1137 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1138 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1139 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1141 /* Disable creation of the texture's aux buffers because the driver
1142 * exposes no EGL API to manage them. That is, there is no API for
1143 * resolving the aux buffer's content to the main buffer nor for
1144 * invalidating the aux buffer's content.
1146 struct intel_mipmap_tree
*mt
=
1147 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1148 image
->offsets
[index
],
1150 image
->strides
[index
],
1151 MIPTREE_LAYOUT_DISABLE_AUX
);
1155 mt
->target
= target
;
1160 planar_mt
->plane
[i
- 1] = mt
;
1166 struct intel_mipmap_tree
*
1167 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1168 __DRIimage
*image
, GLenum target
,
1169 enum isl_colorspace colorspace
,
1170 bool is_winsys_image
)
1172 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1173 assert(colorspace
== ISL_COLORSPACE_NONE
||
1174 colorspace
== ISL_COLORSPACE_YUV
);
1175 return miptree_create_for_planar_image(brw
, image
, target
);
1178 mesa_format format
= image
->format
;
1179 switch (colorspace
) {
1180 case ISL_COLORSPACE_NONE
:
1181 /* Keep the image format unmodified */
1184 case ISL_COLORSPACE_LINEAR
:
1185 format
=_mesa_get_srgb_format_linear(format
);
1188 case ISL_COLORSPACE_SRGB
:
1189 format
=_mesa_get_linear_format_srgb(format
);
1193 unreachable("Inalid colorspace for non-planar image");
1196 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1197 /* The texture storage paths in core Mesa detect if the driver does not
1198 * support the user-requested format, and then searches for a
1199 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1200 * do the fallbacks here for important formats.
1202 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1203 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1204 * the Chrome OS compositor consumes as dma_buf EGLImages.
1206 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1209 if (!brw
->ctx
.TextureFormatSupported
[format
])
1212 /* If this image comes in from a window system, we have different
1213 * requirements than if it comes in via an EGL import operation. Window
1214 * system images can use any form of auxiliary compression we wish because
1215 * they get "flushed" before being handed off to the window system and we
1216 * have the opportunity to do resolves. Window system buffers also may be
1217 * used for scanout so we need to flag that appropriately.
1219 const uint32_t mt_layout_flags
=
1220 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1222 /* Disable creation of the texture's aux buffers because the driver exposes
1223 * no EGL API to manage them. That is, there is no API for resolving the aux
1224 * buffer's content to the main buffer nor for invalidating the aux buffer's
1227 struct intel_mipmap_tree
*mt
=
1228 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1229 image
->offset
, image
->width
, image
->height
, 1,
1230 image
->pitch
, mt_layout_flags
);
1234 mt
->target
= target
;
1235 mt
->level
[0].level_x
= image
->tile_x
;
1236 mt
->level
[0].level_y
= image
->tile_y
;
1237 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1238 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1240 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1241 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1242 * trouble resolving back to destination image due to alignment issues.
1244 if (!brw
->has_surface_tile_offset
) {
1245 uint32_t draw_x
, draw_y
;
1246 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1248 if (draw_x
!= 0 || draw_y
!= 0) {
1249 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1250 intel_miptree_release(&mt
);
1255 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1256 intel_miptree_release(&mt
);
1264 * For a singlesample renderbuffer, this simply wraps the given BO with a
1267 * For a multisample renderbuffer, this wraps the window system's
1268 * (singlesample) BO with a singlesample miptree attached to the
1269 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1270 * that will contain the actual rendering (which is lazily resolved to
1271 * irb->singlesample_mt).
1274 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1275 struct intel_renderbuffer
*irb
,
1276 struct intel_mipmap_tree
*singlesample_mt
,
1277 uint32_t width
, uint32_t height
,
1280 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1281 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1282 mesa_format format
= rb
->Format
;
1283 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1285 /* Only the front and back buffers, which are color buffers, are allocated
1286 * through the image loader.
1288 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1289 _mesa_get_format_base_format(format
) == GL_RGBA
);
1291 assert(singlesample_mt
);
1293 if (num_samples
== 1) {
1294 intel_miptree_release(&irb
->mt
);
1295 irb
->mt
= singlesample_mt
;
1297 assert(!irb
->singlesample_mt
);
1299 intel_miptree_release(&irb
->singlesample_mt
);
1300 irb
->singlesample_mt
= singlesample_mt
;
1303 irb
->mt
->logical_width0
!= width
||
1304 irb
->mt
->logical_height0
!= height
) {
1305 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1310 if (!multisample_mt
)
1313 irb
->need_downsample
= false;
1314 intel_miptree_release(&irb
->mt
);
1315 irb
->mt
= multisample_mt
;
1321 intel_miptree_release(&irb
->mt
);
1325 struct intel_mipmap_tree
*
1326 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1330 uint32_t num_samples
)
1332 struct intel_mipmap_tree
*mt
;
1334 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1335 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1336 MIPTREE_LAYOUT_TILING_ANY
|
1337 MIPTREE_LAYOUT_FOR_SCANOUT
;
1339 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1340 width
, height
, depth
, num_samples
,
1348 intel_miptree_release(&mt
);
1353 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1354 struct intel_mipmap_tree
*src
)
1359 intel_miptree_release(dst
);
1363 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1370 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1372 if (aux_buf
== NULL
)
1375 brw_bo_unreference(aux_buf
->bo
);
1381 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1386 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1387 if (--(*mt
)->refcount
<= 0) {
1390 DBG("%s deleting %p\n", __func__
, *mt
);
1392 brw_bo_unreference((*mt
)->bo
);
1393 intel_miptree_release(&(*mt
)->stencil_mt
);
1394 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1395 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1396 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1397 free_aux_state_map((*mt
)->aux_state
);
1399 intel_miptree_release(&(*mt
)->plane
[0]);
1400 intel_miptree_release(&(*mt
)->plane
[1]);
1402 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1403 free((*mt
)->level
[i
].slice
);
1413 intel_get_image_dims(struct gl_texture_image
*image
,
1414 int *width
, int *height
, int *depth
)
1416 switch (image
->TexObject
->Target
) {
1417 case GL_TEXTURE_1D_ARRAY
:
1418 /* For a 1D Array texture the OpenGL API will treat the image height as
1419 * the number of array slices. For Intel hardware, we treat the 1D array
1420 * as a 2D Array with a height of 1. So, here we want to swap image
1423 assert(image
->Depth
== 1);
1424 *width
= image
->Width
;
1426 *depth
= image
->Height
;
1428 case GL_TEXTURE_CUBE_MAP
:
1429 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1430 * though we really have 6 slices.
1432 assert(image
->Depth
== 1);
1433 *width
= image
->Width
;
1434 *height
= image
->Height
;
1438 *width
= image
->Width
;
1439 *height
= image
->Height
;
1440 *depth
= image
->Depth
;
1446 * Can the image be pulled into a unified mipmap tree? This mirrors
1447 * the completeness test in a lot of ways.
1449 * Not sure whether I want to pass gl_texture_image here.
1452 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1453 struct gl_texture_image
*image
)
1455 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1456 GLuint level
= intelImage
->base
.Base
.Level
;
1457 int width
, height
, depth
;
1459 /* glTexImage* choose the texture object based on the target passed in, and
1460 * objects can't change targets over their lifetimes, so this should be
1463 assert(image
->TexObject
->Target
== mt
->target
);
1465 mesa_format mt_format
= mt
->format
;
1466 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1467 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1468 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1469 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1470 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1471 mt_format
= mt
->etc_format
;
1473 if (image
->TexFormat
!= mt_format
)
1476 intel_get_image_dims(image
, &width
, &height
, &depth
);
1478 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1481 if (mt
->surf
.size
> 0) {
1482 if (level
>= mt
->surf
.levels
)
1485 const unsigned level_depth
=
1486 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1487 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1488 mt
->surf
.logical_level0_px
.array_len
;
1490 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1491 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1492 depth
== level_depth
&&
1493 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1496 int level_depth
= mt
->level
[level
].depth
;
1497 if (mt
->surf
.samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1498 level_depth
/= mt
->surf
.samples
;
1500 /* Test image dimensions against the base level image adjusted for
1501 * minification. This will also catch images not present in the
1502 * tree, changed targets, etc.
1504 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1505 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1506 depth
!= level_depth
) {
1510 /* Core uses sample number of zero to indicate single-sampled. */
1511 if (MAX2(image
->NumSamples
, 1) != mt
->surf
.samples
)
1519 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1521 GLuint x
, GLuint y
, GLuint d
)
1523 mt
->level
[level
].depth
= d
;
1524 mt
->level
[level
].level_x
= x
;
1525 mt
->level
[level
].level_y
= y
;
1527 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1530 assert(mt
->level
[level
].slice
);
1532 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1533 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1538 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1539 GLuint level
, GLuint img
,
1542 if (img
== 0 && level
== 0)
1543 assert(x
== 0 && y
== 0);
1545 assert(img
< mt
->level
[level
].depth
);
1547 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1548 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1550 DBG("%s level %d img %d pos %d,%d\n",
1551 __func__
, level
, img
,
1552 mt
->level
[level
].slice
[img
].x_offset
,
1553 mt
->level
[level
].slice
[img
].y_offset
);
1557 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1558 GLuint level
, GLuint slice
,
1559 GLuint
*x
, GLuint
*y
)
1561 if (level
== 0 && slice
== 0) {
1562 *x
= mt
->level
[0].level_x
;
1563 *y
= mt
->level
[0].level_y
;
1567 if (mt
->surf
.size
> 0) {
1568 uint32_t x_offset_sa
, y_offset_sa
;
1570 /* Miptree itself can have an offset only if it represents a single
1571 * slice in an imported buffer object.
1572 * See intel_miptree_create_for_dri_image().
1574 assert(mt
->level
[0].level_x
== 0);
1575 assert(mt
->level
[0].level_y
== 0);
1577 /* Given level is relative to level zero while the miptree may be
1578 * represent just a subset of all levels starting from 'first_level'.
1580 assert(level
>= mt
->first_level
);
1581 level
-= mt
->first_level
;
1583 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1584 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1585 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1586 &x_offset_sa
, &y_offset_sa
);
1593 assert(slice
< mt
->level
[level
].depth
);
1595 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1596 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1601 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1602 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1603 * and tile_h is set to 1.
1606 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1607 uint32_t *tile_w
, uint32_t *tile_h
)
1618 case ISL_TILING_LINEAR
:
1623 unreachable("not reached");
1629 * This function computes masks that may be used to select the bits of the X
1630 * and Y coordinates that indicate the offset within a tile. If the BO is
1631 * untiled, the masks are set to 0.
1634 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1635 uint32_t *mask_x
, uint32_t *mask_y
)
1637 uint32_t tile_w_bytes
, tile_h
;
1639 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1641 *mask_x
= tile_w_bytes
/ cpp
- 1;
1642 *mask_y
= tile_h
- 1;
1646 * Compute the offset (in bytes) from the start of the BO to the given x
1647 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1648 * multiples of the tile size.
1651 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1652 uint32_t x
, uint32_t y
)
1655 uint32_t pitch
= mt
->surf
.row_pitch
;
1657 switch (mt
->surf
.tiling
) {
1659 unreachable("not reached");
1660 case ISL_TILING_LINEAR
:
1661 return y
* pitch
+ x
* cpp
;
1663 assert((x
% (512 / cpp
)) == 0);
1664 assert((y
% 8) == 0);
1665 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1667 assert((x
% (128 / cpp
)) == 0);
1668 assert((y
% 32) == 0);
1669 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1674 * Rendering with tiled buffers requires that the base address of the buffer
1675 * be aligned to a page boundary. For renderbuffers, and sometimes with
1676 * textures, we may want the surface to point at a texture image level that
1677 * isn't at a page boundary.
1679 * This function returns an appropriately-aligned base offset
1680 * according to the tiling restrictions, plus any required x/y offset
1684 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1685 GLuint level
, GLuint slice
,
1690 uint32_t mask_x
, mask_y
;
1692 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1693 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1695 *tile_x
= x
& mask_x
;
1696 *tile_y
= y
& mask_y
;
1698 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1702 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1703 struct intel_mipmap_tree
*src_mt
,
1704 unsigned src_level
, unsigned src_layer
,
1705 struct intel_mipmap_tree
*dst_mt
,
1706 unsigned dst_level
, unsigned dst_layer
,
1707 unsigned width
, unsigned height
)
1710 ptrdiff_t src_stride
, dst_stride
;
1711 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1712 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1714 intel_miptree_map(brw
, src_mt
,
1715 src_level
, src_layer
,
1718 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1721 intel_miptree_map(brw
, dst_mt
,
1722 dst_level
, dst_layer
,
1725 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1729 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1730 _mesa_get_format_name(src_mt
->format
),
1731 src_mt
, src
, src_stride
,
1732 _mesa_get_format_name(dst_mt
->format
),
1733 dst_mt
, dst
, dst_stride
,
1736 int row_size
= cpp
* width
;
1737 if (src_stride
== row_size
&&
1738 dst_stride
== row_size
) {
1739 memcpy(dst
, src
, row_size
* height
);
1741 for (int i
= 0; i
< height
; i
++) {
1742 memcpy(dst
, src
, row_size
);
1748 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1749 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1751 /* Don't forget to copy the stencil data over, too. We could have skipped
1752 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1753 * shuffling the two data sources in/out of temporary storage instead of
1754 * the direct mapping we get this way.
1756 if (dst_mt
->stencil_mt
) {
1757 assert(src_mt
->stencil_mt
);
1758 intel_miptree_copy_slice_sw(brw
,
1759 src_mt
->stencil_mt
, src_level
, src_layer
,
1760 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1766 intel_miptree_copy_slice(struct brw_context
*brw
,
1767 struct intel_mipmap_tree
*src_mt
,
1768 unsigned src_level
, unsigned src_layer
,
1769 struct intel_mipmap_tree
*dst_mt
,
1770 unsigned dst_level
, unsigned dst_layer
)
1773 mesa_format format
= src_mt
->format
;
1774 uint32_t width
, height
;
1776 if (src_mt
->surf
.size
> 0) {
1777 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1778 src_level
- src_mt
->first_level
);
1779 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1780 src_level
- src_mt
->first_level
);
1783 get_num_phys_layers(&src_mt
->surf
,
1784 src_level
- src_mt
->first_level
));
1786 width
= minify(src_mt
->physical_width0
,
1787 src_level
- src_mt
->first_level
);
1788 height
= minify(src_mt
->physical_height0
,
1789 src_level
- src_mt
->first_level
);
1790 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1793 assert(src_mt
->format
== dst_mt
->format
);
1795 if (dst_mt
->compressed
) {
1797 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1798 height
= ALIGN_NPOT(height
, j
) / j
;
1799 width
= ALIGN_NPOT(width
, i
) / i
;
1802 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1803 * below won't apply since we can't do the depth's Y tiling or the
1804 * stencil's W tiling in the blitter.
1806 if (src_mt
->stencil_mt
) {
1807 intel_miptree_copy_slice_sw(brw
,
1808 src_mt
, src_level
, src_layer
,
1809 dst_mt
, dst_level
, dst_layer
,
1814 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1815 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1817 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1820 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1821 _mesa_get_format_name(src_mt
->format
),
1822 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1823 _mesa_get_format_name(dst_mt
->format
),
1824 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1827 if (!intel_miptree_blit(brw
,
1828 src_mt
, src_level
, src_layer
, 0, 0, false,
1829 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1830 width
, height
, GL_COPY
)) {
1831 perf_debug("miptree validate blit for %s failed\n",
1832 _mesa_get_format_name(format
));
1834 intel_miptree_copy_slice_sw(brw
,
1835 src_mt
, src_level
, src_layer
,
1836 dst_mt
, dst_level
, dst_layer
,
1842 * Copies the image's current data to the given miptree, and associates that
1843 * miptree with the image.
1845 * If \c invalidate is true, then the actual image data does not need to be
1846 * copied, but the image still needs to be associated to the new miptree (this
1847 * is set to true if we're about to clear the image).
1850 intel_miptree_copy_teximage(struct brw_context
*brw
,
1851 struct intel_texture_image
*intelImage
,
1852 struct intel_mipmap_tree
*dst_mt
,
1855 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1856 struct intel_texture_object
*intel_obj
=
1857 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1858 int level
= intelImage
->base
.Base
.Level
;
1859 const unsigned face
= intelImage
->base
.Base
.Face
;
1860 unsigned start_layer
, end_layer
;
1862 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1864 assert(intelImage
->base
.Base
.Height
);
1866 end_layer
= intelImage
->base
.Base
.Height
- 1;
1867 } else if (face
> 0) {
1871 assert(intelImage
->base
.Base
.Depth
);
1873 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1877 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1878 intel_miptree_copy_slice(brw
,
1884 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1885 intel_obj
->needs_validate
= true;
1889 intel_miptree_init_mcs(struct brw_context
*brw
,
1890 struct intel_mipmap_tree
*mt
,
1893 assert(mt
->mcs_buf
!= NULL
);
1895 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1897 * When MCS buffer is enabled and bound to MSRT, it is required that it
1898 * is cleared prior to any rendering.
1900 * Since we don't use the MCS buffer for any purpose other than rendering,
1901 * it makes sense to just clear it immediately upon allocation.
1903 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1905 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1906 if (unlikely(map
== NULL
)) {
1907 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1908 brw_bo_unreference(mt
->mcs_buf
->bo
);
1913 memset(data
, init_value
, mt
->mcs_buf
->size
);
1914 brw_bo_unmap(mt
->mcs_buf
->bo
);
1917 static struct intel_miptree_aux_buffer
*
1918 intel_alloc_aux_buffer(struct brw_context
*brw
,
1920 const struct isl_surf
*aux_surf
,
1921 uint32_t alloc_flags
,
1922 struct intel_mipmap_tree
*mt
)
1924 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1928 buf
->size
= aux_surf
->size
;
1929 buf
->pitch
= aux_surf
->row_pitch
;
1930 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1932 /* ISL has stricter set of alignment rules then the drm allocator.
1933 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1934 * trying to recalculate based on different format block sizes.
1936 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1937 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1943 buf
->surf
= *aux_surf
;
1949 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1950 struct intel_mipmap_tree
*mt
,
1953 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1954 assert(mt
->mcs_buf
== NULL
);
1955 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1957 /* Multisampled miptrees are only supported for single level. */
1958 assert(mt
->first_level
== 0);
1959 enum isl_aux_state
**aux_state
=
1960 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1964 struct isl_surf temp_main_surf
;
1965 struct isl_surf temp_mcs_surf
;
1967 /* Create first an ISL presentation for the main color surface and let ISL
1968 * calculate equivalent MCS surface against it.
1970 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1971 MAYBE_UNUSED
bool ok
=
1972 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1975 /* Buffer needs to be initialised requiring the buffer to be immediately
1976 * mapped to cpu space for writing. Therefore do not use the gpu access
1977 * flag which can cause an unnecessary delay if the backing pages happened
1978 * to be just used by the GPU.
1980 const uint32_t alloc_flags
= 0;
1981 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1982 &temp_mcs_surf
, alloc_flags
, mt
);
1988 mt
->aux_state
= aux_state
;
1990 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1996 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1997 struct intel_mipmap_tree
*mt
)
1999 assert(mt
->mcs_buf
== NULL
);
2000 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
2001 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2003 struct isl_surf temp_main_surf
;
2004 struct isl_surf temp_ccs_surf
;
2006 /* Create first an ISL presentation for the main color surface and let ISL
2007 * calculate equivalent CCS surface against it.
2009 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
2010 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
2014 assert(temp_ccs_surf
.size
&&
2015 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
2017 enum isl_aux_state
**aux_state
=
2018 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
2022 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
2023 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
2025 * "If Software wants to enable Color Compression without Fast clear,
2026 * Software needs to initialize MCS with zeros."
2028 * A CCS value of 0 indicates that the corresponding block is in the
2029 * pass-through state which is what we want.
2031 * For CCS_D, on the other hand, we don't care as we're about to perform a
2032 * fast-clear operation. In that case, being hot in caches more useful.
2034 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
2035 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
2036 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
2037 &temp_ccs_surf
, alloc_flags
, mt
);
2043 mt
->aux_state
= aux_state
;
2049 * Helper for intel_miptree_alloc_hiz() that sets
2050 * \c mt->level[level].has_hiz. Return true if and only if
2051 * \c has_hiz was set.
2054 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
2055 struct intel_mipmap_tree
*mt
,
2058 assert(mt
->hiz_buf
);
2059 assert(mt
->surf
.size
> 0);
2061 if (brw
->gen
>= 8 || brw
->is_haswell
) {
2062 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
2063 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
2065 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
2066 * and the height is 4 aligned. This allows our HiZ support
2067 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
2068 * we can grow the width & height to allow the HiZ op to
2069 * force the proper size alignments.
2071 if (level
> 0 && ((width
& 7) || (height
& 3))) {
2072 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
2077 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
2078 mt
->level
[level
].has_hiz
= true;
2083 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2084 struct intel_mipmap_tree
*mt
)
2086 assert(mt
->hiz_buf
== NULL
);
2087 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
2089 enum isl_aux_state
**aux_state
=
2090 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
2094 struct isl_surf temp_hiz_surf
;
2096 MAYBE_UNUSED
bool ok
=
2097 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
2100 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
2101 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
2102 &temp_hiz_surf
, alloc_flags
, mt
);
2109 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2110 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2112 mt
->aux_state
= aux_state
;
2119 * Allocate the initial aux surface for a miptree based on mt->aux_usage
2121 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
2122 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
2123 * compress clear color so we wait until an actual fast-clear to allocate it.
2126 intel_miptree_alloc_aux(struct brw_context
*brw
,
2127 struct intel_mipmap_tree
*mt
)
2129 switch (mt
->aux_usage
) {
2130 case ISL_AUX_USAGE_NONE
:
2133 case ISL_AUX_USAGE_HIZ
:
2134 assert(!_mesa_is_format_color_format(mt
->format
));
2135 if (!intel_miptree_alloc_hiz(brw
, mt
))
2139 case ISL_AUX_USAGE_MCS
:
2140 assert(_mesa_is_format_color_format(mt
->format
));
2141 assert(mt
->surf
.samples
> 1);
2142 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
2146 case ISL_AUX_USAGE_CCS_D
:
2147 /* Since CCS_D can only compress clear color so we wait until an actual
2148 * fast-clear to allocate it.
2152 case ISL_AUX_USAGE_CCS_E
:
2153 assert(_mesa_is_format_color_format(mt
->format
));
2154 assert(mt
->surf
.samples
== 1);
2155 if (!intel_miptree_alloc_ccs(brw
, mt
))
2160 unreachable("Invalid aux usage");
2165 * Can the miptree sample using the hiz buffer?
2168 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2169 struct intel_mipmap_tree
*mt
)
2171 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2172 * so keep things conservative for now and never enable it unless we're SKL+.
2182 /* It seems the hardware won't fallback to the depth buffer if some of the
2183 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2184 * of the texture to be HiZ enabled.
2186 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
2187 if (!intel_miptree_level_has_hiz(mt
, level
))
2191 /* If compressed multisampling is enabled, then we use it for the auxiliary
2194 * From the BDW PRM (Volume 2d: Command Reference: Structures
2195 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2197 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2198 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2200 * There is no such blurb for 1D textures, but there is sufficient evidence
2201 * that this is broken on SKL+.
2203 return (mt
->surf
.samples
== 1 &&
2204 mt
->target
!= GL_TEXTURE_3D
&&
2205 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2209 * Does the miptree slice have hiz enabled?
2212 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2214 intel_miptree_check_level_layer(mt
, level
, 0);
2215 return mt
->level
[level
].has_hiz
;
2219 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2220 unsigned start_level
, unsigned num_levels
,
2221 unsigned start_layer
, unsigned num_layers
)
2223 assert(_mesa_is_format_color_format(mt
->format
));
2228 /* Clamp the level range to fit the miptree */
2229 assert(start_level
+ num_levels
>= start_level
);
2230 const uint32_t last_level
=
2231 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2232 start_level
= MAX2(mt
->first_level
, start_level
);
2233 num_levels
= last_level
- start_level
+ 1;
2235 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2236 uint32_t level_layers
= mt
->surf
.size
> 0 ?
2237 get_num_phys_layers(&mt
->surf
, level
) : mt
->level
[level
].depth
;
2239 level_layers
= MIN2(num_layers
, level_layers
);
2241 for (unsigned a
= 0; a
< level_layers
; a
++) {
2242 enum isl_aux_state aux_state
=
2243 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2244 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2245 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2254 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2255 const struct intel_mipmap_tree
*mt
,
2256 unsigned level
, unsigned layer
)
2262 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2263 assert(brw
->gen
>= 8 ||
2264 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2266 /* Compression of arrayed msaa surfaces is supported. */
2267 if (mt
->surf
.samples
> 1)
2270 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2271 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2277 static enum blorp_fast_clear_op
2278 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2279 bool ccs_supported
, bool fast_clear_supported
)
2281 assert(ccs_supported
== fast_clear_supported
);
2283 switch (aux_state
) {
2284 case ISL_AUX_STATE_CLEAR
:
2285 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2287 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2289 return BLORP_FAST_CLEAR_OP_NONE
;
2291 case ISL_AUX_STATE_PASS_THROUGH
:
2292 return BLORP_FAST_CLEAR_OP_NONE
;
2294 case ISL_AUX_STATE_RESOLVED
:
2295 case ISL_AUX_STATE_AUX_INVALID
:
2296 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2300 unreachable("Invalid aux state for CCS_D");
2303 static enum blorp_fast_clear_op
2304 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2305 bool ccs_supported
, bool fast_clear_supported
)
2307 switch (aux_state
) {
2308 case ISL_AUX_STATE_CLEAR
:
2309 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2311 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2312 else if (!fast_clear_supported
)
2313 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2315 return BLORP_FAST_CLEAR_OP_NONE
;
2317 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2319 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2321 return BLORP_FAST_CLEAR_OP_NONE
;
2323 case ISL_AUX_STATE_PASS_THROUGH
:
2324 return BLORP_FAST_CLEAR_OP_NONE
;
2326 case ISL_AUX_STATE_RESOLVED
:
2327 case ISL_AUX_STATE_AUX_INVALID
:
2331 unreachable("Invalid aux state for CCS_E");
2335 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2336 struct intel_mipmap_tree
*mt
,
2337 uint32_t level
, uint32_t layer
,
2339 bool fast_clear_supported
)
2341 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2343 enum blorp_fast_clear_op resolve_op
;
2344 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2345 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2346 fast_clear_supported
);
2348 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2349 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2350 fast_clear_supported
);
2353 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2354 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2355 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2357 switch (resolve_op
) {
2358 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2359 /* The CCS full resolve operation destroys the CCS and sets it to the
2360 * pass-through state. (You can also think of this as being both a
2361 * resolve and an ambiguate in one operation.)
2363 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2364 ISL_AUX_STATE_PASS_THROUGH
);
2367 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2368 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2369 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2373 unreachable("Invalid resolve op");
2379 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2380 struct intel_mipmap_tree
*mt
,
2381 uint32_t level
, uint32_t layer
,
2382 bool written_with_ccs
)
2384 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2386 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2387 switch (aux_state
) {
2388 case ISL_AUX_STATE_CLEAR
:
2389 assert(written_with_ccs
);
2390 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2391 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2394 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2395 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2396 assert(written_with_ccs
);
2397 break; /* Nothing to do */
2399 case ISL_AUX_STATE_PASS_THROUGH
:
2400 if (written_with_ccs
) {
2401 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2402 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2408 case ISL_AUX_STATE_RESOLVED
:
2409 case ISL_AUX_STATE_AUX_INVALID
:
2410 unreachable("Invalid aux state for CCS_E");
2413 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2414 /* CCS_D is a bit simpler */
2415 switch (aux_state
) {
2416 case ISL_AUX_STATE_CLEAR
:
2417 assert(written_with_ccs
);
2418 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2419 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2422 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2423 assert(written_with_ccs
);
2424 break; /* Nothing to do */
2426 case ISL_AUX_STATE_PASS_THROUGH
:
2430 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2431 case ISL_AUX_STATE_RESOLVED
:
2432 case ISL_AUX_STATE_AUX_INVALID
:
2433 unreachable("Invalid aux state for CCS_D");
2439 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2440 struct intel_mipmap_tree
*mt
,
2441 uint32_t level
, uint32_t layer
,
2442 bool written_with_aux
)
2444 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2445 case ISL_AUX_STATE_CLEAR
:
2446 assert(written_with_aux
);
2447 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2448 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2451 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2452 assert(written_with_aux
);
2453 break; /* Nothing to do */
2455 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2456 case ISL_AUX_STATE_RESOLVED
:
2457 case ISL_AUX_STATE_PASS_THROUGH
:
2458 case ISL_AUX_STATE_AUX_INVALID
:
2459 unreachable("Invalid aux state for MCS");
2464 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2465 struct intel_mipmap_tree
*mt
,
2466 uint32_t level
, uint32_t layer
,
2467 bool hiz_supported
, bool fast_clear_supported
)
2469 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2470 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2471 case ISL_AUX_STATE_CLEAR
:
2472 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2473 if (!hiz_supported
|| !fast_clear_supported
)
2474 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2477 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2479 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2482 case ISL_AUX_STATE_PASS_THROUGH
:
2483 case ISL_AUX_STATE_RESOLVED
:
2486 case ISL_AUX_STATE_AUX_INVALID
:
2488 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2492 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2493 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2496 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2497 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2498 ISL_AUX_STATE_RESOLVED
);
2501 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2502 /* The HiZ resolve operation is actually an ambiguate */
2503 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2504 ISL_AUX_STATE_PASS_THROUGH
);
2508 unreachable("Invalid HiZ op");
2514 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2515 struct intel_mipmap_tree
*mt
,
2516 uint32_t level
, uint32_t layer
,
2517 bool written_with_hiz
)
2519 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2520 case ISL_AUX_STATE_CLEAR
:
2521 assert(written_with_hiz
);
2522 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2523 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2526 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2527 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2528 assert(written_with_hiz
);
2529 break; /* Nothing to do */
2531 case ISL_AUX_STATE_RESOLVED
:
2532 if (written_with_hiz
) {
2533 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2534 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2536 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2537 ISL_AUX_STATE_AUX_INVALID
);
2541 case ISL_AUX_STATE_PASS_THROUGH
:
2542 if (written_with_hiz
) {
2543 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2544 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2548 case ISL_AUX_STATE_AUX_INVALID
:
2549 assert(!written_with_hiz
);
2554 static inline uint32_t
2555 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2556 uint32_t start_level
, uint32_t num_levels
)
2558 assert(start_level
>= mt
->first_level
);
2559 assert(start_level
<= mt
->last_level
);
2561 if (num_levels
== INTEL_REMAINING_LAYERS
)
2562 num_levels
= mt
->last_level
- start_level
+ 1;
2563 /* Check for overflow */
2564 assert(start_level
+ num_levels
>= start_level
);
2565 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2570 static inline uint32_t
2571 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2572 uint32_t start_layer
, uint32_t num_layers
)
2574 assert(level
<= mt
->last_level
);
2575 uint32_t total_num_layers
;
2577 if (mt
->surf
.size
> 0)
2578 total_num_layers
= get_num_phys_layers(&mt
->surf
, level
);
2580 total_num_layers
= mt
->level
[level
].depth
;
2582 assert(start_layer
< total_num_layers
);
2583 if (num_layers
== INTEL_REMAINING_LAYERS
)
2584 num_layers
= total_num_layers
- start_layer
;
2585 /* Check for overflow */
2586 assert(start_layer
+ num_layers
>= start_layer
);
2587 assert(start_layer
+ num_layers
<= total_num_layers
);
2593 intel_miptree_prepare_access(struct brw_context
*brw
,
2594 struct intel_mipmap_tree
*mt
,
2595 uint32_t start_level
, uint32_t num_levels
,
2596 uint32_t start_layer
, uint32_t num_layers
,
2597 bool aux_supported
, bool fast_clear_supported
)
2599 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2601 if (_mesa_is_format_color_format(mt
->format
)) {
2605 if (mt
->surf
.samples
> 1) {
2606 /* Nothing to do for MSAA */
2607 assert(aux_supported
&& fast_clear_supported
);
2609 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2610 const uint32_t level
= start_level
+ l
;
2611 const uint32_t level_layers
=
2612 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2613 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2614 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2615 start_layer
+ a
, aux_supported
,
2616 fast_clear_supported
);
2620 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2621 /* Nothing to do for stencil */
2626 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2627 const uint32_t level
= start_level
+ l
;
2628 if (!intel_miptree_level_has_hiz(mt
, level
))
2631 const uint32_t level_layers
=
2632 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2633 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2634 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2636 fast_clear_supported
);
2643 intel_miptree_finish_write(struct brw_context
*brw
,
2644 struct intel_mipmap_tree
*mt
, uint32_t level
,
2645 uint32_t start_layer
, uint32_t num_layers
,
2646 bool written_with_aux
)
2648 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2650 if (_mesa_is_format_color_format(mt
->format
)) {
2654 if (mt
->surf
.samples
> 1) {
2655 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2656 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2660 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2661 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2665 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2666 /* Nothing to do for stencil */
2668 if (!intel_miptree_level_has_hiz(mt
, level
))
2671 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2672 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2679 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2680 uint32_t level
, uint32_t layer
)
2682 intel_miptree_check_level_layer(mt
, level
, layer
);
2684 if (_mesa_is_format_color_format(mt
->format
)) {
2685 assert(mt
->mcs_buf
!= NULL
);
2686 assert(mt
->surf
.samples
== 1 ||
2687 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2688 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2689 unreachable("Cannot get aux state for stencil");
2691 assert(intel_miptree_level_has_hiz(mt
, level
));
2694 return mt
->aux_state
[level
][layer
];
2698 intel_miptree_set_aux_state(struct brw_context
*brw
,
2699 struct intel_mipmap_tree
*mt
, uint32_t level
,
2700 uint32_t start_layer
, uint32_t num_layers
,
2701 enum isl_aux_state aux_state
)
2703 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2705 if (_mesa_is_format_color_format(mt
->format
)) {
2706 assert(mt
->mcs_buf
!= NULL
);
2707 assert(mt
->surf
.samples
== 1 ||
2708 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2709 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2710 unreachable("Cannot get aux state for stencil");
2712 assert(intel_miptree_level_has_hiz(mt
, level
));
2715 for (unsigned a
= 0; a
< num_layers
; a
++)
2716 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2719 /* On Gen9 color buffers may be compressed by the hardware (lossless
2720 * compression). There are, however, format restrictions and care needs to be
2721 * taken that the sampler engine is capable for re-interpreting a buffer with
2722 * format different the buffer was originally written with.
2724 * For example, SRGB formats are not compressible and the sampler engine isn't
2725 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2726 * color buffer needs to be resolved so that the sampling surface can be
2727 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2731 can_texture_with_ccs(struct brw_context
*brw
,
2732 struct intel_mipmap_tree
*mt
,
2733 mesa_format view_format
)
2735 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2738 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2739 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2741 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2742 isl_mt_format
, isl_view_format
)) {
2743 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2744 _mesa_get_format_name(view_format
),
2745 _mesa_get_format_name(mt
->format
));
2753 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2754 struct intel_mipmap_tree
*mt
,
2755 mesa_format view_format
,
2756 uint32_t start_level
, uint32_t num_levels
,
2757 uint32_t start_layer
, uint32_t num_layers
,
2758 bool *aux_supported_out
)
2760 bool aux_supported
, clear_supported
;
2761 if (_mesa_is_format_color_format(mt
->format
)) {
2762 if (mt
->surf
.samples
> 1) {
2763 aux_supported
= clear_supported
= true;
2765 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2767 /* Clear color is specified as ints or floats and the conversion is
2768 * done by the sampler. If we have a texture view, we would have to
2769 * perform the clear color conversion manually. Just disable clear
2772 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2774 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2775 aux_supported
= clear_supported
= false;
2777 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2780 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2781 start_layer
, num_layers
,
2782 aux_supported
, clear_supported
);
2783 if (aux_supported_out
)
2784 *aux_supported_out
= aux_supported
;
2788 intel_miptree_prepare_texture(struct brw_context
*brw
,
2789 struct intel_mipmap_tree
*mt
,
2790 mesa_format view_format
,
2791 bool *aux_supported_out
)
2793 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2794 0, INTEL_REMAINING_LEVELS
,
2795 0, INTEL_REMAINING_LAYERS
,
2800 intel_miptree_prepare_image(struct brw_context
*brw
,
2801 struct intel_mipmap_tree
*mt
)
2803 /* The data port doesn't understand any compression */
2804 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2805 0, INTEL_REMAINING_LAYERS
, false, false);
2809 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2810 struct intel_mipmap_tree
*mt
, uint32_t level
,
2811 uint32_t start_layer
, uint32_t num_layers
)
2813 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2814 start_layer
, num_layers
, NULL
);
2818 intel_miptree_prepare_render(struct brw_context
*brw
,
2819 struct intel_mipmap_tree
*mt
, uint32_t level
,
2820 uint32_t start_layer
, uint32_t layer_count
,
2823 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2824 * the single-sampled color renderbuffers because the CCS buffer isn't
2825 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2826 * enabled because otherwise the surface state will be programmed with
2827 * the linear equivalent format anyway.
2829 if (brw
->gen
== 9 && srgb_enabled
&& mt
->surf
.samples
== 1 &&
2830 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2832 /* Lossless compression is not supported for SRGB formats, it
2833 * should be impossible to get here with such surfaces.
2835 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2836 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2842 intel_miptree_finish_render(struct brw_context
*brw
,
2843 struct intel_mipmap_tree
*mt
, uint32_t level
,
2844 uint32_t start_layer
, uint32_t layer_count
)
2846 assert(_mesa_is_format_color_format(mt
->format
));
2847 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2848 mt
->mcs_buf
!= NULL
);
2852 intel_miptree_prepare_depth(struct brw_context
*brw
,
2853 struct intel_mipmap_tree
*mt
, uint32_t level
,
2854 uint32_t start_layer
, uint32_t layer_count
)
2856 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2857 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2861 intel_miptree_finish_depth(struct brw_context
*brw
,
2862 struct intel_mipmap_tree
*mt
, uint32_t level
,
2863 uint32_t start_layer
, uint32_t layer_count
,
2866 if (depth_written
) {
2867 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2868 mt
->hiz_buf
!= NULL
);
2873 * Make it possible to share the BO backing the given miptree with another
2874 * process or another miptree.
2876 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2877 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2878 * ensure that no MCS buffer gets allocated in the future.
2880 * HiZ is similarly unsafe with shared buffers.
2883 intel_miptree_make_shareable(struct brw_context
*brw
,
2884 struct intel_mipmap_tree
*mt
)
2886 /* MCS buffers are also used for multisample buffers, but we can't resolve
2887 * away a multisample MCS buffer because it's an integral part of how the
2888 * pixel data is stored. Fortunately this code path should never be
2889 * reached for multisample buffers.
2891 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2892 mt
->surf
.samples
== 1);
2894 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2895 0, INTEL_REMAINING_LAYERS
, false, false);
2898 brw_bo_unreference(mt
->mcs_buf
->bo
);
2902 /* Any pending MCS/CCS operations are no longer needed. Trying to
2903 * execute any will likely crash due to the missing aux buffer. So let's
2904 * delete all pending ops.
2906 free(mt
->aux_state
);
2907 mt
->aux_state
= NULL
;
2911 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2914 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2915 mt
->level
[l
].has_hiz
= false;
2918 /* Any pending HiZ operations are no longer needed. Trying to execute
2919 * any will likely crash due to the missing aux buffer. So let's delete
2922 free(mt
->aux_state
);
2923 mt
->aux_state
= NULL
;
2926 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2931 * \brief Get pointer offset into stencil buffer.
2933 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2934 * must decode the tile's layout in software.
2937 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2939 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2941 * Even though the returned offset is always positive, the return type is
2943 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2944 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2947 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2949 uint32_t tile_size
= 4096;
2950 uint32_t tile_width
= 64;
2951 uint32_t tile_height
= 64;
2952 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2954 uint32_t tile_x
= x
/ tile_width
;
2955 uint32_t tile_y
= y
/ tile_height
;
2957 /* The byte's address relative to the tile's base addres. */
2958 uint32_t byte_x
= x
% tile_width
;
2959 uint32_t byte_y
= y
% tile_height
;
2961 uintptr_t u
= tile_y
* row_size
2962 + tile_x
* tile_size
2963 + 512 * (byte_x
/ 8)
2965 + 32 * ((byte_y
/ 4) % 2)
2966 + 16 * ((byte_x
/ 4) % 2)
2967 + 8 * ((byte_y
/ 2) % 2)
2968 + 4 * ((byte_x
/ 2) % 2)
2973 /* adjust for bit6 swizzling */
2974 if (((byte_x
/ 8) % 2) == 1) {
2975 if (((byte_y
/ 8) % 2) == 0) {
2987 intel_miptree_updownsample(struct brw_context
*brw
,
2988 struct intel_mipmap_tree
*src
,
2989 struct intel_mipmap_tree
*dst
)
2991 unsigned src_w
, src_h
, dst_w
, dst_h
;
2993 if (src
->surf
.size
> 0) {
2994 src_w
= src
->surf
.logical_level0_px
.width
;
2995 src_h
= src
->surf
.logical_level0_px
.height
;
2997 src_w
= src
->logical_width0
;
2998 src_h
= src
->logical_height0
;
3001 if (dst
->surf
.size
> 0) {
3002 dst_w
= dst
->surf
.logical_level0_px
.width
;
3003 dst_h
= dst
->surf
.logical_level0_px
.height
;
3005 dst_w
= dst
->logical_width0
;
3006 dst_h
= dst
->logical_height0
;
3009 brw_blorp_blit_miptrees(brw
,
3010 src
, 0 /* level */, 0 /* layer */,
3011 src
->format
, SWIZZLE_XYZW
,
3012 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
3015 GL_NEAREST
, false, false /*mirror x, y*/,
3018 if (src
->stencil_mt
) {
3019 if (src
->stencil_mt
->surf
.size
> 0) {
3020 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
3021 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
3023 src_w
= src
->stencil_mt
->logical_width0
;
3024 src_h
= src
->stencil_mt
->logical_height0
;
3027 if (dst
->stencil_mt
->surf
.size
> 0) {
3028 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
3029 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
3031 dst_w
= dst
->stencil_mt
->logical_width0
;
3032 dst_h
= dst
->stencil_mt
->logical_height0
;
3035 brw_blorp_blit_miptrees(brw
,
3036 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
3037 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
3038 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
3039 dst
->stencil_mt
->format
,
3042 GL_NEAREST
, false, false /*mirror x, y*/,
3043 false, false /* decode/encode srgb */);
3048 intel_update_r8stencil(struct brw_context
*brw
,
3049 struct intel_mipmap_tree
*mt
)
3051 assert(brw
->gen
>= 7);
3052 struct intel_mipmap_tree
*src
=
3053 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3054 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
3057 assert(src
->surf
.size
> 0);
3059 if (!mt
->r8stencil_mt
) {
3060 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3061 mt
->r8stencil_mt
= make_surface(
3064 MESA_FORMAT_R_UINT8
,
3065 src
->first_level
, src
->last_level
,
3066 src
->surf
.logical_level0_px
.width
,
3067 src
->surf
.logical_level0_px
.height
,
3068 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3069 src
->surf
.logical_level0_px
.depth
:
3070 src
->surf
.logical_level0_px
.array_len
,
3073 ISL_SURF_USAGE_TEXTURE_BIT
,
3074 BO_ALLOC_FOR_RENDER
, 0, NULL
);
3075 assert(mt
->r8stencil_mt
);
3078 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3080 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3081 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3082 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3083 src
->surf
.phys_level0_sa
.array_len
;
3085 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3086 brw_blorp_copy_miptrees(brw
,
3090 minify(src
->surf
.logical_level0_px
.width
,
3092 minify(src
->surf
.logical_level0_px
.height
,
3097 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3098 src
->r8stencil_needs_update
= false;
3102 intel_miptree_map_raw(struct brw_context
*brw
,
3103 struct intel_mipmap_tree
*mt
,
3106 struct brw_bo
*bo
= mt
->bo
;
3108 if (brw_batch_references(&brw
->batch
, bo
))
3109 intel_batchbuffer_flush(brw
);
3111 return brw_bo_map(brw
, bo
, mode
);
3115 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3117 brw_bo_unmap(mt
->bo
);
3121 intel_miptree_map_gtt(struct brw_context
*brw
,
3122 struct intel_mipmap_tree
*mt
,
3123 struct intel_miptree_map
*map
,
3124 unsigned int level
, unsigned int slice
)
3126 unsigned int bw
, bh
;
3128 unsigned int image_x
, image_y
;
3129 intptr_t x
= map
->x
;
3130 intptr_t y
= map
->y
;
3132 /* For compressed formats, the stride is the number of bytes per
3133 * row of blocks. intel_miptree_get_image_offset() already does
3136 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3137 assert(y
% bh
== 0);
3138 assert(x
% bw
== 0);
3142 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3149 /* Note that in the case of cube maps, the caller must have passed the
3150 * slice number referencing the face.
3152 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3156 map
->stride
= mt
->surf
.row_pitch
;
3157 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3160 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3161 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3162 map
->x
, map
->y
, map
->w
, map
->h
,
3163 mt
, _mesa_get_format_name(mt
->format
),
3164 x
, y
, map
->ptr
, map
->stride
);
3168 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3170 intel_miptree_unmap_raw(mt
);
3174 intel_miptree_map_blit(struct brw_context
*brw
,
3175 struct intel_mipmap_tree
*mt
,
3176 struct intel_miptree_map
*map
,
3177 unsigned int level
, unsigned int slice
)
3179 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3180 /* first_level */ 0,
3184 MIPTREE_LAYOUT_TILING_NONE
);
3186 if (!map
->linear_mt
) {
3187 fprintf(stderr
, "Failed to allocate blit temporary\n");
3190 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3192 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3193 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3194 * invalidate is set, since we'll be writing the whole rectangle from our
3195 * temporary buffer back out.
3197 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3198 if (!intel_miptree_copy(brw
,
3199 mt
, level
, slice
, map
->x
, map
->y
,
3200 map
->linear_mt
, 0, 0, 0, 0,
3202 fprintf(stderr
, "Failed to blit\n");
3207 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3209 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3210 map
->x
, map
->y
, map
->w
, map
->h
,
3211 mt
, _mesa_get_format_name(mt
->format
),
3212 level
, slice
, map
->ptr
, map
->stride
);
3217 intel_miptree_release(&map
->linear_mt
);
3223 intel_miptree_unmap_blit(struct brw_context
*brw
,
3224 struct intel_mipmap_tree
*mt
,
3225 struct intel_miptree_map
*map
,
3229 struct gl_context
*ctx
= &brw
->ctx
;
3231 intel_miptree_unmap_raw(map
->linear_mt
);
3233 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3234 bool ok
= intel_miptree_copy(brw
,
3235 map
->linear_mt
, 0, 0, 0, 0,
3236 mt
, level
, slice
, map
->x
, map
->y
,
3238 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3241 intel_miptree_release(&map
->linear_mt
);
3245 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3247 #if defined(USE_SSE41)
3249 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3250 struct intel_mipmap_tree
*mt
,
3251 struct intel_miptree_map
*map
,
3252 unsigned int level
, unsigned int slice
)
3254 assert(map
->mode
& GL_MAP_READ_BIT
);
3255 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3257 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3258 map
->x
, map
->y
, map
->w
, map
->h
,
3259 mt
, _mesa_get_format_name(mt
->format
),
3260 level
, slice
, map
->ptr
, map
->stride
);
3262 /* Map the original image */
3265 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3269 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3275 src
+= image_y
* mt
->surf
.row_pitch
;
3276 src
+= image_x
* mt
->cpp
;
3278 /* Due to the pixel offsets for the particular image being mapped, our
3279 * src pointer may not be 16-byte aligned. However, if the pitch is
3280 * divisible by 16, then the amount by which it's misaligned will remain
3281 * consistent from row to row.
3283 assert((mt
->surf
.row_pitch
% 16) == 0);
3284 const int misalignment
= ((uintptr_t) src
) & 15;
3286 /* Create an untiled temporary buffer for the mapping. */
3287 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3289 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3291 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3292 /* Offset the destination so it has the same misalignment as src. */
3293 map
->ptr
= map
->buffer
+ misalignment
;
3295 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3297 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3298 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3299 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3301 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3304 intel_miptree_unmap_raw(mt
);
3308 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3309 struct intel_mipmap_tree
*mt
,
3310 struct intel_miptree_map
*map
,
3314 _mesa_align_free(map
->buffer
);
3321 intel_miptree_map_s8(struct brw_context
*brw
,
3322 struct intel_mipmap_tree
*mt
,
3323 struct intel_miptree_map
*map
,
3324 unsigned int level
, unsigned int slice
)
3326 map
->stride
= map
->w
;
3327 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3331 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3332 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3333 * invalidate is set, since we'll be writing the whole rectangle from our
3334 * temporary buffer back out.
3336 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3337 uint8_t *untiled_s8_map
= map
->ptr
;
3338 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3339 unsigned int image_x
, image_y
;
3341 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3343 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3344 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3345 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3346 x
+ image_x
+ map
->x
,
3347 y
+ image_y
+ map
->y
,
3348 brw
->has_swizzling
);
3349 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3353 intel_miptree_unmap_raw(mt
);
3355 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3356 map
->x
, map
->y
, map
->w
, map
->h
,
3357 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3359 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3360 map
->x
, map
->y
, map
->w
, map
->h
,
3361 mt
, map
->ptr
, map
->stride
);
3366 intel_miptree_unmap_s8(struct brw_context
*brw
,
3367 struct intel_mipmap_tree
*mt
,
3368 struct intel_miptree_map
*map
,
3372 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3373 unsigned int image_x
, image_y
;
3374 uint8_t *untiled_s8_map
= map
->ptr
;
3375 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3377 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3379 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3380 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3381 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3382 image_x
+ x
+ map
->x
,
3383 image_y
+ y
+ map
->y
,
3384 brw
->has_swizzling
);
3385 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3389 intel_miptree_unmap_raw(mt
);
3396 intel_miptree_map_etc(struct brw_context
*brw
,
3397 struct intel_mipmap_tree
*mt
,
3398 struct intel_miptree_map
*map
,
3402 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3403 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3404 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3407 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3408 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3410 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3411 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3412 map
->w
, map
->h
, 1));
3413 map
->ptr
= map
->buffer
;
3417 intel_miptree_unmap_etc(struct brw_context
*brw
,
3418 struct intel_mipmap_tree
*mt
,
3419 struct intel_miptree_map
*map
,
3425 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3430 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3431 + image_y
* mt
->surf
.row_pitch
3432 + image_x
* mt
->cpp
;
3434 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3435 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3436 map
->ptr
, map
->stride
,
3439 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3440 map
->ptr
, map
->stride
,
3441 map
->w
, map
->h
, mt
->etc_format
);
3443 intel_miptree_unmap_raw(mt
);
3448 * Mapping function for packed depth/stencil miptrees backed by real separate
3449 * miptrees for depth and stencil.
3451 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3452 * separate from the depth buffer. Yet at the GL API level, we have to expose
3453 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3454 * be able to map that memory for texture storage and glReadPixels-type
3455 * operations. We give Mesa core that access by mallocing a temporary and
3456 * copying the data between the actual backing store and the temporary.
3459 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3460 struct intel_mipmap_tree
*mt
,
3461 struct intel_miptree_map
*map
,
3462 unsigned int level
, unsigned int slice
)
3464 struct intel_mipmap_tree
*z_mt
= mt
;
3465 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3466 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3467 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3469 map
->stride
= map
->w
* packed_bpp
;
3470 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3474 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3475 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3476 * invalidate is set, since we'll be writing the whole rectangle from our
3477 * temporary buffer back out.
3479 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3480 uint32_t *packed_map
= map
->ptr
;
3481 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3482 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3483 unsigned int s_image_x
, s_image_y
;
3484 unsigned int z_image_x
, z_image_y
;
3486 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3487 &s_image_x
, &s_image_y
);
3488 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3489 &z_image_x
, &z_image_y
);
3491 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3492 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3493 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3494 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3497 brw
->has_swizzling
);
3498 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3499 (z_mt
->surf
.row_pitch
/ 4) +
3500 (map_x
+ z_image_x
));
3501 uint8_t s
= s_map
[s_offset
];
3502 uint32_t z
= z_map
[z_offset
];
3504 if (map_z32f_x24s8
) {
3505 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3506 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3508 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3513 intel_miptree_unmap_raw(s_mt
);
3514 intel_miptree_unmap_raw(z_mt
);
3516 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3518 map
->x
, map
->y
, map
->w
, map
->h
,
3519 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3520 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3521 map
->ptr
, map
->stride
);
3523 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3524 map
->x
, map
->y
, map
->w
, map
->h
,
3525 mt
, map
->ptr
, map
->stride
);
3530 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3531 struct intel_mipmap_tree
*mt
,
3532 struct intel_miptree_map
*map
,
3536 struct intel_mipmap_tree
*z_mt
= mt
;
3537 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3538 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3540 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3541 uint32_t *packed_map
= map
->ptr
;
3542 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3543 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3544 unsigned int s_image_x
, s_image_y
;
3545 unsigned int z_image_x
, z_image_y
;
3547 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3548 &s_image_x
, &s_image_y
);
3549 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3550 &z_image_x
, &z_image_y
);
3552 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3553 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3554 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3555 x
+ s_image_x
+ map
->x
,
3556 y
+ s_image_y
+ map
->y
,
3557 brw
->has_swizzling
);
3558 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3559 (z_mt
->surf
.row_pitch
/ 4) +
3560 (x
+ z_image_x
+ map
->x
));
3562 if (map_z32f_x24s8
) {
3563 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3564 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3566 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3567 s_map
[s_offset
] = packed
>> 24;
3568 z_map
[z_offset
] = packed
;
3573 intel_miptree_unmap_raw(s_mt
);
3574 intel_miptree_unmap_raw(z_mt
);
3576 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3578 map
->x
, map
->y
, map
->w
, map
->h
,
3579 z_mt
, _mesa_get_format_name(z_mt
->format
),
3580 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3581 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3582 map
->ptr
, map
->stride
);
3589 * Create and attach a map to the miptree at (level, slice). Return the
3592 static struct intel_miptree_map
*
3593 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3602 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3607 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3608 mt
->level
[level
].slice
[slice
].map
= map
;
3620 * Release the map at (level, slice).
3623 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3627 struct intel_miptree_map
**map
;
3629 map
= &mt
->level
[level
].slice
[slice
].map
;
3635 can_blit_slice(struct intel_mipmap_tree
*mt
,
3636 unsigned int level
, unsigned int slice
)
3638 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3639 if (mt
->surf
.row_pitch
>= 32768)
3646 use_intel_mipree_map_blit(struct brw_context
*brw
,
3647 struct intel_mipmap_tree
*mt
,
3653 /* It's probably not worth swapping to the blit ring because of
3654 * all the overhead involved.
3656 !(mode
& GL_MAP_WRITE_BIT
) &&
3658 (mt
->surf
.tiling
== ISL_TILING_X
||
3659 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3660 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3661 /* Fast copy blit on skl+ supports all tiling formats. */
3663 can_blit_slice(mt
, level
, slice
))
3666 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3667 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3668 assert(can_blit_slice(mt
, level
, slice
));
3676 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3677 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3678 * arithmetic overflow.
3680 * If you call this function and use \a out_stride, then you're doing pointer
3681 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3682 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3683 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3684 * which usually have type uint32_t or GLuint.
3687 intel_miptree_map(struct brw_context
*brw
,
3688 struct intel_mipmap_tree
*mt
,
3697 ptrdiff_t *out_stride
)
3699 struct intel_miptree_map
*map
;
3701 assert(mt
->surf
.samples
== 1);
3703 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3710 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3711 map
->mode
& GL_MAP_WRITE_BIT
);
3713 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3714 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3715 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3716 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3717 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3718 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3719 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3720 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3721 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3722 #if defined(USE_SSE41)
3723 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3724 !mt
->compressed
&& cpu_has_sse4_1
&&
3725 (mt
->surf
.row_pitch
% 16 == 0)) {
3726 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3729 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3732 *out_ptr
= map
->ptr
;
3733 *out_stride
= map
->stride
;
3735 if (map
->ptr
== NULL
)
3736 intel_miptree_release_map(mt
, level
, slice
);
3740 intel_miptree_unmap(struct brw_context
*brw
,
3741 struct intel_mipmap_tree
*mt
,
3745 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3747 assert(mt
->surf
.samples
== 1);
3752 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3753 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3755 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3756 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3757 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3758 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3759 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3760 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3761 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3762 } else if (map
->linear_mt
) {
3763 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3764 #if defined(USE_SSE41)
3765 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3766 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3769 intel_miptree_unmap_gtt(mt
);
3772 intel_miptree_release_map(mt
, level
, slice
);
3776 get_isl_surf_dim(GLenum target
)
3780 case GL_TEXTURE_1D_ARRAY
:
3781 return ISL_SURF_DIM_1D
;
3784 case GL_TEXTURE_2D_ARRAY
:
3785 case GL_TEXTURE_RECTANGLE
:
3786 case GL_TEXTURE_CUBE_MAP
:
3787 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3788 case GL_TEXTURE_2D_MULTISAMPLE
:
3789 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3790 case GL_TEXTURE_EXTERNAL_OES
:
3791 return ISL_SURF_DIM_2D
;
3794 return ISL_SURF_DIM_3D
;
3797 unreachable("Invalid texture target");
3801 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3802 enum isl_tiling tiling
, GLenum target
,
3803 enum miptree_array_layout array_layout
)
3805 if (array_layout
== GEN6_HIZ_STENCIL
)
3806 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3810 case GL_TEXTURE_1D_ARRAY
:
3811 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3812 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3815 case GL_TEXTURE_2D_ARRAY
:
3816 case GL_TEXTURE_RECTANGLE
:
3817 case GL_TEXTURE_2D_MULTISAMPLE
:
3818 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3819 case GL_TEXTURE_EXTERNAL_OES
:
3820 return ISL_DIM_LAYOUT_GEN4_2D
;
3822 case GL_TEXTURE_CUBE_MAP
:
3823 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3824 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3825 ISL_DIM_LAYOUT_GEN4_2D
);
3828 return (devinfo
->gen
>= 9 ?
3829 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3832 unreachable("Invalid texture target");
3836 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3838 if (mt
->format
== MESA_FORMAT_S_UINT8
)
3839 return ISL_TILING_W
;
3840 return mt
->surf
.tiling
;
3844 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3845 const struct intel_mipmap_tree
*mt
,
3846 struct isl_surf
*surf
)
3848 surf
->dim
= get_isl_surf_dim(mt
->target
);
3849 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3850 mt
->surf
.tiling
, mt
->target
,
3852 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3853 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3854 surf
->row_pitch
= mt
->surf
.row_pitch
;
3855 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3857 if (brw
->gen
>= 9) {
3858 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3859 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3860 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3862 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3863 * alignment in terms of surface elements like we want.
3865 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3868 /* On earlier gens it's stored in pixels. */
3870 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3871 surf
->image_alignment_el
=
3872 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3875 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3876 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3877 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3878 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3879 surf
->logical_level0_px
.array_len
= 1;
3881 surf
->logical_level0_px
.depth
= 1;
3882 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3885 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3886 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3887 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3888 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3889 surf
->phys_level0_sa
.array_len
= 1;
3891 surf
->phys_level0_sa
.depth
= 1;
3892 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3895 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3896 surf
->samples
= mt
->surf
.samples
;
3898 surf
->size
= 0; /* TODO */
3899 surf
->alignment
= 0; /* TODO */
3901 switch (surf
->dim_layout
) {
3902 case ISL_DIM_LAYOUT_GEN4_2D
:
3903 case ISL_DIM_LAYOUT_GEN4_3D
:
3904 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3905 if (brw
->gen
>= 9) {
3906 surf
->array_pitch_el_rows
= mt
->qpitch
;
3909 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3910 assert(mt
->qpitch
% bh
== 0);
3911 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3914 case ISL_DIM_LAYOUT_GEN9_1D
:
3915 surf
->array_pitch_el_rows
= 1;
3919 switch (mt
->array_layout
) {
3920 case ALL_LOD_IN_EACH_SLICE
:
3921 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3923 case ALL_SLICES_AT_EACH_LOD
:
3924 case GEN6_HIZ_STENCIL
:
3925 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3928 unreachable("Invalid array layout");
3931 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3932 switch (base_format
) {
3933 case GL_DEPTH_COMPONENT
:
3934 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3936 case GL_STENCIL_INDEX
:
3937 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3939 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3941 case GL_DEPTH_STENCIL
:
3942 /* In this case we only texture from the depth part */
3943 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3944 ISL_SURF_USAGE_TEXTURE_BIT
;
3947 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3948 if (brw
->mesa_format_supports_render
[mt
->format
])
3949 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3953 if (_mesa_is_cube_map_texture(mt
->target
))
3954 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3958 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3959 const struct intel_mipmap_tree
*mt
)
3962 return ISL_AUX_USAGE_HIZ
;
3965 return ISL_AUX_USAGE_NONE
;
3967 return mt
->aux_usage
;