1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 intel_miptree_alloc_mcs(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
58 * Determine which MSAA layout should be used by the MSAA surface being
59 * created, based on the chip generation and the surface type.
61 static enum intel_msaa_layout
62 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
64 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
66 return INTEL_MSAA_LAYOUT_IMS
;
68 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
69 switch (_mesa_get_format_base_format(format
)) {
70 case GL_DEPTH_COMPONENT
:
71 case GL_STENCIL_INDEX
:
72 case GL_DEPTH_STENCIL
:
73 return INTEL_MSAA_LAYOUT_IMS
;
75 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
77 * This field must be set to 0 for all SINT MSRTs when all RT channels
80 * In practice this means that we have to disable MCS for all signed
81 * integer MSAA buffers. The alternative, to disable MCS only when one
82 * of the render target channels is disabled, is impractical because it
83 * would require converting between CMS and UMS MSAA layouts on the fly,
86 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
87 return INTEL_MSAA_LAYOUT_UMS
;
89 return INTEL_MSAA_LAYOUT_CMS
;
96 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
97 * scaled-down bitfield representation of the color buffer which is capable of
98 * recording when blocks of the color buffer are equal to the clear value.
99 * This function returns the block size that will be used by the MCS buffer
100 * corresponding to a certain color miptree.
102 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
103 * beneath the "Fast Color Clear" bullet (p327):
105 * The following table describes the RT alignment
119 * This alignment has the following uses:
121 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
122 * buffer contains 128 blocks horizontally and 256 blocks vertically.
124 * - For figuring out alignment restrictions for a fast clear operation. Fast
125 * clear operations must always clear aligned multiples of 16 blocks
126 * horizontally and 32 blocks vertically.
128 * - For scaling down the coordinates sent through the render pipeline during
129 * a fast clear. X coordinates must be scaled down by 8 times the block
130 * width, and Y coordinates by 16 times the block height.
132 * - For scaling down the coordinates sent through the render pipeline during
133 * a "Render Target Resolve" operation. X coordinates must be scaled down
134 * by half the block width, and Y coordinates by half the block height.
137 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
138 struct intel_mipmap_tree
*mt
,
139 unsigned *width_px
, unsigned *height
)
141 switch (mt
->tiling
) {
143 unreachable("Non-MSRT MCS requires X or Y tiling");
144 /* In release builds, fall through */
146 *width_px
= 32 / mt
->cpp
;
150 *width_px
= 64 / mt
->cpp
;
157 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
160 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
161 * beneath the "Fast Color Clear" bullet (p326):
163 * - Support is limited to tiled render targets.
164 * - Support is for non-mip-mapped and non-array surface types only.
166 * And then later, on p327:
168 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
172 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
173 struct intel_mipmap_tree
*mt
)
175 /* MCS support does not exist prior to Gen7 */
179 /* MCS is only supported for color buffers */
180 switch (_mesa_get_format_base_format(mt
->format
)) {
181 case GL_DEPTH_COMPONENT
:
182 case GL_DEPTH_STENCIL
:
183 case GL_STENCIL_INDEX
:
187 if (mt
->tiling
!= I915_TILING_X
&&
188 mt
->tiling
!= I915_TILING_Y
)
190 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
192 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
194 if (mt
->physical_depth0
!= 1)
197 /* There's no point in using an MCS buffer if the surface isn't in a
200 if (!brw
->format_supported_as_render_target
[mt
->format
])
208 * Determine depth format corresponding to a depth+stencil format,
209 * for separate stencil.
212 intel_depth_format_for_depthstencil_format(mesa_format format
) {
214 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
215 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
216 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
217 return MESA_FORMAT_Z_FLOAT32
;
225 * @param for_bo Indicates that the caller is
226 * intel_miptree_create_for_bo(). If true, then do not create
229 static struct intel_mipmap_tree
*
230 intel_miptree_create_layout(struct brw_context
*brw
,
240 bool force_all_slices_at_each_lod
)
242 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
246 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
247 _mesa_lookup_enum_by_nr(target
),
248 _mesa_get_format_name(format
),
249 first_level
, last_level
, depth0
, mt
);
251 if (target
== GL_TEXTURE_1D_ARRAY
) {
252 /* For a 1D Array texture the OpenGL API will treat the height0
253 * parameter as the number of array slices. For Intel hardware, we treat
254 * the 1D array as a 2D Array with a height of 1.
256 * So, when we first come through this path to create a 1D Array
257 * texture, height0 stores the number of slices, and depth0 is 1. In
258 * this case, we want to swap height0 and depth0.
260 * Since some miptrees will be created based on the base miptree, we may
261 * come through this path and see height0 as 1 and depth0 being the
262 * number of slices. In this case we don't need to do the swap.
264 assert(height0
== 1 || depth0
== 1);
273 mt
->first_level
= first_level
;
274 mt
->last_level
= last_level
;
275 mt
->logical_width0
= width0
;
276 mt
->logical_height0
= height0
;
277 mt
->logical_depth0
= depth0
;
278 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
279 exec_list_make_empty(&mt
->hiz_map
);
281 /* The cpp is bytes per (1, blockheight)-sized block for compressed
282 * textures. This is why you'll see divides by blockheight all over
285 _mesa_get_format_block_size(format
, &bw
, &bh
);
286 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
287 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
289 mt
->num_samples
= num_samples
;
290 mt
->compressed
= _mesa_is_format_compressed(format
);
291 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
294 if (num_samples
> 1) {
295 /* Adjust width/height/depth for MSAA */
296 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
297 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
298 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
299 * "If the surface is multisampled and it is a depth or stencil
300 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
301 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
304 * +----------------------------------------------------------------+
305 * | Num Multisamples | W_l = | H_l = |
306 * +----------------------------------------------------------------+
307 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
308 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
309 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
310 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
311 * +----------------------------------------------------------------+
314 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
315 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
316 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
318 * Another more complicated explanation for these adjustments comes
319 * from the Sandybridge PRM, volume 4, part 1, page 31:
321 * "Any of the other messages (sample*, LOD, load4) used with a
322 * (4x) multisampled surface will in-effect sample a surface with
323 * double the height and width as that indicated in the surface
324 * state. Each pixel position on the original-sized surface is
325 * replaced with a 2x2 of samples with the following arrangement:
330 * Thus, when sampling from a multisampled texture, it behaves as
331 * though the layout in memory for (x,y,sample) is:
333 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
334 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
336 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
337 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
339 * However, the actual layout of multisampled data in memory is:
341 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
342 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
344 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
345 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
347 * This pattern repeats for each 2x2 pixel block.
349 * As a result, when calculating the size of our 4-sample buffer for
350 * an odd width or height, we have to align before scaling up because
351 * sample 3 is in that bottom right 2x2 block.
353 switch (num_samples
) {
355 assert(brw
->gen
>= 8);
356 width0
= ALIGN(width0
, 2) * 2;
357 height0
= ALIGN(height0
, 2);
360 width0
= ALIGN(width0
, 2) * 2;
361 height0
= ALIGN(height0
, 2) * 2;
364 width0
= ALIGN(width0
, 2) * 4;
365 height0
= ALIGN(height0
, 2) * 2;
368 /* num_samples should already have been quantized to 0, 1, 2, 4, or
371 unreachable("not reached");
374 /* Non-interleaved */
375 depth0
*= num_samples
;
379 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
380 * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
381 * TODO: can we use it elsewhere?
383 switch (mt
->msaa_layout
) {
384 case INTEL_MSAA_LAYOUT_NONE
:
385 case INTEL_MSAA_LAYOUT_IMS
:
386 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
388 case INTEL_MSAA_LAYOUT_UMS
:
389 case INTEL_MSAA_LAYOUT_CMS
:
390 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
394 if (target
== GL_TEXTURE_CUBE_MAP
) {
399 mt
->physical_width0
= width0
;
400 mt
->physical_height0
= height0
;
401 mt
->physical_depth0
= depth0
;
404 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
405 (brw
->must_use_separate_stencil
||
406 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
407 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
408 mt
->stencil_mt
= intel_miptree_create(brw
,
418 INTEL_MIPTREE_TILING_ANY
,
419 force_all_slices_at_each_lod
);
420 if (!mt
->stencil_mt
) {
421 intel_miptree_release(&mt
);
425 /* Fix up the Z miptree format for how we're splitting out separate
426 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
428 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
431 if (format
== mt
->format
) {
432 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
433 _mesa_get_format_name(mt
->format
));
437 if (force_all_slices_at_each_lod
)
438 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
440 brw_miptree_layout(brw
, mt
);
446 * \brief Helper function for intel_miptree_create().
449 intel_miptree_choose_tiling(struct brw_context
*brw
,
452 uint32_t num_samples
,
453 enum intel_miptree_tiling_mode requested
,
454 struct intel_mipmap_tree
*mt
)
456 if (format
== MESA_FORMAT_S_UINT8
) {
457 /* The stencil buffer is W tiled. However, we request from the kernel a
458 * non-tiled buffer because the GTT is incapable of W fencing.
460 return I915_TILING_NONE
;
463 /* Some usages may want only one type of tiling, like depth miptrees (Y
464 * tiled), or temporary BOs for uploading data once (linear).
467 case INTEL_MIPTREE_TILING_ANY
:
469 case INTEL_MIPTREE_TILING_Y
:
470 return I915_TILING_Y
;
471 case INTEL_MIPTREE_TILING_NONE
:
472 return I915_TILING_NONE
;
475 if (num_samples
> 1) {
476 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
479 * [DevSNB+]: For multi-sample render targets, this field must be
480 * 1. MSRTs can only be tiled.
482 * Our usual reason for preferring X tiling (fast blits using the
483 * blitting engine) doesn't apply to MSAA, since we'll generally be
484 * downsampling or upsampling when blitting between the MSAA buffer
485 * and another buffer, and the blitting engine doesn't support that.
486 * So use Y tiling, since it makes better use of the cache.
488 return I915_TILING_Y
;
491 GLenum base_format
= _mesa_get_format_base_format(format
);
492 if (base_format
== GL_DEPTH_COMPONENT
||
493 base_format
== GL_DEPTH_STENCIL_EXT
)
494 return I915_TILING_Y
;
496 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
497 * in fact it leads to a less efficient use of memory space and bandwidth
498 * due to tile alignment.
500 if (mt
->logical_height0
== 1)
501 return I915_TILING_NONE
;
503 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
505 /* If the width is much smaller than a tile, don't bother tiling. */
506 if (minimum_pitch
< 64)
507 return I915_TILING_NONE
;
509 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
510 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
511 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
512 mt
->total_width
, mt
->total_height
);
513 return I915_TILING_NONE
;
516 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
518 return I915_TILING_X
;
520 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
521 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
523 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
524 * all the way back to 965, but is permitted on Gen7+.
526 if (brw
->gen
< 7 && mt
->cpp
>= 16)
527 return I915_TILING_X
;
529 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
530 * messages), on p64, under the heading "Surface Vertical Alignment":
532 * This field must be set to VALIGN_4 for all tiled Y Render Target
535 * So if the surface is renderable and uses a vertical alignment of 2,
536 * force it to be X tiled. This is somewhat conservative (it's possible
537 * that the client won't ever render to this surface), but it's difficult
538 * to know that ahead of time. And besides, since we use a vertical
539 * alignment of 4 as often as we can, this shouldn't happen very often.
541 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
542 brw
->format_supported_as_render_target
[format
]) {
543 return I915_TILING_X
;
546 return I915_TILING_Y
| I915_TILING_X
;
551 * Choose an appropriate uncompressed format for a requested
552 * compressed format, if unsupported.
555 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
557 /* No need to lower ETC formats on these platforms,
558 * they are supported natively.
560 if (brw
->gen
>= 8 || brw
->is_baytrail
)
564 case MESA_FORMAT_ETC1_RGB8
:
565 return MESA_FORMAT_R8G8B8X8_UNORM
;
566 case MESA_FORMAT_ETC2_RGB8
:
567 return MESA_FORMAT_R8G8B8X8_UNORM
;
568 case MESA_FORMAT_ETC2_SRGB8
:
569 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
570 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
571 return MESA_FORMAT_B8G8R8A8_SRGB
;
572 case MESA_FORMAT_ETC2_RGBA8_EAC
:
573 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
574 return MESA_FORMAT_R8G8B8A8_UNORM
;
575 case MESA_FORMAT_ETC2_R11_EAC
:
576 return MESA_FORMAT_R_UNORM16
;
577 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
578 return MESA_FORMAT_R_SNORM16
;
579 case MESA_FORMAT_ETC2_RG11_EAC
:
580 return MESA_FORMAT_R16G16_UNORM
;
581 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
582 return MESA_FORMAT_R16G16_SNORM
;
584 /* Non ETC1 / ETC2 format */
590 struct intel_mipmap_tree
*
591 intel_miptree_create(struct brw_context
*brw
,
599 bool expect_accelerated_upload
,
601 enum intel_miptree_tiling_mode requested_tiling
,
602 bool force_all_slices_at_each_lod
)
604 struct intel_mipmap_tree
*mt
;
605 mesa_format tex_format
= format
;
606 mesa_format etc_format
= MESA_FORMAT_NONE
;
607 GLuint total_width
, total_height
;
609 format
= intel_lower_compressed_format(brw
, format
);
611 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
613 mt
= intel_miptree_create_layout(brw
, target
, format
,
614 first_level
, last_level
, width0
,
617 force_all_slices_at_each_lod
);
619 * pitch == 0 || height == 0 indicates the null texture
621 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
622 intel_miptree_release(&mt
);
626 total_width
= mt
->total_width
;
627 total_height
= mt
->total_height
;
629 if (format
== MESA_FORMAT_S_UINT8
) {
630 /* Align to size of W tile, 64x64. */
631 total_width
= ALIGN(total_width
, 64);
632 total_height
= ALIGN(total_height
, 64);
635 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
636 num_samples
, requested_tiling
,
640 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
642 mt
->tiling
= I915_TILING_Y
;
648 mt
->etc_format
= etc_format
;
649 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
650 total_width
, total_height
, mt
->cpp
,
652 (expect_accelerated_upload
?
653 BO_ALLOC_FOR_RENDER
: 0));
656 /* If the BO is too large to fit in the aperture, we need to use the
657 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
658 * handle Y-tiling, so we need to fall back to X.
660 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
661 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
662 mt
->total_width
, mt
->total_height
);
664 mt
->tiling
= I915_TILING_X
;
665 drm_intel_bo_unreference(mt
->bo
);
666 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
667 total_width
, total_height
, mt
->cpp
,
669 (expect_accelerated_upload
?
670 BO_ALLOC_FOR_RENDER
: 0));
677 intel_miptree_release(&mt
);
682 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
683 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
684 intel_miptree_release(&mt
);
689 /* If this miptree is capable of supporting fast color clears, set
690 * fast_clear_state appropriately to ensure that fast clears will occur.
691 * Allocation of the MCS miptree will be deferred until the first fast
692 * clear actually occurs.
694 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
695 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
700 struct intel_mipmap_tree
*
701 intel_miptree_create_for_bo(struct brw_context
*brw
,
710 struct intel_mipmap_tree
*mt
;
711 uint32_t tiling
, swizzle
;
714 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
716 /* Nothing will be able to use this miptree with the BO if the offset isn't
719 if (tiling
!= I915_TILING_NONE
)
720 assert(offset
% 4096 == 0);
722 /* miptrees can't handle negative pitch. If you need flipping of images,
723 * that's outside of the scope of the mt.
727 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
729 mt
= intel_miptree_create_layout(brw
, target
, format
,
731 width
, height
, depth
,
738 drm_intel_bo_reference(bo
);
748 * For a singlesample renderbuffer, this simply wraps the given BO with a
751 * For a multisample renderbuffer, this wraps the window system's
752 * (singlesample) BO with a singlesample miptree attached to the
753 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
754 * that will contain the actual rendering (which is lazily resolved to
755 * irb->singlesample_mt).
758 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
759 struct intel_renderbuffer
*irb
,
761 uint32_t width
, uint32_t height
,
764 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
765 struct intel_mipmap_tree
*multisample_mt
= NULL
;
766 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
767 mesa_format format
= rb
->Format
;
768 int num_samples
= rb
->NumSamples
;
770 /* Only the front and back buffers, which are color buffers, are allocated
771 * through the image loader.
773 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
774 _mesa_get_format_base_format(format
) == GL_RGBA
);
776 singlesample_mt
= intel_miptree_create_for_bo(intel
,
784 if (!singlesample_mt
)
787 /* If this miptree is capable of supporting fast color clears, set
788 * mcs_state appropriately to ensure that fast clears will occur.
789 * Allocation of the MCS miptree will be deferred until the first fast
790 * clear actually occurs.
792 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
793 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
795 if (num_samples
== 0) {
796 intel_miptree_release(&irb
->mt
);
797 irb
->mt
= singlesample_mt
;
799 assert(!irb
->singlesample_mt
);
801 intel_miptree_release(&irb
->singlesample_mt
);
802 irb
->singlesample_mt
= singlesample_mt
;
805 irb
->mt
->logical_width0
!= width
||
806 irb
->mt
->logical_height0
!= height
) {
807 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
815 irb
->need_downsample
= false;
816 intel_miptree_release(&irb
->mt
);
817 irb
->mt
= multisample_mt
;
823 intel_miptree_release(&irb
->singlesample_mt
);
824 intel_miptree_release(&irb
->mt
);
828 struct intel_mipmap_tree
*
829 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
833 uint32_t num_samples
)
835 struct intel_mipmap_tree
*mt
;
838 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
840 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
841 width
, height
, depth
, true, num_samples
,
842 INTEL_MIPTREE_TILING_ANY
, false);
846 if (brw_is_hiz_depth_format(brw
, format
)) {
847 ok
= intel_miptree_alloc_hiz(brw
, mt
);
855 intel_miptree_release(&mt
);
860 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
861 struct intel_mipmap_tree
*src
)
866 intel_miptree_release(dst
);
870 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
878 intel_miptree_release(struct intel_mipmap_tree
**mt
)
883 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
884 if (--(*mt
)->refcount
<= 0) {
887 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
889 drm_intel_bo_unreference((*mt
)->bo
);
890 intel_miptree_release(&(*mt
)->stencil_mt
);
891 if ((*mt
)->hiz_buf
) {
892 if ((*mt
)->hiz_buf
->mt
)
893 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
895 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
896 free((*mt
)->hiz_buf
);
898 intel_miptree_release(&(*mt
)->mcs_mt
);
899 intel_resolve_map_clear(&(*mt
)->hiz_map
);
901 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
902 free((*mt
)->level
[i
].slice
);
911 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
912 int *width
, int *height
, int *depth
)
914 switch (image
->TexObject
->Target
) {
915 case GL_TEXTURE_1D_ARRAY
:
916 *width
= image
->Width
;
918 *depth
= image
->Height
;
921 *width
= image
->Width
;
922 *height
= image
->Height
;
923 *depth
= image
->Depth
;
929 * Can the image be pulled into a unified mipmap tree? This mirrors
930 * the completeness test in a lot of ways.
932 * Not sure whether I want to pass gl_texture_image here.
935 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
936 struct gl_texture_image
*image
)
938 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
939 GLuint level
= intelImage
->base
.Base
.Level
;
940 int width
, height
, depth
;
942 /* glTexImage* choose the texture object based on the target passed in, and
943 * objects can't change targets over their lifetimes, so this should be
946 assert(image
->TexObject
->Target
== mt
->target
);
948 mesa_format mt_format
= mt
->format
;
949 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
950 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
951 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
952 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
953 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
954 mt_format
= mt
->etc_format
;
956 if (image
->TexFormat
!= mt_format
)
959 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
961 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
964 int level_depth
= mt
->level
[level
].depth
;
965 if (mt
->num_samples
> 1) {
966 switch (mt
->msaa_layout
) {
967 case INTEL_MSAA_LAYOUT_NONE
:
968 case INTEL_MSAA_LAYOUT_IMS
:
970 case INTEL_MSAA_LAYOUT_UMS
:
971 case INTEL_MSAA_LAYOUT_CMS
:
972 level_depth
/= mt
->num_samples
;
977 /* Test image dimensions against the base level image adjusted for
978 * minification. This will also catch images not present in the
979 * tree, changed targets, etc.
981 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
982 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
983 depth
!= level_depth
) {
987 if (image
->NumSamples
!= mt
->num_samples
)
995 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
997 GLuint x
, GLuint y
, GLuint d
)
999 mt
->level
[level
].depth
= d
;
1000 mt
->level
[level
].level_x
= x
;
1001 mt
->level
[level
].level_y
= y
;
1003 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
1006 assert(mt
->level
[level
].slice
== NULL
);
1008 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1009 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1010 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1015 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1016 GLuint level
, GLuint img
,
1019 if (img
== 0 && level
== 0)
1020 assert(x
== 0 && y
== 0);
1022 assert(img
< mt
->level
[level
].depth
);
1024 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1025 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1027 DBG("%s level %d img %d pos %d,%d\n",
1028 __FUNCTION__
, level
, img
,
1029 mt
->level
[level
].slice
[img
].x_offset
,
1030 mt
->level
[level
].slice
[img
].y_offset
);
1034 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1035 GLuint level
, GLuint slice
,
1036 GLuint
*x
, GLuint
*y
)
1038 assert(slice
< mt
->level
[level
].depth
);
1040 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1041 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1045 * This function computes masks that may be used to select the bits of the X
1046 * and Y coordinates that indicate the offset within a tile. If the BO is
1047 * untiled, the masks are set to 0.
1050 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1051 uint32_t *mask_x
, uint32_t *mask_y
,
1052 bool map_stencil_as_y_tiled
)
1055 uint32_t tiling
= mt
->tiling
;
1057 if (map_stencil_as_y_tiled
)
1058 tiling
= I915_TILING_Y
;
1062 unreachable("not reached");
1063 case I915_TILING_NONE
:
1064 *mask_x
= *mask_y
= 0;
1067 *mask_x
= 512 / cpp
- 1;
1071 *mask_x
= 128 / cpp
- 1;
1078 * Compute the offset (in bytes) from the start of the BO to the given x
1079 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1080 * multiples of the tile size.
1083 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1084 uint32_t x
, uint32_t y
,
1085 bool map_stencil_as_y_tiled
)
1088 uint32_t pitch
= mt
->pitch
;
1089 uint32_t tiling
= mt
->tiling
;
1091 if (map_stencil_as_y_tiled
) {
1092 tiling
= I915_TILING_Y
;
1094 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1095 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1096 * the resulting surface is twice the pitch of the original miptree,
1097 * since each row in the Y-tiled view corresponds to two rows in the
1098 * actual W-tiled surface. So we need to correct the pitch before
1099 * computing the offsets.
1106 unreachable("not reached");
1107 case I915_TILING_NONE
:
1108 return y
* pitch
+ x
* cpp
;
1110 assert((x
% (512 / cpp
)) == 0);
1111 assert((y
% 8) == 0);
1112 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1114 assert((x
% (128 / cpp
)) == 0);
1115 assert((y
% 32) == 0);
1116 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1121 * Rendering with tiled buffers requires that the base address of the buffer
1122 * be aligned to a page boundary. For renderbuffers, and sometimes with
1123 * textures, we may want the surface to point at a texture image level that
1124 * isn't at a page boundary.
1126 * This function returns an appropriately-aligned base offset
1127 * according to the tiling restrictions, plus any required x/y offset
1131 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1132 GLuint level
, GLuint slice
,
1137 uint32_t mask_x
, mask_y
;
1139 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1140 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1142 *tile_x
= x
& mask_x
;
1143 *tile_y
= y
& mask_y
;
1145 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1149 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1150 struct intel_mipmap_tree
*dst_mt
,
1151 struct intel_mipmap_tree
*src_mt
,
1158 ptrdiff_t src_stride
, dst_stride
;
1159 int cpp
= dst_mt
->cpp
;
1161 intel_miptree_map(brw
, src_mt
,
1165 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1168 intel_miptree_map(brw
, dst_mt
,
1172 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1176 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1177 _mesa_get_format_name(src_mt
->format
),
1178 src_mt
, src
, src_stride
,
1179 _mesa_get_format_name(dst_mt
->format
),
1180 dst_mt
, dst
, dst_stride
,
1183 int row_size
= cpp
* width
;
1184 if (src_stride
== row_size
&&
1185 dst_stride
== row_size
) {
1186 memcpy(dst
, src
, row_size
* height
);
1188 for (int i
= 0; i
< height
; i
++) {
1189 memcpy(dst
, src
, row_size
);
1195 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1196 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1198 /* Don't forget to copy the stencil data over, too. We could have skipped
1199 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1200 * shuffling the two data sources in/out of temporary storage instead of
1201 * the direct mapping we get this way.
1203 if (dst_mt
->stencil_mt
) {
1204 assert(src_mt
->stencil_mt
);
1205 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1206 level
, slice
, width
, height
);
1211 intel_miptree_copy_slice(struct brw_context
*brw
,
1212 struct intel_mipmap_tree
*dst_mt
,
1213 struct intel_mipmap_tree
*src_mt
,
1219 mesa_format format
= src_mt
->format
;
1220 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1221 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1229 assert(depth
< src_mt
->level
[level
].depth
);
1230 assert(src_mt
->format
== dst_mt
->format
);
1232 if (dst_mt
->compressed
) {
1233 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1234 width
= ALIGN(width
, dst_mt
->align_w
);
1237 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1238 * below won't apply since we can't do the depth's Y tiling or the
1239 * stencil's W tiling in the blitter.
1241 if (src_mt
->stencil_mt
) {
1242 intel_miptree_copy_slice_sw(brw
,
1249 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1250 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1251 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1253 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1254 _mesa_get_format_name(src_mt
->format
),
1255 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1256 _mesa_get_format_name(dst_mt
->format
),
1257 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1260 if (!intel_miptree_blit(brw
,
1261 src_mt
, level
, slice
, 0, 0, false,
1262 dst_mt
, level
, slice
, 0, 0, false,
1263 width
, height
, GL_COPY
)) {
1264 perf_debug("miptree validate blit for %s failed\n",
1265 _mesa_get_format_name(format
));
1267 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1273 * Copies the image's current data to the given miptree, and associates that
1274 * miptree with the image.
1276 * If \c invalidate is true, then the actual image data does not need to be
1277 * copied, but the image still needs to be associated to the new miptree (this
1278 * is set to true if we're about to clear the image).
1281 intel_miptree_copy_teximage(struct brw_context
*brw
,
1282 struct intel_texture_image
*intelImage
,
1283 struct intel_mipmap_tree
*dst_mt
,
1286 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1287 struct intel_texture_object
*intel_obj
=
1288 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1289 int level
= intelImage
->base
.Base
.Level
;
1290 int face
= intelImage
->base
.Base
.Face
;
1293 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1294 depth
= intelImage
->base
.Base
.Height
;
1296 depth
= intelImage
->base
.Base
.Depth
;
1299 for (int slice
= 0; slice
< depth
; slice
++) {
1300 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1304 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1305 intel_obj
->needs_validate
= true;
1309 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1310 struct intel_mipmap_tree
*mt
,
1313 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1314 assert(mt
->mcs_mt
== NULL
);
1316 /* Choose the correct format for the MCS buffer. All that really matters
1317 * is that we allocate the right buffer size, since we'll always be
1318 * accessing this miptree using MCS-specific hardware mechanisms, which
1319 * infer the correct format based on num_samples.
1322 switch (num_samples
) {
1325 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1328 format
= MESA_FORMAT_R_UNORM8
;
1331 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1332 * for each sample, plus 8 padding bits).
1334 format
= MESA_FORMAT_R_UINT32
;
1337 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1340 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1342 * "The MCS surface must be stored as Tile Y."
1344 mt
->mcs_mt
= intel_miptree_create(brw
,
1350 mt
->logical_height0
,
1353 0 /* num_samples */,
1354 INTEL_MIPTREE_TILING_Y
,
1357 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1359 * When MCS buffer is enabled and bound to MSRT, it is required that it
1360 * is cleared prior to any rendering.
1362 * Since we don't use the MCS buffer for any purpose other than rendering,
1363 * it makes sense to just clear it immediately upon allocation.
1365 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1367 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1368 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1369 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1370 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1377 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1378 struct intel_mipmap_tree
*mt
)
1380 assert(mt
->mcs_mt
== NULL
);
1382 /* The format of the MCS buffer is opaque to the driver; all that matters
1383 * is that we get its size and pitch right. We'll pretend that the format
1384 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1385 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1386 * the block width and then a further factor of 4. Since an MCS tile
1387 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1388 * we'll need to scale the height down by the block height and then a
1389 * further factor of 8.
1391 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1392 unsigned block_width_px
;
1393 unsigned block_height
;
1394 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1395 unsigned width_divisor
= block_width_px
* 4;
1396 unsigned height_divisor
= block_height
* 8;
1397 unsigned mcs_width
=
1398 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1399 unsigned mcs_height
=
1400 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1401 assert(mt
->logical_depth0
== 1);
1402 mt
->mcs_mt
= intel_miptree_create(brw
,
1411 0 /* num_samples */,
1412 INTEL_MIPTREE_TILING_Y
,
1420 * Helper for intel_miptree_alloc_hiz() that sets
1421 * \c mt->level[level].has_hiz. Return true if and only if
1422 * \c has_hiz was set.
1425 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1426 struct intel_mipmap_tree
*mt
,
1429 assert(mt
->hiz_buf
);
1431 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1432 uint32_t width
= minify(mt
->physical_width0
, level
);
1433 uint32_t height
= minify(mt
->physical_height0
, level
);
1435 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1436 * and the height is 4 aligned. This allows our HiZ support
1437 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1438 * we can grow the width & height to allow the HiZ op to
1439 * force the proper size alignments.
1441 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1442 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1447 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1448 mt
->level
[level
].has_hiz
= true;
1454 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1455 * buffer dimensions and allocates a bo for the hiz buffer.
1457 static struct intel_miptree_aux_buffer
*
1458 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1459 struct intel_mipmap_tree
*mt
)
1461 unsigned z_width
= mt
->logical_width0
;
1462 unsigned z_height
= mt
->logical_height0
;
1463 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1464 unsigned hz_width
, hz_height
;
1465 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1470 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1471 * adjustments required for Z_Height and Z_Width based on multisampling.
1473 switch (mt
->num_samples
) {
1487 unreachable("unsupported sample count");
1490 const unsigned vertical_align
= 8; /* 'j' in the docs */
1491 const unsigned H0
= z_height
;
1492 const unsigned h0
= ALIGN(H0
, vertical_align
);
1493 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1494 const unsigned Z0
= z_depth
;
1496 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1497 hz_width
= ALIGN(z_width
, 16);
1499 if (mt
->target
== GL_TEXTURE_3D
) {
1503 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1504 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1505 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1506 hz_height
+= h_i
* Z_i
;
1507 H_i
= minify(H_i
, 1);
1508 Z_i
= minify(Z_i
, 1);
1511 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1513 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1515 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1516 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1517 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1518 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1519 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1521 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1522 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1526 unsigned long pitch
;
1527 uint32_t tiling
= I915_TILING_Y
;
1528 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1529 hz_width
, hz_height
, 1,
1531 BO_ALLOC_FOR_RENDER
);
1535 } else if (tiling
!= I915_TILING_Y
) {
1536 drm_intel_bo_unreference(buf
->bo
);
1548 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1549 * buffer dimensions and allocates a bo for the hiz buffer.
1551 static struct intel_miptree_aux_buffer
*
1552 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1553 struct intel_mipmap_tree
*mt
)
1555 unsigned z_width
= mt
->logical_width0
;
1556 unsigned z_height
= mt
->logical_height0
;
1557 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1558 unsigned hz_width
, hz_height
;
1559 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1564 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1565 * adjustments required for Z_Height and Z_Width based on multisampling.
1567 switch (mt
->num_samples
) {
1581 unreachable("unsupported sample count");
1584 const unsigned vertical_align
= 8; /* 'j' in the docs */
1585 const unsigned H0
= z_height
;
1586 const unsigned h0
= ALIGN(H0
, vertical_align
);
1587 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1588 const unsigned Z0
= z_depth
;
1590 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1591 hz_width
= ALIGN(z_width
, 16);
1595 unsigned sum_h_i
= 0;
1596 unsigned hz_height_3d_sum
= 0;
1597 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1598 unsigned i
= level
- mt
->first_level
;
1599 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1600 /* sum(i=2 to m; h_i) */
1604 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1605 hz_height_3d_sum
+= h_i
* Z_i
;
1606 H_i
= minify(H_i
, 1);
1607 Z_i
= minify(Z_i
, 1);
1609 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1610 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1612 if (mt
->target
== GL_TEXTURE_3D
) {
1613 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1614 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1616 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1617 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1618 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1619 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1620 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1622 * We can can just take our hz_height calculation from above, and
1623 * multiply by 6 for the cube map and cube map array types.
1629 unsigned long pitch
;
1630 uint32_t tiling
= I915_TILING_Y
;
1631 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1632 hz_width
, hz_height
, 1,
1634 BO_ALLOC_FOR_RENDER
);
1638 } else if (tiling
!= I915_TILING_Y
) {
1639 drm_intel_bo_unreference(buf
->bo
);
1650 static struct intel_miptree_aux_buffer
*
1651 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1652 struct intel_mipmap_tree
*mt
)
1654 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1655 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1660 buf
->mt
= intel_miptree_create(brw
,
1666 mt
->logical_height0
,
1670 INTEL_MIPTREE_TILING_ANY
,
1671 force_all_slices_at_each_lod
);
1677 buf
->bo
= buf
->mt
->bo
;
1678 buf
->pitch
= buf
->mt
->pitch
;
1679 buf
->qpitch
= buf
->mt
->qpitch
;
1686 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1687 struct intel_mipmap_tree
*mt
)
1689 assert(mt
->hiz_buf
== NULL
);
1691 if (brw
->gen
== 7) {
1692 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1693 } else if (brw
->gen
>= 8) {
1694 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1696 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1702 /* Mark that all slices need a HiZ resolve. */
1703 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1704 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1707 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1708 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1709 exec_node_init(&m
->link
);
1712 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1714 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1722 * Does the miptree slice have hiz enabled?
1725 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1727 intel_miptree_check_level_layer(mt
, level
, 0);
1728 return mt
->level
[level
].has_hiz
;
1732 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1736 if (!intel_miptree_level_has_hiz(mt
, level
))
1739 intel_resolve_map_set(&mt
->hiz_map
,
1740 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1745 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1749 if (!intel_miptree_level_has_hiz(mt
, level
))
1752 intel_resolve_map_set(&mt
->hiz_map
,
1753 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1757 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1761 uint32_t end_layer
= mt
->level
[level
].depth
;
1763 for (layer
= 0; layer
< end_layer
; layer
++) {
1764 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1769 intel_miptree_slice_resolve(struct brw_context
*brw
,
1770 struct intel_mipmap_tree
*mt
,
1773 enum gen6_hiz_op need
)
1775 intel_miptree_check_level_layer(mt
, level
, layer
);
1777 struct intel_resolve_map
*item
=
1778 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1780 if (!item
|| item
->need
!= need
)
1783 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1784 intel_resolve_map_remove(item
);
1789 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1790 struct intel_mipmap_tree
*mt
,
1794 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1795 GEN6_HIZ_OP_HIZ_RESOLVE
);
1799 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1800 struct intel_mipmap_tree
*mt
,
1804 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1805 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1809 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1810 struct intel_mipmap_tree
*mt
,
1811 enum gen6_hiz_op need
)
1813 bool did_resolve
= false;
1815 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1816 if (map
->need
!= need
)
1819 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1820 intel_resolve_map_remove(map
);
1828 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1829 struct intel_mipmap_tree
*mt
)
1831 return intel_miptree_all_slices_resolve(brw
, mt
,
1832 GEN6_HIZ_OP_HIZ_RESOLVE
);
1836 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1837 struct intel_mipmap_tree
*mt
)
1839 return intel_miptree_all_slices_resolve(brw
, mt
,
1840 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1845 intel_miptree_resolve_color(struct brw_context
*brw
,
1846 struct intel_mipmap_tree
*mt
)
1848 switch (mt
->fast_clear_state
) {
1849 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1850 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1851 /* No resolve needed */
1853 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1854 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1855 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1856 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1857 brw_meta_resolve_color(brw
, mt
);
1864 * Make it possible to share the BO backing the given miptree with another
1865 * process or another miptree.
1867 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1868 * then discard the MCS buffer, if present. We also set the fast_clear_state
1869 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1870 * allocated in the future.
1873 intel_miptree_make_shareable(struct brw_context
*brw
,
1874 struct intel_mipmap_tree
*mt
)
1876 /* MCS buffers are also used for multisample buffers, but we can't resolve
1877 * away a multisample MCS buffer because it's an integral part of how the
1878 * pixel data is stored. Fortunately this code path should never be
1879 * reached for multisample buffers.
1881 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1884 intel_miptree_resolve_color(brw
, mt
);
1885 intel_miptree_release(&mt
->mcs_mt
);
1886 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1892 * \brief Get pointer offset into stencil buffer.
1894 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1895 * must decode the tile's layout in software.
1898 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1900 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1902 * Even though the returned offset is always positive, the return type is
1904 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1905 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1908 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1910 uint32_t tile_size
= 4096;
1911 uint32_t tile_width
= 64;
1912 uint32_t tile_height
= 64;
1913 uint32_t row_size
= 64 * stride
;
1915 uint32_t tile_x
= x
/ tile_width
;
1916 uint32_t tile_y
= y
/ tile_height
;
1918 /* The byte's address relative to the tile's base addres. */
1919 uint32_t byte_x
= x
% tile_width
;
1920 uint32_t byte_y
= y
% tile_height
;
1922 uintptr_t u
= tile_y
* row_size
1923 + tile_x
* tile_size
1924 + 512 * (byte_x
/ 8)
1926 + 32 * ((byte_y
/ 4) % 2)
1927 + 16 * ((byte_x
/ 4) % 2)
1928 + 8 * ((byte_y
/ 2) % 2)
1929 + 4 * ((byte_x
/ 2) % 2)
1934 /* adjust for bit6 swizzling */
1935 if (((byte_x
/ 8) % 2) == 1) {
1936 if (((byte_y
/ 8) % 2) == 0) {
1948 intel_miptree_updownsample(struct brw_context
*brw
,
1949 struct intel_mipmap_tree
*src
,
1950 struct intel_mipmap_tree
*dst
)
1953 brw_blorp_blit_miptrees(brw
,
1954 src
, 0 /* level */, 0 /* layer */, src
->format
,
1955 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
1957 src
->logical_width0
, src
->logical_height0
,
1959 dst
->logical_width0
, dst
->logical_height0
,
1960 GL_NEAREST
, false, false /*mirror x, y*/);
1961 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1962 brw_meta_stencil_updownsample(brw
, src
, dst
);
1964 brw_meta_updownsample(brw
, src
, dst
);
1967 if (src
->stencil_mt
) {
1968 if (brw
->gen
>= 8) {
1969 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1973 brw_blorp_blit_miptrees(brw
,
1974 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1975 src
->stencil_mt
->format
,
1976 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1977 dst
->stencil_mt
->format
,
1979 src
->logical_width0
, src
->logical_height0
,
1981 dst
->logical_width0
, dst
->logical_height0
,
1982 GL_NEAREST
, false, false /*mirror x, y*/);
1987 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1989 /* CPU accesses to color buffers don't understand fast color clears, so
1990 * resolve any pending fast color clears before we map.
1992 intel_miptree_resolve_color(brw
, mt
);
1994 drm_intel_bo
*bo
= mt
->bo
;
1996 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1997 intel_batchbuffer_flush(brw
);
1999 if (mt
->tiling
!= I915_TILING_NONE
)
2000 brw_bo_map_gtt(brw
, bo
, "miptree");
2002 brw_bo_map(brw
, bo
, true, "miptree");
2008 intel_miptree_unmap_raw(struct brw_context
*brw
,
2009 struct intel_mipmap_tree
*mt
)
2011 drm_intel_bo_unmap(mt
->bo
);
2015 intel_miptree_map_gtt(struct brw_context
*brw
,
2016 struct intel_mipmap_tree
*mt
,
2017 struct intel_miptree_map
*map
,
2018 unsigned int level
, unsigned int slice
)
2020 unsigned int bw
, bh
;
2022 unsigned int image_x
, image_y
;
2023 intptr_t x
= map
->x
;
2024 intptr_t y
= map
->y
;
2026 /* For compressed formats, the stride is the number of bytes per
2027 * row of blocks. intel_miptree_get_image_offset() already does
2030 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2031 assert(y
% bh
== 0);
2034 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2039 /* Note that in the case of cube maps, the caller must have passed the
2040 * slice number referencing the face.
2042 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2046 map
->stride
= mt
->pitch
;
2047 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2050 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2051 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __FUNCTION__
,
2052 map
->x
, map
->y
, map
->w
, map
->h
,
2053 mt
, _mesa_get_format_name(mt
->format
),
2054 x
, y
, map
->ptr
, map
->stride
);
2058 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2059 struct intel_mipmap_tree
*mt
,
2060 struct intel_miptree_map
*map
,
2064 intel_miptree_unmap_raw(brw
, mt
);
2068 intel_miptree_map_blit(struct brw_context
*brw
,
2069 struct intel_mipmap_tree
*mt
,
2070 struct intel_miptree_map
*map
,
2071 unsigned int level
, unsigned int slice
)
2073 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2077 INTEL_MIPTREE_TILING_NONE
,
2080 fprintf(stderr
, "Failed to allocate blit temporary\n");
2083 map
->stride
= map
->mt
->pitch
;
2085 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2086 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2087 * invalidate is set, since we'll be writing the whole rectangle from our
2088 * temporary buffer back out.
2090 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2091 if (!intel_miptree_blit(brw
,
2093 map
->x
, map
->y
, false,
2096 map
->w
, map
->h
, GL_COPY
)) {
2097 fprintf(stderr
, "Failed to blit\n");
2102 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2104 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
2105 map
->x
, map
->y
, map
->w
, map
->h
,
2106 mt
, _mesa_get_format_name(mt
->format
),
2107 level
, slice
, map
->ptr
, map
->stride
);
2112 intel_miptree_release(&map
->mt
);
2118 intel_miptree_unmap_blit(struct brw_context
*brw
,
2119 struct intel_mipmap_tree
*mt
,
2120 struct intel_miptree_map
*map
,
2124 struct gl_context
*ctx
= &brw
->ctx
;
2126 intel_miptree_unmap_raw(brw
, map
->mt
);
2128 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2129 bool ok
= intel_miptree_blit(brw
,
2133 map
->x
, map
->y
, false,
2134 map
->w
, map
->h
, GL_COPY
);
2135 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2138 intel_miptree_release(&map
->mt
);
2142 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2144 #if defined(USE_SSE41)
2146 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2147 struct intel_mipmap_tree
*mt
,
2148 struct intel_miptree_map
*map
,
2149 unsigned int level
, unsigned int slice
)
2151 assert(map
->mode
& GL_MAP_READ_BIT
);
2152 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2154 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
2155 map
->x
, map
->y
, map
->w
, map
->h
,
2156 mt
, _mesa_get_format_name(mt
->format
),
2157 level
, slice
, map
->ptr
, map
->stride
);
2159 /* Map the original image */
2162 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2166 void *src
= intel_miptree_map_raw(brw
, mt
);
2169 src
+= image_y
* mt
->pitch
;
2170 src
+= image_x
* mt
->cpp
;
2172 /* Due to the pixel offsets for the particular image being mapped, our
2173 * src pointer may not be 16-byte aligned. However, if the pitch is
2174 * divisible by 16, then the amount by which it's misaligned will remain
2175 * consistent from row to row.
2177 assert((mt
->pitch
% 16) == 0);
2178 const int misalignment
= ((uintptr_t) src
) & 15;
2180 /* Create an untiled temporary buffer for the mapping. */
2181 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2183 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2185 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2186 /* Offset the destination so it has the same misalignment as src. */
2187 map
->ptr
= map
->buffer
+ misalignment
;
2189 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2191 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2192 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2193 void *src_ptr
= src
+ y
* mt
->pitch
;
2195 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2198 intel_miptree_unmap_raw(brw
, mt
);
2202 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2203 struct intel_mipmap_tree
*mt
,
2204 struct intel_miptree_map
*map
,
2208 _mesa_align_free(map
->buffer
);
2215 intel_miptree_map_s8(struct brw_context
*brw
,
2216 struct intel_mipmap_tree
*mt
,
2217 struct intel_miptree_map
*map
,
2218 unsigned int level
, unsigned int slice
)
2220 map
->stride
= map
->w
;
2221 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2225 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2226 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2227 * invalidate is set, since we'll be writing the whole rectangle from our
2228 * temporary buffer back out.
2230 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2231 uint8_t *untiled_s8_map
= map
->ptr
;
2232 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2233 unsigned int image_x
, image_y
;
2235 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2237 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2238 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2239 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2240 x
+ image_x
+ map
->x
,
2241 y
+ image_y
+ map
->y
,
2242 brw
->has_swizzling
);
2243 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2247 intel_miptree_unmap_raw(brw
, mt
);
2249 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
2250 map
->x
, map
->y
, map
->w
, map
->h
,
2251 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2253 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2254 map
->x
, map
->y
, map
->w
, map
->h
,
2255 mt
, map
->ptr
, map
->stride
);
2260 intel_miptree_unmap_s8(struct brw_context
*brw
,
2261 struct intel_mipmap_tree
*mt
,
2262 struct intel_miptree_map
*map
,
2266 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2267 unsigned int image_x
, image_y
;
2268 uint8_t *untiled_s8_map
= map
->ptr
;
2269 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2271 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2273 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2274 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2275 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2278 brw
->has_swizzling
);
2279 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2283 intel_miptree_unmap_raw(brw
, mt
);
2290 intel_miptree_map_etc(struct brw_context
*brw
,
2291 struct intel_mipmap_tree
*mt
,
2292 struct intel_miptree_map
*map
,
2296 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2297 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2298 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2301 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2302 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2304 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2305 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2306 map
->w
, map
->h
, 1));
2307 map
->ptr
= map
->buffer
;
2311 intel_miptree_unmap_etc(struct brw_context
*brw
,
2312 struct intel_mipmap_tree
*mt
,
2313 struct intel_miptree_map
*map
,
2319 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2324 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2325 + image_y
* mt
->pitch
2326 + image_x
* mt
->cpp
;
2328 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2329 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2330 map
->ptr
, map
->stride
,
2333 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2334 map
->ptr
, map
->stride
,
2335 map
->w
, map
->h
, mt
->etc_format
);
2337 intel_miptree_unmap_raw(brw
, mt
);
2342 * Mapping function for packed depth/stencil miptrees backed by real separate
2343 * miptrees for depth and stencil.
2345 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2346 * separate from the depth buffer. Yet at the GL API level, we have to expose
2347 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2348 * be able to map that memory for texture storage and glReadPixels-type
2349 * operations. We give Mesa core that access by mallocing a temporary and
2350 * copying the data between the actual backing store and the temporary.
2353 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2354 struct intel_mipmap_tree
*mt
,
2355 struct intel_miptree_map
*map
,
2356 unsigned int level
, unsigned int slice
)
2358 struct intel_mipmap_tree
*z_mt
= mt
;
2359 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2360 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2361 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2363 map
->stride
= map
->w
* packed_bpp
;
2364 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2368 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2369 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2370 * invalidate is set, since we'll be writing the whole rectangle from our
2371 * temporary buffer back out.
2373 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2374 uint32_t *packed_map
= map
->ptr
;
2375 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2376 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2377 unsigned int s_image_x
, s_image_y
;
2378 unsigned int z_image_x
, z_image_y
;
2380 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2381 &s_image_x
, &s_image_y
);
2382 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2383 &z_image_x
, &z_image_y
);
2385 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2386 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2387 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2388 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2391 brw
->has_swizzling
);
2392 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2394 (map_x
+ z_image_x
));
2395 uint8_t s
= s_map
[s_offset
];
2396 uint32_t z
= z_map
[z_offset
];
2398 if (map_z32f_x24s8
) {
2399 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2400 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2402 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2407 intel_miptree_unmap_raw(brw
, s_mt
);
2408 intel_miptree_unmap_raw(brw
, z_mt
);
2410 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2412 map
->x
, map
->y
, map
->w
, map
->h
,
2413 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2414 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2415 map
->ptr
, map
->stride
);
2417 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2418 map
->x
, map
->y
, map
->w
, map
->h
,
2419 mt
, map
->ptr
, map
->stride
);
2424 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2425 struct intel_mipmap_tree
*mt
,
2426 struct intel_miptree_map
*map
,
2430 struct intel_mipmap_tree
*z_mt
= mt
;
2431 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2432 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2434 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2435 uint32_t *packed_map
= map
->ptr
;
2436 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2437 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2438 unsigned int s_image_x
, s_image_y
;
2439 unsigned int z_image_x
, z_image_y
;
2441 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2442 &s_image_x
, &s_image_y
);
2443 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2444 &z_image_x
, &z_image_y
);
2446 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2447 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2448 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2449 x
+ s_image_x
+ map
->x
,
2450 y
+ s_image_y
+ map
->y
,
2451 brw
->has_swizzling
);
2452 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2454 (x
+ z_image_x
+ map
->x
));
2456 if (map_z32f_x24s8
) {
2457 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2458 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2460 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2461 s_map
[s_offset
] = packed
>> 24;
2462 z_map
[z_offset
] = packed
;
2467 intel_miptree_unmap_raw(brw
, s_mt
);
2468 intel_miptree_unmap_raw(brw
, z_mt
);
2470 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2472 map
->x
, map
->y
, map
->w
, map
->h
,
2473 z_mt
, _mesa_get_format_name(z_mt
->format
),
2474 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2475 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2476 map
->ptr
, map
->stride
);
2483 * Create and attach a map to the miptree at (level, slice). Return the
2486 static struct intel_miptree_map
*
2487 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2496 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2501 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2502 mt
->level
[level
].slice
[slice
].map
= map
;
2514 * Release the map at (level, slice).
2517 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2521 struct intel_miptree_map
**map
;
2523 map
= &mt
->level
[level
].slice
[slice
].map
;
2529 can_blit_slice(struct intel_mipmap_tree
*mt
,
2530 unsigned int level
, unsigned int slice
)
2534 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2535 if (image_x
>= 32768 || image_y
>= 32768)
2538 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2539 if (mt
->pitch
>= 32768)
2546 use_intel_mipree_map_blit(struct brw_context
*brw
,
2547 struct intel_mipmap_tree
*mt
,
2553 /* It's probably not worth swapping to the blit ring because of
2554 * all the overhead involved.
2556 !(mode
& GL_MAP_WRITE_BIT
) &&
2558 (mt
->tiling
== I915_TILING_X
||
2559 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2560 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2561 can_blit_slice(mt
, level
, slice
))
2564 if (mt
->tiling
!= I915_TILING_NONE
&&
2565 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2566 assert(can_blit_slice(mt
, level
, slice
));
2574 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2575 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2576 * arithmetic overflow.
2578 * If you call this function and use \a out_stride, then you're doing pointer
2579 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2580 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2581 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2582 * which usually have type uint32_t or GLuint.
2585 intel_miptree_map(struct brw_context
*brw
,
2586 struct intel_mipmap_tree
*mt
,
2595 ptrdiff_t *out_stride
)
2597 struct intel_miptree_map
*map
;
2599 assert(mt
->num_samples
<= 1);
2601 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2608 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2609 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2610 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2613 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2614 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2615 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2616 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2617 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2618 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2619 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2620 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2621 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2622 #if defined(USE_SSE41)
2623 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2624 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2627 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2630 *out_ptr
= map
->ptr
;
2631 *out_stride
= map
->stride
;
2633 if (map
->ptr
== NULL
)
2634 intel_miptree_release_map(mt
, level
, slice
);
2638 intel_miptree_unmap(struct brw_context
*brw
,
2639 struct intel_mipmap_tree
*mt
,
2643 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2645 assert(mt
->num_samples
<= 1);
2650 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2651 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2653 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2654 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2655 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2656 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2657 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2658 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2659 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2660 } else if (map
->mt
) {
2661 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2662 #if defined(USE_SSE41)
2663 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2664 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2667 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2670 intel_miptree_release_map(mt
, level
, slice
);