2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
289 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
290 unsigned depth0
, struct intel_mipmap_level
*table
)
292 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
294 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
296 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
297 if (!table
[level
].slice
)
304 for (unsigned level
= first_level
; level
<= last_level
; level
++)
305 free(table
[level
].slice
);
311 * @param for_bo Indicates that the caller is
312 * intel_miptree_create_for_bo(). If true, then do not create
315 static struct intel_mipmap_tree
*
316 intel_miptree_create_layout(struct brw_context
*brw
,
325 uint32_t layout_flags
)
327 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
331 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
332 _mesa_enum_to_string(target
),
333 _mesa_get_format_name(format
),
334 first_level
, last_level
, depth0
, mt
);
336 if (target
== GL_TEXTURE_1D_ARRAY
)
337 assert(height0
== 1);
341 mt
->first_level
= first_level
;
342 mt
->last_level
= last_level
;
343 mt
->logical_width0
= width0
;
344 mt
->logical_height0
= height0
;
345 mt
->logical_depth0
= depth0
;
346 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
347 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
348 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
349 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
350 mt
->aux_state
= NULL
;
351 mt
->cpp
= _mesa_get_format_bytes(format
);
352 mt
->num_samples
= num_samples
;
353 mt
->compressed
= _mesa_is_format_compressed(format
);
354 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
357 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
358 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
360 int depth_multiply
= 1;
361 if (num_samples
> 1) {
362 /* Adjust width/height/depth for MSAA */
363 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
364 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
365 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
366 * "If the surface is multisampled and it is a depth or stencil
367 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
368 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
371 * +----------------------------------------------------------------+
372 * | Num Multisamples | W_l = | H_l = |
373 * +----------------------------------------------------------------+
374 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
375 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
376 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
377 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
378 * +----------------------------------------------------------------+
381 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
382 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
383 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
385 * Another more complicated explanation for these adjustments comes
386 * from the Sandybridge PRM, volume 4, part 1, page 31:
388 * "Any of the other messages (sample*, LOD, load4) used with a
389 * (4x) multisampled surface will in-effect sample a surface with
390 * double the height and width as that indicated in the surface
391 * state. Each pixel position on the original-sized surface is
392 * replaced with a 2x2 of samples with the following arrangement:
397 * Thus, when sampling from a multisampled texture, it behaves as
398 * though the layout in memory for (x,y,sample) is:
400 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
401 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
403 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
404 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
406 * However, the actual layout of multisampled data in memory is:
408 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
409 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
411 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
412 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
414 * This pattern repeats for each 2x2 pixel block.
416 * As a result, when calculating the size of our 4-sample buffer for
417 * an odd width or height, we have to align before scaling up because
418 * sample 3 is in that bottom right 2x2 block.
420 switch (num_samples
) {
422 assert(brw
->gen
>= 8);
423 width0
= ALIGN(width0
, 2) * 2;
424 height0
= ALIGN(height0
, 2);
427 width0
= ALIGN(width0
, 2) * 2;
428 height0
= ALIGN(height0
, 2) * 2;
431 width0
= ALIGN(width0
, 2) * 4;
432 height0
= ALIGN(height0
, 2) * 2;
435 width0
= ALIGN(width0
, 2) * 4;
436 height0
= ALIGN(height0
, 2) * 4;
439 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
442 unreachable("not reached");
445 /* Non-interleaved */
446 depth_multiply
= num_samples
;
447 depth0
*= depth_multiply
;
451 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
457 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
458 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
459 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
460 * used on Gen8 to make it pick a qpitch value which doesn't include space
461 * for the mipmaps. On Gen9 this is not necessary because it will
462 * automatically pick a packed qpitch value whenever mt->first_level ==
464 * TODO: can we use it elsewhere?
465 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
468 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
470 switch (mt
->msaa_layout
) {
471 case INTEL_MSAA_LAYOUT_NONE
:
472 case INTEL_MSAA_LAYOUT_IMS
:
473 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
475 case INTEL_MSAA_LAYOUT_UMS
:
476 case INTEL_MSAA_LAYOUT_CMS
:
477 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
482 if (target
== GL_TEXTURE_CUBE_MAP
)
483 assert(depth0
== 6 * depth_multiply
);
485 mt
->physical_width0
= width0
;
486 mt
->physical_height0
= height0
;
487 mt
->physical_depth0
= depth0
;
489 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
490 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
491 (brw
->must_use_separate_stencil
||
492 (brw
->has_separate_stencil
&&
493 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
494 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
496 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
499 mt
->stencil_mt
= intel_miptree_create(brw
,
510 if (!mt
->stencil_mt
) {
511 intel_miptree_release(&mt
);
514 mt
->stencil_mt
->r8stencil_needs_update
= true;
516 /* Fix up the Z miptree format for how we're splitting out separate
517 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
519 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
522 if (format
== mt
->format
) {
523 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
524 _mesa_get_format_name(mt
->format
));
528 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
529 mt
->array_layout
= GEN6_HIZ_STENCIL
;
532 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
533 * multisampled or have an AUX buffer attached to it.
535 * GEN | MSRT | AUX_CCS_* or AUX_MCS
536 * -------------------------------------------
537 * 9 | HALIGN_16 | HALIGN_16
538 * 8 | HALIGN_ANY | HALIGN_16
542 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
543 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
544 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
545 } else if (brw
->gen
>= 9 && num_samples
> 1) {
546 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
548 const UNUSED
bool is_lossless_compressed_aux
=
549 brw
->gen
>= 9 && num_samples
== 1 &&
550 mt
->format
== MESA_FORMAT_R_UINT32
;
552 /* For now, nothing else has this requirement */
553 assert(is_lossless_compressed_aux
||
554 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
557 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
558 intel_miptree_release(&mt
);
562 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
563 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
570 * Choose an appropriate uncompressed format for a requested
571 * compressed format, if unsupported.
574 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
576 /* No need to lower ETC formats on these platforms,
577 * they are supported natively.
579 if (brw
->gen
>= 8 || brw
->is_baytrail
)
583 case MESA_FORMAT_ETC1_RGB8
:
584 return MESA_FORMAT_R8G8B8X8_UNORM
;
585 case MESA_FORMAT_ETC2_RGB8
:
586 return MESA_FORMAT_R8G8B8X8_UNORM
;
587 case MESA_FORMAT_ETC2_SRGB8
:
588 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
589 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
590 return MESA_FORMAT_B8G8R8A8_SRGB
;
591 case MESA_FORMAT_ETC2_RGBA8_EAC
:
592 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
593 return MESA_FORMAT_R8G8B8A8_UNORM
;
594 case MESA_FORMAT_ETC2_R11_EAC
:
595 return MESA_FORMAT_R_UNORM16
;
596 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
597 return MESA_FORMAT_R_SNORM16
;
598 case MESA_FORMAT_ETC2_RG11_EAC
:
599 return MESA_FORMAT_R16G16_UNORM
;
600 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
601 return MESA_FORMAT_R16G16_SNORM
;
603 /* Non ETC1 / ETC2 format */
608 /** \brief Assert that the level and layer are valid for the miptree. */
610 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
618 assert(level
>= mt
->first_level
);
619 assert(level
<= mt
->last_level
);
621 if (mt
->surf
.size
> 0)
622 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
623 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
624 mt
->surf
.phys_level0_sa
.array_len
));
626 assert(layer
< mt
->level
[level
].depth
);
629 static enum isl_aux_state
**
630 create_aux_state_map(struct intel_mipmap_tree
*mt
,
631 enum isl_aux_state initial
)
633 const uint32_t levels
= mt
->last_level
+ 1;
635 uint32_t total_slices
= 0;
636 for (uint32_t level
= 0; level
< levels
; level
++)
637 total_slices
+= mt
->level
[level
].depth
;
639 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
641 /* We're going to allocate a single chunk of data for both the per-level
642 * reference array and the arrays of aux_state. This makes cleanup
643 * significantly easier.
645 const size_t total_size
= per_level_array_size
+
646 total_slices
* sizeof(enum isl_aux_state
);
647 void *data
= malloc(total_size
);
651 enum isl_aux_state
**per_level_arr
= data
;
652 enum isl_aux_state
*s
= data
+ per_level_array_size
;
653 for (uint32_t level
= 0; level
< levels
; level
++) {
654 per_level_arr
[level
] = s
;
655 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
658 assert((void *)s
== data
+ total_size
);
660 return per_level_arr
;
664 free_aux_state_map(enum isl_aux_state
**state
)
669 static struct intel_mipmap_tree
*
670 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
671 unsigned first_level
, unsigned last_level
,
672 unsigned width0
, unsigned height0
, unsigned depth0
,
673 unsigned num_samples
, enum isl_tiling isl_tiling
,
674 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
677 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
681 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
687 if (target
== GL_TEXTURE_CUBE_MAP
||
688 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
689 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
691 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
693 _mesa_enum_to_string(target
),
694 _mesa_get_format_name(format
),
695 num_samples
, width0
, height0
, depth0
,
696 first_level
, last_level
, mt
);
698 struct isl_surf_init_info init_info
= {
699 .dim
= get_isl_surf_dim(target
),
700 .format
= translate_tex_format(brw
, format
, false),
703 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
704 .levels
= last_level
- first_level
+ 1,
705 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
706 .samples
= MAX2(num_samples
, 1),
707 .usage
= isl_usage_flags
,
708 .tiling_flags
= 1u << isl_tiling
711 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
714 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
717 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
719 isl_tiling_to_bufmgr_tiling(isl_tiling
),
720 mt
->surf
.row_pitch
, alloc_flags
);
727 mt
->first_level
= first_level
;
728 mt
->last_level
= last_level
;
732 mt
->aux_state
= NULL
;
737 intel_miptree_release(&mt
);
741 static struct intel_mipmap_tree
*
742 miptree_create(struct brw_context
*brw
,
751 uint32_t layout_flags
)
753 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
754 return make_surface(brw
, target
, format
, first_level
, last_level
,
755 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
756 ISL_SURF_USAGE_STENCIL_BIT
|
757 ISL_SURF_USAGE_TEXTURE_BIT
,
758 BO_ALLOC_FOR_RENDER
, NULL
);
760 struct intel_mipmap_tree
*mt
;
761 mesa_format tex_format
= format
;
762 mesa_format etc_format
= MESA_FORMAT_NONE
;
763 uint32_t alloc_flags
= 0;
765 format
= intel_lower_compressed_format(brw
, format
);
767 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
769 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
770 mt
= intel_miptree_create_layout(brw
, target
, format
,
771 first_level
, last_level
, width0
,
772 height0
, depth0
, num_samples
,
777 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
778 mt
->tiling
= I915_TILING_Y
;
780 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
781 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
783 mt
->etc_format
= etc_format
;
785 if (format
== MESA_FORMAT_S_UINT8
) {
786 /* Align to size of W tile, 64x64. */
787 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
788 ALIGN(mt
->total_width
, 64),
789 ALIGN(mt
->total_height
, 64),
790 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
793 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
794 mt
->total_width
, mt
->total_height
,
795 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
799 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
800 mt
->bo
->cache_coherent
= false;
805 struct intel_mipmap_tree
*
806 intel_miptree_create(struct brw_context
*brw
,
815 uint32_t layout_flags
)
817 struct intel_mipmap_tree
*mt
= miptree_create(
819 first_level
, last_level
,
820 width0
, height0
, depth0
, num_samples
,
823 /* If the BO is too large to fit in the aperture, we need to use the
824 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
825 * handle Y-tiling, so we need to fall back to X.
827 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
828 mt
->tiling
== I915_TILING_Y
) {
829 const uint32_t alloc_flags
=
830 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
831 BO_ALLOC_FOR_RENDER
: 0;
832 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
833 mt
->total_width
, mt
->total_height
);
835 mt
->tiling
= I915_TILING_X
;
836 brw_bo_unreference(mt
->bo
);
837 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
838 mt
->total_width
, mt
->total_height
, mt
->cpp
,
839 mt
->tiling
, &mt
->pitch
, alloc_flags
);
845 intel_miptree_release(&mt
);
850 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
851 assert(mt
->num_samples
> 1);
852 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
853 intel_miptree_release(&mt
);
858 /* If this miptree is capable of supporting fast color clears, set
859 * fast_clear_state appropriately to ensure that fast clears will occur.
860 * Allocation of the MCS miptree will be deferred until the first fast
861 * clear actually occurs or when compressed single sampled buffer is
862 * written by the GPU for the first time.
864 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
865 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
866 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
867 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
869 /* On Gen9+ clients are not currently capable of consuming compressed
870 * single-sampled buffers. Disabling compression allows us to skip
873 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
874 const bool is_lossless_compressed
=
875 unlikely(!lossless_compression_disabled
) &&
876 brw
->gen
>= 9 && !mt
->is_scanout
&&
877 intel_miptree_supports_lossless_compressed(brw
, mt
);
879 if (is_lossless_compressed
) {
880 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
887 struct intel_mipmap_tree
*
888 intel_miptree_create_for_bo(struct brw_context
*brw
,
896 uint32_t layout_flags
)
898 struct intel_mipmap_tree
*mt
;
899 uint32_t tiling
, swizzle
;
902 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
904 /* Nothing will be able to use this miptree with the BO if the offset isn't
907 if (tiling
!= I915_TILING_NONE
)
908 assert(offset
% 4096 == 0);
910 /* miptrees can't handle negative pitch. If you need flipping of images,
911 * that's outside of the scope of the mt.
915 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
917 /* The BO already has a tiling format and we shouldn't confuse the lower
918 * layers by making it try to find a tiling format again.
920 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
921 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
923 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
924 mt
= intel_miptree_create_layout(brw
, target
, format
,
926 width
, height
, depth
, 0,
931 brw_bo_reference(bo
);
941 * For a singlesample renderbuffer, this simply wraps the given BO with a
944 * For a multisample renderbuffer, this wraps the window system's
945 * (singlesample) BO with a singlesample miptree attached to the
946 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
947 * that will contain the actual rendering (which is lazily resolved to
948 * irb->singlesample_mt).
951 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
952 struct intel_renderbuffer
*irb
,
954 uint32_t width
, uint32_t height
,
957 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
958 struct intel_mipmap_tree
*multisample_mt
= NULL
;
959 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
960 mesa_format format
= rb
->Format
;
961 int num_samples
= rb
->NumSamples
;
963 /* Only the front and back buffers, which are color buffers, are allocated
964 * through the image loader.
966 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
967 _mesa_get_format_base_format(format
) == GL_RGBA
);
969 singlesample_mt
= intel_miptree_create_for_bo(intel
,
977 MIPTREE_LAYOUT_FOR_SCANOUT
);
978 if (!singlesample_mt
)
981 /* If this miptree is capable of supporting fast color clears, set
982 * mcs_state appropriately to ensure that fast clears will occur.
983 * Allocation of the MCS miptree will be deferred until the first fast
984 * clear actually occurs.
986 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
987 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
988 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
991 if (num_samples
== 0) {
992 intel_miptree_release(&irb
->mt
);
993 irb
->mt
= singlesample_mt
;
995 assert(!irb
->singlesample_mt
);
997 intel_miptree_release(&irb
->singlesample_mt
);
998 irb
->singlesample_mt
= singlesample_mt
;
1001 irb
->mt
->logical_width0
!= width
||
1002 irb
->mt
->logical_height0
!= height
) {
1003 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1008 if (!multisample_mt
)
1011 irb
->need_downsample
= false;
1012 intel_miptree_release(&irb
->mt
);
1013 irb
->mt
= multisample_mt
;
1019 intel_miptree_release(&irb
->singlesample_mt
);
1020 intel_miptree_release(&irb
->mt
);
1024 struct intel_mipmap_tree
*
1025 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1029 uint32_t num_samples
)
1031 struct intel_mipmap_tree
*mt
;
1034 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1035 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1036 MIPTREE_LAYOUT_TILING_ANY
|
1037 MIPTREE_LAYOUT_FOR_SCANOUT
;
1039 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1040 width
, height
, depth
, num_samples
,
1045 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
1046 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1054 intel_miptree_release(&mt
);
1059 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1060 struct intel_mipmap_tree
*src
)
1065 intel_miptree_release(dst
);
1069 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1076 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
1078 if (hiz_buf
== NULL
)
1082 intel_miptree_release(&hiz_buf
->mt
);
1084 brw_bo_unreference(hiz_buf
->aux_base
.bo
);
1090 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1095 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1096 if (--(*mt
)->refcount
<= 0) {
1099 DBG("%s deleting %p\n", __func__
, *mt
);
1101 brw_bo_unreference((*mt
)->bo
);
1102 intel_miptree_release(&(*mt
)->stencil_mt
);
1103 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1104 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
1105 if ((*mt
)->mcs_buf
) {
1106 brw_bo_unreference((*mt
)->mcs_buf
->bo
);
1107 free((*mt
)->mcs_buf
);
1109 free_aux_state_map((*mt
)->aux_state
);
1111 intel_miptree_release(&(*mt
)->plane
[0]);
1112 intel_miptree_release(&(*mt
)->plane
[1]);
1114 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1115 free((*mt
)->level
[i
].slice
);
1125 intel_get_image_dims(struct gl_texture_image
*image
,
1126 int *width
, int *height
, int *depth
)
1128 switch (image
->TexObject
->Target
) {
1129 case GL_TEXTURE_1D_ARRAY
:
1130 /* For a 1D Array texture the OpenGL API will treat the image height as
1131 * the number of array slices. For Intel hardware, we treat the 1D array
1132 * as a 2D Array with a height of 1. So, here we want to swap image
1135 assert(image
->Depth
== 1);
1136 *width
= image
->Width
;
1138 *depth
= image
->Height
;
1140 case GL_TEXTURE_CUBE_MAP
:
1141 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1142 * though we really have 6 slices.
1144 assert(image
->Depth
== 1);
1145 *width
= image
->Width
;
1146 *height
= image
->Height
;
1150 *width
= image
->Width
;
1151 *height
= image
->Height
;
1152 *depth
= image
->Depth
;
1158 * Can the image be pulled into a unified mipmap tree? This mirrors
1159 * the completeness test in a lot of ways.
1161 * Not sure whether I want to pass gl_texture_image here.
1164 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1165 struct gl_texture_image
*image
)
1167 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1168 GLuint level
= intelImage
->base
.Base
.Level
;
1169 int width
, height
, depth
;
1171 /* glTexImage* choose the texture object based on the target passed in, and
1172 * objects can't change targets over their lifetimes, so this should be
1175 assert(image
->TexObject
->Target
== mt
->target
);
1177 mesa_format mt_format
= mt
->format
;
1178 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1179 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1180 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1181 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1182 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1183 mt_format
= mt
->etc_format
;
1185 if (image
->TexFormat
!= mt_format
)
1188 intel_get_image_dims(image
, &width
, &height
, &depth
);
1190 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1193 if (mt
->surf
.size
> 0) {
1194 if (level
>= mt
->surf
.levels
)
1197 const unsigned level_depth
=
1198 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1199 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1200 mt
->surf
.logical_level0_px
.array_len
;
1202 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1203 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1204 depth
== level_depth
&&
1205 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1208 int level_depth
= mt
->level
[level
].depth
;
1209 if (mt
->num_samples
> 1) {
1210 switch (mt
->msaa_layout
) {
1211 case INTEL_MSAA_LAYOUT_NONE
:
1212 case INTEL_MSAA_LAYOUT_IMS
:
1214 case INTEL_MSAA_LAYOUT_UMS
:
1215 case INTEL_MSAA_LAYOUT_CMS
:
1216 level_depth
/= mt
->num_samples
;
1221 /* Test image dimensions against the base level image adjusted for
1222 * minification. This will also catch images not present in the
1223 * tree, changed targets, etc.
1225 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1226 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1227 depth
!= level_depth
) {
1231 if (image
->NumSamples
!= mt
->num_samples
)
1239 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1241 GLuint x
, GLuint y
, GLuint d
)
1243 mt
->level
[level
].depth
= d
;
1244 mt
->level
[level
].level_x
= x
;
1245 mt
->level
[level
].level_y
= y
;
1247 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1250 assert(mt
->level
[level
].slice
);
1252 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1253 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1258 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1259 GLuint level
, GLuint img
,
1262 if (img
== 0 && level
== 0)
1263 assert(x
== 0 && y
== 0);
1265 assert(img
< mt
->level
[level
].depth
);
1267 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1268 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1270 DBG("%s level %d img %d pos %d,%d\n",
1271 __func__
, level
, img
,
1272 mt
->level
[level
].slice
[img
].x_offset
,
1273 mt
->level
[level
].slice
[img
].y_offset
);
1277 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1278 GLuint level
, GLuint slice
,
1279 GLuint
*x
, GLuint
*y
)
1281 if (mt
->surf
.size
> 0) {
1282 uint32_t x_offset_sa
, y_offset_sa
;
1284 /* Given level is relative to level zero while the miptree may be
1285 * represent just a subset of all levels starting from 'first_level'.
1287 assert(level
>= mt
->first_level
);
1288 level
-= mt
->first_level
;
1290 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1291 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1292 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1293 &x_offset_sa
, &y_offset_sa
);
1300 assert(slice
< mt
->level
[level
].depth
);
1302 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1303 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1308 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1309 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1310 * and tile_h is set to 1.
1313 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1314 uint32_t *tile_w
, uint32_t *tile_h
)
1325 case I915_TILING_NONE
:
1330 unreachable("not reached");
1336 * This function computes masks that may be used to select the bits of the X
1337 * and Y coordinates that indicate the offset within a tile. If the BO is
1338 * untiled, the masks are set to 0.
1341 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1342 uint32_t *mask_x
, uint32_t *mask_y
)
1344 uint32_t tile_w_bytes
, tile_h
;
1346 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1348 *mask_x
= tile_w_bytes
/ cpp
- 1;
1349 *mask_y
= tile_h
- 1;
1353 * Compute the offset (in bytes) from the start of the BO to the given x
1354 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1355 * multiples of the tile size.
1358 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1359 uint32_t x
, uint32_t y
)
1362 uint32_t pitch
= mt
->pitch
;
1363 uint32_t tiling
= mt
->tiling
;
1367 unreachable("not reached");
1368 case I915_TILING_NONE
:
1369 return y
* pitch
+ x
* cpp
;
1371 assert((x
% (512 / cpp
)) == 0);
1372 assert((y
% 8) == 0);
1373 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1375 assert((x
% (128 / cpp
)) == 0);
1376 assert((y
% 32) == 0);
1377 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1382 * Rendering with tiled buffers requires that the base address of the buffer
1383 * be aligned to a page boundary. For renderbuffers, and sometimes with
1384 * textures, we may want the surface to point at a texture image level that
1385 * isn't at a page boundary.
1387 * This function returns an appropriately-aligned base offset
1388 * according to the tiling restrictions, plus any required x/y offset
1392 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1393 GLuint level
, GLuint slice
,
1398 uint32_t mask_x
, mask_y
;
1400 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1401 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1403 *tile_x
= x
& mask_x
;
1404 *tile_y
= y
& mask_y
;
1406 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1410 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1411 struct intel_mipmap_tree
*src_mt
,
1412 unsigned src_level
, unsigned src_layer
,
1413 struct intel_mipmap_tree
*dst_mt
,
1414 unsigned dst_level
, unsigned dst_layer
,
1415 unsigned width
, unsigned height
)
1418 ptrdiff_t src_stride
, dst_stride
;
1419 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1420 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1422 intel_miptree_map(brw
, src_mt
,
1423 src_level
, src_layer
,
1426 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1429 intel_miptree_map(brw
, dst_mt
,
1430 dst_level
, dst_layer
,
1433 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1437 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1438 _mesa_get_format_name(src_mt
->format
),
1439 src_mt
, src
, src_stride
,
1440 _mesa_get_format_name(dst_mt
->format
),
1441 dst_mt
, dst
, dst_stride
,
1444 int row_size
= cpp
* width
;
1445 if (src_stride
== row_size
&&
1446 dst_stride
== row_size
) {
1447 memcpy(dst
, src
, row_size
* height
);
1449 for (int i
= 0; i
< height
; i
++) {
1450 memcpy(dst
, src
, row_size
);
1456 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1457 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1459 /* Don't forget to copy the stencil data over, too. We could have skipped
1460 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1461 * shuffling the two data sources in/out of temporary storage instead of
1462 * the direct mapping we get this way.
1464 if (dst_mt
->stencil_mt
) {
1465 assert(src_mt
->stencil_mt
);
1466 intel_miptree_copy_slice_sw(brw
,
1467 src_mt
->stencil_mt
, src_level
, src_layer
,
1468 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1474 intel_miptree_copy_slice(struct brw_context
*brw
,
1475 struct intel_mipmap_tree
*src_mt
,
1476 unsigned src_level
, unsigned src_layer
,
1477 struct intel_mipmap_tree
*dst_mt
,
1478 unsigned dst_level
, unsigned dst_layer
)
1481 mesa_format format
= src_mt
->format
;
1482 uint32_t width
, height
;
1484 if (src_mt
->surf
.size
> 0) {
1485 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1486 src_level
- src_mt
->first_level
);
1487 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1488 src_level
- src_mt
->first_level
);
1490 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1491 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1492 src_level
- src_mt
->first_level
));
1494 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1496 width
= minify(src_mt
->physical_width0
,
1497 src_level
- src_mt
->first_level
);
1498 height
= minify(src_mt
->physical_height0
,
1499 src_level
- src_mt
->first_level
);
1500 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1503 assert(src_mt
->format
== dst_mt
->format
);
1505 if (dst_mt
->compressed
) {
1507 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1508 height
= ALIGN_NPOT(height
, j
) / j
;
1509 width
= ALIGN_NPOT(width
, i
) / i
;
1512 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1513 * below won't apply since we can't do the depth's Y tiling or the
1514 * stencil's W tiling in the blitter.
1516 if (src_mt
->stencil_mt
) {
1517 intel_miptree_copy_slice_sw(brw
,
1518 src_mt
, src_level
, src_layer
,
1519 dst_mt
, dst_level
, dst_layer
,
1524 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1525 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1527 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1530 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1531 _mesa_get_format_name(src_mt
->format
),
1532 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1533 _mesa_get_format_name(dst_mt
->format
),
1534 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1537 if (!intel_miptree_blit(brw
,
1538 src_mt
, src_level
, src_layer
, 0, 0, false,
1539 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1540 width
, height
, GL_COPY
)) {
1541 perf_debug("miptree validate blit for %s failed\n",
1542 _mesa_get_format_name(format
));
1544 intel_miptree_copy_slice_sw(brw
,
1545 src_mt
, src_level
, src_layer
,
1546 dst_mt
, dst_level
, dst_layer
,
1552 * Copies the image's current data to the given miptree, and associates that
1553 * miptree with the image.
1555 * If \c invalidate is true, then the actual image data does not need to be
1556 * copied, but the image still needs to be associated to the new miptree (this
1557 * is set to true if we're about to clear the image).
1560 intel_miptree_copy_teximage(struct brw_context
*brw
,
1561 struct intel_texture_image
*intelImage
,
1562 struct intel_mipmap_tree
*dst_mt
,
1565 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1566 struct intel_texture_object
*intel_obj
=
1567 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1568 int level
= intelImage
->base
.Base
.Level
;
1569 const unsigned face
= intelImage
->base
.Base
.Face
;
1570 unsigned start_layer
, end_layer
;
1572 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1574 assert(intelImage
->base
.Base
.Height
);
1576 end_layer
= intelImage
->base
.Base
.Height
- 1;
1577 } else if (face
> 0) {
1581 assert(intelImage
->base
.Base
.Depth
);
1583 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1587 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1588 intel_miptree_copy_slice(brw
,
1594 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1595 intel_obj
->needs_validate
= true;
1599 intel_miptree_init_mcs(struct brw_context
*brw
,
1600 struct intel_mipmap_tree
*mt
,
1603 assert(mt
->mcs_buf
!= NULL
);
1605 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1607 * When MCS buffer is enabled and bound to MSRT, it is required that it
1608 * is cleared prior to any rendering.
1610 * Since we don't use the MCS buffer for any purpose other than rendering,
1611 * it makes sense to just clear it immediately upon allocation.
1613 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1615 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1616 if (unlikely(map
== NULL
)) {
1617 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1618 brw_bo_unreference(mt
->mcs_buf
->bo
);
1623 memset(data
, init_value
, mt
->mcs_buf
->size
);
1624 brw_bo_unmap(mt
->mcs_buf
->bo
);
1627 static struct intel_miptree_aux_buffer
*
1628 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1629 struct intel_mipmap_tree
*mt
,
1632 unsigned mcs_height
,
1633 uint32_t layout_flags
)
1635 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1636 struct intel_mipmap_tree
*temp_mt
;
1641 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1643 * "The MCS surface must be stored as Tile Y."
1645 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1646 temp_mt
= miptree_create(brw
,
1654 0 /* num_samples */,
1661 buf
->bo
= temp_mt
->bo
;
1662 buf
->offset
= temp_mt
->offset
;
1663 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1664 buf
->pitch
= temp_mt
->pitch
;
1665 buf
->qpitch
= temp_mt
->qpitch
;
1667 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1668 * structure should go away. We use miptree create simply as a means to make
1669 * sure all the constraints for the buffer are satisfied.
1671 brw_bo_reference(temp_mt
->bo
);
1672 intel_miptree_release(&temp_mt
);
1678 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1679 struct intel_mipmap_tree
*mt
,
1682 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1683 assert(mt
->mcs_buf
== NULL
);
1684 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1686 /* Choose the correct format for the MCS buffer. All that really matters
1687 * is that we allocate the right buffer size, since we'll always be
1688 * accessing this miptree using MCS-specific hardware mechanisms, which
1689 * infer the correct format based on num_samples.
1692 switch (num_samples
) {
1695 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1698 format
= MESA_FORMAT_R_UNORM8
;
1701 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1702 * for each sample, plus 8 padding bits).
1704 format
= MESA_FORMAT_R_UINT32
;
1707 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1710 format
= MESA_FORMAT_RG_UINT32
;
1713 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1716 /* Multisampled miptrees are only supported for single level. */
1717 assert(mt
->first_level
== 0);
1718 enum isl_aux_state
**aux_state
=
1719 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1724 intel_mcs_miptree_buf_create(brw
, mt
,
1727 mt
->logical_height0
,
1728 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1734 mt
->aux_state
= aux_state
;
1736 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1742 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1743 struct intel_mipmap_tree
*mt
,
1744 bool is_lossless_compressed
)
1746 assert(mt
->mcs_buf
== NULL
);
1747 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1749 struct isl_surf temp_main_surf
;
1750 struct isl_surf temp_ccs_surf
;
1752 /* Create first an ISL presentation for the main color surface and let ISL
1753 * calculate equivalent CCS surface against it.
1755 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1756 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1759 assert(temp_ccs_surf
.size
&&
1760 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1762 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1766 enum isl_aux_state
**aux_state
=
1767 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1773 buf
->size
= temp_ccs_surf
.size
;
1774 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1775 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1777 /* In case of compression mcs buffer needs to be initialised requiring the
1778 * buffer to be immediately mapped to cpu space for writing. Therefore do
1779 * not use the gpu access flag which can cause an unnecessary delay if the
1780 * backing pages happened to be just used by the GPU.
1782 const uint32_t alloc_flags
=
1783 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1785 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree", buf
->size
,
1786 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1794 mt
->aux_state
= aux_state
;
1796 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1797 * used for lossless compression which requires similar initialisation
1798 * as multi-sample compression.
1800 if (is_lossless_compressed
) {
1801 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1802 * resolve. Initialize it accordingly in case the first renderer is
1803 * cpu (or other none compression aware party).
1805 * This is also explicitly stated in the spec (MCS Buffer for Render
1807 * "If Software wants to enable Color Compression without Fast clear,
1808 * Software needs to initialize MCS with zeros."
1810 intel_miptree_init_mcs(brw
, mt
, 0);
1811 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1818 * Helper for intel_miptree_alloc_hiz() that sets
1819 * \c mt->level[level].has_hiz. Return true if and only if
1820 * \c has_hiz was set.
1823 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1824 struct intel_mipmap_tree
*mt
,
1827 assert(mt
->hiz_buf
);
1829 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1830 uint32_t width
= minify(mt
->physical_width0
, level
);
1831 uint32_t height
= minify(mt
->physical_height0
, level
);
1833 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1834 * and the height is 4 aligned. This allows our HiZ support
1835 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1836 * we can grow the width & height to allow the HiZ op to
1837 * force the proper size alignments.
1839 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1840 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1845 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1846 mt
->level
[level
].has_hiz
= true;
1852 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1853 * buffer dimensions and allocates a bo for the hiz buffer.
1855 static struct intel_miptree_hiz_buffer
*
1856 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1857 struct intel_mipmap_tree
*mt
)
1859 unsigned z_width
= mt
->logical_width0
;
1860 unsigned z_height
= mt
->logical_height0
;
1861 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1862 unsigned hz_width
, hz_height
;
1863 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1868 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1869 * adjustments required for Z_Height and Z_Width based on multisampling.
1871 switch (mt
->num_samples
) {
1885 unreachable("unsupported sample count");
1888 const unsigned vertical_align
= 8; /* 'j' in the docs */
1889 const unsigned H0
= z_height
;
1890 const unsigned h0
= ALIGN(H0
, vertical_align
);
1891 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1892 const unsigned Z0
= z_depth
;
1894 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1895 hz_width
= ALIGN(z_width
, 16);
1897 if (mt
->target
== GL_TEXTURE_3D
) {
1901 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1902 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1903 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1904 hz_height
+= h_i
* Z_i
;
1905 H_i
= minify(H_i
, 1);
1906 Z_i
= minify(Z_i
, 1);
1909 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1911 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1913 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1914 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1915 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1918 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
1919 hz_width
, hz_height
, 1,
1920 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1921 BO_ALLOC_FOR_RENDER
);
1922 if (!buf
->aux_base
.bo
) {
1927 buf
->aux_base
.size
= hz_width
* hz_height
;
1934 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1935 * buffer dimensions and allocates a bo for the hiz buffer.
1937 static struct intel_miptree_hiz_buffer
*
1938 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1939 struct intel_mipmap_tree
*mt
)
1941 unsigned z_width
= mt
->logical_width0
;
1942 unsigned z_height
= mt
->logical_height0
;
1943 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1944 unsigned hz_width
, hz_height
;
1945 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1950 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1951 * adjustments required for Z_Height and Z_Width based on multisampling.
1954 switch (mt
->num_samples
) {
1968 unreachable("unsupported sample count");
1972 const unsigned vertical_align
= 8; /* 'j' in the docs */
1973 const unsigned H0
= z_height
;
1974 const unsigned h0
= ALIGN(H0
, vertical_align
);
1975 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1976 const unsigned Z0
= z_depth
;
1978 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1979 hz_width
= ALIGN(z_width
, 16);
1983 unsigned sum_h_i
= 0;
1984 unsigned hz_height_3d_sum
= 0;
1985 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1986 unsigned i
= level
- mt
->first_level
;
1987 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1988 /* sum(i=2 to m; h_i) */
1992 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1993 hz_height_3d_sum
+= h_i
* Z_i
;
1994 H_i
= minify(H_i
, 1);
1995 Z_i
= minify(Z_i
, 1);
1997 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1998 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
2000 if (mt
->target
== GL_TEXTURE_3D
) {
2001 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
2002 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
2004 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
2005 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
2008 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
2009 hz_width
, hz_height
, 1,
2010 I915_TILING_Y
, &buf
->aux_base
.pitch
,
2011 BO_ALLOC_FOR_RENDER
);
2012 if (!buf
->aux_base
.bo
) {
2017 buf
->aux_base
.size
= hz_width
* hz_height
;
2023 static struct intel_miptree_hiz_buffer
*
2024 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
2025 struct intel_mipmap_tree
*mt
)
2027 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
2028 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
2031 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
2036 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
2037 buf
->mt
= intel_miptree_create(brw
,
2043 mt
->logical_height0
,
2052 buf
->aux_base
.bo
= buf
->mt
->bo
;
2053 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
2054 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
2055 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
* 2;
2061 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
2062 struct intel_mipmap_tree
*mt
)
2067 if (mt
->hiz_buf
!= NULL
)
2070 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
2073 switch (mt
->format
) {
2074 case MESA_FORMAT_Z_FLOAT32
:
2075 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
2076 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
2077 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
2078 case MESA_FORMAT_Z_UNORM16
:
2086 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2087 struct intel_mipmap_tree
*mt
)
2089 assert(mt
->hiz_buf
== NULL
);
2090 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
2092 enum isl_aux_state
**aux_state
=
2093 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
2097 if (brw
->gen
== 7) {
2098 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
2099 } else if (brw
->gen
>= 8) {
2100 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
2102 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
2110 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2111 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2113 mt
->aux_state
= aux_state
;
2119 * Can the miptree sample using the hiz buffer?
2122 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2123 struct intel_mipmap_tree
*mt
)
2125 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2126 * so keep things conservative for now and never enable it unless we're SKL+.
2136 /* It seems the hardware won't fallback to the depth buffer if some of the
2137 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2138 * of the texture to be HiZ enabled.
2140 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2141 if (!intel_miptree_level_has_hiz(mt
, level
))
2145 /* If compressed multisampling is enabled, then we use it for the auxiliary
2148 * From the BDW PRM (Volume 2d: Command Reference: Structures
2149 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2151 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2152 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2154 * There is no such blurb for 1D textures, but there is sufficient evidence
2155 * that this is broken on SKL+.
2157 return (mt
->num_samples
<= 1 &&
2158 mt
->target
!= GL_TEXTURE_3D
&&
2159 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2163 * Does the miptree slice have hiz enabled?
2166 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2168 intel_miptree_check_level_layer(mt
, level
, 0);
2169 return mt
->level
[level
].has_hiz
;
2173 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2174 unsigned start_level
, unsigned num_levels
,
2175 unsigned start_layer
, unsigned num_layers
)
2177 assert(_mesa_is_format_color_format(mt
->format
));
2182 /* Clamp the level range to fit the miptree */
2183 assert(start_level
+ num_levels
>= start_level
);
2184 const uint32_t last_level
=
2185 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2186 start_level
= MAX2(mt
->first_level
, start_level
);
2187 num_levels
= last_level
- start_level
+ 1;
2189 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2190 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2191 for (unsigned a
= 0; a
< level_layers
; a
++) {
2192 enum isl_aux_state aux_state
=
2193 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2194 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2195 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2204 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2205 const struct intel_mipmap_tree
*mt
,
2206 unsigned level
, unsigned layer
)
2209 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2212 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2213 assert(brw
->gen
>= 8 ||
2214 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2216 /* Compression of arrayed msaa surfaces is supported. */
2217 if (mt
->num_samples
> 1)
2220 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2221 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2227 static enum blorp_fast_clear_op
2228 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2229 bool ccs_supported
, bool fast_clear_supported
)
2231 assert(ccs_supported
== fast_clear_supported
);
2233 switch (aux_state
) {
2234 case ISL_AUX_STATE_CLEAR
:
2235 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2237 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2239 return BLORP_FAST_CLEAR_OP_NONE
;
2241 case ISL_AUX_STATE_PASS_THROUGH
:
2242 return BLORP_FAST_CLEAR_OP_NONE
;
2244 case ISL_AUX_STATE_RESOLVED
:
2245 case ISL_AUX_STATE_AUX_INVALID
:
2246 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2250 unreachable("Invalid aux state for CCS_D");
2253 static enum blorp_fast_clear_op
2254 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2255 bool ccs_supported
, bool fast_clear_supported
)
2257 switch (aux_state
) {
2258 case ISL_AUX_STATE_CLEAR
:
2259 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2261 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2262 else if (!fast_clear_supported
)
2263 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2265 return BLORP_FAST_CLEAR_OP_NONE
;
2267 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2269 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2271 return BLORP_FAST_CLEAR_OP_NONE
;
2273 case ISL_AUX_STATE_PASS_THROUGH
:
2274 return BLORP_FAST_CLEAR_OP_NONE
;
2276 case ISL_AUX_STATE_RESOLVED
:
2277 case ISL_AUX_STATE_AUX_INVALID
:
2281 unreachable("Invalid aux state for CCS_E");
2285 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2286 struct intel_mipmap_tree
*mt
,
2287 uint32_t level
, uint32_t layer
,
2289 bool fast_clear_supported
)
2291 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2293 enum blorp_fast_clear_op resolve_op
;
2294 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2295 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2296 fast_clear_supported
);
2298 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2299 fast_clear_supported
);
2302 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2303 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2304 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2306 switch (resolve_op
) {
2307 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2308 /* The CCS full resolve operation destroys the CCS and sets it to the
2309 * pass-through state. (You can also think of this as being both a
2310 * resolve and an ambiguate in one operation.)
2312 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2313 ISL_AUX_STATE_PASS_THROUGH
);
2316 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2317 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2318 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2322 unreachable("Invalid resolve op");
2328 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2329 struct intel_mipmap_tree
*mt
,
2330 uint32_t level
, uint32_t layer
,
2331 bool written_with_ccs
)
2333 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2335 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2336 switch (aux_state
) {
2337 case ISL_AUX_STATE_CLEAR
:
2338 assert(written_with_ccs
);
2339 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2340 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2343 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2344 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2345 assert(written_with_ccs
);
2346 break; /* Nothing to do */
2348 case ISL_AUX_STATE_PASS_THROUGH
:
2349 if (written_with_ccs
) {
2350 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2351 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2357 case ISL_AUX_STATE_RESOLVED
:
2358 case ISL_AUX_STATE_AUX_INVALID
:
2359 unreachable("Invalid aux state for CCS_E");
2362 /* CCS_D is a bit simpler */
2363 switch (aux_state
) {
2364 case ISL_AUX_STATE_CLEAR
:
2365 assert(written_with_ccs
);
2366 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2367 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2370 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2371 assert(written_with_ccs
);
2372 break; /* Nothing to do */
2374 case ISL_AUX_STATE_PASS_THROUGH
:
2378 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2379 case ISL_AUX_STATE_RESOLVED
:
2380 case ISL_AUX_STATE_AUX_INVALID
:
2381 unreachable("Invalid aux state for CCS_D");
2387 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2388 struct intel_mipmap_tree
*mt
,
2389 uint32_t level
, uint32_t layer
,
2390 bool written_with_aux
)
2392 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2393 case ISL_AUX_STATE_CLEAR
:
2394 assert(written_with_aux
);
2395 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2396 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2399 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2400 assert(written_with_aux
);
2401 break; /* Nothing to do */
2403 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2404 case ISL_AUX_STATE_RESOLVED
:
2405 case ISL_AUX_STATE_PASS_THROUGH
:
2406 case ISL_AUX_STATE_AUX_INVALID
:
2407 unreachable("Invalid aux state for MCS");
2412 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2413 struct intel_mipmap_tree
*mt
,
2414 uint32_t level
, uint32_t layer
,
2415 bool hiz_supported
, bool fast_clear_supported
)
2417 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2418 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2419 case ISL_AUX_STATE_CLEAR
:
2420 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2421 if (!hiz_supported
|| !fast_clear_supported
)
2422 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2425 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2427 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2430 case ISL_AUX_STATE_PASS_THROUGH
:
2431 case ISL_AUX_STATE_RESOLVED
:
2434 case ISL_AUX_STATE_AUX_INVALID
:
2436 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2440 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2441 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2444 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2445 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2446 ISL_AUX_STATE_RESOLVED
);
2449 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2450 /* The HiZ resolve operation is actually an ambiguate */
2451 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2452 ISL_AUX_STATE_PASS_THROUGH
);
2456 unreachable("Invalid HiZ op");
2462 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2463 struct intel_mipmap_tree
*mt
,
2464 uint32_t level
, uint32_t layer
,
2465 bool written_with_hiz
)
2467 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2468 case ISL_AUX_STATE_CLEAR
:
2469 assert(written_with_hiz
);
2470 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2471 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2474 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2475 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2476 assert(written_with_hiz
);
2477 break; /* Nothing to do */
2479 case ISL_AUX_STATE_RESOLVED
:
2480 if (written_with_hiz
) {
2481 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2482 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2484 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2485 ISL_AUX_STATE_AUX_INVALID
);
2489 case ISL_AUX_STATE_PASS_THROUGH
:
2490 if (written_with_hiz
) {
2491 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2492 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2496 case ISL_AUX_STATE_AUX_INVALID
:
2497 assert(!written_with_hiz
);
2502 static inline uint32_t
2503 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2504 uint32_t start_level
, uint32_t num_levels
)
2506 assert(start_level
>= mt
->first_level
);
2507 assert(start_level
<= mt
->last_level
);
2509 if (num_levels
== INTEL_REMAINING_LAYERS
)
2510 num_levels
= mt
->last_level
- start_level
+ 1;
2511 /* Check for overflow */
2512 assert(start_level
+ num_levels
>= start_level
);
2513 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2518 static inline uint32_t
2519 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2520 uint32_t start_layer
, uint32_t num_layers
)
2522 assert(level
<= mt
->last_level
);
2523 uint32_t total_num_layers
;
2525 if (mt
->surf
.size
> 0)
2526 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2527 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2528 mt
->surf
.phys_level0_sa
.array_len
;
2530 total_num_layers
= mt
->level
[level
].depth
;
2532 assert(start_layer
< total_num_layers
);
2533 if (num_layers
== INTEL_REMAINING_LAYERS
)
2534 num_layers
= total_num_layers
- start_layer
;
2535 /* Check for overflow */
2536 assert(start_layer
+ num_layers
>= start_layer
);
2537 assert(start_layer
+ num_layers
<= total_num_layers
);
2543 intel_miptree_prepare_access(struct brw_context
*brw
,
2544 struct intel_mipmap_tree
*mt
,
2545 uint32_t start_level
, uint32_t num_levels
,
2546 uint32_t start_layer
, uint32_t num_layers
,
2547 bool aux_supported
, bool fast_clear_supported
)
2549 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2551 if (_mesa_is_format_color_format(mt
->format
)) {
2555 if (mt
->num_samples
> 1) {
2556 /* Nothing to do for MSAA */
2557 assert(aux_supported
&& fast_clear_supported
);
2559 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2560 const uint32_t level
= start_level
+ l
;
2561 const uint32_t level_layers
=
2562 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2563 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2564 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2565 start_layer
+ a
, aux_supported
,
2566 fast_clear_supported
);
2570 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2571 /* Nothing to do for stencil */
2576 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2577 const uint32_t level
= start_level
+ l
;
2578 if (!intel_miptree_level_has_hiz(mt
, level
))
2581 const uint32_t level_layers
=
2582 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2583 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2584 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2586 fast_clear_supported
);
2593 intel_miptree_finish_write(struct brw_context
*brw
,
2594 struct intel_mipmap_tree
*mt
, uint32_t level
,
2595 uint32_t start_layer
, uint32_t num_layers
,
2596 bool written_with_aux
)
2598 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2600 if (_mesa_is_format_color_format(mt
->format
)) {
2604 if (mt
->num_samples
> 1) {
2605 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2606 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2610 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2611 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2615 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2616 /* Nothing to do for stencil */
2618 if (!intel_miptree_level_has_hiz(mt
, level
))
2621 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2622 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2629 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2630 uint32_t level
, uint32_t layer
)
2632 intel_miptree_check_level_layer(mt
, level
, layer
);
2634 if (_mesa_is_format_color_format(mt
->format
)) {
2635 assert(mt
->mcs_buf
!= NULL
);
2636 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2637 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2638 unreachable("Cannot get aux state for stencil");
2640 assert(intel_miptree_level_has_hiz(mt
, level
));
2643 return mt
->aux_state
[level
][layer
];
2647 intel_miptree_set_aux_state(struct brw_context
*brw
,
2648 struct intel_mipmap_tree
*mt
, uint32_t level
,
2649 uint32_t start_layer
, uint32_t num_layers
,
2650 enum isl_aux_state aux_state
)
2652 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2654 if (_mesa_is_format_color_format(mt
->format
)) {
2655 assert(mt
->mcs_buf
!= NULL
);
2656 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2657 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2658 unreachable("Cannot get aux state for stencil");
2660 assert(intel_miptree_level_has_hiz(mt
, level
));
2663 for (unsigned a
= 0; a
< num_layers
; a
++)
2664 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2667 /* On Gen9 color buffers may be compressed by the hardware (lossless
2668 * compression). There are, however, format restrictions and care needs to be
2669 * taken that the sampler engine is capable for re-interpreting a buffer with
2670 * format different the buffer was originally written with.
2672 * For example, SRGB formats are not compressible and the sampler engine isn't
2673 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2674 * color buffer needs to be resolved so that the sampling surface can be
2675 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2679 can_texture_with_ccs(struct brw_context
*brw
,
2680 struct intel_mipmap_tree
*mt
,
2681 mesa_format view_format
)
2683 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2686 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2687 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2689 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2690 isl_mt_format
, isl_view_format
)) {
2691 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2692 _mesa_get_format_name(view_format
),
2693 _mesa_get_format_name(mt
->format
));
2701 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2702 struct intel_mipmap_tree
*mt
,
2703 mesa_format view_format
,
2704 uint32_t start_level
, uint32_t num_levels
,
2705 uint32_t start_layer
, uint32_t num_layers
,
2706 bool *aux_supported_out
)
2708 bool aux_supported
, clear_supported
;
2709 if (_mesa_is_format_color_format(mt
->format
)) {
2710 if (mt
->num_samples
> 1) {
2711 aux_supported
= clear_supported
= true;
2713 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2715 /* Clear color is specified as ints or floats and the conversion is
2716 * done by the sampler. If we have a texture view, we would have to
2717 * perform the clear color conversion manually. Just disable clear
2720 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2722 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2723 aux_supported
= clear_supported
= false;
2725 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2728 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2729 start_layer
, num_layers
,
2730 aux_supported
, clear_supported
);
2731 if (aux_supported_out
)
2732 *aux_supported_out
= aux_supported
;
2736 intel_miptree_prepare_texture(struct brw_context
*brw
,
2737 struct intel_mipmap_tree
*mt
,
2738 mesa_format view_format
,
2739 bool *aux_supported_out
)
2741 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2742 0, INTEL_REMAINING_LEVELS
,
2743 0, INTEL_REMAINING_LAYERS
,
2748 intel_miptree_prepare_image(struct brw_context
*brw
,
2749 struct intel_mipmap_tree
*mt
)
2751 /* The data port doesn't understand any compression */
2752 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2753 0, INTEL_REMAINING_LAYERS
, false, false);
2757 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2758 struct intel_mipmap_tree
*mt
, uint32_t level
,
2759 uint32_t start_layer
, uint32_t num_layers
)
2761 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2762 start_layer
, num_layers
, NULL
);
2766 intel_miptree_prepare_render(struct brw_context
*brw
,
2767 struct intel_mipmap_tree
*mt
, uint32_t level
,
2768 uint32_t start_layer
, uint32_t layer_count
,
2771 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2772 * the single-sampled color renderbuffers because the CCS buffer isn't
2773 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2774 * enabled because otherwise the surface state will be programmed with
2775 * the linear equivalent format anyway.
2777 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2778 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2780 /* Lossless compression is not supported for SRGB formats, it
2781 * should be impossible to get here with such surfaces.
2783 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2784 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2788 /* For layered rendering non-compressed fast cleared buffers need to be
2789 * resolved. Surface state can carry only one fast color clear value
2790 * while each layer may have its own fast clear color value. For
2791 * compressed buffers color value is available in the color buffer.
2793 if (layer_count
> 1 &&
2794 !(mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) &&
2795 !intel_miptree_is_lossless_compressed(brw
, mt
)) {
2796 assert(brw
->gen
>= 8);
2798 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2804 intel_miptree_finish_render(struct brw_context
*brw
,
2805 struct intel_mipmap_tree
*mt
, uint32_t level
,
2806 uint32_t start_layer
, uint32_t layer_count
)
2808 assert(_mesa_is_format_color_format(mt
->format
));
2809 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2810 mt
->mcs_buf
!= NULL
);
2814 intel_miptree_prepare_depth(struct brw_context
*brw
,
2815 struct intel_mipmap_tree
*mt
, uint32_t level
,
2816 uint32_t start_layer
, uint32_t layer_count
)
2818 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2819 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2823 intel_miptree_finish_depth(struct brw_context
*brw
,
2824 struct intel_mipmap_tree
*mt
, uint32_t level
,
2825 uint32_t start_layer
, uint32_t layer_count
,
2828 if (depth_written
) {
2829 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2830 mt
->hiz_buf
!= NULL
);
2835 * Make it possible to share the BO backing the given miptree with another
2836 * process or another miptree.
2838 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2839 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2840 * ensure that no MCS buffer gets allocated in the future.
2842 * HiZ is similarly unsafe with shared buffers.
2845 intel_miptree_make_shareable(struct brw_context
*brw
,
2846 struct intel_mipmap_tree
*mt
)
2848 /* MCS buffers are also used for multisample buffers, but we can't resolve
2849 * away a multisample MCS buffer because it's an integral part of how the
2850 * pixel data is stored. Fortunately this code path should never be
2851 * reached for multisample buffers.
2853 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2855 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2856 0, INTEL_REMAINING_LAYERS
, false, false);
2859 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2860 brw_bo_unreference(mt
->mcs_buf
->bo
);
2864 /* Any pending MCS/CCS operations are no longer needed. Trying to
2865 * execute any will likely crash due to the missing aux buffer. So let's
2866 * delete all pending ops.
2868 free(mt
->aux_state
);
2869 mt
->aux_state
= NULL
;
2873 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2874 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2877 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2878 mt
->level
[l
].has_hiz
= false;
2881 /* Any pending HiZ operations are no longer needed. Trying to execute
2882 * any will likely crash due to the missing aux buffer. So let's delete
2885 free(mt
->aux_state
);
2886 mt
->aux_state
= NULL
;
2892 * \brief Get pointer offset into stencil buffer.
2894 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2895 * must decode the tile's layout in software.
2898 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2900 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2902 * Even though the returned offset is always positive, the return type is
2904 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2905 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2908 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2910 uint32_t tile_size
= 4096;
2911 uint32_t tile_width
= 64;
2912 uint32_t tile_height
= 64;
2913 uint32_t row_size
= 64 * stride
;
2915 uint32_t tile_x
= x
/ tile_width
;
2916 uint32_t tile_y
= y
/ tile_height
;
2918 /* The byte's address relative to the tile's base addres. */
2919 uint32_t byte_x
= x
% tile_width
;
2920 uint32_t byte_y
= y
% tile_height
;
2922 uintptr_t u
= tile_y
* row_size
2923 + tile_x
* tile_size
2924 + 512 * (byte_x
/ 8)
2926 + 32 * ((byte_y
/ 4) % 2)
2927 + 16 * ((byte_x
/ 4) % 2)
2928 + 8 * ((byte_y
/ 2) % 2)
2929 + 4 * ((byte_x
/ 2) % 2)
2934 /* adjust for bit6 swizzling */
2935 if (((byte_x
/ 8) % 2) == 1) {
2936 if (((byte_y
/ 8) % 2) == 0) {
2948 intel_miptree_updownsample(struct brw_context
*brw
,
2949 struct intel_mipmap_tree
*src
,
2950 struct intel_mipmap_tree
*dst
)
2952 unsigned src_w
, src_h
, dst_w
, dst_h
;
2954 if (src
->surf
.size
> 0) {
2955 src_w
= src
->surf
.logical_level0_px
.width
;
2956 src_h
= src
->surf
.logical_level0_px
.height
;
2958 src_w
= src
->logical_width0
;
2959 src_h
= src
->logical_height0
;
2962 if (dst
->surf
.size
> 0) {
2963 dst_w
= dst
->surf
.logical_level0_px
.width
;
2964 dst_h
= dst
->surf
.logical_level0_px
.height
;
2966 dst_w
= dst
->logical_width0
;
2967 dst_h
= dst
->logical_height0
;
2970 brw_blorp_blit_miptrees(brw
,
2971 src
, 0 /* level */, 0 /* layer */,
2972 src
->format
, SWIZZLE_XYZW
,
2973 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2976 GL_NEAREST
, false, false /*mirror x, y*/,
2979 if (src
->stencil_mt
) {
2980 if (src
->stencil_mt
->surf
.size
> 0) {
2981 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2982 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2984 src_w
= src
->stencil_mt
->logical_width0
;
2985 src_h
= src
->stencil_mt
->logical_height0
;
2988 if (dst
->stencil_mt
->surf
.size
> 0) {
2989 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2990 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2992 dst_w
= dst
->stencil_mt
->logical_width0
;
2993 dst_h
= dst
->stencil_mt
->logical_height0
;
2996 brw_blorp_blit_miptrees(brw
,
2997 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2998 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2999 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
3000 dst
->stencil_mt
->format
,
3003 GL_NEAREST
, false, false /*mirror x, y*/,
3004 false, false /* decode/encode srgb */);
3009 intel_update_r8stencil(struct brw_context
*brw
,
3010 struct intel_mipmap_tree
*mt
)
3012 assert(brw
->gen
>= 7);
3013 struct intel_mipmap_tree
*src
=
3014 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3015 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
3018 if (!mt
->r8stencil_mt
) {
3019 const uint32_t r8stencil_flags
=
3020 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
3021 MIPTREE_LAYOUT_DISABLE_AUX
;
3022 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3023 mt
->r8stencil_mt
= intel_miptree_create(brw
,
3025 MESA_FORMAT_R_UINT8
,
3028 src
->logical_width0
,
3029 src
->logical_height0
,
3030 src
->logical_depth0
,
3033 assert(mt
->r8stencil_mt
);
3036 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3038 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3039 const unsigned depth
= src
->level
[level
].depth
;
3041 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3042 brw_blorp_copy_miptrees(brw
,
3046 minify(src
->logical_width0
, level
),
3047 minify(src
->logical_height0
, level
));
3051 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3052 src
->r8stencil_needs_update
= false;
3056 intel_miptree_map_raw(struct brw_context
*brw
,
3057 struct intel_mipmap_tree
*mt
,
3060 struct brw_bo
*bo
= mt
->bo
;
3062 if (brw_batch_references(&brw
->batch
, bo
))
3063 intel_batchbuffer_flush(brw
);
3065 return brw_bo_map(brw
, bo
, mode
);
3069 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3071 brw_bo_unmap(mt
->bo
);
3075 intel_miptree_map_gtt(struct brw_context
*brw
,
3076 struct intel_mipmap_tree
*mt
,
3077 struct intel_miptree_map
*map
,
3078 unsigned int level
, unsigned int slice
)
3080 unsigned int bw
, bh
;
3082 unsigned int image_x
, image_y
;
3083 intptr_t x
= map
->x
;
3084 intptr_t y
= map
->y
;
3086 /* For compressed formats, the stride is the number of bytes per
3087 * row of blocks. intel_miptree_get_image_offset() already does
3090 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3091 assert(y
% bh
== 0);
3092 assert(x
% bw
== 0);
3096 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
3101 /* Note that in the case of cube maps, the caller must have passed the
3102 * slice number referencing the face.
3104 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3108 map
->stride
= mt
->pitch
;
3109 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3112 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3113 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3114 map
->x
, map
->y
, map
->w
, map
->h
,
3115 mt
, _mesa_get_format_name(mt
->format
),
3116 x
, y
, map
->ptr
, map
->stride
);
3120 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3122 intel_miptree_unmap_raw(mt
);
3126 intel_miptree_map_blit(struct brw_context
*brw
,
3127 struct intel_mipmap_tree
*mt
,
3128 struct intel_miptree_map
*map
,
3129 unsigned int level
, unsigned int slice
)
3131 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3132 /* first_level */ 0,
3136 MIPTREE_LAYOUT_TILING_NONE
);
3138 if (!map
->linear_mt
) {
3139 fprintf(stderr
, "Failed to allocate blit temporary\n");
3142 map
->stride
= map
->linear_mt
->pitch
;
3144 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3145 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3146 * invalidate is set, since we'll be writing the whole rectangle from our
3147 * temporary buffer back out.
3149 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3150 if (!intel_miptree_copy(brw
,
3151 mt
, level
, slice
, map
->x
, map
->y
,
3152 map
->linear_mt
, 0, 0, 0, 0,
3154 fprintf(stderr
, "Failed to blit\n");
3159 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3161 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3162 map
->x
, map
->y
, map
->w
, map
->h
,
3163 mt
, _mesa_get_format_name(mt
->format
),
3164 level
, slice
, map
->ptr
, map
->stride
);
3169 intel_miptree_release(&map
->linear_mt
);
3175 intel_miptree_unmap_blit(struct brw_context
*brw
,
3176 struct intel_mipmap_tree
*mt
,
3177 struct intel_miptree_map
*map
,
3181 struct gl_context
*ctx
= &brw
->ctx
;
3183 intel_miptree_unmap_raw(map
->linear_mt
);
3185 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3186 bool ok
= intel_miptree_copy(brw
,
3187 map
->linear_mt
, 0, 0, 0, 0,
3188 mt
, level
, slice
, map
->x
, map
->y
,
3190 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3193 intel_miptree_release(&map
->linear_mt
);
3197 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3199 #if defined(USE_SSE41)
3201 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3202 struct intel_mipmap_tree
*mt
,
3203 struct intel_miptree_map
*map
,
3204 unsigned int level
, unsigned int slice
)
3206 assert(map
->mode
& GL_MAP_READ_BIT
);
3207 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3209 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3210 map
->x
, map
->y
, map
->w
, map
->h
,
3211 mt
, _mesa_get_format_name(mt
->format
),
3212 level
, slice
, map
->ptr
, map
->stride
);
3214 /* Map the original image */
3217 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3221 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3227 src
+= image_y
* mt
->pitch
;
3228 src
+= image_x
* mt
->cpp
;
3230 /* Due to the pixel offsets for the particular image being mapped, our
3231 * src pointer may not be 16-byte aligned. However, if the pitch is
3232 * divisible by 16, then the amount by which it's misaligned will remain
3233 * consistent from row to row.
3235 assert((mt
->pitch
% 16) == 0);
3236 const int misalignment
= ((uintptr_t) src
) & 15;
3238 /* Create an untiled temporary buffer for the mapping. */
3239 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3241 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3243 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3244 /* Offset the destination so it has the same misalignment as src. */
3245 map
->ptr
= map
->buffer
+ misalignment
;
3247 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3249 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3250 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3251 void *src_ptr
= src
+ y
* mt
->pitch
;
3253 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3256 intel_miptree_unmap_raw(mt
);
3260 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3261 struct intel_mipmap_tree
*mt
,
3262 struct intel_miptree_map
*map
,
3266 _mesa_align_free(map
->buffer
);
3273 intel_miptree_map_s8(struct brw_context
*brw
,
3274 struct intel_mipmap_tree
*mt
,
3275 struct intel_miptree_map
*map
,
3276 unsigned int level
, unsigned int slice
)
3278 map
->stride
= map
->w
;
3279 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3283 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3284 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3285 * invalidate is set, since we'll be writing the whole rectangle from our
3286 * temporary buffer back out.
3288 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3289 /* ISL uses a stencil pitch value that is expected by hardware whereas
3290 * traditional miptree uses half of that. Below the value gets supplied
3291 * to intel_offset_S8() which expects the legacy interpretation.
3293 const unsigned pitch
= mt
->surf
.size
> 0 ?
3294 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3295 uint8_t *untiled_s8_map
= map
->ptr
;
3296 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3297 unsigned int image_x
, image_y
;
3299 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3301 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3302 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3303 ptrdiff_t offset
= intel_offset_S8(pitch
,
3304 x
+ image_x
+ map
->x
,
3305 y
+ image_y
+ map
->y
,
3306 brw
->has_swizzling
);
3307 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3311 intel_miptree_unmap_raw(mt
);
3313 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3314 map
->x
, map
->y
, map
->w
, map
->h
,
3315 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3317 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3318 map
->x
, map
->y
, map
->w
, map
->h
,
3319 mt
, map
->ptr
, map
->stride
);
3324 intel_miptree_unmap_s8(struct brw_context
*brw
,
3325 struct intel_mipmap_tree
*mt
,
3326 struct intel_miptree_map
*map
,
3330 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3331 /* ISL uses a stencil pitch value that is expected by hardware whereas
3332 * traditional miptree uses half of that. Below the value gets supplied
3333 * to intel_offset_S8() which expects the legacy interpretation.
3335 const unsigned pitch
= mt
->surf
.size
> 0 ?
3336 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3337 unsigned int image_x
, image_y
;
3338 uint8_t *untiled_s8_map
= map
->ptr
;
3339 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3341 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3343 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3344 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3345 ptrdiff_t offset
= intel_offset_S8(pitch
,
3346 image_x
+ x
+ map
->x
,
3347 image_y
+ y
+ map
->y
,
3348 brw
->has_swizzling
);
3349 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3353 intel_miptree_unmap_raw(mt
);
3360 intel_miptree_map_etc(struct brw_context
*brw
,
3361 struct intel_mipmap_tree
*mt
,
3362 struct intel_miptree_map
*map
,
3366 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3367 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3368 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3371 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3372 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3374 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3375 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3376 map
->w
, map
->h
, 1));
3377 map
->ptr
= map
->buffer
;
3381 intel_miptree_unmap_etc(struct brw_context
*brw
,
3382 struct intel_mipmap_tree
*mt
,
3383 struct intel_miptree_map
*map
,
3389 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3394 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3395 + image_y
* mt
->pitch
3396 + image_x
* mt
->cpp
;
3398 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3399 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3400 map
->ptr
, map
->stride
,
3403 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3404 map
->ptr
, map
->stride
,
3405 map
->w
, map
->h
, mt
->etc_format
);
3407 intel_miptree_unmap_raw(mt
);
3412 * Mapping function for packed depth/stencil miptrees backed by real separate
3413 * miptrees for depth and stencil.
3415 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3416 * separate from the depth buffer. Yet at the GL API level, we have to expose
3417 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3418 * be able to map that memory for texture storage and glReadPixels-type
3419 * operations. We give Mesa core that access by mallocing a temporary and
3420 * copying the data between the actual backing store and the temporary.
3423 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3424 struct intel_mipmap_tree
*mt
,
3425 struct intel_miptree_map
*map
,
3426 unsigned int level
, unsigned int slice
)
3428 struct intel_mipmap_tree
*z_mt
= mt
;
3429 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3430 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3431 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3433 map
->stride
= map
->w
* packed_bpp
;
3434 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3438 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3439 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3440 * invalidate is set, since we'll be writing the whole rectangle from our
3441 * temporary buffer back out.
3443 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3444 /* ISL uses a stencil pitch value that is expected by hardware whereas
3445 * traditional miptree uses half of that. Below the value gets supplied
3446 * to intel_offset_S8() which expects the legacy interpretation.
3448 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3449 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3450 uint32_t *packed_map
= map
->ptr
;
3451 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3452 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3453 unsigned int s_image_x
, s_image_y
;
3454 unsigned int z_image_x
, z_image_y
;
3456 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3457 &s_image_x
, &s_image_y
);
3458 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3459 &z_image_x
, &z_image_y
);
3461 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3462 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3463 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3464 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3467 brw
->has_swizzling
);
3468 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3470 (map_x
+ z_image_x
));
3471 uint8_t s
= s_map
[s_offset
];
3472 uint32_t z
= z_map
[z_offset
];
3474 if (map_z32f_x24s8
) {
3475 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3476 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3478 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3483 intel_miptree_unmap_raw(s_mt
);
3484 intel_miptree_unmap_raw(z_mt
);
3486 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3488 map
->x
, map
->y
, map
->w
, map
->h
,
3489 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3490 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3491 map
->ptr
, map
->stride
);
3493 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3494 map
->x
, map
->y
, map
->w
, map
->h
,
3495 mt
, map
->ptr
, map
->stride
);
3500 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3501 struct intel_mipmap_tree
*mt
,
3502 struct intel_miptree_map
*map
,
3506 struct intel_mipmap_tree
*z_mt
= mt
;
3507 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3508 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3510 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3511 /* ISL uses a stencil pitch value that is expected by hardware whereas
3512 * traditional miptree uses half of that. Below the value gets supplied
3513 * to intel_offset_S8() which expects the legacy interpretation.
3515 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3516 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3517 uint32_t *packed_map
= map
->ptr
;
3518 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3519 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3520 unsigned int s_image_x
, s_image_y
;
3521 unsigned int z_image_x
, z_image_y
;
3523 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3524 &s_image_x
, &s_image_y
);
3525 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3526 &z_image_x
, &z_image_y
);
3528 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3529 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3530 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3531 x
+ s_image_x
+ map
->x
,
3532 y
+ s_image_y
+ map
->y
,
3533 brw
->has_swizzling
);
3534 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3536 (x
+ z_image_x
+ map
->x
));
3538 if (map_z32f_x24s8
) {
3539 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3540 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3542 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3543 s_map
[s_offset
] = packed
>> 24;
3544 z_map
[z_offset
] = packed
;
3549 intel_miptree_unmap_raw(s_mt
);
3550 intel_miptree_unmap_raw(z_mt
);
3552 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3554 map
->x
, map
->y
, map
->w
, map
->h
,
3555 z_mt
, _mesa_get_format_name(z_mt
->format
),
3556 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3557 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3558 map
->ptr
, map
->stride
);
3565 * Create and attach a map to the miptree at (level, slice). Return the
3568 static struct intel_miptree_map
*
3569 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3578 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3583 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3584 mt
->level
[level
].slice
[slice
].map
= map
;
3596 * Release the map at (level, slice).
3599 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3603 struct intel_miptree_map
**map
;
3605 map
= &mt
->level
[level
].slice
[slice
].map
;
3611 can_blit_slice(struct intel_mipmap_tree
*mt
,
3612 unsigned int level
, unsigned int slice
)
3614 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3615 if (mt
->pitch
>= 32768)
3622 use_intel_mipree_map_blit(struct brw_context
*brw
,
3623 struct intel_mipmap_tree
*mt
,
3629 /* It's probably not worth swapping to the blit ring because of
3630 * all the overhead involved.
3632 !(mode
& GL_MAP_WRITE_BIT
) &&
3634 (mt
->tiling
== I915_TILING_X
||
3635 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3636 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3637 /* Fast copy blit on skl+ supports all tiling formats. */
3639 can_blit_slice(mt
, level
, slice
))
3642 if (mt
->tiling
!= I915_TILING_NONE
&&
3643 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3644 assert(can_blit_slice(mt
, level
, slice
));
3652 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3653 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3654 * arithmetic overflow.
3656 * If you call this function and use \a out_stride, then you're doing pointer
3657 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3658 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3659 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3660 * which usually have type uint32_t or GLuint.
3663 intel_miptree_map(struct brw_context
*brw
,
3664 struct intel_mipmap_tree
*mt
,
3673 ptrdiff_t *out_stride
)
3675 struct intel_miptree_map
*map
;
3677 assert(mt
->num_samples
<= 1);
3679 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3686 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3687 map
->mode
& GL_MAP_WRITE_BIT
);
3689 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3690 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3691 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3692 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3693 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3694 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3695 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3696 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3697 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3698 #if defined(USE_SSE41)
3699 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3700 !mt
->compressed
&& cpu_has_sse4_1
&&
3701 (mt
->pitch
% 16 == 0)) {
3702 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3705 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3708 *out_ptr
= map
->ptr
;
3709 *out_stride
= map
->stride
;
3711 if (map
->ptr
== NULL
)
3712 intel_miptree_release_map(mt
, level
, slice
);
3716 intel_miptree_unmap(struct brw_context
*brw
,
3717 struct intel_mipmap_tree
*mt
,
3721 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3723 assert(mt
->num_samples
<= 1);
3728 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3729 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3731 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3732 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3733 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3734 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3735 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3736 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3737 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3738 } else if (map
->linear_mt
) {
3739 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3740 #if defined(USE_SSE41)
3741 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3742 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3745 intel_miptree_unmap_gtt(mt
);
3748 intel_miptree_release_map(mt
, level
, slice
);
3752 get_isl_surf_dim(GLenum target
)
3756 case GL_TEXTURE_1D_ARRAY
:
3757 return ISL_SURF_DIM_1D
;
3760 case GL_TEXTURE_2D_ARRAY
:
3761 case GL_TEXTURE_RECTANGLE
:
3762 case GL_TEXTURE_CUBE_MAP
:
3763 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3764 case GL_TEXTURE_2D_MULTISAMPLE
:
3765 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3766 case GL_TEXTURE_EXTERNAL_OES
:
3767 return ISL_SURF_DIM_2D
;
3770 return ISL_SURF_DIM_3D
;
3773 unreachable("Invalid texture target");
3777 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3778 GLenum target
, enum miptree_array_layout array_layout
)
3780 if (array_layout
== GEN6_HIZ_STENCIL
)
3781 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3785 case GL_TEXTURE_1D_ARRAY
:
3786 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3787 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3790 case GL_TEXTURE_2D_ARRAY
:
3791 case GL_TEXTURE_RECTANGLE
:
3792 case GL_TEXTURE_2D_MULTISAMPLE
:
3793 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3794 case GL_TEXTURE_EXTERNAL_OES
:
3795 return ISL_DIM_LAYOUT_GEN4_2D
;
3797 case GL_TEXTURE_CUBE_MAP
:
3798 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3799 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3800 ISL_DIM_LAYOUT_GEN4_2D
);
3803 return (devinfo
->gen
>= 9 ?
3804 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3807 unreachable("Invalid texture target");
3811 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3813 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3814 return ISL_TILING_W
;
3816 switch (mt
->tiling
) {
3817 case I915_TILING_NONE
:
3818 return ISL_TILING_LINEAR
;
3820 return ISL_TILING_X
;
3822 return ISL_TILING_Y0
;
3824 unreachable("Invalid tiling mode");
3830 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3831 const struct intel_mipmap_tree
*mt
,
3832 struct isl_surf
*surf
)
3834 surf
->dim
= get_isl_surf_dim(mt
->target
);
3835 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3836 mt
->tiling
, mt
->target
,
3839 if (mt
->num_samples
> 1) {
3840 switch (mt
->msaa_layout
) {
3841 case INTEL_MSAA_LAYOUT_IMS
:
3842 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3844 case INTEL_MSAA_LAYOUT_UMS
:
3845 case INTEL_MSAA_LAYOUT_CMS
:
3846 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3849 unreachable("Invalid MSAA layout");
3852 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3855 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3857 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3858 /* The ISL definition of row_pitch matches the surface state pitch field
3859 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3860 * the factor of 2 for W-tiling in row_pitch.
3862 surf
->row_pitch
= 2 * mt
->pitch
;
3864 surf
->row_pitch
= mt
->pitch
;
3867 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3869 if (brw
->gen
>= 9) {
3870 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3871 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3872 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3874 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3875 * alignment in terms of surface elements like we want.
3877 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3880 /* On earlier gens it's stored in pixels. */
3882 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3883 surf
->image_alignment_el
=
3884 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3887 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3888 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3889 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3890 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3891 surf
->logical_level0_px
.array_len
= 1;
3893 surf
->logical_level0_px
.depth
= 1;
3894 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3897 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3898 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3899 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3900 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3901 surf
->phys_level0_sa
.array_len
= 1;
3903 surf
->phys_level0_sa
.depth
= 1;
3904 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3907 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3908 surf
->samples
= MAX2(mt
->num_samples
, 1);
3910 surf
->size
= 0; /* TODO */
3911 surf
->alignment
= 0; /* TODO */
3913 switch (surf
->dim_layout
) {
3914 case ISL_DIM_LAYOUT_GEN4_2D
:
3915 case ISL_DIM_LAYOUT_GEN4_3D
:
3916 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3917 if (brw
->gen
>= 9) {
3918 surf
->array_pitch_el_rows
= mt
->qpitch
;
3921 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3922 assert(mt
->qpitch
% bh
== 0);
3923 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3926 case ISL_DIM_LAYOUT_GEN9_1D
:
3927 surf
->array_pitch_el_rows
= 1;
3931 switch (mt
->array_layout
) {
3932 case ALL_LOD_IN_EACH_SLICE
:
3933 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3935 case ALL_SLICES_AT_EACH_LOD
:
3936 case GEN6_HIZ_STENCIL
:
3937 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3940 unreachable("Invalid array layout");
3943 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3944 switch (base_format
) {
3945 case GL_DEPTH_COMPONENT
:
3946 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3948 case GL_STENCIL_INDEX
:
3949 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3951 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3953 case GL_DEPTH_STENCIL
:
3954 /* In this case we only texture from the depth part */
3955 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3956 ISL_SURF_USAGE_TEXTURE_BIT
;
3959 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3960 if (brw
->format_supported_as_render_target
[mt
->format
])
3961 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3965 if (_mesa_is_cube_map_texture(mt
->target
))
3966 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3970 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3971 const struct intel_mipmap_tree
*mt
)
3974 return ISL_AUX_USAGE_HIZ
;
3977 return ISL_AUX_USAGE_NONE
;
3979 if (mt
->num_samples
> 1) {
3980 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3981 return ISL_AUX_USAGE_MCS
;
3984 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3985 assert(brw
->gen
>= 9);
3986 return ISL_AUX_USAGE_CCS_E
;
3989 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0)
3990 return ISL_AUX_USAGE_CCS_D
;
3992 unreachable("Invalid MCS miptree");
3995 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3996 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3997 * PASS IT INTO isl_surf_fill_state.
4000 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
4001 const struct intel_mipmap_tree
*mt
,
4002 enum isl_aux_usage usage
,
4003 struct isl_surf
*surf
)
4005 uint32_t aux_pitch
, aux_qpitch
;
4007 aux_pitch
= mt
->mcs_buf
->pitch
;
4008 aux_qpitch
= mt
->mcs_buf
->qpitch
;
4009 } else if (mt
->hiz_buf
) {
4010 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
4011 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
4016 /* Start with a copy of the original surface. */
4017 intel_miptree_get_isl_surf(brw
, mt
, surf
);
4019 /* Figure out the format and tiling of the auxiliary surface */
4021 case ISL_AUX_USAGE_NONE
:
4022 unreachable("Invalid auxiliary usage");
4024 case ISL_AUX_USAGE_HIZ
:
4025 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
4028 case ISL_AUX_USAGE_MCS
:
4031 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
4032 * HALIGN 16 must be used."
4035 assert(mt
->halign
== 16);
4037 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
4040 case ISL_AUX_USAGE_CCS_D
:
4041 case ISL_AUX_USAGE_CCS_E
:
4043 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
4045 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
4047 * From the hardware spec for GEN9:
4049 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
4050 * HALIGN 16 must be used."
4052 assert(mt
->num_samples
<= 1);
4054 assert(mt
->halign
== 16);
4056 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
4060 /* We want the pitch of the actual aux buffer. */
4061 surf
->row_pitch
= aux_pitch
;
4063 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
4064 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
4065 * in elements of the primary color surface so we have to divide by the
4066 * compression block height.
4068 surf
->array_pitch_el_rows
=
4069 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;