1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
38 #include "intel_fbo.h"
40 #include "brw_blorp.h"
41 #include "brw_context.h"
43 #include "main/enums.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 target_to_target(GLenum target
)
56 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
57 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
59 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
61 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
62 return GL_TEXTURE_CUBE_MAP_ARB
;
70 * Determine which MSAA layout should be used by the MSAA surface being
71 * created, based on the chip generation and the surface type.
73 static enum intel_msaa_layout
74 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
76 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
81 switch (_mesa_get_format_base_format(format
)) {
82 case GL_DEPTH_COMPONENT
:
83 case GL_STENCIL_INDEX
:
84 case GL_DEPTH_STENCIL
:
85 return INTEL_MSAA_LAYOUT_IMS
;
87 /* Disable MCS on Broadwell for now. We can enable it once things
88 * are working without it.
91 perf_debug("Missing CMS support on Broadwell.\n");
92 return INTEL_MSAA_LAYOUT_UMS
;
95 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
97 * This field must be set to 0 for all SINT MSRTs when all RT channels
100 * In practice this means that we have to disable MCS for all signed
101 * integer MSAA buffers. The alternative, to disable MCS only when one
102 * of the render target channels is disabled, is impractical because it
103 * would require converting between CMS and UMS MSAA layouts on the fly,
104 * which is expensive.
106 if (_mesa_get_format_datatype(format
) == GL_INT
) {
107 /* TODO: is this workaround needed for future chipsets? */
108 assert(brw
->gen
== 7);
109 return INTEL_MSAA_LAYOUT_UMS
;
111 return INTEL_MSAA_LAYOUT_CMS
;
118 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
119 * scaled-down bitfield representation of the color buffer which is capable of
120 * recording when blocks of the color buffer are equal to the clear value.
121 * This function returns the block size that will be used by the MCS buffer
122 * corresponding to a certain color miptree.
124 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
125 * beneath the "Fast Color Clear" bullet (p327):
127 * The following table describes the RT alignment
141 * This alignment has the following uses:
143 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
144 * buffer contains 128 blocks horizontally and 256 blocks vertically.
146 * - For figuring out alignment restrictions for a fast clear operation. Fast
147 * clear operations must always clear aligned multiples of 16 blocks
148 * horizontally and 32 blocks vertically.
150 * - For scaling down the coordinates sent through the render pipeline during
151 * a fast clear. X coordinates must be scaled down by 8 times the block
152 * width, and Y coordinates by 16 times the block height.
154 * - For scaling down the coordinates sent through the render pipeline during
155 * a "Render Target Resolve" operation. X coordinates must be scaled down
156 * by half the block width, and Y coordinates by half the block height.
159 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
160 struct intel_mipmap_tree
*mt
,
161 unsigned *width_px
, unsigned *height
)
163 switch (mt
->region
->tiling
) {
165 assert(!"Non-MSRT MCS requires X or Y tiling");
166 /* In release builds, fall through */
168 *width_px
= 32 / mt
->cpp
;
172 *width_px
= 64 / mt
->cpp
;
179 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
182 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
183 * beneath the "Fast Color Clear" bullet (p326):
185 * - Support is limited to tiled render targets.
186 * - Support is for non-mip-mapped and non-array surface types only.
188 * And then later, on p327:
190 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
194 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
195 struct intel_mipmap_tree
*mt
)
197 /* MCS support does not exist prior to Gen7 */
198 if (brw
->gen
< 7 || brw
->gen
>= 8)
201 /* MCS is only supported for color buffers */
202 switch (_mesa_get_format_base_format(mt
->format
)) {
203 case GL_DEPTH_COMPONENT
:
204 case GL_DEPTH_STENCIL
:
205 case GL_STENCIL_INDEX
:
209 if (mt
->region
->tiling
!= I915_TILING_X
&&
210 mt
->region
->tiling
!= I915_TILING_Y
)
212 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
214 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
216 if (mt
->physical_depth0
!= 1)
219 /* There's no point in using an MCS buffer if the surface isn't in a
222 if (!brw
->format_supported_as_render_target
[mt
->format
])
230 * @param for_bo Indicates that the caller is
231 * intel_miptree_create_for_bo(). If true, then do not create
234 struct intel_mipmap_tree
*
235 intel_miptree_create_layout(struct brw_context
*brw
,
246 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
250 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
251 _mesa_lookup_enum_by_nr(target
),
252 _mesa_get_format_name(format
),
253 first_level
, last_level
, mt
);
255 mt
->target
= target_to_target(target
);
257 mt
->first_level
= first_level
;
258 mt
->last_level
= last_level
;
259 mt
->logical_width0
= width0
;
260 mt
->logical_height0
= height0
;
261 mt
->logical_depth0
= depth0
;
262 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
264 /* The cpp is bytes per (1, blockheight)-sized block for compressed
265 * textures. This is why you'll see divides by blockheight all over
268 _mesa_get_format_block_size(format
, &bw
, &bh
);
269 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
270 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
272 mt
->num_samples
= num_samples
;
273 mt
->compressed
= _mesa_is_format_compressed(format
);
274 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
277 if (num_samples
> 1) {
278 /* Adjust width/height/depth for MSAA */
279 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
280 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
281 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
283 * "Any of the other messages (sample*, LOD, load4) used with a
284 * (4x) multisampled surface will in-effect sample a surface with
285 * double the height and width as that indicated in the surface
286 * state. Each pixel position on the original-sized surface is
287 * replaced with a 2x2 of samples with the following arrangement:
292 * Thus, when sampling from a multisampled texture, it behaves as
293 * though the layout in memory for (x,y,sample) is:
295 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
296 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
298 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
299 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
301 * However, the actual layout of multisampled data in memory is:
303 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
304 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
306 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
307 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
309 * This pattern repeats for each 2x2 pixel block.
311 * As a result, when calculating the size of our 4-sample buffer for
312 * an odd width or height, we have to align before scaling up because
313 * sample 3 is in that bottom right 2x2 block.
315 switch (num_samples
) {
317 assert(brw
->gen
>= 8);
318 width0
= ALIGN(width0
, 2) * 2;
319 height0
= ALIGN(height0
, 2);
322 width0
= ALIGN(width0
, 2) * 2;
323 height0
= ALIGN(height0
, 2) * 2;
326 width0
= ALIGN(width0
, 2) * 4;
327 height0
= ALIGN(height0
, 2) * 2;
330 /* num_samples should already have been quantized to 0, 1, 2, 4, or
336 /* Non-interleaved */
337 depth0
*= num_samples
;
341 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
344 switch (mt
->msaa_layout
) {
345 case INTEL_MSAA_LAYOUT_NONE
:
346 case INTEL_MSAA_LAYOUT_IMS
:
347 mt
->array_spacing_lod0
= false;
349 case INTEL_MSAA_LAYOUT_UMS
:
350 case INTEL_MSAA_LAYOUT_CMS
:
351 mt
->array_spacing_lod0
= true;
355 if (target
== GL_TEXTURE_CUBE_MAP
) {
360 mt
->physical_width0
= width0
;
361 mt
->physical_height0
= height0
;
362 mt
->physical_depth0
= depth0
;
365 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
366 (brw
->must_use_separate_stencil
||
367 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
368 mt
->stencil_mt
= intel_miptree_create(brw
,
378 INTEL_MIPTREE_TILING_ANY
);
379 if (!mt
->stencil_mt
) {
380 intel_miptree_release(&mt
);
384 /* Fix up the Z miptree format for how we're splitting out separate
385 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
387 if (mt
->format
== MESA_FORMAT_Z24_UNORM_S8_UINT
) {
388 mt
->format
= MESA_FORMAT_Z24_UNORM_X8_UINT
;
389 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_S8X24_UINT
) {
390 mt
->format
= MESA_FORMAT_Z_FLOAT32
;
393 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
394 _mesa_get_format_name(mt
->format
));
398 brw_miptree_layout(brw
, mt
);
404 * \brief Helper function for intel_miptree_create().
407 intel_miptree_choose_tiling(struct brw_context
*brw
,
410 uint32_t num_samples
,
411 enum intel_miptree_tiling_mode requested
,
412 struct intel_mipmap_tree
*mt
)
414 if (format
== MESA_FORMAT_S_UINT8
) {
415 /* The stencil buffer is W tiled. However, we request from the kernel a
416 * non-tiled buffer because the GTT is incapable of W fencing.
418 return I915_TILING_NONE
;
421 /* Some usages may want only one type of tiling, like depth miptrees (Y
422 * tiled), or temporary BOs for uploading data once (linear).
425 case INTEL_MIPTREE_TILING_ANY
:
427 case INTEL_MIPTREE_TILING_Y
:
428 return I915_TILING_Y
;
429 case INTEL_MIPTREE_TILING_NONE
:
430 return I915_TILING_NONE
;
433 if (num_samples
> 1) {
434 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
437 * [DevSNB+]: For multi-sample render targets, this field must be
438 * 1. MSRTs can only be tiled.
440 * Our usual reason for preferring X tiling (fast blits using the
441 * blitting engine) doesn't apply to MSAA, since we'll generally be
442 * downsampling or upsampling when blitting between the MSAA buffer
443 * and another buffer, and the blitting engine doesn't support that.
444 * So use Y tiling, since it makes better use of the cache.
446 return I915_TILING_Y
;
449 GLenum base_format
= _mesa_get_format_base_format(format
);
450 if (base_format
== GL_DEPTH_COMPONENT
||
451 base_format
== GL_DEPTH_STENCIL_EXT
)
452 return I915_TILING_Y
;
454 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
456 /* If the width is much smaller than a tile, don't bother tiling. */
457 if (minimum_pitch
< 64)
458 return I915_TILING_NONE
;
460 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
461 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
462 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
463 mt
->total_width
, mt
->total_height
);
464 return I915_TILING_NONE
;
467 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
469 return I915_TILING_X
;
471 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
472 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
474 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
475 * all the way back to 965, but is explicitly permitted on Gen7.
477 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
478 return I915_TILING_X
;
480 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
481 * messages), on p64, under the heading "Surface Vertical Alignment":
483 * This field must be set to VALIGN_4 for all tiled Y Render Target
486 * So if the surface is renderable and uses a vertical alignment of 2,
487 * force it to be X tiled. This is somewhat conservative (it's possible
488 * that the client won't ever render to this surface), but it's difficult
489 * to know that ahead of time. And besides, since we use a vertical
490 * alignment of 4 as often as we can, this shouldn't happen very often.
492 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
493 brw
->format_supported_as_render_target
[format
]) {
494 return I915_TILING_X
;
497 return I915_TILING_Y
| I915_TILING_X
;
500 struct intel_mipmap_tree
*
501 intel_miptree_create(struct brw_context
*brw
,
509 bool expect_accelerated_upload
,
511 enum intel_miptree_tiling_mode requested_tiling
)
513 struct intel_mipmap_tree
*mt
;
514 mesa_format tex_format
= format
;
515 mesa_format etc_format
= MESA_FORMAT_NONE
;
516 GLuint total_width
, total_height
;
518 if (brw
->gen
< 8 && !brw
->is_baytrail
) {
520 case MESA_FORMAT_ETC1_RGB8
:
521 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
523 case MESA_FORMAT_ETC2_RGB8
:
524 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
526 case MESA_FORMAT_ETC2_SRGB8
:
527 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
528 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
529 format
= MESA_FORMAT_B8G8R8A8_SRGB
;
531 case MESA_FORMAT_ETC2_RGBA8_EAC
:
532 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
533 format
= MESA_FORMAT_R8G8B8A8_UNORM
;
535 case MESA_FORMAT_ETC2_R11_EAC
:
536 format
= MESA_FORMAT_R_UNORM16
;
538 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
539 format
= MESA_FORMAT_R_SNORM16
;
541 case MESA_FORMAT_ETC2_RG11_EAC
:
542 format
= MESA_FORMAT_R16G16_UNORM
;
544 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
545 format
= MESA_FORMAT_R16G16_SNORM
;
548 /* Non ETC1 / ETC2 format */
553 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
555 mt
= intel_miptree_create_layout(brw
, target
, format
,
556 first_level
, last_level
, width0
,
560 * pitch == 0 || height == 0 indicates the null texture
562 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
563 intel_miptree_release(&mt
);
567 total_width
= mt
->total_width
;
568 total_height
= mt
->total_height
;
570 if (format
== MESA_FORMAT_S_UINT8
) {
571 /* Align to size of W tile, 64x64. */
572 total_width
= ALIGN(total_width
, 64);
573 total_height
= ALIGN(total_height
, 64);
576 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
577 num_samples
, requested_tiling
,
579 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
581 mt
->etc_format
= etc_format
;
582 mt
->region
= intel_region_alloc(brw
->intelScreen
,
583 y_or_x
? I915_TILING_Y
: tiling
,
587 expect_accelerated_upload
);
589 /* If the region is too large to fit in the aperture, we need to use the
590 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
591 * so we need to fall back to X.
593 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
594 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
595 mt
->total_width
, mt
->total_height
);
596 intel_region_release(&mt
->region
);
598 mt
->region
= intel_region_alloc(brw
->intelScreen
,
603 expect_accelerated_upload
);
609 intel_miptree_release(&mt
);
614 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
615 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
616 intel_miptree_release(&mt
);
621 /* If this miptree is capable of supporting fast color clears, set
622 * fast_clear_state appropriately to ensure that fast clears will occur.
623 * Allocation of the MCS miptree will be deferred until the first fast
624 * clear actually occurs.
626 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
627 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
632 struct intel_mipmap_tree
*
633 intel_miptree_create_for_bo(struct brw_context
*brw
,
642 struct intel_mipmap_tree
*mt
;
644 struct intel_region
*region
= calloc(1, sizeof(*region
));
648 /* Nothing will be able to use this miptree with the BO if the offset isn't
651 if (tiling
!= I915_TILING_NONE
)
652 assert(offset
% 4096 == 0);
654 /* miptrees can't handle negative pitch. If you need flipping of images,
655 * that's outside of the scope of the mt.
659 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
662 true, 0 /* num_samples */);
668 region
->cpp
= mt
->cpp
;
669 region
->width
= width
;
670 region
->height
= height
;
671 region
->pitch
= pitch
;
672 region
->refcount
= 1;
673 drm_intel_bo_reference(bo
);
675 region
->tiling
= tiling
;
684 * For a singlesample image buffer, this simply wraps the given region with a miptree.
686 * For a multisample image buffer, this wraps the given region with
687 * a singlesample miptree, then creates a multisample miptree into which the
688 * singlesample miptree is embedded as a child.
691 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
692 struct intel_renderbuffer
*irb
,
693 struct intel_region
*region
)
695 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
696 struct intel_mipmap_tree
*multisample_mt
= NULL
;
697 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
698 mesa_format format
= rb
->Format
;
699 int num_samples
= rb
->NumSamples
;
701 intel_miptree_release(&irb
->mt
);
703 /* Only the front and back buffers, which are color buffers, are allocated
704 * through the image loader.
706 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
707 _mesa_get_format_base_format(format
) == GL_RGBA
);
709 singlesample_mt
= intel_miptree_create_for_bo(intel
,
717 if (!singlesample_mt
)
719 singlesample_mt
->region
->name
= region
->name
;
721 /* If this miptree is capable of supporting fast color clears, set
722 * mcs_state appropriately to ensure that fast clears will occur.
723 * Allocation of the MCS miptree will be deferred until the first fast
724 * clear actually occurs.
726 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
727 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
729 if (num_samples
== 0) {
730 irb
->mt
= singlesample_mt
;
734 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
739 if (!multisample_mt
) {
740 intel_miptree_release(&singlesample_mt
);
744 irb
->need_downsample
= false;
745 irb
->mt
= multisample_mt
;
746 irb
->singlesample_mt
= singlesample_mt
;
749 struct intel_mipmap_tree
*
750 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
754 uint32_t num_samples
)
756 struct intel_mipmap_tree
*mt
;
759 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
761 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
762 width
, height
, depth
, true, num_samples
,
763 INTEL_MIPTREE_TILING_ANY
);
767 if (brw_is_hiz_depth_format(brw
, format
)) {
768 ok
= intel_miptree_alloc_hiz(brw
, mt
);
776 intel_miptree_release(&mt
);
781 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
782 struct intel_mipmap_tree
*src
)
787 intel_miptree_release(dst
);
791 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
799 intel_miptree_release(struct intel_mipmap_tree
**mt
)
804 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
805 if (--(*mt
)->refcount
<= 0) {
808 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
810 intel_region_release(&((*mt
)->region
));
811 intel_miptree_release(&(*mt
)->stencil_mt
);
812 intel_miptree_release(&(*mt
)->hiz_mt
);
813 intel_miptree_release(&(*mt
)->mcs_mt
);
814 intel_resolve_map_clear(&(*mt
)->hiz_map
);
816 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
817 free((*mt
)->level
[i
].slice
);
826 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
827 int *width
, int *height
, int *depth
)
829 switch (image
->TexObject
->Target
) {
830 case GL_TEXTURE_1D_ARRAY
:
831 *width
= image
->Width
;
833 *depth
= image
->Height
;
836 *width
= image
->Width
;
837 *height
= image
->Height
;
838 *depth
= image
->Depth
;
844 * Can the image be pulled into a unified mipmap tree? This mirrors
845 * the completeness test in a lot of ways.
847 * Not sure whether I want to pass gl_texture_image here.
850 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
851 struct gl_texture_image
*image
)
853 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
854 GLuint level
= intelImage
->base
.Base
.Level
;
855 int width
, height
, depth
;
857 /* glTexImage* choose the texture object based on the target passed in, and
858 * objects can't change targets over their lifetimes, so this should be
861 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
863 mesa_format mt_format
= mt
->format
;
864 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
865 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
866 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
867 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
868 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
869 mt_format
= mt
->etc_format
;
871 if (image
->TexFormat
!= mt_format
)
874 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
876 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
879 /* Test image dimensions against the base level image adjusted for
880 * minification. This will also catch images not present in the
881 * tree, changed targets, etc.
883 if (width
!= minify(mt
->logical_width0
, level
) ||
884 height
!= minify(mt
->logical_height0
, level
) ||
885 depth
!= mt
->level
[level
].depth
) {
889 if (image
->NumSamples
!= mt
->num_samples
)
897 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
899 GLuint x
, GLuint y
, GLuint d
)
901 mt
->level
[level
].depth
= d
;
902 mt
->level
[level
].level_x
= x
;
903 mt
->level
[level
].level_y
= y
;
905 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
908 assert(mt
->level
[level
].slice
== NULL
);
910 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
911 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
912 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
917 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
918 GLuint level
, GLuint img
,
921 if (img
== 0 && level
== 0)
922 assert(x
== 0 && y
== 0);
924 assert(img
< mt
->level
[level
].depth
);
926 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
927 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
929 DBG("%s level %d img %d pos %d,%d\n",
930 __FUNCTION__
, level
, img
,
931 mt
->level
[level
].slice
[img
].x_offset
,
932 mt
->level
[level
].slice
[img
].y_offset
);
936 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
937 GLuint level
, GLuint slice
,
938 GLuint
*x
, GLuint
*y
)
940 assert(slice
< mt
->level
[level
].depth
);
942 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
943 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
947 * Rendering with tiled buffers requires that the base address of the buffer
948 * be aligned to a page boundary. For renderbuffers, and sometimes with
949 * textures, we may want the surface to point at a texture image level that
950 * isn't at a page boundary.
952 * This function returns an appropriately-aligned base offset
953 * according to the tiling restrictions, plus any required x/y offset
957 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
958 GLuint level
, GLuint slice
,
962 struct intel_region
*region
= mt
->region
;
964 uint32_t mask_x
, mask_y
;
966 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
967 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
969 *tile_x
= x
& mask_x
;
970 *tile_y
= y
& mask_y
;
972 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
977 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
978 struct intel_mipmap_tree
*dst_mt
,
979 struct intel_mipmap_tree
*src_mt
,
986 int src_stride
, dst_stride
;
987 int cpp
= dst_mt
->cpp
;
989 intel_miptree_map(brw
, src_mt
,
993 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
996 intel_miptree_map(brw
, dst_mt
,
1000 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1004 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1005 _mesa_get_format_name(src_mt
->format
),
1006 src_mt
, src
, src_stride
,
1007 _mesa_get_format_name(dst_mt
->format
),
1008 dst_mt
, dst
, dst_stride
,
1011 int row_size
= cpp
* width
;
1012 if (src_stride
== row_size
&&
1013 dst_stride
== row_size
) {
1014 memcpy(dst
, src
, row_size
* height
);
1016 for (int i
= 0; i
< height
; i
++) {
1017 memcpy(dst
, src
, row_size
);
1023 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1024 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1026 /* Don't forget to copy the stencil data over, too. We could have skipped
1027 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1028 * shuffling the two data sources in/out of temporary storage instead of
1029 * the direct mapping we get this way.
1031 if (dst_mt
->stencil_mt
) {
1032 assert(src_mt
->stencil_mt
);
1033 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1034 level
, slice
, width
, height
);
1039 intel_miptree_copy_slice(struct brw_context
*brw
,
1040 struct intel_mipmap_tree
*dst_mt
,
1041 struct intel_mipmap_tree
*src_mt
,
1047 mesa_format format
= src_mt
->format
;
1048 uint32_t width
= minify(src_mt
->physical_width0
, level
);
1049 uint32_t height
= minify(src_mt
->physical_height0
, level
);
1057 assert(depth
< src_mt
->level
[level
].depth
);
1058 assert(src_mt
->format
== dst_mt
->format
);
1060 if (dst_mt
->compressed
) {
1061 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1062 width
= ALIGN(width
, dst_mt
->align_w
);
1065 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1066 * below won't apply since we can't do the depth's Y tiling or the
1067 * stencil's W tiling in the blitter.
1069 if (src_mt
->stencil_mt
) {
1070 intel_miptree_copy_slice_sw(brw
,
1077 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1078 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1079 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1081 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1082 _mesa_get_format_name(src_mt
->format
),
1083 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1084 _mesa_get_format_name(dst_mt
->format
),
1085 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1088 if (!intel_miptree_blit(brw
,
1089 src_mt
, level
, slice
, 0, 0, false,
1090 dst_mt
, level
, slice
, 0, 0, false,
1091 width
, height
, GL_COPY
)) {
1092 perf_debug("miptree validate blit for %s failed\n",
1093 _mesa_get_format_name(format
));
1095 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1101 * Copies the image's current data to the given miptree, and associates that
1102 * miptree with the image.
1104 * If \c invalidate is true, then the actual image data does not need to be
1105 * copied, but the image still needs to be associated to the new miptree (this
1106 * is set to true if we're about to clear the image).
1109 intel_miptree_copy_teximage(struct brw_context
*brw
,
1110 struct intel_texture_image
*intelImage
,
1111 struct intel_mipmap_tree
*dst_mt
,
1114 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1115 struct intel_texture_object
*intel_obj
=
1116 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1117 int level
= intelImage
->base
.Base
.Level
;
1118 int face
= intelImage
->base
.Base
.Face
;
1119 GLuint depth
= intelImage
->base
.Base
.Depth
;
1122 for (int slice
= 0; slice
< depth
; slice
++) {
1123 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1127 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1128 intel_obj
->needs_validate
= true;
1132 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1133 struct intel_mipmap_tree
*mt
,
1136 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1137 assert(mt
->mcs_mt
== NULL
);
1139 /* Choose the correct format for the MCS buffer. All that really matters
1140 * is that we allocate the right buffer size, since we'll always be
1141 * accessing this miptree using MCS-specific hardware mechanisms, which
1142 * infer the correct format based on num_samples.
1145 switch (num_samples
) {
1147 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1150 format
= MESA_FORMAT_R_UNORM8
;
1153 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1154 * for each sample, plus 8 padding bits).
1156 format
= MESA_FORMAT_R_UINT32
;
1159 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1163 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1165 * "The MCS surface must be stored as Tile Y."
1167 mt
->mcs_mt
= intel_miptree_create(brw
,
1173 mt
->logical_height0
,
1176 0 /* num_samples */,
1177 INTEL_MIPTREE_TILING_Y
);
1179 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1181 * When MCS buffer is enabled and bound to MSRT, it is required that it
1182 * is cleared prior to any rendering.
1184 * Since we don't use the MCS buffer for any purpose other than rendering,
1185 * it makes sense to just clear it immediately upon allocation.
1187 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1189 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1190 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1191 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1192 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1199 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1200 struct intel_mipmap_tree
*mt
)
1202 assert(mt
->mcs_mt
== NULL
);
1204 /* The format of the MCS buffer is opaque to the driver; all that matters
1205 * is that we get its size and pitch right. We'll pretend that the format
1206 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1207 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1208 * the block width and then a further factor of 4. Since an MCS tile
1209 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1210 * we'll need to scale the height down by the block height and then a
1211 * further factor of 8.
1213 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1214 unsigned block_width_px
;
1215 unsigned block_height
;
1216 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1217 unsigned width_divisor
= block_width_px
* 4;
1218 unsigned height_divisor
= block_height
* 8;
1219 unsigned mcs_width
=
1220 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1221 unsigned mcs_height
=
1222 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1223 assert(mt
->logical_depth0
== 1);
1224 mt
->mcs_mt
= intel_miptree_create(brw
,
1233 0 /* num_samples */,
1234 INTEL_MIPTREE_TILING_Y
);
1241 * Helper for intel_miptree_alloc_hiz() that sets
1242 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1243 * \c has_hiz was set.
1246 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1247 struct intel_mipmap_tree
*mt
,
1253 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1254 uint32_t width
= minify(mt
->physical_width0
, level
);
1255 uint32_t height
= minify(mt
->physical_height0
, level
);
1257 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1258 * and the height is 4 aligned. This allows our HiZ support
1259 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1260 * we can grow the width & height to allow the HiZ op to
1261 * force the proper size alignments.
1263 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1268 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1275 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1276 struct intel_mipmap_tree
*mt
)
1278 assert(mt
->hiz_mt
== NULL
);
1279 mt
->hiz_mt
= intel_miptree_create(brw
,
1285 mt
->logical_height0
,
1289 INTEL_MIPTREE_TILING_ANY
);
1294 /* Mark that all slices need a HiZ resolve. */
1295 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1296 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1297 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1298 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1301 head
->next
= malloc(sizeof(*head
->next
));
1302 head
->next
->prev
= head
;
1303 head
->next
->next
= NULL
;
1306 head
->level
= level
;
1307 head
->layer
= layer
;
1308 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1316 * Does the miptree slice have hiz enabled?
1319 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1323 intel_miptree_check_level_layer(mt
, level
, layer
);
1324 return mt
->level
[level
].slice
[layer
].has_hiz
;
1328 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1332 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1335 intel_resolve_map_set(&mt
->hiz_map
,
1336 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1341 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1345 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1348 intel_resolve_map_set(&mt
->hiz_map
,
1349 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1353 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1357 uint32_t end_layer
= mt
->level
[level
].depth
;
1359 for (layer
= 0; layer
< end_layer
; layer
++) {
1360 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1365 intel_miptree_slice_resolve(struct brw_context
*brw
,
1366 struct intel_mipmap_tree
*mt
,
1369 enum gen6_hiz_op need
)
1371 intel_miptree_check_level_layer(mt
, level
, layer
);
1373 struct intel_resolve_map
*item
=
1374 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1376 if (!item
|| item
->need
!= need
)
1379 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1380 intel_resolve_map_remove(item
);
1385 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1386 struct intel_mipmap_tree
*mt
,
1390 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1391 GEN6_HIZ_OP_HIZ_RESOLVE
);
1395 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1396 struct intel_mipmap_tree
*mt
,
1400 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1401 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1405 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1406 struct intel_mipmap_tree
*mt
,
1407 enum gen6_hiz_op need
)
1409 bool did_resolve
= false;
1410 struct intel_resolve_map
*i
, *next
;
1412 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1414 if (i
->need
!= need
)
1417 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1418 intel_resolve_map_remove(i
);
1426 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1427 struct intel_mipmap_tree
*mt
)
1429 return intel_miptree_all_slices_resolve(brw
, mt
,
1430 GEN6_HIZ_OP_HIZ_RESOLVE
);
1434 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1435 struct intel_mipmap_tree
*mt
)
1437 return intel_miptree_all_slices_resolve(brw
, mt
,
1438 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1443 intel_miptree_resolve_color(struct brw_context
*brw
,
1444 struct intel_mipmap_tree
*mt
)
1446 switch (mt
->fast_clear_state
) {
1447 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1448 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1449 /* No resolve needed */
1451 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1452 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1453 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1454 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1455 brw_blorp_resolve_color(brw
, mt
);
1462 * Make it possible to share the region backing the given miptree with another
1463 * process or another miptree.
1465 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1466 * then discard the MCS buffer, if present. We also set the fast_clear_state
1467 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1468 * allocated in the future.
1471 intel_miptree_make_shareable(struct brw_context
*brw
,
1472 struct intel_mipmap_tree
*mt
)
1474 /* MCS buffers are also used for multisample buffers, but we can't resolve
1475 * away a multisample MCS buffer because it's an integral part of how the
1476 * pixel data is stored. Fortunately this code path should never be
1477 * reached for multisample buffers.
1479 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1482 intel_miptree_resolve_color(brw
, mt
);
1483 intel_miptree_release(&mt
->mcs_mt
);
1484 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1490 * \brief Get pointer offset into stencil buffer.
1492 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1493 * must decode the tile's layout in software.
1496 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1498 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1500 * Even though the returned offset is always positive, the return type is
1502 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1503 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1506 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1508 uint32_t tile_size
= 4096;
1509 uint32_t tile_width
= 64;
1510 uint32_t tile_height
= 64;
1511 uint32_t row_size
= 64 * stride
;
1513 uint32_t tile_x
= x
/ tile_width
;
1514 uint32_t tile_y
= y
/ tile_height
;
1516 /* The byte's address relative to the tile's base addres. */
1517 uint32_t byte_x
= x
% tile_width
;
1518 uint32_t byte_y
= y
% tile_height
;
1520 uintptr_t u
= tile_y
* row_size
1521 + tile_x
* tile_size
1522 + 512 * (byte_x
/ 8)
1524 + 32 * ((byte_y
/ 4) % 2)
1525 + 16 * ((byte_x
/ 4) % 2)
1526 + 8 * ((byte_y
/ 2) % 2)
1527 + 4 * ((byte_x
/ 2) % 2)
1532 /* adjust for bit6 swizzling */
1533 if (((byte_x
/ 8) % 2) == 1) {
1534 if (((byte_y
/ 8) % 2) == 0) {
1546 intel_miptree_updownsample(struct brw_context
*brw
,
1547 struct intel_mipmap_tree
*src
,
1548 struct intel_mipmap_tree
*dst
)
1550 brw_blorp_blit_miptrees(brw
,
1551 src
, 0 /* level */, 0 /* layer */,
1552 dst
, 0 /* level */, 0 /* layer */,
1554 src
->logical_width0
, src
->logical_height0
,
1556 dst
->logical_width0
, dst
->logical_height0
,
1557 GL_NEAREST
, false, false /*mirror x, y*/);
1559 if (src
->stencil_mt
) {
1560 brw_blorp_blit_miptrees(brw
,
1561 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1562 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1564 src
->logical_width0
, src
->logical_height0
,
1566 dst
->logical_width0
, dst
->logical_height0
,
1567 GL_NEAREST
, false, false /*mirror x, y*/);
1572 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1574 /* CPU accesses to color buffers don't understand fast color clears, so
1575 * resolve any pending fast color clears before we map.
1577 intel_miptree_resolve_color(brw
, mt
);
1579 drm_intel_bo
*bo
= mt
->region
->bo
;
1581 intel_batchbuffer_flush(brw
);
1583 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1584 brw_bo_map_gtt(brw
, bo
, "miptree");
1586 brw_bo_map(brw
, bo
, true, "miptree");
1592 intel_miptree_unmap_raw(struct brw_context
*brw
,
1593 struct intel_mipmap_tree
*mt
)
1595 drm_intel_bo_unmap(mt
->region
->bo
);
1599 intel_miptree_map_gtt(struct brw_context
*brw
,
1600 struct intel_mipmap_tree
*mt
,
1601 struct intel_miptree_map
*map
,
1602 unsigned int level
, unsigned int slice
)
1604 unsigned int bw
, bh
;
1606 unsigned int image_x
, image_y
;
1610 /* For compressed formats, the stride is the number of bytes per
1611 * row of blocks. intel_miptree_get_image_offset() already does
1614 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1615 assert(y
% bh
== 0);
1618 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1623 /* Note that in the case of cube maps, the caller must have passed the
1624 * slice number referencing the face.
1626 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1630 map
->stride
= mt
->region
->pitch
;
1631 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1634 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1635 map
->x
, map
->y
, map
->w
, map
->h
,
1636 mt
, _mesa_get_format_name(mt
->format
),
1637 x
, y
, map
->ptr
, map
->stride
);
1641 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1642 struct intel_mipmap_tree
*mt
,
1643 struct intel_miptree_map
*map
,
1647 intel_miptree_unmap_raw(brw
, mt
);
1651 intel_miptree_map_blit(struct brw_context
*brw
,
1652 struct intel_mipmap_tree
*mt
,
1653 struct intel_miptree_map
*map
,
1654 unsigned int level
, unsigned int slice
)
1656 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1660 INTEL_MIPTREE_TILING_NONE
);
1662 fprintf(stderr
, "Failed to allocate blit temporary\n");
1665 map
->stride
= map
->mt
->region
->pitch
;
1667 if (!intel_miptree_blit(brw
,
1669 map
->x
, map
->y
, false,
1672 map
->w
, map
->h
, GL_COPY
)) {
1673 fprintf(stderr
, "Failed to blit\n");
1677 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1679 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1680 map
->x
, map
->y
, map
->w
, map
->h
,
1681 mt
, _mesa_get_format_name(mt
->format
),
1682 level
, slice
, map
->ptr
, map
->stride
);
1687 intel_miptree_release(&map
->mt
);
1693 intel_miptree_unmap_blit(struct brw_context
*brw
,
1694 struct intel_mipmap_tree
*mt
,
1695 struct intel_miptree_map
*map
,
1699 struct gl_context
*ctx
= &brw
->ctx
;
1701 intel_miptree_unmap_raw(brw
, map
->mt
);
1703 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1704 bool ok
= intel_miptree_blit(brw
,
1708 map
->x
, map
->y
, false,
1709 map
->w
, map
->h
, GL_COPY
);
1710 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1713 intel_miptree_release(&map
->mt
);
1718 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1721 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1722 struct intel_mipmap_tree
*mt
,
1723 struct intel_miptree_map
*map
,
1724 unsigned int level
, unsigned int slice
)
1726 assert(map
->mode
& GL_MAP_READ_BIT
);
1727 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1729 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1730 map
->x
, map
->y
, map
->w
, map
->h
,
1731 mt
, _mesa_get_format_name(mt
->format
),
1732 level
, slice
, map
->ptr
, map
->stride
);
1734 /* Map the original image */
1737 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1741 void *src
= intel_miptree_map_raw(brw
, mt
);
1744 src
+= image_y
* mt
->region
->pitch
;
1745 src
+= image_x
* mt
->region
->cpp
;
1747 /* Due to the pixel offsets for the particular image being mapped, our
1748 * src pointer may not be 16-byte aligned. However, if the pitch is
1749 * divisible by 16, then the amount by which it's misaligned will remain
1750 * consistent from row to row.
1752 assert((mt
->region
->pitch
% 16) == 0);
1753 const int misalignment
= ((uintptr_t) src
) & 15;
1755 /* Create an untiled temporary buffer for the mapping. */
1756 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1758 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1760 map
->buffer
= malloc(map
->stride
* map
->h
);
1761 /* Offset the destination so it has the same misalignment as src. */
1762 map
->ptr
= map
->buffer
+ misalignment
;
1764 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1766 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1767 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1768 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1770 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1773 intel_miptree_unmap_raw(brw
, mt
);
1777 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1778 struct intel_mipmap_tree
*mt
,
1779 struct intel_miptree_map
*map
,
1790 intel_miptree_map_s8(struct brw_context
*brw
,
1791 struct intel_mipmap_tree
*mt
,
1792 struct intel_miptree_map
*map
,
1793 unsigned int level
, unsigned int slice
)
1795 map
->stride
= map
->w
;
1796 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1800 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1801 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1802 * invalidate is set, since we'll be writing the whole rectangle from our
1803 * temporary buffer back out.
1805 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1806 uint8_t *untiled_s8_map
= map
->ptr
;
1807 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1808 unsigned int image_x
, image_y
;
1810 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1812 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1813 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1814 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1815 x
+ image_x
+ map
->x
,
1816 y
+ image_y
+ map
->y
,
1817 brw
->has_swizzling
);
1818 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1822 intel_miptree_unmap_raw(brw
, mt
);
1824 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1825 map
->x
, map
->y
, map
->w
, map
->h
,
1826 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1828 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1829 map
->x
, map
->y
, map
->w
, map
->h
,
1830 mt
, map
->ptr
, map
->stride
);
1835 intel_miptree_unmap_s8(struct brw_context
*brw
,
1836 struct intel_mipmap_tree
*mt
,
1837 struct intel_miptree_map
*map
,
1841 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1842 unsigned int image_x
, image_y
;
1843 uint8_t *untiled_s8_map
= map
->ptr
;
1844 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1846 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1848 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1849 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1850 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1853 brw
->has_swizzling
);
1854 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1858 intel_miptree_unmap_raw(brw
, mt
);
1865 intel_miptree_map_etc(struct brw_context
*brw
,
1866 struct intel_mipmap_tree
*mt
,
1867 struct intel_miptree_map
*map
,
1871 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1872 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1873 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1876 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1877 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1879 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1880 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1881 map
->w
, map
->h
, 1));
1882 map
->ptr
= map
->buffer
;
1886 intel_miptree_unmap_etc(struct brw_context
*brw
,
1887 struct intel_mipmap_tree
*mt
,
1888 struct intel_miptree_map
*map
,
1894 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1899 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
1900 + image_y
* mt
->region
->pitch
1901 + image_x
* mt
->region
->cpp
;
1903 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1904 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1905 map
->ptr
, map
->stride
,
1908 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1909 map
->ptr
, map
->stride
,
1910 map
->w
, map
->h
, mt
->etc_format
);
1912 intel_miptree_unmap_raw(brw
, mt
);
1917 * Mapping function for packed depth/stencil miptrees backed by real separate
1918 * miptrees for depth and stencil.
1920 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1921 * separate from the depth buffer. Yet at the GL API level, we have to expose
1922 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1923 * be able to map that memory for texture storage and glReadPixels-type
1924 * operations. We give Mesa core that access by mallocing a temporary and
1925 * copying the data between the actual backing store and the temporary.
1928 intel_miptree_map_depthstencil(struct brw_context
*brw
,
1929 struct intel_mipmap_tree
*mt
,
1930 struct intel_miptree_map
*map
,
1931 unsigned int level
, unsigned int slice
)
1933 struct intel_mipmap_tree
*z_mt
= mt
;
1934 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1935 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
1936 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1938 map
->stride
= map
->w
* packed_bpp
;
1939 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1943 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1944 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1945 * invalidate is set, since we'll be writing the whole rectangle from our
1946 * temporary buffer back out.
1948 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1949 uint32_t *packed_map
= map
->ptr
;
1950 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1951 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
1952 unsigned int s_image_x
, s_image_y
;
1953 unsigned int z_image_x
, z_image_y
;
1955 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1956 &s_image_x
, &s_image_y
);
1957 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1958 &z_image_x
, &z_image_y
);
1960 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1961 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1962 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1963 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1966 brw
->has_swizzling
);
1967 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1968 (z_mt
->region
->pitch
/ 4) +
1969 (map_x
+ z_image_x
));
1970 uint8_t s
= s_map
[s_offset
];
1971 uint32_t z
= z_map
[z_offset
];
1973 if (map_z32f_x24s8
) {
1974 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1975 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1977 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1982 intel_miptree_unmap_raw(brw
, s_mt
);
1983 intel_miptree_unmap_raw(brw
, z_mt
);
1985 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1987 map
->x
, map
->y
, map
->w
, map
->h
,
1988 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1989 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1990 map
->ptr
, map
->stride
);
1992 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1993 map
->x
, map
->y
, map
->w
, map
->h
,
1994 mt
, map
->ptr
, map
->stride
);
1999 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2000 struct intel_mipmap_tree
*mt
,
2001 struct intel_miptree_map
*map
,
2005 struct intel_mipmap_tree
*z_mt
= mt
;
2006 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2007 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2009 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2010 uint32_t *packed_map
= map
->ptr
;
2011 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2012 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2013 unsigned int s_image_x
, s_image_y
;
2014 unsigned int z_image_x
, z_image_y
;
2016 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2017 &s_image_x
, &s_image_y
);
2018 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2019 &z_image_x
, &z_image_y
);
2021 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2022 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2023 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2024 x
+ s_image_x
+ map
->x
,
2025 y
+ s_image_y
+ map
->y
,
2026 brw
->has_swizzling
);
2027 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2028 (z_mt
->region
->pitch
/ 4) +
2031 if (map_z32f_x24s8
) {
2032 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2033 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2035 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2036 s_map
[s_offset
] = packed
>> 24;
2037 z_map
[z_offset
] = packed
;
2042 intel_miptree_unmap_raw(brw
, s_mt
);
2043 intel_miptree_unmap_raw(brw
, z_mt
);
2045 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2047 map
->x
, map
->y
, map
->w
, map
->h
,
2048 z_mt
, _mesa_get_format_name(z_mt
->format
),
2049 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2050 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2051 map
->ptr
, map
->stride
);
2058 * Create and attach a map to the miptree at (level, slice). Return the
2061 static struct intel_miptree_map
*
2062 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2071 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2076 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2077 mt
->level
[level
].slice
[slice
].map
= map
;
2089 * Release the map at (level, slice).
2092 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2096 struct intel_miptree_map
**map
;
2098 map
= &mt
->level
[level
].slice
[slice
].map
;
2104 can_blit_slice(struct intel_mipmap_tree
*mt
,
2105 unsigned int level
, unsigned int slice
)
2109 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2110 if (image_x
>= 32768 || image_y
>= 32768)
2113 if (mt
->region
->pitch
>= 32768)
2120 intel_miptree_map(struct brw_context
*brw
,
2121 struct intel_mipmap_tree
*mt
,
2132 struct intel_miptree_map
*map
;
2134 assert(mt
->num_samples
<= 1);
2136 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2143 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2144 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2145 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2148 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2149 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2150 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2151 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2152 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2153 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2154 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2156 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2157 else if (brw
->has_llc
&&
2158 !(mode
& GL_MAP_WRITE_BIT
) &&
2160 (mt
->region
->tiling
== I915_TILING_X
||
2161 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2162 can_blit_slice(mt
, level
, slice
)) {
2163 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2164 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2165 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2166 assert(can_blit_slice(mt
, level
, slice
));
2167 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2169 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2170 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2173 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2176 *out_ptr
= map
->ptr
;
2177 *out_stride
= map
->stride
;
2179 if (map
->ptr
== NULL
)
2180 intel_miptree_release_map(mt
, level
, slice
);
2184 intel_miptree_unmap(struct brw_context
*brw
,
2185 struct intel_mipmap_tree
*mt
,
2189 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2191 assert(mt
->num_samples
<= 1);
2196 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2197 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2199 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2200 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2201 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2202 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2203 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2204 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2205 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2206 } else if (map
->mt
) {
2207 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2209 } else if (map
->buffer
) {
2210 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2213 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2216 intel_miptree_release_map(mt
, level
, slice
);