2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
);
53 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
56 intel_miptree_alloc_mcs(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*mt
,
61 * Determine which MSAA layout should be used by the MSAA surface being
62 * created, based on the chip generation and the surface type.
64 static enum intel_msaa_layout
65 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
66 bool disable_aux_buffers
)
68 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
70 return INTEL_MSAA_LAYOUT_IMS
;
72 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
73 switch (_mesa_get_format_base_format(format
)) {
74 case GL_DEPTH_COMPONENT
:
75 case GL_STENCIL_INDEX
:
76 case GL_DEPTH_STENCIL
:
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
81 * This field must be set to 0 for all SINT MSRTs when all RT channels
84 * In practice this means that we have to disable MCS for all signed
85 * integer MSAA buffers. The alternative, to disable MCS only when one
86 * of the render target channels is disabled, is impractical because it
87 * would require converting between CMS and UMS MSAA layouts on the fly,
90 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
91 return INTEL_MSAA_LAYOUT_UMS
;
92 } else if (disable_aux_buffers
) {
93 /* We can't use the CMS layout because it uses an aux buffer, the MCS
94 * buffer. So fallback to UMS, which is identical to CMS without the
96 return INTEL_MSAA_LAYOUT_UMS
;
98 return INTEL_MSAA_LAYOUT_CMS
;
105 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
106 * scaled-down bitfield representation of the color buffer which is capable of
107 * recording when blocks of the color buffer are equal to the clear value.
108 * This function returns the block size that will be used by the MCS buffer
109 * corresponding to a certain color miptree.
111 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
112 * beneath the "Fast Color Clear" bullet (p327):
114 * The following table describes the RT alignment
128 * This alignment has the following uses:
130 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
131 * buffer contains 128 blocks horizontally and 256 blocks vertically.
133 * - For figuring out alignment restrictions for a fast clear operation. Fast
134 * clear operations must always clear aligned multiples of 16 blocks
135 * horizontally and 32 blocks vertically.
137 * - For scaling down the coordinates sent through the render pipeline during
138 * a fast clear. X coordinates must be scaled down by 8 times the block
139 * width, and Y coordinates by 16 times the block height.
141 * - For scaling down the coordinates sent through the render pipeline during
142 * a "Render Target Resolve" operation. X coordinates must be scaled down
143 * by half the block width, and Y coordinates by half the block height.
146 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
147 unsigned *width_px
, unsigned *height
)
149 switch (mt
->tiling
) {
151 unreachable("Non-MSRT MCS requires X or Y tiling");
152 /* In release builds, fall through */
154 *width_px
= 32 / mt
->cpp
;
158 *width_px
= 64 / mt
->cpp
;
164 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
166 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
167 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
171 * Gen9 changes the restriction to Y-tile only.
174 return tiling
== I915_TILING_Y
;
175 else if (brw
->gen
>= 7)
176 return tiling
!= I915_TILING_NONE
;
182 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
183 * can be used. This doesn't (and should not) inspect any of the properties of
186 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
187 * beneath the "Fast Color Clear" bullet (p326):
189 * - Support is for non-mip-mapped and non-array surface types only.
191 * And then later, on p327:
193 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
197 intel_miptree_is_fast_clear_capable(struct brw_context
*brw
,
198 struct intel_mipmap_tree
*mt
)
200 /* MCS support does not exist prior to Gen7 */
204 if (mt
->disable_aux_buffers
)
207 /* MCS is only supported for color buffers */
208 switch (_mesa_get_format_base_format(mt
->format
)) {
209 case GL_DEPTH_COMPONENT
:
210 case GL_DEPTH_STENCIL
:
211 case GL_STENCIL_INDEX
:
215 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
217 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
219 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
220 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
225 if (mt
->physical_depth0
!= 1) {
227 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
228 mt
->logical_width0
, mt
->logical_height0
,
229 mt
->physical_depth0
);
235 /* There's no point in using an MCS buffer if the surface isn't in a
238 if (!brw
->format_supported_as_render_target
[mt
->format
])
246 * Determine depth format corresponding to a depth+stencil format,
247 * for separate stencil.
250 intel_depth_format_for_depthstencil_format(mesa_format format
) {
252 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
253 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 return MESA_FORMAT_Z_FLOAT32
;
263 * @param for_bo Indicates that the caller is
264 * intel_miptree_create_for_bo(). If true, then do not create
267 static struct intel_mipmap_tree
*
268 intel_miptree_create_layout(struct brw_context
*brw
,
277 uint32_t layout_flags
)
279 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
283 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
284 _mesa_enum_to_string(target
),
285 _mesa_get_format_name(format
),
286 first_level
, last_level
, depth0
, mt
);
288 if (target
== GL_TEXTURE_1D_ARRAY
) {
289 /* For a 1D Array texture the OpenGL API will treat the height0
290 * parameter as the number of array slices. For Intel hardware, we treat
291 * the 1D array as a 2D Array with a height of 1.
293 * So, when we first come through this path to create a 1D Array
294 * texture, height0 stores the number of slices, and depth0 is 1. In
295 * this case, we want to swap height0 and depth0.
297 * Since some miptrees will be created based on the base miptree, we may
298 * come through this path and see height0 as 1 and depth0 being the
299 * number of slices. In this case we don't need to do the swap.
301 assert(height0
== 1 || depth0
== 1);
310 mt
->first_level
= first_level
;
311 mt
->last_level
= last_level
;
312 mt
->logical_width0
= width0
;
313 mt
->logical_height0
= height0
;
314 mt
->logical_depth0
= depth0
;
315 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
316 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
317 exec_list_make_empty(&mt
->hiz_map
);
318 mt
->cpp
= _mesa_get_format_bytes(format
);
319 mt
->num_samples
= num_samples
;
320 mt
->compressed
= _mesa_is_format_compressed(format
);
321 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
324 if (num_samples
> 1) {
325 /* Adjust width/height/depth for MSAA */
326 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
327 mt
->disable_aux_buffers
);
328 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
329 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
330 * "If the surface is multisampled and it is a depth or stencil
331 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
332 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
335 * +----------------------------------------------------------------+
336 * | Num Multisamples | W_l = | H_l = |
337 * +----------------------------------------------------------------+
338 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
339 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
340 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
341 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
342 * +----------------------------------------------------------------+
345 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
346 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
347 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
349 * Another more complicated explanation for these adjustments comes
350 * from the Sandybridge PRM, volume 4, part 1, page 31:
352 * "Any of the other messages (sample*, LOD, load4) used with a
353 * (4x) multisampled surface will in-effect sample a surface with
354 * double the height and width as that indicated in the surface
355 * state. Each pixel position on the original-sized surface is
356 * replaced with a 2x2 of samples with the following arrangement:
361 * Thus, when sampling from a multisampled texture, it behaves as
362 * though the layout in memory for (x,y,sample) is:
364 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
365 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
367 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
368 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
370 * However, the actual layout of multisampled data in memory is:
372 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
373 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
375 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
376 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
378 * This pattern repeats for each 2x2 pixel block.
380 * As a result, when calculating the size of our 4-sample buffer for
381 * an odd width or height, we have to align before scaling up because
382 * sample 3 is in that bottom right 2x2 block.
384 switch (num_samples
) {
386 assert(brw
->gen
>= 8);
387 width0
= ALIGN(width0
, 2) * 2;
388 height0
= ALIGN(height0
, 2);
391 width0
= ALIGN(width0
, 2) * 2;
392 height0
= ALIGN(height0
, 2) * 2;
395 width0
= ALIGN(width0
, 2) * 4;
396 height0
= ALIGN(height0
, 2) * 2;
399 /* num_samples should already have been quantized to 0, 1, 2, 4, or
402 unreachable("not reached");
405 /* Non-interleaved */
406 depth0
*= num_samples
;
410 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
411 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
412 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
413 * used on Gen8 to make it pick a qpitch value which doesn't include space
414 * for the mipmaps. On Gen9 this is not necessary because it will
415 * automatically pick a packed qpitch value whenever mt->first_level ==
417 * TODO: can we use it elsewhere?
418 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
421 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
423 switch (mt
->msaa_layout
) {
424 case INTEL_MSAA_LAYOUT_NONE
:
425 case INTEL_MSAA_LAYOUT_IMS
:
426 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
428 case INTEL_MSAA_LAYOUT_UMS
:
429 case INTEL_MSAA_LAYOUT_CMS
:
430 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
435 if (target
== GL_TEXTURE_CUBE_MAP
) {
440 mt
->physical_width0
= width0
;
441 mt
->physical_height0
= height0
;
442 mt
->physical_depth0
= depth0
;
444 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
445 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
446 (brw
->must_use_separate_stencil
||
447 (brw
->has_separate_stencil
&&
448 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
449 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
451 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
452 MIPTREE_LAYOUT_TILING_ANY
;
455 mt
->stencil_mt
= intel_miptree_create(brw
,
466 if (!mt
->stencil_mt
) {
467 intel_miptree_release(&mt
);
471 /* Fix up the Z miptree format for how we're splitting out separate
472 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
474 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
477 if (format
== mt
->format
) {
478 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
479 _mesa_get_format_name(mt
->format
));
483 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
484 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
487 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
488 * multisampled or have an AUX buffer attached to it.
490 * GEN | MSRT | AUX_CCS_* or AUX_MCS
491 * -------------------------------------------
492 * 9 | HALIGN_16 | HALIGN_16
493 * 8 | HALIGN_ANY | HALIGN_16
497 if (intel_miptree_is_fast_clear_capable(brw
, mt
)) {
498 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
499 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
500 } else if (brw
->gen
>= 9 && num_samples
> 1) {
501 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
503 /* For now, nothing else has this requirement */
504 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
507 brw_miptree_layout(brw
, mt
, layout_flags
);
509 if (mt
->disable_aux_buffers
)
510 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
517 * Choose an appropriate uncompressed format for a requested
518 * compressed format, if unsupported.
521 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
523 /* No need to lower ETC formats on these platforms,
524 * they are supported natively.
526 if (brw
->gen
>= 8 || brw
->is_baytrail
)
530 case MESA_FORMAT_ETC1_RGB8
:
531 return MESA_FORMAT_R8G8B8X8_UNORM
;
532 case MESA_FORMAT_ETC2_RGB8
:
533 return MESA_FORMAT_R8G8B8X8_UNORM
;
534 case MESA_FORMAT_ETC2_SRGB8
:
535 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
536 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
537 return MESA_FORMAT_B8G8R8A8_SRGB
;
538 case MESA_FORMAT_ETC2_RGBA8_EAC
:
539 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
540 return MESA_FORMAT_R8G8B8A8_UNORM
;
541 case MESA_FORMAT_ETC2_R11_EAC
:
542 return MESA_FORMAT_R_UNORM16
;
543 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
544 return MESA_FORMAT_R_SNORM16
;
545 case MESA_FORMAT_ETC2_RG11_EAC
:
546 return MESA_FORMAT_R16G16_UNORM
;
547 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
548 return MESA_FORMAT_R16G16_SNORM
;
550 /* Non ETC1 / ETC2 format */
555 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
557 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
558 unsigned long *pitch
)
560 const uint32_t bpp
= mt
->cpp
* 8;
561 const uint32_t aspect_ratio
= (bpp
== 16 || bpp
== 64) ? 2 : 1;
562 uint32_t tile_width
, tile_height
;
563 unsigned long stride
, size
, aligned_y
;
565 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
580 unreachable("not reached");
583 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
586 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
587 stride
= mt
->total_width
* mt
->cpp
;
588 tile_width
= tile_height
* mt
->cpp
* aspect_ratio
;
589 stride
= ALIGN(stride
, tile_width
);
590 size
= stride
* aligned_y
;
592 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
593 assert(size
% 4096 == 0);
596 assert(size
% (64 * 1024) == 0);
597 *alignment
= 64 * 1024;
603 struct intel_mipmap_tree
*
604 intel_miptree_create(struct brw_context
*brw
,
613 uint32_t layout_flags
)
615 struct intel_mipmap_tree
*mt
;
616 mesa_format tex_format
= format
;
617 mesa_format etc_format
= MESA_FORMAT_NONE
;
618 GLuint total_width
, total_height
;
619 uint32_t alloc_flags
= 0;
621 format
= intel_lower_compressed_format(brw
, format
);
623 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
625 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
626 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
627 mt
= intel_miptree_create_layout(brw
, target
, format
,
628 first_level
, last_level
, width0
,
629 height0
, depth0
, num_samples
,
632 * pitch == 0 || height == 0 indicates the null texture
634 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
635 intel_miptree_release(&mt
);
639 total_width
= mt
->total_width
;
640 total_height
= mt
->total_height
;
642 if (format
== MESA_FORMAT_S_UINT8
) {
643 /* Align to size of W tile, 64x64. */
644 total_width
= ALIGN(total_width
, 64);
645 total_height
= ALIGN(total_height
, 64);
650 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
652 mt
->tiling
= I915_TILING_Y
;
655 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
656 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
659 mt
->etc_format
= etc_format
;
661 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
662 unsigned alignment
= 0;
664 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
666 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
669 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
670 total_width
, total_height
, mt
->cpp
,
677 /* If the BO is too large to fit in the aperture, we need to use the
678 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
679 * handle Y-tiling, so we need to fall back to X.
681 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
682 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
683 mt
->total_width
, mt
->total_height
);
685 mt
->tiling
= I915_TILING_X
;
686 drm_intel_bo_unreference(mt
->bo
);
687 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
688 total_width
, total_height
, mt
->cpp
,
689 &mt
->tiling
, &pitch
, alloc_flags
);
696 intel_miptree_release(&mt
);
701 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
702 assert(mt
->num_samples
> 1);
703 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
704 intel_miptree_release(&mt
);
709 /* If this miptree is capable of supporting fast color clears, set
710 * fast_clear_state appropriately to ensure that fast clears will occur.
711 * Allocation of the MCS miptree will be deferred until the first fast
712 * clear actually occurs.
714 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
715 intel_miptree_is_fast_clear_capable(brw
, mt
)) {
716 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
717 assert(brw
->gen
< 8 || mt
->align_w
== 16 || num_samples
<= 1);
723 struct intel_mipmap_tree
*
724 intel_miptree_create_for_bo(struct brw_context
*brw
,
732 uint32_t layout_flags
)
734 struct intel_mipmap_tree
*mt
;
735 uint32_t tiling
, swizzle
;
738 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
740 /* Nothing will be able to use this miptree with the BO if the offset isn't
743 if (tiling
!= I915_TILING_NONE
)
744 assert(offset
% 4096 == 0);
746 /* miptrees can't handle negative pitch. If you need flipping of images,
747 * that's outside of the scope of the mt.
751 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
753 /* The BO already has a tiling format and we shouldn't confuse the lower
754 * layers by making it try to find a tiling format again.
756 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
757 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
759 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
760 mt
= intel_miptree_create_layout(brw
, target
, format
,
762 width
, height
, depth
, 0,
767 drm_intel_bo_reference(bo
);
777 * For a singlesample renderbuffer, this simply wraps the given BO with a
780 * For a multisample renderbuffer, this wraps the window system's
781 * (singlesample) BO with a singlesample miptree attached to the
782 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
783 * that will contain the actual rendering (which is lazily resolved to
784 * irb->singlesample_mt).
787 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
788 struct intel_renderbuffer
*irb
,
790 uint32_t width
, uint32_t height
,
793 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
794 struct intel_mipmap_tree
*multisample_mt
= NULL
;
795 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
796 mesa_format format
= rb
->Format
;
797 int num_samples
= rb
->NumSamples
;
799 /* Only the front and back buffers, which are color buffers, are allocated
800 * through the image loader.
802 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
803 _mesa_get_format_base_format(format
) == GL_RGBA
);
805 singlesample_mt
= intel_miptree_create_for_bo(intel
,
814 if (!singlesample_mt
)
817 /* If this miptree is capable of supporting fast color clears, set
818 * mcs_state appropriately to ensure that fast clears will occur.
819 * Allocation of the MCS miptree will be deferred until the first fast
820 * clear actually occurs.
822 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
823 intel_miptree_is_fast_clear_capable(intel
, singlesample_mt
))
824 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
826 if (num_samples
== 0) {
827 intel_miptree_release(&irb
->mt
);
828 irb
->mt
= singlesample_mt
;
830 assert(!irb
->singlesample_mt
);
832 intel_miptree_release(&irb
->singlesample_mt
);
833 irb
->singlesample_mt
= singlesample_mt
;
836 irb
->mt
->logical_width0
!= width
||
837 irb
->mt
->logical_height0
!= height
) {
838 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
846 irb
->need_downsample
= false;
847 intel_miptree_release(&irb
->mt
);
848 irb
->mt
= multisample_mt
;
854 intel_miptree_release(&irb
->singlesample_mt
);
855 intel_miptree_release(&irb
->mt
);
859 struct intel_mipmap_tree
*
860 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
864 uint32_t num_samples
)
866 struct intel_mipmap_tree
*mt
;
869 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
870 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
871 MIPTREE_LAYOUT_TILING_ANY
;
874 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
875 width
, height
, depth
, num_samples
,
880 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
881 ok
= intel_miptree_alloc_hiz(brw
, mt
);
889 intel_miptree_release(&mt
);
894 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
895 struct intel_mipmap_tree
*src
)
900 intel_miptree_release(dst
);
904 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
912 intel_miptree_release(struct intel_mipmap_tree
**mt
)
917 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
918 if (--(*mt
)->refcount
<= 0) {
921 DBG("%s deleting %p\n", __func__
, *mt
);
923 drm_intel_bo_unreference((*mt
)->bo
);
924 intel_miptree_release(&(*mt
)->stencil_mt
);
925 if ((*mt
)->hiz_buf
) {
926 if ((*mt
)->hiz_buf
->mt
)
927 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
929 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
930 free((*mt
)->hiz_buf
);
932 intel_miptree_release(&(*mt
)->mcs_mt
);
933 intel_resolve_map_clear(&(*mt
)->hiz_map
);
935 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
936 free((*mt
)->level
[i
].slice
);
945 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
946 int *width
, int *height
, int *depth
)
948 switch (image
->TexObject
->Target
) {
949 case GL_TEXTURE_1D_ARRAY
:
950 *width
= image
->Width
;
952 *depth
= image
->Height
;
955 *width
= image
->Width
;
956 *height
= image
->Height
;
957 *depth
= image
->Depth
;
963 * Can the image be pulled into a unified mipmap tree? This mirrors
964 * the completeness test in a lot of ways.
966 * Not sure whether I want to pass gl_texture_image here.
969 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
970 struct gl_texture_image
*image
)
972 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
973 GLuint level
= intelImage
->base
.Base
.Level
;
974 int width
, height
, depth
;
976 /* glTexImage* choose the texture object based on the target passed in, and
977 * objects can't change targets over their lifetimes, so this should be
980 assert(image
->TexObject
->Target
== mt
->target
);
982 mesa_format mt_format
= mt
->format
;
983 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
984 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
985 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
986 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
987 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
988 mt_format
= mt
->etc_format
;
990 if (image
->TexFormat
!= mt_format
)
993 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
995 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
998 int level_depth
= mt
->level
[level
].depth
;
999 if (mt
->num_samples
> 1) {
1000 switch (mt
->msaa_layout
) {
1001 case INTEL_MSAA_LAYOUT_NONE
:
1002 case INTEL_MSAA_LAYOUT_IMS
:
1004 case INTEL_MSAA_LAYOUT_UMS
:
1005 case INTEL_MSAA_LAYOUT_CMS
:
1006 level_depth
/= mt
->num_samples
;
1011 /* Test image dimensions against the base level image adjusted for
1012 * minification. This will also catch images not present in the
1013 * tree, changed targets, etc.
1015 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1016 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1017 depth
!= level_depth
) {
1021 if (image
->NumSamples
!= mt
->num_samples
)
1029 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1031 GLuint x
, GLuint y
, GLuint d
)
1033 mt
->level
[level
].depth
= d
;
1034 mt
->level
[level
].level_x
= x
;
1035 mt
->level
[level
].level_y
= y
;
1037 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1040 assert(mt
->level
[level
].slice
== NULL
);
1042 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1043 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1044 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1049 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1050 GLuint level
, GLuint img
,
1053 if (img
== 0 && level
== 0)
1054 assert(x
== 0 && y
== 0);
1056 assert(img
< mt
->level
[level
].depth
);
1058 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1059 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1061 DBG("%s level %d img %d pos %d,%d\n",
1062 __func__
, level
, img
,
1063 mt
->level
[level
].slice
[img
].x_offset
,
1064 mt
->level
[level
].slice
[img
].y_offset
);
1068 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1069 GLuint level
, GLuint slice
,
1070 GLuint
*x
, GLuint
*y
)
1072 assert(slice
< mt
->level
[level
].depth
);
1074 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1075 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1079 * This function computes masks that may be used to select the bits of the X
1080 * and Y coordinates that indicate the offset within a tile. If the BO is
1081 * untiled, the masks are set to 0.
1084 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1085 uint32_t *mask_x
, uint32_t *mask_y
,
1086 bool map_stencil_as_y_tiled
)
1089 uint32_t tiling
= mt
->tiling
;
1091 if (map_stencil_as_y_tiled
)
1092 tiling
= I915_TILING_Y
;
1096 unreachable("not reached");
1097 case I915_TILING_NONE
:
1098 *mask_x
= *mask_y
= 0;
1101 *mask_x
= 512 / cpp
- 1;
1105 *mask_x
= 128 / cpp
- 1;
1112 * Compute the offset (in bytes) from the start of the BO to the given x
1113 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1114 * multiples of the tile size.
1117 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1118 uint32_t x
, uint32_t y
,
1119 bool map_stencil_as_y_tiled
)
1122 uint32_t pitch
= mt
->pitch
;
1123 uint32_t tiling
= mt
->tiling
;
1125 if (map_stencil_as_y_tiled
) {
1126 tiling
= I915_TILING_Y
;
1128 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1129 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1130 * the resulting surface is twice the pitch of the original miptree,
1131 * since each row in the Y-tiled view corresponds to two rows in the
1132 * actual W-tiled surface. So we need to correct the pitch before
1133 * computing the offsets.
1140 unreachable("not reached");
1141 case I915_TILING_NONE
:
1142 return y
* pitch
+ x
* cpp
;
1144 assert((x
% (512 / cpp
)) == 0);
1145 assert((y
% 8) == 0);
1146 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1148 assert((x
% (128 / cpp
)) == 0);
1149 assert((y
% 32) == 0);
1150 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1155 * Rendering with tiled buffers requires that the base address of the buffer
1156 * be aligned to a page boundary. For renderbuffers, and sometimes with
1157 * textures, we may want the surface to point at a texture image level that
1158 * isn't at a page boundary.
1160 * This function returns an appropriately-aligned base offset
1161 * according to the tiling restrictions, plus any required x/y offset
1165 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1166 GLuint level
, GLuint slice
,
1171 uint32_t mask_x
, mask_y
;
1173 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1174 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1176 *tile_x
= x
& mask_x
;
1177 *tile_y
= y
& mask_y
;
1179 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1183 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1184 struct intel_mipmap_tree
*dst_mt
,
1185 struct intel_mipmap_tree
*src_mt
,
1192 ptrdiff_t src_stride
, dst_stride
;
1193 int cpp
= dst_mt
->cpp
;
1195 intel_miptree_map(brw
, src_mt
,
1199 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1202 intel_miptree_map(brw
, dst_mt
,
1206 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1210 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1211 _mesa_get_format_name(src_mt
->format
),
1212 src_mt
, src
, src_stride
,
1213 _mesa_get_format_name(dst_mt
->format
),
1214 dst_mt
, dst
, dst_stride
,
1217 int row_size
= cpp
* width
;
1218 if (src_stride
== row_size
&&
1219 dst_stride
== row_size
) {
1220 memcpy(dst
, src
, row_size
* height
);
1222 for (int i
= 0; i
< height
; i
++) {
1223 memcpy(dst
, src
, row_size
);
1229 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1230 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1232 /* Don't forget to copy the stencil data over, too. We could have skipped
1233 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1234 * shuffling the two data sources in/out of temporary storage instead of
1235 * the direct mapping we get this way.
1237 if (dst_mt
->stencil_mt
) {
1238 assert(src_mt
->stencil_mt
);
1239 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1240 level
, slice
, width
, height
);
1245 intel_miptree_copy_slice(struct brw_context
*brw
,
1246 struct intel_mipmap_tree
*dst_mt
,
1247 struct intel_mipmap_tree
*src_mt
,
1253 mesa_format format
= src_mt
->format
;
1254 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1255 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1263 assert(depth
< src_mt
->level
[level
].depth
);
1264 assert(src_mt
->format
== dst_mt
->format
);
1266 if (dst_mt
->compressed
) {
1268 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1269 height
= ALIGN_NPOT(height
, j
) / j
;
1270 width
= ALIGN_NPOT(width
, i
) / i
;
1273 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1274 * below won't apply since we can't do the depth's Y tiling or the
1275 * stencil's W tiling in the blitter.
1277 if (src_mt
->stencil_mt
) {
1278 intel_miptree_copy_slice_sw(brw
,
1285 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1286 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1287 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1289 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1290 _mesa_get_format_name(src_mt
->format
),
1291 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1292 _mesa_get_format_name(dst_mt
->format
),
1293 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1296 if (!intel_miptree_blit(brw
,
1297 src_mt
, level
, slice
, 0, 0, false,
1298 dst_mt
, level
, slice
, 0, 0, false,
1299 width
, height
, GL_COPY
)) {
1300 perf_debug("miptree validate blit for %s failed\n",
1301 _mesa_get_format_name(format
));
1303 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1309 * Copies the image's current data to the given miptree, and associates that
1310 * miptree with the image.
1312 * If \c invalidate is true, then the actual image data does not need to be
1313 * copied, but the image still needs to be associated to the new miptree (this
1314 * is set to true if we're about to clear the image).
1317 intel_miptree_copy_teximage(struct brw_context
*brw
,
1318 struct intel_texture_image
*intelImage
,
1319 struct intel_mipmap_tree
*dst_mt
,
1322 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1323 struct intel_texture_object
*intel_obj
=
1324 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1325 int level
= intelImage
->base
.Base
.Level
;
1326 int face
= intelImage
->base
.Base
.Face
;
1329 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1330 depth
= intelImage
->base
.Base
.Height
;
1332 depth
= intelImage
->base
.Base
.Depth
;
1335 for (int slice
= 0; slice
< depth
; slice
++) {
1336 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1340 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1341 intel_obj
->needs_validate
= true;
1345 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1346 struct intel_mipmap_tree
*mt
,
1349 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1350 assert(mt
->mcs_mt
== NULL
);
1351 assert(!mt
->disable_aux_buffers
);
1353 /* Choose the correct format for the MCS buffer. All that really matters
1354 * is that we allocate the right buffer size, since we'll always be
1355 * accessing this miptree using MCS-specific hardware mechanisms, which
1356 * infer the correct format based on num_samples.
1359 switch (num_samples
) {
1362 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1365 format
= MESA_FORMAT_R_UNORM8
;
1368 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1369 * for each sample, plus 8 padding bits).
1371 format
= MESA_FORMAT_R_UINT32
;
1374 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1377 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1379 * "The MCS surface must be stored as Tile Y."
1381 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1382 MIPTREE_LAYOUT_TILING_Y
;
1383 mt
->mcs_mt
= intel_miptree_create(brw
,
1389 mt
->logical_height0
,
1391 0 /* num_samples */,
1394 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1396 * When MCS buffer is enabled and bound to MSRT, it is required that it
1397 * is cleared prior to any rendering.
1399 * Since we don't use the MCS buffer for any purpose other than rendering,
1400 * it makes sense to just clear it immediately upon allocation.
1402 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1404 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1405 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1406 intel_miptree_unmap_raw(mt
->mcs_mt
);
1407 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1414 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1415 struct intel_mipmap_tree
*mt
)
1417 assert(mt
->mcs_mt
== NULL
);
1418 assert(!mt
->disable_aux_buffers
);
1420 /* The format of the MCS buffer is opaque to the driver; all that matters
1421 * is that we get its size and pitch right. We'll pretend that the format
1422 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1423 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1424 * the block width and then a further factor of 4. Since an MCS tile
1425 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1426 * we'll need to scale the height down by the block height and then a
1427 * further factor of 8.
1429 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1430 unsigned block_width_px
;
1431 unsigned block_height
;
1432 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1433 unsigned width_divisor
= block_width_px
* 4;
1434 unsigned height_divisor
= block_height
* 8;
1435 unsigned mcs_width
=
1436 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1437 unsigned mcs_height
=
1438 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1439 assert(mt
->logical_depth0
== 1);
1440 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1441 MIPTREE_LAYOUT_TILING_Y
;
1442 if (brw
->gen
>= 8) {
1443 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1445 mt
->mcs_mt
= intel_miptree_create(brw
,
1453 0 /* num_samples */,
1461 * Helper for intel_miptree_alloc_hiz() that sets
1462 * \c mt->level[level].has_hiz. Return true if and only if
1463 * \c has_hiz was set.
1466 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1467 struct intel_mipmap_tree
*mt
,
1470 assert(mt
->hiz_buf
);
1472 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1473 uint32_t width
= minify(mt
->physical_width0
, level
);
1474 uint32_t height
= minify(mt
->physical_height0
, level
);
1476 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1477 * and the height is 4 aligned. This allows our HiZ support
1478 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1479 * we can grow the width & height to allow the HiZ op to
1480 * force the proper size alignments.
1482 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1483 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1488 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1489 mt
->level
[level
].has_hiz
= true;
1495 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1496 * buffer dimensions and allocates a bo for the hiz buffer.
1498 static struct intel_miptree_aux_buffer
*
1499 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1500 struct intel_mipmap_tree
*mt
)
1502 unsigned z_width
= mt
->logical_width0
;
1503 unsigned z_height
= mt
->logical_height0
;
1504 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1505 unsigned hz_width
, hz_height
;
1506 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1511 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1512 * adjustments required for Z_Height and Z_Width based on multisampling.
1514 switch (mt
->num_samples
) {
1528 unreachable("unsupported sample count");
1531 const unsigned vertical_align
= 8; /* 'j' in the docs */
1532 const unsigned H0
= z_height
;
1533 const unsigned h0
= ALIGN(H0
, vertical_align
);
1534 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1535 const unsigned Z0
= z_depth
;
1537 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1538 hz_width
= ALIGN(z_width
, 16);
1540 if (mt
->target
== GL_TEXTURE_3D
) {
1544 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1545 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1546 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1547 hz_height
+= h_i
* Z_i
;
1548 H_i
= minify(H_i
, 1);
1549 Z_i
= minify(Z_i
, 1);
1552 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1554 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1556 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1557 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1558 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1559 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1560 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1562 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1563 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1567 unsigned long pitch
;
1568 uint32_t tiling
= I915_TILING_Y
;
1569 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1570 hz_width
, hz_height
, 1,
1572 BO_ALLOC_FOR_RENDER
);
1576 } else if (tiling
!= I915_TILING_Y
) {
1577 drm_intel_bo_unreference(buf
->bo
);
1589 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1590 * buffer dimensions and allocates a bo for the hiz buffer.
1592 static struct intel_miptree_aux_buffer
*
1593 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1594 struct intel_mipmap_tree
*mt
)
1596 unsigned z_width
= mt
->logical_width0
;
1597 unsigned z_height
= mt
->logical_height0
;
1598 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1599 unsigned hz_width
, hz_height
;
1600 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1605 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1606 * adjustments required for Z_Height and Z_Width based on multisampling.
1609 switch (mt
->num_samples
) {
1623 unreachable("unsupported sample count");
1627 const unsigned vertical_align
= 8; /* 'j' in the docs */
1628 const unsigned H0
= z_height
;
1629 const unsigned h0
= ALIGN(H0
, vertical_align
);
1630 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1631 const unsigned Z0
= z_depth
;
1633 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1634 hz_width
= ALIGN(z_width
, 16);
1638 unsigned sum_h_i
= 0;
1639 unsigned hz_height_3d_sum
= 0;
1640 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1641 unsigned i
= level
- mt
->first_level
;
1642 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1643 /* sum(i=2 to m; h_i) */
1647 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1648 hz_height_3d_sum
+= h_i
* Z_i
;
1649 H_i
= minify(H_i
, 1);
1650 Z_i
= minify(Z_i
, 1);
1652 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1653 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1655 if (mt
->target
== GL_TEXTURE_3D
) {
1656 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1657 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1659 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1660 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1661 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1662 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1663 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1665 * We can can just take our hz_height calculation from above, and
1666 * multiply by 6 for the cube map and cube map array types.
1672 unsigned long pitch
;
1673 uint32_t tiling
= I915_TILING_Y
;
1674 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1675 hz_width
, hz_height
, 1,
1677 BO_ALLOC_FOR_RENDER
);
1681 } else if (tiling
!= I915_TILING_Y
) {
1682 drm_intel_bo_unreference(buf
->bo
);
1693 static struct intel_miptree_aux_buffer
*
1694 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1695 struct intel_mipmap_tree
*mt
)
1697 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1698 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1701 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1706 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1707 buf
->mt
= intel_miptree_create(brw
,
1713 mt
->logical_height0
,
1722 buf
->bo
= buf
->mt
->bo
;
1723 buf
->pitch
= buf
->mt
->pitch
;
1724 buf
->qpitch
= buf
->mt
->qpitch
;
1730 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1731 struct intel_mipmap_tree
*mt
)
1736 if (mt
->hiz_buf
!= NULL
)
1739 if (mt
->disable_aux_buffers
)
1742 switch (mt
->format
) {
1743 case MESA_FORMAT_Z_FLOAT32
:
1744 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1745 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1746 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1747 case MESA_FORMAT_Z_UNORM16
:
1755 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1756 struct intel_mipmap_tree
*mt
)
1758 assert(mt
->hiz_buf
== NULL
);
1759 assert(!mt
->disable_aux_buffers
);
1761 if (brw
->gen
== 7) {
1762 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1763 } else if (brw
->gen
>= 8) {
1764 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1766 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1772 /* Mark that all slices need a HiZ resolve. */
1773 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1774 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1777 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1778 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1779 exec_node_init(&m
->link
);
1782 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1784 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1792 * Does the miptree slice have hiz enabled?
1795 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1797 intel_miptree_check_level_layer(mt
, level
, 0);
1798 return mt
->level
[level
].has_hiz
;
1802 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1806 if (!intel_miptree_level_has_hiz(mt
, level
))
1809 intel_resolve_map_set(&mt
->hiz_map
,
1810 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1815 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1819 if (!intel_miptree_level_has_hiz(mt
, level
))
1822 intel_resolve_map_set(&mt
->hiz_map
,
1823 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1827 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1831 uint32_t end_layer
= mt
->level
[level
].depth
;
1833 for (layer
= 0; layer
< end_layer
; layer
++) {
1834 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1839 intel_miptree_slice_resolve(struct brw_context
*brw
,
1840 struct intel_mipmap_tree
*mt
,
1843 enum gen6_hiz_op need
)
1845 intel_miptree_check_level_layer(mt
, level
, layer
);
1847 struct intel_resolve_map
*item
=
1848 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1850 if (!item
|| item
->need
!= need
)
1853 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1854 intel_resolve_map_remove(item
);
1859 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1860 struct intel_mipmap_tree
*mt
,
1864 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1865 GEN6_HIZ_OP_HIZ_RESOLVE
);
1869 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1870 struct intel_mipmap_tree
*mt
,
1874 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1875 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1879 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1880 struct intel_mipmap_tree
*mt
,
1881 enum gen6_hiz_op need
)
1883 bool did_resolve
= false;
1885 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1886 if (map
->need
!= need
)
1889 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1890 intel_resolve_map_remove(map
);
1898 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1899 struct intel_mipmap_tree
*mt
)
1901 return intel_miptree_all_slices_resolve(brw
, mt
,
1902 GEN6_HIZ_OP_HIZ_RESOLVE
);
1906 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1907 struct intel_mipmap_tree
*mt
)
1909 return intel_miptree_all_slices_resolve(brw
, mt
,
1910 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1915 intel_miptree_resolve_color(struct brw_context
*brw
,
1916 struct intel_mipmap_tree
*mt
)
1918 switch (mt
->fast_clear_state
) {
1919 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1920 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1921 /* No resolve needed */
1923 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1924 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1925 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1926 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1927 brw_meta_resolve_color(brw
, mt
);
1934 * Make it possible to share the BO backing the given miptree with another
1935 * process or another miptree.
1937 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1938 * then discard the MCS buffer, if present. We also set the fast_clear_state
1939 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1940 * allocated in the future.
1943 intel_miptree_make_shareable(struct brw_context
*brw
,
1944 struct intel_mipmap_tree
*mt
)
1946 /* MCS buffers are also used for multisample buffers, but we can't resolve
1947 * away a multisample MCS buffer because it's an integral part of how the
1948 * pixel data is stored. Fortunately this code path should never be
1949 * reached for multisample buffers.
1951 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1954 intel_miptree_resolve_color(brw
, mt
);
1955 intel_miptree_release(&mt
->mcs_mt
);
1956 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1962 * \brief Get pointer offset into stencil buffer.
1964 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1965 * must decode the tile's layout in software.
1968 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1970 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1972 * Even though the returned offset is always positive, the return type is
1974 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1975 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1978 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1980 uint32_t tile_size
= 4096;
1981 uint32_t tile_width
= 64;
1982 uint32_t tile_height
= 64;
1983 uint32_t row_size
= 64 * stride
;
1985 uint32_t tile_x
= x
/ tile_width
;
1986 uint32_t tile_y
= y
/ tile_height
;
1988 /* The byte's address relative to the tile's base addres. */
1989 uint32_t byte_x
= x
% tile_width
;
1990 uint32_t byte_y
= y
% tile_height
;
1992 uintptr_t u
= tile_y
* row_size
1993 + tile_x
* tile_size
1994 + 512 * (byte_x
/ 8)
1996 + 32 * ((byte_y
/ 4) % 2)
1997 + 16 * ((byte_x
/ 4) % 2)
1998 + 8 * ((byte_y
/ 2) % 2)
1999 + 4 * ((byte_x
/ 2) % 2)
2004 /* adjust for bit6 swizzling */
2005 if (((byte_x
/ 8) % 2) == 1) {
2006 if (((byte_y
/ 8) % 2) == 0) {
2018 intel_miptree_updownsample(struct brw_context
*brw
,
2019 struct intel_mipmap_tree
*src
,
2020 struct intel_mipmap_tree
*dst
)
2023 brw_blorp_blit_miptrees(brw
,
2024 src
, 0 /* level */, 0 /* layer */, src
->format
,
2025 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2027 src
->logical_width0
, src
->logical_height0
,
2029 dst
->logical_width0
, dst
->logical_height0
,
2030 GL_NEAREST
, false, false /*mirror x, y*/);
2031 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2032 brw_meta_stencil_updownsample(brw
, src
, dst
);
2034 brw_meta_updownsample(brw
, src
, dst
);
2037 if (src
->stencil_mt
) {
2038 if (brw
->gen
>= 8) {
2039 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2043 brw_blorp_blit_miptrees(brw
,
2044 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2045 src
->stencil_mt
->format
,
2046 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2047 dst
->stencil_mt
->format
,
2049 src
->logical_width0
, src
->logical_height0
,
2051 dst
->logical_width0
, dst
->logical_height0
,
2052 GL_NEAREST
, false, false /*mirror x, y*/);
2057 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2059 /* CPU accesses to color buffers don't understand fast color clears, so
2060 * resolve any pending fast color clears before we map.
2062 intel_miptree_resolve_color(brw
, mt
);
2064 drm_intel_bo
*bo
= mt
->bo
;
2066 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2067 intel_batchbuffer_flush(brw
);
2069 if (mt
->tiling
!= I915_TILING_NONE
)
2070 brw_bo_map_gtt(brw
, bo
, "miptree");
2072 brw_bo_map(brw
, bo
, true, "miptree");
2078 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2080 drm_intel_bo_unmap(mt
->bo
);
2084 intel_miptree_map_gtt(struct brw_context
*brw
,
2085 struct intel_mipmap_tree
*mt
,
2086 struct intel_miptree_map
*map
,
2087 unsigned int level
, unsigned int slice
)
2089 unsigned int bw
, bh
;
2091 unsigned int image_x
, image_y
;
2092 intptr_t x
= map
->x
;
2093 intptr_t y
= map
->y
;
2095 /* For compressed formats, the stride is the number of bytes per
2096 * row of blocks. intel_miptree_get_image_offset() already does
2099 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2100 assert(y
% bh
== 0);
2101 assert(x
% bw
== 0);
2105 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2110 /* Note that in the case of cube maps, the caller must have passed the
2111 * slice number referencing the face.
2113 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2117 map
->stride
= mt
->pitch
;
2118 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2121 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2122 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2123 map
->x
, map
->y
, map
->w
, map
->h
,
2124 mt
, _mesa_get_format_name(mt
->format
),
2125 x
, y
, map
->ptr
, map
->stride
);
2129 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2131 intel_miptree_unmap_raw(mt
);
2135 intel_miptree_map_blit(struct brw_context
*brw
,
2136 struct intel_mipmap_tree
*mt
,
2137 struct intel_miptree_map
*map
,
2138 unsigned int level
, unsigned int slice
)
2140 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2143 0, MIPTREE_LAYOUT_TILING_NONE
);
2146 fprintf(stderr
, "Failed to allocate blit temporary\n");
2149 map
->stride
= map
->mt
->pitch
;
2151 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2152 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2153 * invalidate is set, since we'll be writing the whole rectangle from our
2154 * temporary buffer back out.
2156 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2157 if (!intel_miptree_blit(brw
,
2159 map
->x
, map
->y
, false,
2162 map
->w
, map
->h
, GL_COPY
)) {
2163 fprintf(stderr
, "Failed to blit\n");
2168 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2170 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2171 map
->x
, map
->y
, map
->w
, map
->h
,
2172 mt
, _mesa_get_format_name(mt
->format
),
2173 level
, slice
, map
->ptr
, map
->stride
);
2178 intel_miptree_release(&map
->mt
);
2184 intel_miptree_unmap_blit(struct brw_context
*brw
,
2185 struct intel_mipmap_tree
*mt
,
2186 struct intel_miptree_map
*map
,
2190 struct gl_context
*ctx
= &brw
->ctx
;
2192 intel_miptree_unmap_raw(map
->mt
);
2194 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2195 bool ok
= intel_miptree_blit(brw
,
2199 map
->x
, map
->y
, false,
2200 map
->w
, map
->h
, GL_COPY
);
2201 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2204 intel_miptree_release(&map
->mt
);
2208 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2210 #if defined(USE_SSE41)
2212 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2213 struct intel_mipmap_tree
*mt
,
2214 struct intel_miptree_map
*map
,
2215 unsigned int level
, unsigned int slice
)
2217 assert(map
->mode
& GL_MAP_READ_BIT
);
2218 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2220 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2221 map
->x
, map
->y
, map
->w
, map
->h
,
2222 mt
, _mesa_get_format_name(mt
->format
),
2223 level
, slice
, map
->ptr
, map
->stride
);
2225 /* Map the original image */
2228 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2232 void *src
= intel_miptree_map_raw(brw
, mt
);
2235 src
+= image_y
* mt
->pitch
;
2236 src
+= image_x
* mt
->cpp
;
2238 /* Due to the pixel offsets for the particular image being mapped, our
2239 * src pointer may not be 16-byte aligned. However, if the pitch is
2240 * divisible by 16, then the amount by which it's misaligned will remain
2241 * consistent from row to row.
2243 assert((mt
->pitch
% 16) == 0);
2244 const int misalignment
= ((uintptr_t) src
) & 15;
2246 /* Create an untiled temporary buffer for the mapping. */
2247 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2249 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2251 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2252 /* Offset the destination so it has the same misalignment as src. */
2253 map
->ptr
= map
->buffer
+ misalignment
;
2255 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2257 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2258 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2259 void *src_ptr
= src
+ y
* mt
->pitch
;
2261 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2264 intel_miptree_unmap_raw(mt
);
2268 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2269 struct intel_mipmap_tree
*mt
,
2270 struct intel_miptree_map
*map
,
2274 _mesa_align_free(map
->buffer
);
2281 intel_miptree_map_s8(struct brw_context
*brw
,
2282 struct intel_mipmap_tree
*mt
,
2283 struct intel_miptree_map
*map
,
2284 unsigned int level
, unsigned int slice
)
2286 map
->stride
= map
->w
;
2287 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2291 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2292 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2293 * invalidate is set, since we'll be writing the whole rectangle from our
2294 * temporary buffer back out.
2296 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2297 uint8_t *untiled_s8_map
= map
->ptr
;
2298 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2299 unsigned int image_x
, image_y
;
2301 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2303 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2304 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2305 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2306 x
+ image_x
+ map
->x
,
2307 y
+ image_y
+ map
->y
,
2308 brw
->has_swizzling
);
2309 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2313 intel_miptree_unmap_raw(mt
);
2315 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2316 map
->x
, map
->y
, map
->w
, map
->h
,
2317 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2319 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2320 map
->x
, map
->y
, map
->w
, map
->h
,
2321 mt
, map
->ptr
, map
->stride
);
2326 intel_miptree_unmap_s8(struct brw_context
*brw
,
2327 struct intel_mipmap_tree
*mt
,
2328 struct intel_miptree_map
*map
,
2332 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2333 unsigned int image_x
, image_y
;
2334 uint8_t *untiled_s8_map
= map
->ptr
;
2335 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2337 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2339 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2340 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2341 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2344 brw
->has_swizzling
);
2345 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2349 intel_miptree_unmap_raw(mt
);
2356 intel_miptree_map_etc(struct brw_context
*brw
,
2357 struct intel_mipmap_tree
*mt
,
2358 struct intel_miptree_map
*map
,
2362 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2363 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2364 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2367 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2368 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2370 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2371 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2372 map
->w
, map
->h
, 1));
2373 map
->ptr
= map
->buffer
;
2377 intel_miptree_unmap_etc(struct brw_context
*brw
,
2378 struct intel_mipmap_tree
*mt
,
2379 struct intel_miptree_map
*map
,
2385 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2390 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2391 + image_y
* mt
->pitch
2392 + image_x
* mt
->cpp
;
2394 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2395 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2396 map
->ptr
, map
->stride
,
2399 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2400 map
->ptr
, map
->stride
,
2401 map
->w
, map
->h
, mt
->etc_format
);
2403 intel_miptree_unmap_raw(mt
);
2408 * Mapping function for packed depth/stencil miptrees backed by real separate
2409 * miptrees for depth and stencil.
2411 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2412 * separate from the depth buffer. Yet at the GL API level, we have to expose
2413 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2414 * be able to map that memory for texture storage and glReadPixels-type
2415 * operations. We give Mesa core that access by mallocing a temporary and
2416 * copying the data between the actual backing store and the temporary.
2419 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2420 struct intel_mipmap_tree
*mt
,
2421 struct intel_miptree_map
*map
,
2422 unsigned int level
, unsigned int slice
)
2424 struct intel_mipmap_tree
*z_mt
= mt
;
2425 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2426 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2427 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2429 map
->stride
= map
->w
* packed_bpp
;
2430 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2434 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2435 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2436 * invalidate is set, since we'll be writing the whole rectangle from our
2437 * temporary buffer back out.
2439 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2440 uint32_t *packed_map
= map
->ptr
;
2441 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2442 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2443 unsigned int s_image_x
, s_image_y
;
2444 unsigned int z_image_x
, z_image_y
;
2446 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2447 &s_image_x
, &s_image_y
);
2448 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2449 &z_image_x
, &z_image_y
);
2451 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2452 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2453 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2454 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2457 brw
->has_swizzling
);
2458 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2460 (map_x
+ z_image_x
));
2461 uint8_t s
= s_map
[s_offset
];
2462 uint32_t z
= z_map
[z_offset
];
2464 if (map_z32f_x24s8
) {
2465 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2466 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2468 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2473 intel_miptree_unmap_raw(s_mt
);
2474 intel_miptree_unmap_raw(z_mt
);
2476 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2478 map
->x
, map
->y
, map
->w
, map
->h
,
2479 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2480 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2481 map
->ptr
, map
->stride
);
2483 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2484 map
->x
, map
->y
, map
->w
, map
->h
,
2485 mt
, map
->ptr
, map
->stride
);
2490 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2491 struct intel_mipmap_tree
*mt
,
2492 struct intel_miptree_map
*map
,
2496 struct intel_mipmap_tree
*z_mt
= mt
;
2497 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2498 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2500 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2501 uint32_t *packed_map
= map
->ptr
;
2502 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2503 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2504 unsigned int s_image_x
, s_image_y
;
2505 unsigned int z_image_x
, z_image_y
;
2507 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2508 &s_image_x
, &s_image_y
);
2509 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2510 &z_image_x
, &z_image_y
);
2512 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2513 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2514 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2515 x
+ s_image_x
+ map
->x
,
2516 y
+ s_image_y
+ map
->y
,
2517 brw
->has_swizzling
);
2518 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2520 (x
+ z_image_x
+ map
->x
));
2522 if (map_z32f_x24s8
) {
2523 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2524 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2526 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2527 s_map
[s_offset
] = packed
>> 24;
2528 z_map
[z_offset
] = packed
;
2533 intel_miptree_unmap_raw(s_mt
);
2534 intel_miptree_unmap_raw(z_mt
);
2536 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2538 map
->x
, map
->y
, map
->w
, map
->h
,
2539 z_mt
, _mesa_get_format_name(z_mt
->format
),
2540 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2541 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2542 map
->ptr
, map
->stride
);
2549 * Create and attach a map to the miptree at (level, slice). Return the
2552 static struct intel_miptree_map
*
2553 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2562 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2567 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2568 mt
->level
[level
].slice
[slice
].map
= map
;
2580 * Release the map at (level, slice).
2583 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2587 struct intel_miptree_map
**map
;
2589 map
= &mt
->level
[level
].slice
[slice
].map
;
2595 can_blit_slice(struct intel_mipmap_tree
*mt
,
2596 unsigned int level
, unsigned int slice
)
2600 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2601 if (image_x
>= 32768 || image_y
>= 32768)
2604 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2605 if (mt
->pitch
>= 32768)
2612 use_intel_mipree_map_blit(struct brw_context
*brw
,
2613 struct intel_mipmap_tree
*mt
,
2619 /* It's probably not worth swapping to the blit ring because of
2620 * all the overhead involved.
2622 !(mode
& GL_MAP_WRITE_BIT
) &&
2624 (mt
->tiling
== I915_TILING_X
||
2625 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2626 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2627 can_blit_slice(mt
, level
, slice
))
2630 if (mt
->tiling
!= I915_TILING_NONE
&&
2631 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2632 assert(can_blit_slice(mt
, level
, slice
));
2640 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2641 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2642 * arithmetic overflow.
2644 * If you call this function and use \a out_stride, then you're doing pointer
2645 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2646 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2647 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2648 * which usually have type uint32_t or GLuint.
2651 intel_miptree_map(struct brw_context
*brw
,
2652 struct intel_mipmap_tree
*mt
,
2661 ptrdiff_t *out_stride
)
2663 struct intel_miptree_map
*map
;
2665 assert(mt
->num_samples
<= 1);
2667 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2674 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2675 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2676 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2679 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2680 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2681 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2682 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2683 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2684 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2685 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2686 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2687 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2688 #if defined(USE_SSE41)
2689 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2690 !mt
->compressed
&& cpu_has_sse4_1
&&
2691 (mt
->pitch
% 16 == 0)) {
2692 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2695 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2698 *out_ptr
= map
->ptr
;
2699 *out_stride
= map
->stride
;
2701 if (map
->ptr
== NULL
)
2702 intel_miptree_release_map(mt
, level
, slice
);
2706 intel_miptree_unmap(struct brw_context
*brw
,
2707 struct intel_mipmap_tree
*mt
,
2711 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2713 assert(mt
->num_samples
<= 1);
2718 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2719 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2721 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2722 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2723 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2724 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2725 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2726 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2727 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2728 } else if (map
->mt
) {
2729 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2730 #if defined(USE_SSE41)
2731 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2732 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2735 intel_miptree_unmap_gtt(mt
);
2738 intel_miptree_release_map(mt
, level
, slice
);