2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
230 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
231 const bool arrayed
= mt
->physical_depth0
!= 1;
234 /* Multisample surfaces with the CMS layout are not layered surfaces,
235 * yet still have physical_depth0 > 1. Assert that we don't
236 * accidentally reject a multisampled surface here. We should have
237 * rejected it earlier by explicitly checking the sample count.
239 assert(mt
->num_samples
<= 1);
242 /* Handle the hardware restrictions...
244 * All GENs have the following restriction: "MCS buffer for non-MSRT is
245 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
247 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
248 * Non-MultiSampler Render Target Restrictions) Support is for
249 * non-mip-mapped and non-array surface types only.
251 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
252 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
253 * surfaces are supported with MCS buffer layout with these alignments in
254 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
256 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
257 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
258 * surfaces are supported with MCS buffer layout with these alignments in
259 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
261 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
264 /* Not implemented yet. */
266 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
267 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
271 /* Not implemented yet. */
273 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
274 mt
->logical_width0
, mt
->logical_height0
,
275 mt
->physical_depth0
);
279 /* There's no point in using an MCS buffer if the surface isn't in a
282 if (!brw
->format_supported_as_render_target
[mt
->format
])
286 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
287 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
288 return isl_format_supports_lossless_compression(&brw
->screen
->devinfo
,
294 /* On Gen9 support for color buffer compression was extended to single
295 * sampled surfaces. This is a helper considering both auxiliary buffer
296 * type and number of samples telling if the given miptree represents
297 * the new single sampled case - also called lossless compression.
300 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
301 const struct intel_mipmap_tree
*mt
)
303 /* Only available from Gen9 onwards. */
307 /* Compression always requires auxiliary buffer. */
311 /* Single sample compression is represented re-using msaa compression
312 * layout type: "Compressed Multisampled Surfaces".
314 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
317 /* And finally distinguish between msaa and single sample case. */
318 return mt
->num_samples
<= 1;
322 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
323 const struct intel_mipmap_tree
*mt
)
325 /* For now compression is only enabled for integer formats even though
326 * there exist supported floating point formats also. This is a heuristic
327 * decision based on current public benchmarks. In none of the cases these
328 * formats provided any improvement but a few cases were seen to regress.
329 * Hence these are left to to be enabled in the future when they are known
332 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
335 /* Fast clear mechanism and lossless compression go hand in hand. */
336 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
339 /* Fast clear can be also used to clear srgb surfaces by using equivalent
340 * linear format. This trick, however, can't be extended to be used with
341 * lossless compression and therefore a check is needed to see if the format
344 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
348 * Determine depth format corresponding to a depth+stencil format,
349 * for separate stencil.
352 intel_depth_format_for_depthstencil_format(mesa_format format
) {
354 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
355 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
356 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
357 return MESA_FORMAT_Z_FLOAT32
;
365 * @param for_bo Indicates that the caller is
366 * intel_miptree_create_for_bo(). If true, then do not create
369 static struct intel_mipmap_tree
*
370 intel_miptree_create_layout(struct brw_context
*brw
,
379 uint32_t layout_flags
)
381 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
385 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
386 _mesa_enum_to_string(target
),
387 _mesa_get_format_name(format
),
388 first_level
, last_level
, depth0
, mt
);
390 if (target
== GL_TEXTURE_1D_ARRAY
)
391 assert(height0
== 1);
395 mt
->first_level
= first_level
;
396 mt
->last_level
= last_level
;
397 mt
->logical_width0
= width0
;
398 mt
->logical_height0
= height0
;
399 mt
->logical_depth0
= depth0
;
400 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
401 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
403 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
404 exec_list_make_empty(&mt
->hiz_map
);
405 mt
->cpp
= _mesa_get_format_bytes(format
);
406 mt
->num_samples
= num_samples
;
407 mt
->compressed
= _mesa_is_format_compressed(format
);
408 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
411 int depth_multiply
= 1;
412 if (num_samples
> 1) {
413 /* Adjust width/height/depth for MSAA */
414 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
415 mt
->disable_aux_buffers
);
416 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
417 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
418 * "If the surface is multisampled and it is a depth or stencil
419 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
420 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
423 * +----------------------------------------------------------------+
424 * | Num Multisamples | W_l = | H_l = |
425 * +----------------------------------------------------------------+
426 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
427 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
428 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
429 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
430 * +----------------------------------------------------------------+
433 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
434 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
435 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
437 * Another more complicated explanation for these adjustments comes
438 * from the Sandybridge PRM, volume 4, part 1, page 31:
440 * "Any of the other messages (sample*, LOD, load4) used with a
441 * (4x) multisampled surface will in-effect sample a surface with
442 * double the height and width as that indicated in the surface
443 * state. Each pixel position on the original-sized surface is
444 * replaced with a 2x2 of samples with the following arrangement:
449 * Thus, when sampling from a multisampled texture, it behaves as
450 * though the layout in memory for (x,y,sample) is:
452 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
453 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
455 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
456 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
458 * However, the actual layout of multisampled data in memory is:
460 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
461 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
463 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
464 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
466 * This pattern repeats for each 2x2 pixel block.
468 * As a result, when calculating the size of our 4-sample buffer for
469 * an odd width or height, we have to align before scaling up because
470 * sample 3 is in that bottom right 2x2 block.
472 switch (num_samples
) {
474 assert(brw
->gen
>= 8);
475 width0
= ALIGN(width0
, 2) * 2;
476 height0
= ALIGN(height0
, 2);
479 width0
= ALIGN(width0
, 2) * 2;
480 height0
= ALIGN(height0
, 2) * 2;
483 width0
= ALIGN(width0
, 2) * 4;
484 height0
= ALIGN(height0
, 2) * 2;
487 width0
= ALIGN(width0
, 2) * 4;
488 height0
= ALIGN(height0
, 2) * 4;
491 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
494 unreachable("not reached");
497 /* Non-interleaved */
498 depth_multiply
= num_samples
;
499 depth0
*= depth_multiply
;
503 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
504 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
505 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
506 * used on Gen8 to make it pick a qpitch value which doesn't include space
507 * for the mipmaps. On Gen9 this is not necessary because it will
508 * automatically pick a packed qpitch value whenever mt->first_level ==
510 * TODO: can we use it elsewhere?
511 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
514 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
516 switch (mt
->msaa_layout
) {
517 case INTEL_MSAA_LAYOUT_NONE
:
518 case INTEL_MSAA_LAYOUT_IMS
:
519 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
521 case INTEL_MSAA_LAYOUT_UMS
:
522 case INTEL_MSAA_LAYOUT_CMS
:
523 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
528 if (target
== GL_TEXTURE_CUBE_MAP
)
529 assert(depth0
== 6 * depth_multiply
);
531 mt
->physical_width0
= width0
;
532 mt
->physical_height0
= height0
;
533 mt
->physical_depth0
= depth0
;
535 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
536 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
537 (brw
->must_use_separate_stencil
||
538 (brw
->has_separate_stencil
&&
539 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
540 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
542 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
543 MIPTREE_LAYOUT_TILING_ANY
;
546 mt
->stencil_mt
= intel_miptree_create(brw
,
557 if (!mt
->stencil_mt
) {
558 intel_miptree_release(&mt
);
561 mt
->stencil_mt
->r8stencil_needs_update
= true;
563 /* Fix up the Z miptree format for how we're splitting out separate
564 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
566 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
569 if (format
== mt
->format
) {
570 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
571 _mesa_get_format_name(mt
->format
));
575 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
576 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
579 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
580 * multisampled or have an AUX buffer attached to it.
582 * GEN | MSRT | AUX_CCS_* or AUX_MCS
583 * -------------------------------------------
584 * 9 | HALIGN_16 | HALIGN_16
585 * 8 | HALIGN_ANY | HALIGN_16
589 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
590 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
591 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
592 } else if (brw
->gen
>= 9 && num_samples
> 1) {
593 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
595 const UNUSED
bool is_lossless_compressed_aux
=
596 brw
->gen
>= 9 && num_samples
== 1 &&
597 mt
->format
== MESA_FORMAT_R_UINT32
;
599 /* For now, nothing else has this requirement */
600 assert(is_lossless_compressed_aux
||
601 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
604 brw_miptree_layout(brw
, mt
, layout_flags
);
606 if (mt
->disable_aux_buffers
)
607 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
614 * Choose an appropriate uncompressed format for a requested
615 * compressed format, if unsupported.
618 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
620 /* No need to lower ETC formats on these platforms,
621 * they are supported natively.
623 if (brw
->gen
>= 8 || brw
->is_baytrail
)
627 case MESA_FORMAT_ETC1_RGB8
:
628 return MESA_FORMAT_R8G8B8X8_UNORM
;
629 case MESA_FORMAT_ETC2_RGB8
:
630 return MESA_FORMAT_R8G8B8X8_UNORM
;
631 case MESA_FORMAT_ETC2_SRGB8
:
632 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
633 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
634 return MESA_FORMAT_B8G8R8A8_SRGB
;
635 case MESA_FORMAT_ETC2_RGBA8_EAC
:
636 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
637 return MESA_FORMAT_R8G8B8A8_UNORM
;
638 case MESA_FORMAT_ETC2_R11_EAC
:
639 return MESA_FORMAT_R_UNORM16
;
640 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
641 return MESA_FORMAT_R_SNORM16
;
642 case MESA_FORMAT_ETC2_RG11_EAC
:
643 return MESA_FORMAT_R16G16_UNORM
;
644 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
645 return MESA_FORMAT_R16G16_SNORM
;
647 /* Non ETC1 / ETC2 format */
652 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
654 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
655 unsigned long *pitch
)
657 uint32_t tile_width
, tile_height
;
658 unsigned long stride
, size
, aligned_y
;
660 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
661 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
662 &tile_width
, &tile_height
);
664 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
665 stride
= mt
->total_width
* mt
->cpp
;
666 stride
= ALIGN(stride
, tile_width
);
667 size
= stride
* aligned_y
;
669 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
670 assert(size
% 4096 == 0);
673 assert(size
% (64 * 1024) == 0);
674 *alignment
= 64 * 1024;
680 static struct intel_mipmap_tree
*
681 miptree_create(struct brw_context
*brw
,
690 uint32_t layout_flags
)
692 struct intel_mipmap_tree
*mt
;
693 mesa_format tex_format
= format
;
694 mesa_format etc_format
= MESA_FORMAT_NONE
;
695 uint32_t alloc_flags
= 0;
697 format
= intel_lower_compressed_format(brw
, format
);
699 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
701 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
702 mt
= intel_miptree_create_layout(brw
, target
, format
,
703 first_level
, last_level
, width0
,
704 height0
, depth0
, num_samples
,
707 * pitch == 0 || height == 0 indicates the null texture
709 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
710 intel_miptree_release(&mt
);
714 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
715 mt
->tiling
= I915_TILING_Y
;
717 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
718 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
721 mt
->etc_format
= etc_format
;
723 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
724 unsigned alignment
= 0;
726 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
728 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
731 if (format
== MESA_FORMAT_S_UINT8
) {
732 /* Align to size of W tile, 64x64. */
733 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
734 ALIGN(mt
->total_width
, 64),
735 ALIGN(mt
->total_height
, 64),
736 mt
->cpp
, &mt
->tiling
, &pitch
,
739 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
740 mt
->total_width
, mt
->total_height
,
741 mt
->cpp
, &mt
->tiling
, &pitch
,
751 struct intel_mipmap_tree
*
752 intel_miptree_create(struct brw_context
*brw
,
761 uint32_t layout_flags
)
763 struct intel_mipmap_tree
*mt
= miptree_create(
765 first_level
, last_level
,
766 width0
, height0
, depth0
, num_samples
,
769 /* If the BO is too large to fit in the aperture, we need to use the
770 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
771 * handle Y-tiling, so we need to fall back to X.
773 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
774 mt
->tiling
== I915_TILING_Y
) {
775 unsigned long pitch
= mt
->pitch
;
776 const uint32_t alloc_flags
=
777 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
778 BO_ALLOC_FOR_RENDER
: 0;
779 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
780 mt
->total_width
, mt
->total_height
);
782 mt
->tiling
= I915_TILING_X
;
783 drm_intel_bo_unreference(mt
->bo
);
784 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
785 mt
->total_width
, mt
->total_height
, mt
->cpp
,
786 &mt
->tiling
, &pitch
, alloc_flags
);
793 intel_miptree_release(&mt
);
798 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
799 assert(mt
->num_samples
> 1);
800 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
801 intel_miptree_release(&mt
);
806 /* If this miptree is capable of supporting fast color clears, set
807 * fast_clear_state appropriately to ensure that fast clears will occur.
808 * Allocation of the MCS miptree will be deferred until the first fast
809 * clear actually occurs or when compressed single sampled buffer is
810 * written by the GPU for the first time.
812 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
813 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
815 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
817 /* On Gen9+ clients are not currently capable of consuming compressed
818 * single-sampled buffers. Disabling compression allows us to skip
821 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
822 const bool is_lossless_compressed
=
823 unlikely(!lossless_compression_disabled
) &&
824 brw
->gen
>= 9 && !mt
->is_scanout
&&
825 intel_miptree_supports_lossless_compressed(brw
, mt
);
827 if (is_lossless_compressed
) {
828 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
835 struct intel_mipmap_tree
*
836 intel_miptree_create_for_bo(struct brw_context
*brw
,
844 uint32_t layout_flags
)
846 struct intel_mipmap_tree
*mt
;
847 uint32_t tiling
, swizzle
;
850 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
852 /* Nothing will be able to use this miptree with the BO if the offset isn't
855 if (tiling
!= I915_TILING_NONE
)
856 assert(offset
% 4096 == 0);
858 /* miptrees can't handle negative pitch. If you need flipping of images,
859 * that's outside of the scope of the mt.
863 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
865 /* The BO already has a tiling format and we shouldn't confuse the lower
866 * layers by making it try to find a tiling format again.
868 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
869 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
871 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
872 mt
= intel_miptree_create_layout(brw
, target
, format
,
874 width
, height
, depth
, 0,
879 drm_intel_bo_reference(bo
);
889 * For a singlesample renderbuffer, this simply wraps the given BO with a
892 * For a multisample renderbuffer, this wraps the window system's
893 * (singlesample) BO with a singlesample miptree attached to the
894 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
895 * that will contain the actual rendering (which is lazily resolved to
896 * irb->singlesample_mt).
899 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
900 struct intel_renderbuffer
*irb
,
902 uint32_t width
, uint32_t height
,
905 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
906 struct intel_mipmap_tree
*multisample_mt
= NULL
;
907 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
908 mesa_format format
= rb
->Format
;
909 int num_samples
= rb
->NumSamples
;
911 /* Only the front and back buffers, which are color buffers, are allocated
912 * through the image loader.
914 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
915 _mesa_get_format_base_format(format
) == GL_RGBA
);
917 singlesample_mt
= intel_miptree_create_for_bo(intel
,
925 MIPTREE_LAYOUT_FOR_SCANOUT
);
926 if (!singlesample_mt
)
929 /* If this miptree is capable of supporting fast color clears, set
930 * mcs_state appropriately to ensure that fast clears will occur.
931 * Allocation of the MCS miptree will be deferred until the first fast
932 * clear actually occurs.
934 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
935 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
936 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
939 if (num_samples
== 0) {
940 intel_miptree_release(&irb
->mt
);
941 irb
->mt
= singlesample_mt
;
943 assert(!irb
->singlesample_mt
);
945 intel_miptree_release(&irb
->singlesample_mt
);
946 irb
->singlesample_mt
= singlesample_mt
;
949 irb
->mt
->logical_width0
!= width
||
950 irb
->mt
->logical_height0
!= height
) {
951 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
959 irb
->need_downsample
= false;
960 intel_miptree_release(&irb
->mt
);
961 irb
->mt
= multisample_mt
;
967 intel_miptree_release(&irb
->singlesample_mt
);
968 intel_miptree_release(&irb
->mt
);
972 struct intel_mipmap_tree
*
973 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
977 uint32_t num_samples
)
979 struct intel_mipmap_tree
*mt
;
982 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
983 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
984 MIPTREE_LAYOUT_TILING_ANY
|
985 MIPTREE_LAYOUT_FOR_SCANOUT
;
987 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
988 width
, height
, depth
, num_samples
,
993 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
994 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1002 intel_miptree_release(&mt
);
1007 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1008 struct intel_mipmap_tree
*src
)
1013 intel_miptree_release(dst
);
1017 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1025 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1030 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1031 if (--(*mt
)->refcount
<= 0) {
1034 DBG("%s deleting %p\n", __func__
, *mt
);
1036 drm_intel_bo_unreference((*mt
)->bo
);
1037 intel_miptree_release(&(*mt
)->stencil_mt
);
1038 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1039 if ((*mt
)->hiz_buf
) {
1040 if ((*mt
)->hiz_buf
->mt
)
1041 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1043 drm_intel_bo_unreference((*mt
)->hiz_buf
->aux_base
.bo
);
1044 free((*mt
)->hiz_buf
);
1046 if ((*mt
)->mcs_buf
) {
1047 drm_intel_bo_unreference((*mt
)->mcs_buf
->bo
);
1048 free((*mt
)->mcs_buf
);
1050 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1052 intel_miptree_release(&(*mt
)->plane
[0]);
1053 intel_miptree_release(&(*mt
)->plane
[1]);
1055 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1056 free((*mt
)->level
[i
].slice
);
1066 intel_get_image_dims(struct gl_texture_image
*image
,
1067 int *width
, int *height
, int *depth
)
1069 switch (image
->TexObject
->Target
) {
1070 case GL_TEXTURE_1D_ARRAY
:
1071 /* For a 1D Array texture the OpenGL API will treat the image height as
1072 * the number of array slices. For Intel hardware, we treat the 1D array
1073 * as a 2D Array with a height of 1. So, here we want to swap image
1076 assert(image
->Depth
== 1);
1077 *width
= image
->Width
;
1079 *depth
= image
->Height
;
1081 case GL_TEXTURE_CUBE_MAP
:
1082 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1083 * though we really have 6 slices.
1085 assert(image
->Depth
== 1);
1086 *width
= image
->Width
;
1087 *height
= image
->Height
;
1091 *width
= image
->Width
;
1092 *height
= image
->Height
;
1093 *depth
= image
->Depth
;
1099 * Can the image be pulled into a unified mipmap tree? This mirrors
1100 * the completeness test in a lot of ways.
1102 * Not sure whether I want to pass gl_texture_image here.
1105 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1106 struct gl_texture_image
*image
)
1108 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1109 GLuint level
= intelImage
->base
.Base
.Level
;
1110 int width
, height
, depth
;
1112 /* glTexImage* choose the texture object based on the target passed in, and
1113 * objects can't change targets over their lifetimes, so this should be
1116 assert(image
->TexObject
->Target
== mt
->target
);
1118 mesa_format mt_format
= mt
->format
;
1119 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1120 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1121 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1122 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1123 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1124 mt_format
= mt
->etc_format
;
1126 if (image
->TexFormat
!= mt_format
)
1129 intel_get_image_dims(image
, &width
, &height
, &depth
);
1131 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1134 int level_depth
= mt
->level
[level
].depth
;
1135 if (mt
->num_samples
> 1) {
1136 switch (mt
->msaa_layout
) {
1137 case INTEL_MSAA_LAYOUT_NONE
:
1138 case INTEL_MSAA_LAYOUT_IMS
:
1140 case INTEL_MSAA_LAYOUT_UMS
:
1141 case INTEL_MSAA_LAYOUT_CMS
:
1142 level_depth
/= mt
->num_samples
;
1147 /* Test image dimensions against the base level image adjusted for
1148 * minification. This will also catch images not present in the
1149 * tree, changed targets, etc.
1151 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1152 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1153 depth
!= level_depth
) {
1157 if (image
->NumSamples
!= mt
->num_samples
)
1165 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1167 GLuint x
, GLuint y
, GLuint d
)
1169 mt
->level
[level
].depth
= d
;
1170 mt
->level
[level
].level_x
= x
;
1171 mt
->level
[level
].level_y
= y
;
1173 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1176 assert(mt
->level
[level
].slice
== NULL
);
1178 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1179 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1180 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1185 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1186 GLuint level
, GLuint img
,
1189 if (img
== 0 && level
== 0)
1190 assert(x
== 0 && y
== 0);
1192 assert(img
< mt
->level
[level
].depth
);
1194 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1195 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1197 DBG("%s level %d img %d pos %d,%d\n",
1198 __func__
, level
, img
,
1199 mt
->level
[level
].slice
[img
].x_offset
,
1200 mt
->level
[level
].slice
[img
].y_offset
);
1204 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1205 GLuint level
, GLuint slice
,
1206 GLuint
*x
, GLuint
*y
)
1208 assert(slice
< mt
->level
[level
].depth
);
1210 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1211 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1216 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1217 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1218 * and tile_h is set to 1.
1221 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1222 uint32_t *tile_w
, uint32_t *tile_h
)
1224 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1234 case I915_TILING_NONE
:
1239 unreachable("not reached");
1242 uint32_t aspect_ratio
= 1;
1243 assert(_mesa_is_pow_two(cpp
));
1258 unreachable("not reached");
1261 if (cpp
== 2 || cpp
== 8)
1264 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1267 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1273 * This function computes masks that may be used to select the bits of the X
1274 * and Y coordinates that indicate the offset within a tile. If the BO is
1275 * untiled, the masks are set to 0.
1278 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1279 uint32_t *mask_x
, uint32_t *mask_y
)
1281 uint32_t tile_w_bytes
, tile_h
;
1283 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1285 *mask_x
= tile_w_bytes
/ cpp
- 1;
1286 *mask_y
= tile_h
- 1;
1290 * Compute the offset (in bytes) from the start of the BO to the given x
1291 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1292 * multiples of the tile size.
1295 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1296 uint32_t x
, uint32_t y
)
1299 uint32_t pitch
= mt
->pitch
;
1300 uint32_t tiling
= mt
->tiling
;
1304 unreachable("not reached");
1305 case I915_TILING_NONE
:
1306 return y
* pitch
+ x
* cpp
;
1308 assert((x
% (512 / cpp
)) == 0);
1309 assert((y
% 8) == 0);
1310 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1312 assert((x
% (128 / cpp
)) == 0);
1313 assert((y
% 32) == 0);
1314 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1319 * Rendering with tiled buffers requires that the base address of the buffer
1320 * be aligned to a page boundary. For renderbuffers, and sometimes with
1321 * textures, we may want the surface to point at a texture image level that
1322 * isn't at a page boundary.
1324 * This function returns an appropriately-aligned base offset
1325 * according to the tiling restrictions, plus any required x/y offset
1329 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1330 GLuint level
, GLuint slice
,
1335 uint32_t mask_x
, mask_y
;
1337 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, &mask_x
, &mask_y
);
1338 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1340 *tile_x
= x
& mask_x
;
1341 *tile_y
= y
& mask_y
;
1343 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1347 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1348 struct intel_mipmap_tree
*dst_mt
,
1349 struct intel_mipmap_tree
*src_mt
,
1356 ptrdiff_t src_stride
, dst_stride
;
1357 int cpp
= dst_mt
->cpp
;
1359 intel_miptree_map(brw
, src_mt
,
1363 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1366 intel_miptree_map(brw
, dst_mt
,
1370 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1374 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1375 _mesa_get_format_name(src_mt
->format
),
1376 src_mt
, src
, src_stride
,
1377 _mesa_get_format_name(dst_mt
->format
),
1378 dst_mt
, dst
, dst_stride
,
1381 int row_size
= cpp
* width
;
1382 if (src_stride
== row_size
&&
1383 dst_stride
== row_size
) {
1384 memcpy(dst
, src
, row_size
* height
);
1386 for (int i
= 0; i
< height
; i
++) {
1387 memcpy(dst
, src
, row_size
);
1393 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1394 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1396 /* Don't forget to copy the stencil data over, too. We could have skipped
1397 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1398 * shuffling the two data sources in/out of temporary storage instead of
1399 * the direct mapping we get this way.
1401 if (dst_mt
->stencil_mt
) {
1402 assert(src_mt
->stencil_mt
);
1403 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1404 level
, slice
, width
, height
);
1409 intel_miptree_copy_slice(struct brw_context
*brw
,
1410 struct intel_mipmap_tree
*dst_mt
,
1411 struct intel_mipmap_tree
*src_mt
,
1417 mesa_format format
= src_mt
->format
;
1418 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1419 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1427 assert(depth
< src_mt
->level
[level
].depth
);
1428 assert(src_mt
->format
== dst_mt
->format
);
1430 if (dst_mt
->compressed
) {
1432 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1433 height
= ALIGN_NPOT(height
, j
) / j
;
1434 width
= ALIGN_NPOT(width
, i
) / i
;
1437 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1438 * below won't apply since we can't do the depth's Y tiling or the
1439 * stencil's W tiling in the blitter.
1441 if (src_mt
->stencil_mt
) {
1442 intel_miptree_copy_slice_sw(brw
,
1449 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1450 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1451 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1453 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1454 _mesa_get_format_name(src_mt
->format
),
1455 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1456 _mesa_get_format_name(dst_mt
->format
),
1457 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1460 if (!intel_miptree_blit(brw
,
1461 src_mt
, level
, slice
, 0, 0, false,
1462 dst_mt
, level
, slice
, 0, 0, false,
1463 width
, height
, GL_COPY
)) {
1464 perf_debug("miptree validate blit for %s failed\n",
1465 _mesa_get_format_name(format
));
1467 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1473 * Copies the image's current data to the given miptree, and associates that
1474 * miptree with the image.
1476 * If \c invalidate is true, then the actual image data does not need to be
1477 * copied, but the image still needs to be associated to the new miptree (this
1478 * is set to true if we're about to clear the image).
1481 intel_miptree_copy_teximage(struct brw_context
*brw
,
1482 struct intel_texture_image
*intelImage
,
1483 struct intel_mipmap_tree
*dst_mt
,
1486 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1487 struct intel_texture_object
*intel_obj
=
1488 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1489 int level
= intelImage
->base
.Base
.Level
;
1490 int face
= intelImage
->base
.Base
.Face
;
1493 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1494 depth
= intelImage
->base
.Base
.Height
;
1496 depth
= intelImage
->base
.Base
.Depth
;
1499 for (int slice
= 0; slice
< depth
; slice
++) {
1500 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1504 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1505 intel_obj
->needs_validate
= true;
1509 intel_miptree_init_mcs(struct brw_context
*brw
,
1510 struct intel_mipmap_tree
*mt
,
1513 assert(mt
->mcs_buf
!= NULL
);
1515 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1517 * When MCS buffer is enabled and bound to MSRT, it is required that it
1518 * is cleared prior to any rendering.
1520 * Since we don't use the MCS buffer for any purpose other than rendering,
1521 * it makes sense to just clear it immediately upon allocation.
1523 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1525 const int ret
= brw_bo_map_gtt(brw
, mt
->mcs_buf
->bo
, "miptree");
1526 if (unlikely(ret
)) {
1527 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1528 drm_intel_bo_unreference(mt
->mcs_buf
->bo
);
1532 void *data
= mt
->mcs_buf
->bo
->virtual;
1533 memset(data
, init_value
, mt
->mcs_buf
->size
);
1534 drm_intel_bo_unmap(mt
->mcs_buf
->bo
);
1537 static struct intel_miptree_aux_buffer
*
1538 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1539 struct intel_mipmap_tree
*mt
,
1542 unsigned mcs_height
,
1543 uint32_t layout_flags
)
1545 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1546 struct intel_mipmap_tree
*temp_mt
;
1551 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1553 * "The MCS surface must be stored as Tile Y."
1555 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1556 temp_mt
= miptree_create(brw
,
1564 0 /* num_samples */,
1571 buf
->bo
= temp_mt
->bo
;
1572 buf
->offset
= temp_mt
->offset
;
1573 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1574 buf
->pitch
= temp_mt
->pitch
;
1575 buf
->qpitch
= temp_mt
->qpitch
;
1577 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1578 * structure should go away. We use miptree create simply as a means to make
1579 * sure all the constraints for the buffer are satisfied.
1581 drm_intel_bo_reference(temp_mt
->bo
);
1582 intel_miptree_release(&temp_mt
);
1588 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1589 struct intel_mipmap_tree
*mt
,
1592 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1593 assert(mt
->mcs_buf
== NULL
);
1594 assert(!mt
->disable_aux_buffers
);
1596 /* Choose the correct format for the MCS buffer. All that really matters
1597 * is that we allocate the right buffer size, since we'll always be
1598 * accessing this miptree using MCS-specific hardware mechanisms, which
1599 * infer the correct format based on num_samples.
1602 switch (num_samples
) {
1605 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1608 format
= MESA_FORMAT_R_UNORM8
;
1611 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1612 * for each sample, plus 8 padding bits).
1614 format
= MESA_FORMAT_R_UINT32
;
1617 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1620 format
= MESA_FORMAT_RG_UINT32
;
1623 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1627 intel_mcs_miptree_buf_create(brw
, mt
,
1630 mt
->logical_height0
,
1631 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1635 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1636 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1643 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1644 struct intel_mipmap_tree
*mt
,
1645 bool is_lossless_compressed
)
1647 assert(mt
->mcs_buf
== NULL
);
1648 assert(!mt
->disable_aux_buffers
);
1649 assert(!mt
->no_ccs
);
1651 /* The format of the MCS buffer is opaque to the driver; all that matters
1652 * is that we get its size and pitch right. We'll pretend that the format
1653 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1654 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1655 * the block width and then a further factor of 4. Since an MCS tile
1656 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1657 * we'll need to scale the height down by the block height and then a
1658 * further factor of 8.
1660 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1661 unsigned block_width_px
;
1662 unsigned block_height
;
1663 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1664 unsigned width_divisor
= block_width_px
* 4;
1665 unsigned height_divisor
= block_height
* 8;
1667 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1669 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1670 * in the main surface. In Skylake, it's two bits. The extra bit
1671 * doubles the MCS height, not width, because in Skylake the MCS is always
1675 height_divisor
/= 2;
1677 unsigned mcs_width
=
1678 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1679 unsigned mcs_height
=
1680 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1681 assert(mt
->logical_depth0
== 1);
1683 uint32_t layout_flags
=
1684 (brw
->gen
>= 8) ? MIPTREE_LAYOUT_FORCE_HALIGN16
: 0;
1685 /* In case of compression mcs buffer needs to be initialised requiring the
1686 * buffer to be immediately mapped to cpu space for writing. Therefore do
1687 * not use the gpu access flag which can cause an unnecessary delay if the
1688 * backing pages happened to be just used by the GPU.
1690 if (!is_lossless_compressed
)
1691 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1693 mt
->mcs_buf
= intel_mcs_miptree_buf_create(brw
, mt
,
1701 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1702 * used for lossless compression which requires similar initialisation
1703 * as multi-sample compression.
1705 if (is_lossless_compressed
) {
1706 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1707 * resolve. Initialize it accordingly in case the first renderer is
1708 * cpu (or other none compression aware party).
1710 * This is also explicitly stated in the spec (MCS Buffer for Render
1712 * "If Software wants to enable Color Compression without Fast clear,
1713 * Software needs to initialize MCS with zeros."
1715 intel_miptree_init_mcs(brw
, mt
, 0);
1716 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1717 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1724 * Helper for intel_miptree_alloc_hiz() that sets
1725 * \c mt->level[level].has_hiz. Return true if and only if
1726 * \c has_hiz was set.
1729 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1730 struct intel_mipmap_tree
*mt
,
1733 assert(mt
->hiz_buf
);
1735 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1736 uint32_t width
= minify(mt
->physical_width0
, level
);
1737 uint32_t height
= minify(mt
->physical_height0
, level
);
1739 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1740 * and the height is 4 aligned. This allows our HiZ support
1741 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1742 * we can grow the width & height to allow the HiZ op to
1743 * force the proper size alignments.
1745 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1746 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1751 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1752 mt
->level
[level
].has_hiz
= true;
1758 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1759 * buffer dimensions and allocates a bo for the hiz buffer.
1761 static struct intel_miptree_hiz_buffer
*
1762 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1763 struct intel_mipmap_tree
*mt
)
1765 unsigned z_width
= mt
->logical_width0
;
1766 unsigned z_height
= mt
->logical_height0
;
1767 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1768 unsigned hz_width
, hz_height
;
1769 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1774 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1775 * adjustments required for Z_Height and Z_Width based on multisampling.
1777 switch (mt
->num_samples
) {
1791 unreachable("unsupported sample count");
1794 const unsigned vertical_align
= 8; /* 'j' in the docs */
1795 const unsigned H0
= z_height
;
1796 const unsigned h0
= ALIGN(H0
, vertical_align
);
1797 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1798 const unsigned Z0
= z_depth
;
1800 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1801 hz_width
= ALIGN(z_width
, 16);
1803 if (mt
->target
== GL_TEXTURE_3D
) {
1807 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1808 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1809 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1810 hz_height
+= h_i
* Z_i
;
1811 H_i
= minify(H_i
, 1);
1812 Z_i
= minify(Z_i
, 1);
1815 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1817 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1819 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1820 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1821 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1824 unsigned long pitch
;
1825 uint32_t tiling
= I915_TILING_Y
;
1826 buf
->aux_base
.bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1827 hz_width
, hz_height
, 1,
1829 BO_ALLOC_FOR_RENDER
);
1830 if (!buf
->aux_base
.bo
) {
1833 } else if (tiling
!= I915_TILING_Y
) {
1834 drm_intel_bo_unreference(buf
->aux_base
.bo
);
1839 buf
->aux_base
.size
= hz_width
* hz_height
;
1840 buf
->aux_base
.pitch
= pitch
;
1847 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1848 * buffer dimensions and allocates a bo for the hiz buffer.
1850 static struct intel_miptree_hiz_buffer
*
1851 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1852 struct intel_mipmap_tree
*mt
)
1854 unsigned z_width
= mt
->logical_width0
;
1855 unsigned z_height
= mt
->logical_height0
;
1856 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1857 unsigned hz_width
, hz_height
;
1858 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1863 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1864 * adjustments required for Z_Height and Z_Width based on multisampling.
1867 switch (mt
->num_samples
) {
1881 unreachable("unsupported sample count");
1885 const unsigned vertical_align
= 8; /* 'j' in the docs */
1886 const unsigned H0
= z_height
;
1887 const unsigned h0
= ALIGN(H0
, vertical_align
);
1888 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1889 const unsigned Z0
= z_depth
;
1891 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1892 hz_width
= ALIGN(z_width
, 16);
1896 unsigned sum_h_i
= 0;
1897 unsigned hz_height_3d_sum
= 0;
1898 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1899 unsigned i
= level
- mt
->first_level
;
1900 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1901 /* sum(i=2 to m; h_i) */
1905 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1906 hz_height_3d_sum
+= h_i
* Z_i
;
1907 H_i
= minify(H_i
, 1);
1908 Z_i
= minify(Z_i
, 1);
1910 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1911 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1913 if (mt
->target
== GL_TEXTURE_3D
) {
1914 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1915 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1917 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1918 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1921 unsigned long pitch
;
1922 uint32_t tiling
= I915_TILING_Y
;
1923 buf
->aux_base
.bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1924 hz_width
, hz_height
, 1,
1926 BO_ALLOC_FOR_RENDER
);
1927 if (!buf
->aux_base
.bo
) {
1930 } else if (tiling
!= I915_TILING_Y
) {
1931 drm_intel_bo_unreference(buf
->aux_base
.bo
);
1936 buf
->aux_base
.size
= hz_width
* hz_height
;
1937 buf
->aux_base
.pitch
= pitch
;
1943 static struct intel_miptree_hiz_buffer
*
1944 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1945 struct intel_mipmap_tree
*mt
)
1947 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1948 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1951 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1956 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1957 buf
->mt
= intel_miptree_create(brw
,
1963 mt
->logical_height0
,
1972 buf
->aux_base
.bo
= buf
->mt
->bo
;
1973 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1974 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1975 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
;
1981 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1982 struct intel_mipmap_tree
*mt
)
1987 if (mt
->hiz_buf
!= NULL
)
1990 if (mt
->disable_aux_buffers
)
1993 switch (mt
->format
) {
1994 case MESA_FORMAT_Z_FLOAT32
:
1995 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1996 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1997 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1998 case MESA_FORMAT_Z_UNORM16
:
2006 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2007 struct intel_mipmap_tree
*mt
)
2009 assert(mt
->hiz_buf
== NULL
);
2010 assert(!mt
->disable_aux_buffers
);
2012 if (brw
->gen
== 7) {
2013 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
2014 } else if (brw
->gen
>= 8) {
2015 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
2017 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
2023 /* Mark that all slices need a HiZ resolve. */
2024 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2025 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
2028 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
2029 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
2030 exec_node_init(&m
->link
);
2033 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2035 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
2043 * Can the miptree sample using the hiz buffer?
2046 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2047 struct intel_mipmap_tree
*mt
)
2049 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2050 * so keep things conservative for now and never enable it unless we're SKL+.
2060 /* It seems the hardware won't fallback to the depth buffer if some of the
2061 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2062 * of the texture to be HiZ enabled.
2064 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2065 if (!intel_miptree_level_has_hiz(mt
, level
))
2069 /* If compressed multisampling is enabled, then we use it for the auxiliary
2072 * From the BDW PRM (Volume 2d: Command Reference: Structures
2073 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2075 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2076 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2078 * There is no such blurb for 1D textures, but there is sufficient evidence
2079 * that this is broken on SKL+.
2081 return (mt
->num_samples
<= 1 &&
2082 mt
->target
!= GL_TEXTURE_3D
&&
2083 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2087 * Does the miptree slice have hiz enabled?
2090 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2092 intel_miptree_check_level_layer(mt
, level
, 0);
2093 return mt
->level
[level
].has_hiz
;
2097 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2101 if (!intel_miptree_level_has_hiz(mt
, level
))
2104 intel_resolve_map_set(&mt
->hiz_map
,
2105 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2110 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2114 if (!intel_miptree_level_has_hiz(mt
, level
))
2117 intel_resolve_map_set(&mt
->hiz_map
,
2118 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2122 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2126 uint32_t end_layer
= mt
->level
[level
].depth
;
2128 for (layer
= 0; layer
< end_layer
; layer
++) {
2129 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2134 intel_miptree_slice_resolve(struct brw_context
*brw
,
2135 struct intel_mipmap_tree
*mt
,
2138 enum blorp_hiz_op need
)
2140 intel_miptree_check_level_layer(mt
, level
, layer
);
2142 struct intel_resolve_map
*item
=
2143 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2145 if (!item
|| item
->need
!= need
)
2148 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2149 intel_resolve_map_remove(item
);
2154 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2155 struct intel_mipmap_tree
*mt
,
2159 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2160 BLORP_HIZ_OP_HIZ_RESOLVE
);
2164 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2165 struct intel_mipmap_tree
*mt
,
2169 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2170 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2174 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2175 struct intel_mipmap_tree
*mt
,
2176 enum blorp_hiz_op need
)
2178 bool did_resolve
= false;
2180 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2181 if (map
->need
!= need
)
2184 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2185 intel_resolve_map_remove(map
);
2193 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2194 struct intel_mipmap_tree
*mt
)
2196 return intel_miptree_all_slices_resolve(brw
, mt
,
2197 BLORP_HIZ_OP_HIZ_RESOLVE
);
2201 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2202 struct intel_mipmap_tree
*mt
)
2204 return intel_miptree_all_slices_resolve(brw
, mt
,
2205 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2208 enum intel_fast_clear_state
2209 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree
*mt
,
2210 unsigned level
, unsigned layer
)
2212 return mt
->fast_clear_state
;
2216 intel_miptree_check_color_resolve(const struct intel_mipmap_tree
*mt
,
2217 unsigned level
, unsigned layer
)
2219 if (mt
->no_ccs
|| !mt
->mcs_buf
)
2222 /* Fast color clear is not supported for mipmapped surfaces. */
2223 assert(level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0);
2225 /* Compression of arrayed msaa surfaces is supported. */
2226 if (mt
->num_samples
> 1)
2229 /* Fast color clear is not supported for non-msaa arrays. */
2230 assert(layer
== 0 && mt
->logical_depth0
== 1);
2237 intel_miptree_set_fast_clear_state(struct intel_mipmap_tree
*mt
,
2239 unsigned first_layer
,
2240 unsigned num_layers
,
2241 enum intel_fast_clear_state new_state
)
2243 intel_miptree_check_color_resolve(mt
, level
, first_layer
);
2245 assert(first_layer
+ num_layers
<= mt
->physical_depth0
);
2247 mt
->fast_clear_state
= new_state
;
2251 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2252 unsigned start_level
, unsigned num_levels
,
2253 unsigned start_layer
, unsigned num_layers
)
2255 return mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
;
2259 intel_miptree_used_for_rendering(const struct brw_context
*brw
,
2260 struct intel_mipmap_tree
*mt
, unsigned level
,
2261 unsigned start_layer
, unsigned num_layers
)
2263 const bool is_lossless_compressed
=
2264 intel_miptree_is_lossless_compressed(brw
, mt
);
2266 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2267 const enum intel_fast_clear_state fast_clear_state
=
2268 intel_miptree_get_fast_clear_state(mt
, level
, start_layer
+ i
);
2270 /* If the buffer was previously in fast clear state, change it to
2271 * unresolved state, since it won't be guaranteed to be clear after
2274 if (is_lossless_compressed
||
2275 fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
) {
2276 intel_miptree_set_fast_clear_state(
2277 mt
, level
, start_layer
+ i
, 1,
2278 INTEL_FAST_CLEAR_STATE_UNRESOLVED
);
2284 intel_miptree_needs_color_resolve(const struct brw_context
*brw
,
2285 const struct intel_mipmap_tree
*mt
,
2291 const bool is_lossless_compressed
=
2292 intel_miptree_is_lossless_compressed(brw
, mt
);
2294 /* From gen9 onwards there is new compression scheme for single sampled
2295 * surfaces called "lossless compressed". These don't need to be always
2298 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) && is_lossless_compressed
)
2301 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2302 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_NONE
&& !is_lossless_compressed
)
2309 intel_miptree_resolve_color(struct brw_context
*brw
,
2310 struct intel_mipmap_tree
*mt
, unsigned level
,
2311 unsigned start_layer
, unsigned num_layers
,
2314 intel_miptree_check_color_resolve(mt
, level
, start_layer
);
2316 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2319 switch (mt
->fast_clear_state
) {
2320 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2321 /* No resolve needed */
2323 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2324 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2325 /* For now arrayed fast clear is not supported. */
2326 assert(num_layers
== 1);
2327 brw_blorp_resolve_color(brw
, mt
, level
, start_layer
);
2330 unreachable("Invalid fast clear state");
2335 intel_miptree_all_slices_resolve_color(struct brw_context
*brw
,
2336 struct intel_mipmap_tree
*mt
,
2339 intel_miptree_resolve_color(brw
, mt
, 0, 0, 1, flags
);
2343 * Make it possible to share the BO backing the given miptree with another
2344 * process or another miptree.
2346 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2347 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2348 * ensure that no MCS buffer gets allocated in the future.
2351 intel_miptree_make_shareable(struct brw_context
*brw
,
2352 struct intel_mipmap_tree
*mt
)
2354 /* MCS buffers are also used for multisample buffers, but we can't resolve
2355 * away a multisample MCS buffer because it's an integral part of how the
2356 * pixel data is stored. Fortunately this code path should never be
2357 * reached for multisample buffers.
2359 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2362 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2369 * \brief Get pointer offset into stencil buffer.
2371 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2372 * must decode the tile's layout in software.
2375 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2377 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2379 * Even though the returned offset is always positive, the return type is
2381 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2382 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2385 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2387 uint32_t tile_size
= 4096;
2388 uint32_t tile_width
= 64;
2389 uint32_t tile_height
= 64;
2390 uint32_t row_size
= 64 * stride
;
2392 uint32_t tile_x
= x
/ tile_width
;
2393 uint32_t tile_y
= y
/ tile_height
;
2395 /* The byte's address relative to the tile's base addres. */
2396 uint32_t byte_x
= x
% tile_width
;
2397 uint32_t byte_y
= y
% tile_height
;
2399 uintptr_t u
= tile_y
* row_size
2400 + tile_x
* tile_size
2401 + 512 * (byte_x
/ 8)
2403 + 32 * ((byte_y
/ 4) % 2)
2404 + 16 * ((byte_x
/ 4) % 2)
2405 + 8 * ((byte_y
/ 2) % 2)
2406 + 4 * ((byte_x
/ 2) % 2)
2411 /* adjust for bit6 swizzling */
2412 if (((byte_x
/ 8) % 2) == 1) {
2413 if (((byte_y
/ 8) % 2) == 0) {
2425 intel_miptree_updownsample(struct brw_context
*brw
,
2426 struct intel_mipmap_tree
*src
,
2427 struct intel_mipmap_tree
*dst
)
2429 brw_blorp_blit_miptrees(brw
,
2430 src
, 0 /* level */, 0 /* layer */,
2431 src
->format
, SWIZZLE_XYZW
,
2432 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2434 src
->logical_width0
, src
->logical_height0
,
2436 dst
->logical_width0
, dst
->logical_height0
,
2437 GL_NEAREST
, false, false /*mirror x, y*/,
2440 if (src
->stencil_mt
) {
2441 brw_blorp_blit_miptrees(brw
,
2442 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2443 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2444 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2445 dst
->stencil_mt
->format
,
2447 src
->logical_width0
, src
->logical_height0
,
2449 dst
->logical_width0
, dst
->logical_height0
,
2450 GL_NEAREST
, false, false /*mirror x, y*/,
2451 false, false /* decode/encode srgb */);
2456 intel_update_r8stencil(struct brw_context
*brw
,
2457 struct intel_mipmap_tree
*mt
)
2459 assert(brw
->gen
>= 7);
2460 struct intel_mipmap_tree
*src
=
2461 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2462 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2465 if (!mt
->r8stencil_mt
) {
2466 const uint32_t r8stencil_flags
=
2467 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2468 MIPTREE_LAYOUT_DISABLE_AUX
;
2469 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2470 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2472 MESA_FORMAT_R_UINT8
,
2475 src
->logical_width0
,
2476 src
->logical_height0
,
2477 src
->logical_depth0
,
2480 assert(mt
->r8stencil_mt
);
2483 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2485 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2486 const unsigned depth
= src
->level
[level
].depth
;
2487 const int layers_per_blit
=
2488 (dst
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
2489 dst
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
2490 dst
->num_samples
: 1;
2492 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2493 brw_blorp_blit_miptrees(brw
,
2495 src
->format
, SWIZZLE_X
,
2496 dst
, level
, layers_per_blit
* layer
,
2497 MESA_FORMAT_R_UNORM8
,
2499 minify(src
->logical_width0
, level
),
2500 minify(src
->logical_height0
, level
),
2502 minify(dst
->logical_width0
, level
),
2503 minify(dst
->logical_height0
, level
),
2504 GL_NEAREST
, false, false /*mirror x, y*/,
2505 false, false /* decode/encode srgb */);
2509 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2510 src
->r8stencil_needs_update
= false;
2514 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2516 /* CPU accesses to color buffers don't understand fast color clears, so
2517 * resolve any pending fast color clears before we map.
2519 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2521 drm_intel_bo
*bo
= mt
->bo
;
2523 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2524 intel_batchbuffer_flush(brw
);
2526 if (mt
->tiling
!= I915_TILING_NONE
)
2527 brw_bo_map_gtt(brw
, bo
, "miptree");
2529 brw_bo_map(brw
, bo
, true, "miptree");
2535 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2537 drm_intel_bo_unmap(mt
->bo
);
2541 intel_miptree_map_gtt(struct brw_context
*brw
,
2542 struct intel_mipmap_tree
*mt
,
2543 struct intel_miptree_map
*map
,
2544 unsigned int level
, unsigned int slice
)
2546 unsigned int bw
, bh
;
2548 unsigned int image_x
, image_y
;
2549 intptr_t x
= map
->x
;
2550 intptr_t y
= map
->y
;
2552 /* For compressed formats, the stride is the number of bytes per
2553 * row of blocks. intel_miptree_get_image_offset() already does
2556 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2557 assert(y
% bh
== 0);
2558 assert(x
% bw
== 0);
2562 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2567 /* Note that in the case of cube maps, the caller must have passed the
2568 * slice number referencing the face.
2570 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2574 map
->stride
= mt
->pitch
;
2575 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2578 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2579 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2580 map
->x
, map
->y
, map
->w
, map
->h
,
2581 mt
, _mesa_get_format_name(mt
->format
),
2582 x
, y
, map
->ptr
, map
->stride
);
2586 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2588 intel_miptree_unmap_raw(mt
);
2592 intel_miptree_map_blit(struct brw_context
*brw
,
2593 struct intel_mipmap_tree
*mt
,
2594 struct intel_miptree_map
*map
,
2595 unsigned int level
, unsigned int slice
)
2597 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2598 /* first_level */ 0,
2602 MIPTREE_LAYOUT_TILING_NONE
);
2604 if (!map
->linear_mt
) {
2605 fprintf(stderr
, "Failed to allocate blit temporary\n");
2608 map
->stride
= map
->linear_mt
->pitch
;
2610 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2611 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2612 * invalidate is set, since we'll be writing the whole rectangle from our
2613 * temporary buffer back out.
2615 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2616 if (!intel_miptree_blit(brw
,
2618 map
->x
, map
->y
, false,
2619 map
->linear_mt
, 0, 0,
2621 map
->w
, map
->h
, GL_COPY
)) {
2622 fprintf(stderr
, "Failed to blit\n");
2627 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2629 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2630 map
->x
, map
->y
, map
->w
, map
->h
,
2631 mt
, _mesa_get_format_name(mt
->format
),
2632 level
, slice
, map
->ptr
, map
->stride
);
2637 intel_miptree_release(&map
->linear_mt
);
2643 intel_miptree_unmap_blit(struct brw_context
*brw
,
2644 struct intel_mipmap_tree
*mt
,
2645 struct intel_miptree_map
*map
,
2649 struct gl_context
*ctx
= &brw
->ctx
;
2651 intel_miptree_unmap_raw(map
->linear_mt
);
2653 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2654 bool ok
= intel_miptree_blit(brw
,
2655 map
->linear_mt
, 0, 0,
2658 map
->x
, map
->y
, false,
2659 map
->w
, map
->h
, GL_COPY
);
2660 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2663 intel_miptree_release(&map
->linear_mt
);
2667 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2669 #if defined(USE_SSE41)
2671 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2672 struct intel_mipmap_tree
*mt
,
2673 struct intel_miptree_map
*map
,
2674 unsigned int level
, unsigned int slice
)
2676 assert(map
->mode
& GL_MAP_READ_BIT
);
2677 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2679 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2680 map
->x
, map
->y
, map
->w
, map
->h
,
2681 mt
, _mesa_get_format_name(mt
->format
),
2682 level
, slice
, map
->ptr
, map
->stride
);
2684 /* Map the original image */
2687 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2691 void *src
= intel_miptree_map_raw(brw
, mt
);
2697 src
+= image_y
* mt
->pitch
;
2698 src
+= image_x
* mt
->cpp
;
2700 /* Due to the pixel offsets for the particular image being mapped, our
2701 * src pointer may not be 16-byte aligned. However, if the pitch is
2702 * divisible by 16, then the amount by which it's misaligned will remain
2703 * consistent from row to row.
2705 assert((mt
->pitch
% 16) == 0);
2706 const int misalignment
= ((uintptr_t) src
) & 15;
2708 /* Create an untiled temporary buffer for the mapping. */
2709 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2711 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2713 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2714 /* Offset the destination so it has the same misalignment as src. */
2715 map
->ptr
= map
->buffer
+ misalignment
;
2717 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2719 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2720 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2721 void *src_ptr
= src
+ y
* mt
->pitch
;
2723 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2726 intel_miptree_unmap_raw(mt
);
2730 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2731 struct intel_mipmap_tree
*mt
,
2732 struct intel_miptree_map
*map
,
2736 _mesa_align_free(map
->buffer
);
2743 intel_miptree_map_s8(struct brw_context
*brw
,
2744 struct intel_mipmap_tree
*mt
,
2745 struct intel_miptree_map
*map
,
2746 unsigned int level
, unsigned int slice
)
2748 map
->stride
= map
->w
;
2749 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2753 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2754 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2755 * invalidate is set, since we'll be writing the whole rectangle from our
2756 * temporary buffer back out.
2758 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2759 uint8_t *untiled_s8_map
= map
->ptr
;
2760 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2761 unsigned int image_x
, image_y
;
2763 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2765 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2766 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2767 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2768 x
+ image_x
+ map
->x
,
2769 y
+ image_y
+ map
->y
,
2770 brw
->has_swizzling
);
2771 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2775 intel_miptree_unmap_raw(mt
);
2777 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2778 map
->x
, map
->y
, map
->w
, map
->h
,
2779 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2781 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2782 map
->x
, map
->y
, map
->w
, map
->h
,
2783 mt
, map
->ptr
, map
->stride
);
2788 intel_miptree_unmap_s8(struct brw_context
*brw
,
2789 struct intel_mipmap_tree
*mt
,
2790 struct intel_miptree_map
*map
,
2794 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2795 unsigned int image_x
, image_y
;
2796 uint8_t *untiled_s8_map
= map
->ptr
;
2797 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2799 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2801 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2802 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2803 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2804 image_x
+ x
+ map
->x
,
2805 image_y
+ y
+ map
->y
,
2806 brw
->has_swizzling
);
2807 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2811 intel_miptree_unmap_raw(mt
);
2818 intel_miptree_map_etc(struct brw_context
*brw
,
2819 struct intel_mipmap_tree
*mt
,
2820 struct intel_miptree_map
*map
,
2824 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2825 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2826 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2829 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2830 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2832 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2833 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2834 map
->w
, map
->h
, 1));
2835 map
->ptr
= map
->buffer
;
2839 intel_miptree_unmap_etc(struct brw_context
*brw
,
2840 struct intel_mipmap_tree
*mt
,
2841 struct intel_miptree_map
*map
,
2847 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2852 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2853 + image_y
* mt
->pitch
2854 + image_x
* mt
->cpp
;
2856 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2857 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2858 map
->ptr
, map
->stride
,
2861 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2862 map
->ptr
, map
->stride
,
2863 map
->w
, map
->h
, mt
->etc_format
);
2865 intel_miptree_unmap_raw(mt
);
2870 * Mapping function for packed depth/stencil miptrees backed by real separate
2871 * miptrees for depth and stencil.
2873 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2874 * separate from the depth buffer. Yet at the GL API level, we have to expose
2875 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2876 * be able to map that memory for texture storage and glReadPixels-type
2877 * operations. We give Mesa core that access by mallocing a temporary and
2878 * copying the data between the actual backing store and the temporary.
2881 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2882 struct intel_mipmap_tree
*mt
,
2883 struct intel_miptree_map
*map
,
2884 unsigned int level
, unsigned int slice
)
2886 struct intel_mipmap_tree
*z_mt
= mt
;
2887 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2888 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2889 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2891 map
->stride
= map
->w
* packed_bpp
;
2892 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2896 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2897 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2898 * invalidate is set, since we'll be writing the whole rectangle from our
2899 * temporary buffer back out.
2901 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2902 uint32_t *packed_map
= map
->ptr
;
2903 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2904 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2905 unsigned int s_image_x
, s_image_y
;
2906 unsigned int z_image_x
, z_image_y
;
2908 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2909 &s_image_x
, &s_image_y
);
2910 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2911 &z_image_x
, &z_image_y
);
2913 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2914 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2915 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2916 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2919 brw
->has_swizzling
);
2920 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2922 (map_x
+ z_image_x
));
2923 uint8_t s
= s_map
[s_offset
];
2924 uint32_t z
= z_map
[z_offset
];
2926 if (map_z32f_x24s8
) {
2927 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2928 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2930 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2935 intel_miptree_unmap_raw(s_mt
);
2936 intel_miptree_unmap_raw(z_mt
);
2938 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2940 map
->x
, map
->y
, map
->w
, map
->h
,
2941 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2942 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2943 map
->ptr
, map
->stride
);
2945 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2946 map
->x
, map
->y
, map
->w
, map
->h
,
2947 mt
, map
->ptr
, map
->stride
);
2952 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2953 struct intel_mipmap_tree
*mt
,
2954 struct intel_miptree_map
*map
,
2958 struct intel_mipmap_tree
*z_mt
= mt
;
2959 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2960 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2962 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2963 uint32_t *packed_map
= map
->ptr
;
2964 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2965 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2966 unsigned int s_image_x
, s_image_y
;
2967 unsigned int z_image_x
, z_image_y
;
2969 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2970 &s_image_x
, &s_image_y
);
2971 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2972 &z_image_x
, &z_image_y
);
2974 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2975 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2976 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2977 x
+ s_image_x
+ map
->x
,
2978 y
+ s_image_y
+ map
->y
,
2979 brw
->has_swizzling
);
2980 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2982 (x
+ z_image_x
+ map
->x
));
2984 if (map_z32f_x24s8
) {
2985 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2986 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2988 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2989 s_map
[s_offset
] = packed
>> 24;
2990 z_map
[z_offset
] = packed
;
2995 intel_miptree_unmap_raw(s_mt
);
2996 intel_miptree_unmap_raw(z_mt
);
2998 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3000 map
->x
, map
->y
, map
->w
, map
->h
,
3001 z_mt
, _mesa_get_format_name(z_mt
->format
),
3002 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3003 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3004 map
->ptr
, map
->stride
);
3011 * Create and attach a map to the miptree at (level, slice). Return the
3014 static struct intel_miptree_map
*
3015 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3024 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3029 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3030 mt
->level
[level
].slice
[slice
].map
= map
;
3042 * Release the map at (level, slice).
3045 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3049 struct intel_miptree_map
**map
;
3051 map
= &mt
->level
[level
].slice
[slice
].map
;
3057 can_blit_slice(struct intel_mipmap_tree
*mt
,
3058 unsigned int level
, unsigned int slice
)
3060 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3061 if (mt
->pitch
>= 32768)
3068 use_intel_mipree_map_blit(struct brw_context
*brw
,
3069 struct intel_mipmap_tree
*mt
,
3075 /* It's probably not worth swapping to the blit ring because of
3076 * all the overhead involved. But, we must use blitter for the
3077 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
3079 (!(mode
& GL_MAP_WRITE_BIT
) ||
3080 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
3082 (mt
->tiling
== I915_TILING_X
||
3083 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3084 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3085 /* Fast copy blit on skl+ supports all tiling formats. */
3087 can_blit_slice(mt
, level
, slice
))
3090 if (mt
->tiling
!= I915_TILING_NONE
&&
3091 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3092 assert(can_blit_slice(mt
, level
, slice
));
3100 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3101 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3102 * arithmetic overflow.
3104 * If you call this function and use \a out_stride, then you're doing pointer
3105 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3106 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3107 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3108 * which usually have type uint32_t or GLuint.
3111 intel_miptree_map(struct brw_context
*brw
,
3112 struct intel_mipmap_tree
*mt
,
3121 ptrdiff_t *out_stride
)
3123 struct intel_miptree_map
*map
;
3125 assert(mt
->num_samples
<= 1);
3127 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3134 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
3135 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3136 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
3139 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3140 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3141 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3142 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3143 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3144 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3145 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3146 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3147 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3148 #if defined(USE_SSE41)
3149 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3150 !mt
->compressed
&& cpu_has_sse4_1
&&
3151 (mt
->pitch
% 16 == 0)) {
3152 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3155 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
3156 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
3157 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3160 *out_ptr
= map
->ptr
;
3161 *out_stride
= map
->stride
;
3163 if (map
->ptr
== NULL
)
3164 intel_miptree_release_map(mt
, level
, slice
);
3168 intel_miptree_unmap(struct brw_context
*brw
,
3169 struct intel_mipmap_tree
*mt
,
3173 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3175 assert(mt
->num_samples
<= 1);
3180 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3181 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3183 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3184 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3185 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3186 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3187 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3188 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3189 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3190 } else if (map
->linear_mt
) {
3191 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3192 #if defined(USE_SSE41)
3193 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3194 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3197 intel_miptree_unmap_gtt(mt
);
3200 intel_miptree_release_map(mt
, level
, slice
);
3204 get_isl_surf_dim(GLenum target
)
3208 case GL_TEXTURE_1D_ARRAY
:
3209 return ISL_SURF_DIM_1D
;
3212 case GL_TEXTURE_2D_ARRAY
:
3213 case GL_TEXTURE_RECTANGLE
:
3214 case GL_TEXTURE_CUBE_MAP
:
3215 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3216 case GL_TEXTURE_2D_MULTISAMPLE
:
3217 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3218 case GL_TEXTURE_EXTERNAL_OES
:
3219 return ISL_SURF_DIM_2D
;
3222 return ISL_SURF_DIM_3D
;
3225 unreachable("Invalid texture target");
3229 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3234 case GL_TEXTURE_1D_ARRAY
:
3235 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3236 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3239 case GL_TEXTURE_2D_ARRAY
:
3240 case GL_TEXTURE_RECTANGLE
:
3241 case GL_TEXTURE_2D_MULTISAMPLE
:
3242 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3243 case GL_TEXTURE_EXTERNAL_OES
:
3244 return ISL_DIM_LAYOUT_GEN4_2D
;
3246 case GL_TEXTURE_CUBE_MAP
:
3247 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3248 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3249 ISL_DIM_LAYOUT_GEN4_2D
);
3252 return (devinfo
->gen
>= 9 ?
3253 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3256 unreachable("Invalid texture target");
3260 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3262 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3263 return ISL_TILING_W
;
3265 switch (mt
->tiling
) {
3266 case I915_TILING_NONE
:
3267 return ISL_TILING_LINEAR
;
3269 return ISL_TILING_X
;
3271 switch (mt
->tr_mode
) {
3272 case INTEL_MIPTREE_TRMODE_NONE
:
3273 return ISL_TILING_Y0
;
3274 case INTEL_MIPTREE_TRMODE_YF
:
3275 return ISL_TILING_Yf
;
3276 case INTEL_MIPTREE_TRMODE_YS
:
3277 return ISL_TILING_Ys
;
3279 unreachable("Invalid tiled resource mode");
3282 unreachable("Invalid tiling mode");
3288 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3289 const struct intel_mipmap_tree
*mt
,
3290 struct isl_surf
*surf
)
3292 surf
->dim
= get_isl_surf_dim(mt
->target
);
3293 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3294 mt
->tiling
, mt
->target
);
3296 if (mt
->num_samples
> 1) {
3297 switch (mt
->msaa_layout
) {
3298 case INTEL_MSAA_LAYOUT_IMS
:
3299 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3301 case INTEL_MSAA_LAYOUT_UMS
:
3302 case INTEL_MSAA_LAYOUT_CMS
:
3303 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3306 unreachable("Invalid MSAA layout");
3309 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3312 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3314 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3315 /* The ISL definition of row_pitch matches the surface state pitch field
3316 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3317 * the factor of 2 for W-tiling in row_pitch.
3319 surf
->row_pitch
= 2 * mt
->pitch
;
3321 surf
->row_pitch
= mt
->pitch
;
3324 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3326 if (brw
->gen
>= 9) {
3327 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3328 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3329 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3331 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3332 * alignment in terms of surface elements like we want.
3334 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3337 /* On earlier gens it's stored in pixels. */
3339 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3340 surf
->image_alignment_el
=
3341 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3344 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3345 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3346 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3347 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3348 surf
->logical_level0_px
.array_len
= 1;
3350 surf
->logical_level0_px
.depth
= 1;
3351 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3354 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3355 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3356 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3357 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3358 surf
->phys_level0_sa
.array_len
= 1;
3360 surf
->phys_level0_sa
.depth
= 1;
3361 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3364 surf
->levels
= mt
->last_level
+ 1;
3365 surf
->samples
= MAX2(mt
->num_samples
, 1);
3367 surf
->size
= 0; /* TODO */
3368 surf
->alignment
= 0; /* TODO */
3370 switch (surf
->dim_layout
) {
3371 case ISL_DIM_LAYOUT_GEN4_2D
:
3372 case ISL_DIM_LAYOUT_GEN4_3D
:
3373 if (brw
->gen
>= 9) {
3374 surf
->array_pitch_el_rows
= mt
->qpitch
;
3377 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3378 assert(mt
->qpitch
% bh
== 0);
3379 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3382 case ISL_DIM_LAYOUT_GEN9_1D
:
3383 surf
->array_pitch_el_rows
= 1;
3387 switch (mt
->array_layout
) {
3388 case ALL_LOD_IN_EACH_SLICE
:
3389 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3391 case ALL_SLICES_AT_EACH_LOD
:
3392 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3395 unreachable("Invalid array layout");
3398 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3399 switch (base_format
) {
3400 case GL_DEPTH_COMPONENT
:
3401 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3403 case GL_STENCIL_INDEX
:
3404 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3406 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3408 case GL_DEPTH_STENCIL
:
3409 /* In this case we only texture from the depth part */
3410 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3411 ISL_SURF_USAGE_TEXTURE_BIT
;
3414 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3415 if (brw
->format_supported_as_render_target
[mt
->format
])
3416 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3420 if (_mesa_is_cube_map_texture(mt
->target
))
3421 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3424 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3425 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3426 * PASS IT INTO isl_surf_fill_state.
3429 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3430 const struct intel_mipmap_tree
*mt
,
3431 struct isl_surf
*surf
,
3432 enum isl_aux_usage
*usage
)
3434 uint32_t aux_pitch
, aux_qpitch
;
3436 aux_pitch
= mt
->mcs_buf
->pitch
;
3437 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3439 if (mt
->num_samples
> 1) {
3440 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3441 *usage
= ISL_AUX_USAGE_MCS
;
3442 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3443 assert(brw
->gen
>= 9);
3444 *usage
= ISL_AUX_USAGE_CCS_E
;
3445 } else if (!mt
->no_ccs
) {
3446 *usage
= ISL_AUX_USAGE_CCS_D
;
3448 unreachable("Invalid MCS miptree");
3450 } else if (mt
->hiz_buf
) {
3451 if (mt
->hiz_buf
->mt
) {
3452 aux_pitch
= mt
->hiz_buf
->mt
->pitch
;
3453 aux_qpitch
= mt
->hiz_buf
->mt
->qpitch
;
3455 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3456 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3459 *usage
= ISL_AUX_USAGE_HIZ
;
3461 *usage
= ISL_AUX_USAGE_NONE
;
3465 /* Start with a copy of the original surface. */
3466 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3468 /* Figure out the format and tiling of the auxiliary surface */
3470 case ISL_AUX_USAGE_NONE
:
3471 unreachable("Invalid auxiliary usage");
3473 case ISL_AUX_USAGE_HIZ
:
3474 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3477 case ISL_AUX_USAGE_MCS
:
3480 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3481 * HALIGN 16 must be used."
3484 assert(mt
->halign
== 16);
3486 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3489 case ISL_AUX_USAGE_CCS_D
:
3490 case ISL_AUX_USAGE_CCS_E
:
3492 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3494 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3496 * From the hardware spec for GEN9:
3498 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3499 * HALIGN 16 must be used."
3501 assert(mt
->num_samples
<= 1);
3503 assert(mt
->halign
== 16);
3505 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3509 /* We want the pitch of the actual aux buffer. */
3510 surf
->row_pitch
= aux_pitch
;
3512 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3513 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3514 * in elements of the primary color surface so we have to divide by the
3515 * compression block height.
3517 surf
->array_pitch_el_rows
=
3518 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3521 union isl_color_value
3522 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3523 const struct intel_mipmap_tree
*mt
)
3525 union isl_color_value clear_color
;
3527 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3528 clear_color
.i32
[0] = mt
->depth_clear_value
;
3529 clear_color
.i32
[1] = 0;
3530 clear_color
.i32
[2] = 0;
3531 clear_color
.i32
[3] = 0;
3532 } else if (brw
->gen
>= 9) {
3533 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3534 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3535 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3536 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3537 } else if (_mesa_is_format_integer(mt
->format
)) {
3538 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3539 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3540 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3541 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3543 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3544 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3545 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3546 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;