1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 * Determine which MSAA layout should be used by the MSAA surface being
54 * created, based on the chip generation and the surface type.
56 static enum intel_msaa_layout
57 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
59 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
61 return INTEL_MSAA_LAYOUT_IMS
;
63 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
64 switch (_mesa_get_format_base_format(format
)) {
65 case GL_DEPTH_COMPONENT
:
66 case GL_STENCIL_INDEX
:
67 case GL_DEPTH_STENCIL
:
68 return INTEL_MSAA_LAYOUT_IMS
;
70 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
72 * This field must be set to 0 for all SINT MSRTs when all RT channels
75 * In practice this means that we have to disable MCS for all signed
76 * integer MSAA buffers. The alternative, to disable MCS only when one
77 * of the render target channels is disabled, is impractical because it
78 * would require converting between CMS and UMS MSAA layouts on the fly,
81 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
82 return INTEL_MSAA_LAYOUT_UMS
;
84 return INTEL_MSAA_LAYOUT_CMS
;
91 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
92 * scaled-down bitfield representation of the color buffer which is capable of
93 * recording when blocks of the color buffer are equal to the clear value.
94 * This function returns the block size that will be used by the MCS buffer
95 * corresponding to a certain color miptree.
97 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
98 * beneath the "Fast Color Clear" bullet (p327):
100 * The following table describes the RT alignment
114 * This alignment has the following uses:
116 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
117 * buffer contains 128 blocks horizontally and 256 blocks vertically.
119 * - For figuring out alignment restrictions for a fast clear operation. Fast
120 * clear operations must always clear aligned multiples of 16 blocks
121 * horizontally and 32 blocks vertically.
123 * - For scaling down the coordinates sent through the render pipeline during
124 * a fast clear. X coordinates must be scaled down by 8 times the block
125 * width, and Y coordinates by 16 times the block height.
127 * - For scaling down the coordinates sent through the render pipeline during
128 * a "Render Target Resolve" operation. X coordinates must be scaled down
129 * by half the block width, and Y coordinates by half the block height.
132 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
133 struct intel_mipmap_tree
*mt
,
134 unsigned *width_px
, unsigned *height
)
136 switch (mt
->tiling
) {
138 unreachable("Non-MSRT MCS requires X or Y tiling");
139 /* In release builds, fall through */
141 *width_px
= 32 / mt
->cpp
;
145 *width_px
= 64 / mt
->cpp
;
152 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
155 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
156 * beneath the "Fast Color Clear" bullet (p326):
158 * - Support is limited to tiled render targets.
159 * - Support is for non-mip-mapped and non-array surface types only.
161 * And then later, on p327:
163 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
167 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
168 struct intel_mipmap_tree
*mt
)
170 /* MCS support does not exist prior to Gen7 */
174 /* MCS is only supported for color buffers */
175 switch (_mesa_get_format_base_format(mt
->format
)) {
176 case GL_DEPTH_COMPONENT
:
177 case GL_DEPTH_STENCIL
:
178 case GL_STENCIL_INDEX
:
182 if (mt
->tiling
!= I915_TILING_X
&&
183 mt
->tiling
!= I915_TILING_Y
)
185 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
187 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
189 if (mt
->physical_depth0
!= 1)
192 /* There's no point in using an MCS buffer if the surface isn't in a
195 if (!brw
->format_supported_as_render_target
[mt
->format
])
203 * Determine depth format corresponding to a depth+stencil format,
204 * for separate stencil.
207 intel_depth_format_for_depthstencil_format(mesa_format format
) {
209 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
210 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
211 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
212 return MESA_FORMAT_Z_FLOAT32
;
220 * @param for_bo Indicates that the caller is
221 * intel_miptree_create_for_bo(). If true, then do not create
224 struct intel_mipmap_tree
*
225 intel_miptree_create_layout(struct brw_context
*brw
,
235 bool force_all_slices_at_each_lod
)
237 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
241 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
242 _mesa_lookup_enum_by_nr(target
),
243 _mesa_get_format_name(format
),
244 first_level
, last_level
, depth0
, mt
);
246 if (target
== GL_TEXTURE_1D_ARRAY
) {
247 /* For a 1D Array texture the OpenGL API will treat the height0
248 * parameter as the number of array slices. For Intel hardware, we treat
249 * the 1D array as a 2D Array with a height of 1.
251 * So, when we first come through this path to create a 1D Array
252 * texture, height0 stores the number of slices, and depth0 is 1. In
253 * this case, we want to swap height0 and depth0.
255 * Since some miptrees will be created based on the base miptree, we may
256 * come through this path and see height0 as 1 and depth0 being the
257 * number of slices. In this case we don't need to do the swap.
259 assert(height0
== 1 || depth0
== 1);
268 mt
->first_level
= first_level
;
269 mt
->last_level
= last_level
;
270 mt
->logical_width0
= width0
;
271 mt
->logical_height0
= height0
;
272 mt
->logical_depth0
= depth0
;
273 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
274 exec_list_make_empty(&mt
->hiz_map
);
276 /* The cpp is bytes per (1, blockheight)-sized block for compressed
277 * textures. This is why you'll see divides by blockheight all over
280 _mesa_get_format_block_size(format
, &bw
, &bh
);
281 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
282 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
284 mt
->num_samples
= num_samples
;
285 mt
->compressed
= _mesa_is_format_compressed(format
);
286 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
289 if (num_samples
> 1) {
290 /* Adjust width/height/depth for MSAA */
291 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
292 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
293 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
295 * "Any of the other messages (sample*, LOD, load4) used with a
296 * (4x) multisampled surface will in-effect sample a surface with
297 * double the height and width as that indicated in the surface
298 * state. Each pixel position on the original-sized surface is
299 * replaced with a 2x2 of samples with the following arrangement:
304 * Thus, when sampling from a multisampled texture, it behaves as
305 * though the layout in memory for (x,y,sample) is:
307 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
308 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
310 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
311 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
313 * However, the actual layout of multisampled data in memory is:
315 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
316 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
318 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
319 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
321 * This pattern repeats for each 2x2 pixel block.
323 * As a result, when calculating the size of our 4-sample buffer for
324 * an odd width or height, we have to align before scaling up because
325 * sample 3 is in that bottom right 2x2 block.
327 switch (num_samples
) {
329 assert(brw
->gen
>= 8);
330 width0
= ALIGN(width0
, 2) * 2;
331 height0
= ALIGN(height0
, 2);
334 width0
= ALIGN(width0
, 2) * 2;
335 height0
= ALIGN(height0
, 2) * 2;
338 width0
= ALIGN(width0
, 2) * 4;
339 height0
= ALIGN(height0
, 2) * 2;
342 /* num_samples should already have been quantized to 0, 1, 2, 4, or
345 unreachable("not reached");
348 /* Non-interleaved */
349 depth0
*= num_samples
;
353 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
354 * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
355 * TODO: can we use it elsewhere?
357 switch (mt
->msaa_layout
) {
358 case INTEL_MSAA_LAYOUT_NONE
:
359 case INTEL_MSAA_LAYOUT_IMS
:
360 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
362 case INTEL_MSAA_LAYOUT_UMS
:
363 case INTEL_MSAA_LAYOUT_CMS
:
364 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
368 if (target
== GL_TEXTURE_CUBE_MAP
) {
373 mt
->physical_width0
= width0
;
374 mt
->physical_height0
= height0
;
375 mt
->physical_depth0
= depth0
;
378 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
379 (brw
->must_use_separate_stencil
||
380 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
381 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
382 mt
->stencil_mt
= intel_miptree_create(brw
,
392 INTEL_MIPTREE_TILING_ANY
,
393 force_all_slices_at_each_lod
);
394 if (!mt
->stencil_mt
) {
395 intel_miptree_release(&mt
);
399 /* Fix up the Z miptree format for how we're splitting out separate
400 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
402 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
405 if (format
== mt
->format
) {
406 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
407 _mesa_get_format_name(mt
->format
));
411 if (force_all_slices_at_each_lod
)
412 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
414 brw_miptree_layout(brw
, mt
);
420 * \brief Helper function for intel_miptree_create().
423 intel_miptree_choose_tiling(struct brw_context
*brw
,
426 uint32_t num_samples
,
427 enum intel_miptree_tiling_mode requested
,
428 struct intel_mipmap_tree
*mt
)
430 if (format
== MESA_FORMAT_S_UINT8
) {
431 /* The stencil buffer is W tiled. However, we request from the kernel a
432 * non-tiled buffer because the GTT is incapable of W fencing.
434 return I915_TILING_NONE
;
437 /* Some usages may want only one type of tiling, like depth miptrees (Y
438 * tiled), or temporary BOs for uploading data once (linear).
441 case INTEL_MIPTREE_TILING_ANY
:
443 case INTEL_MIPTREE_TILING_Y
:
444 return I915_TILING_Y
;
445 case INTEL_MIPTREE_TILING_NONE
:
446 return I915_TILING_NONE
;
449 if (num_samples
> 1) {
450 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
453 * [DevSNB+]: For multi-sample render targets, this field must be
454 * 1. MSRTs can only be tiled.
456 * Our usual reason for preferring X tiling (fast blits using the
457 * blitting engine) doesn't apply to MSAA, since we'll generally be
458 * downsampling or upsampling when blitting between the MSAA buffer
459 * and another buffer, and the blitting engine doesn't support that.
460 * So use Y tiling, since it makes better use of the cache.
462 return I915_TILING_Y
;
465 GLenum base_format
= _mesa_get_format_base_format(format
);
466 if (base_format
== GL_DEPTH_COMPONENT
||
467 base_format
== GL_DEPTH_STENCIL_EXT
)
468 return I915_TILING_Y
;
470 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
472 /* If the width is much smaller than a tile, don't bother tiling. */
473 if (minimum_pitch
< 64)
474 return I915_TILING_NONE
;
476 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
477 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
478 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
479 mt
->total_width
, mt
->total_height
);
480 return I915_TILING_NONE
;
483 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
485 return I915_TILING_X
;
487 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
488 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
490 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
491 * all the way back to 965, but is explicitly permitted on Gen7.
493 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
494 return I915_TILING_X
;
496 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
497 * messages), on p64, under the heading "Surface Vertical Alignment":
499 * This field must be set to VALIGN_4 for all tiled Y Render Target
502 * So if the surface is renderable and uses a vertical alignment of 2,
503 * force it to be X tiled. This is somewhat conservative (it's possible
504 * that the client won't ever render to this surface), but it's difficult
505 * to know that ahead of time. And besides, since we use a vertical
506 * alignment of 4 as often as we can, this shouldn't happen very often.
508 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
509 brw
->format_supported_as_render_target
[format
]) {
510 return I915_TILING_X
;
513 return I915_TILING_Y
| I915_TILING_X
;
518 * Choose an appropriate uncompressed format for a requested
519 * compressed format, if unsupported.
522 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
524 /* No need to lower ETC formats on these platforms,
525 * they are supported natively.
527 if (brw
->gen
>= 8 || brw
->is_baytrail
)
531 case MESA_FORMAT_ETC1_RGB8
:
532 return MESA_FORMAT_R8G8B8X8_UNORM
;
533 case MESA_FORMAT_ETC2_RGB8
:
534 return MESA_FORMAT_R8G8B8X8_UNORM
;
535 case MESA_FORMAT_ETC2_SRGB8
:
536 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
537 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
538 return MESA_FORMAT_B8G8R8A8_SRGB
;
539 case MESA_FORMAT_ETC2_RGBA8_EAC
:
540 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
541 return MESA_FORMAT_R8G8B8A8_UNORM
;
542 case MESA_FORMAT_ETC2_R11_EAC
:
543 return MESA_FORMAT_R_UNORM16
;
544 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
545 return MESA_FORMAT_R_SNORM16
;
546 case MESA_FORMAT_ETC2_RG11_EAC
:
547 return MESA_FORMAT_R16G16_UNORM
;
548 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
549 return MESA_FORMAT_R16G16_SNORM
;
551 /* Non ETC1 / ETC2 format */
557 struct intel_mipmap_tree
*
558 intel_miptree_create(struct brw_context
*brw
,
566 bool expect_accelerated_upload
,
568 enum intel_miptree_tiling_mode requested_tiling
,
569 bool force_all_slices_at_each_lod
)
571 struct intel_mipmap_tree
*mt
;
572 mesa_format tex_format
= format
;
573 mesa_format etc_format
= MESA_FORMAT_NONE
;
574 GLuint total_width
, total_height
;
576 format
= intel_lower_compressed_format(brw
, format
);
578 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
580 mt
= intel_miptree_create_layout(brw
, target
, format
,
581 first_level
, last_level
, width0
,
584 force_all_slices_at_each_lod
);
586 * pitch == 0 || height == 0 indicates the null texture
588 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
589 intel_miptree_release(&mt
);
593 total_width
= mt
->total_width
;
594 total_height
= mt
->total_height
;
596 if (format
== MESA_FORMAT_S_UINT8
) {
597 /* Align to size of W tile, 64x64. */
598 total_width
= ALIGN(total_width
, 64);
599 total_height
= ALIGN(total_height
, 64);
602 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
603 num_samples
, requested_tiling
,
607 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
609 mt
->tiling
= I915_TILING_Y
;
615 mt
->etc_format
= etc_format
;
616 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
617 total_width
, total_height
, mt
->cpp
,
619 (expect_accelerated_upload
?
620 BO_ALLOC_FOR_RENDER
: 0));
623 /* If the BO is too large to fit in the aperture, we need to use the
624 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
625 * so we need to fall back to X.
627 if (y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
628 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
629 mt
->total_width
, mt
->total_height
);
631 mt
->tiling
= I915_TILING_X
;
632 drm_intel_bo_unreference(mt
->bo
);
633 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
634 total_width
, total_height
, mt
->cpp
,
636 (expect_accelerated_upload
?
637 BO_ALLOC_FOR_RENDER
: 0));
644 intel_miptree_release(&mt
);
649 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
650 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
651 intel_miptree_release(&mt
);
656 /* If this miptree is capable of supporting fast color clears, set
657 * fast_clear_state appropriately to ensure that fast clears will occur.
658 * Allocation of the MCS miptree will be deferred until the first fast
659 * clear actually occurs.
661 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
662 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
667 struct intel_mipmap_tree
*
668 intel_miptree_create_for_bo(struct brw_context
*brw
,
676 struct intel_mipmap_tree
*mt
;
677 uint32_t tiling
, swizzle
;
679 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
681 /* Nothing will be able to use this miptree with the BO if the offset isn't
684 if (tiling
!= I915_TILING_NONE
)
685 assert(offset
% 4096 == 0);
687 /* miptrees can't handle negative pitch. If you need flipping of images,
688 * that's outside of the scope of the mt.
692 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
701 drm_intel_bo_reference(bo
);
711 * For a singlesample renderbuffer, this simply wraps the given BO with a
714 * For a multisample renderbuffer, this wraps the window system's
715 * (singlesample) BO with a singlesample miptree attached to the
716 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
717 * that will contain the actual rendering (which is lazily resolved to
718 * irb->singlesample_mt).
721 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
722 struct intel_renderbuffer
*irb
,
724 uint32_t width
, uint32_t height
,
727 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
728 struct intel_mipmap_tree
*multisample_mt
= NULL
;
729 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
730 mesa_format format
= rb
->Format
;
731 int num_samples
= rb
->NumSamples
;
733 /* Only the front and back buffers, which are color buffers, are allocated
734 * through the image loader.
736 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
737 _mesa_get_format_base_format(format
) == GL_RGBA
);
739 singlesample_mt
= intel_miptree_create_for_bo(intel
,
746 if (!singlesample_mt
)
749 /* If this miptree is capable of supporting fast color clears, set
750 * mcs_state appropriately to ensure that fast clears will occur.
751 * Allocation of the MCS miptree will be deferred until the first fast
752 * clear actually occurs.
754 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
755 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
757 if (num_samples
== 0) {
758 intel_miptree_release(&irb
->mt
);
759 irb
->mt
= singlesample_mt
;
761 assert(!irb
->singlesample_mt
);
763 intel_miptree_release(&irb
->singlesample_mt
);
764 irb
->singlesample_mt
= singlesample_mt
;
767 irb
->mt
->logical_width0
!= width
||
768 irb
->mt
->logical_height0
!= height
) {
769 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
777 irb
->need_downsample
= false;
778 intel_miptree_release(&irb
->mt
);
779 irb
->mt
= multisample_mt
;
785 intel_miptree_release(&irb
->singlesample_mt
);
786 intel_miptree_release(&irb
->mt
);
790 struct intel_mipmap_tree
*
791 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
795 uint32_t num_samples
)
797 struct intel_mipmap_tree
*mt
;
800 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
802 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
803 width
, height
, depth
, true, num_samples
,
804 INTEL_MIPTREE_TILING_ANY
, false);
808 if (brw_is_hiz_depth_format(brw
, format
)) {
809 ok
= intel_miptree_alloc_hiz(brw
, mt
);
817 intel_miptree_release(&mt
);
822 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
823 struct intel_mipmap_tree
*src
)
828 intel_miptree_release(dst
);
832 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
840 intel_miptree_release(struct intel_mipmap_tree
**mt
)
845 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
846 if (--(*mt
)->refcount
<= 0) {
849 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
851 drm_intel_bo_unreference((*mt
)->bo
);
852 intel_miptree_release(&(*mt
)->stencil_mt
);
853 intel_miptree_release(&(*mt
)->hiz_mt
);
854 intel_miptree_release(&(*mt
)->mcs_mt
);
855 intel_resolve_map_clear(&(*mt
)->hiz_map
);
857 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
858 free((*mt
)->level
[i
].slice
);
867 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
868 int *width
, int *height
, int *depth
)
870 switch (image
->TexObject
->Target
) {
871 case GL_TEXTURE_1D_ARRAY
:
872 *width
= image
->Width
;
874 *depth
= image
->Height
;
877 *width
= image
->Width
;
878 *height
= image
->Height
;
879 *depth
= image
->Depth
;
885 * Can the image be pulled into a unified mipmap tree? This mirrors
886 * the completeness test in a lot of ways.
888 * Not sure whether I want to pass gl_texture_image here.
891 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
892 struct gl_texture_image
*image
)
894 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
895 GLuint level
= intelImage
->base
.Base
.Level
;
896 int width
, height
, depth
;
898 /* glTexImage* choose the texture object based on the target passed in, and
899 * objects can't change targets over their lifetimes, so this should be
902 assert(image
->TexObject
->Target
== mt
->target
);
904 mesa_format mt_format
= mt
->format
;
905 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
906 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
907 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
908 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
909 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
910 mt_format
= mt
->etc_format
;
912 if (image
->TexFormat
!= mt_format
)
915 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
917 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
920 int level_depth
= mt
->level
[level
].depth
;
921 if (mt
->num_samples
> 1) {
922 switch (mt
->msaa_layout
) {
923 case INTEL_MSAA_LAYOUT_NONE
:
924 case INTEL_MSAA_LAYOUT_IMS
:
926 case INTEL_MSAA_LAYOUT_UMS
:
927 case INTEL_MSAA_LAYOUT_CMS
:
928 level_depth
/= mt
->num_samples
;
933 /* Test image dimensions against the base level image adjusted for
934 * minification. This will also catch images not present in the
935 * tree, changed targets, etc.
937 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
938 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
939 depth
!= level_depth
) {
943 if (image
->NumSamples
!= mt
->num_samples
)
951 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
953 GLuint x
, GLuint y
, GLuint d
)
955 mt
->level
[level
].depth
= d
;
956 mt
->level
[level
].level_x
= x
;
957 mt
->level
[level
].level_y
= y
;
959 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
962 assert(mt
->level
[level
].slice
== NULL
);
964 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
965 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
966 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
971 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
972 GLuint level
, GLuint img
,
975 if (img
== 0 && level
== 0)
976 assert(x
== 0 && y
== 0);
978 assert(img
< mt
->level
[level
].depth
);
980 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
981 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
983 DBG("%s level %d img %d pos %d,%d\n",
984 __FUNCTION__
, level
, img
,
985 mt
->level
[level
].slice
[img
].x_offset
,
986 mt
->level
[level
].slice
[img
].y_offset
);
990 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
991 GLuint level
, GLuint slice
,
992 GLuint
*x
, GLuint
*y
)
994 assert(slice
< mt
->level
[level
].depth
);
996 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
997 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1001 * This function computes masks that may be used to select the bits of the X
1002 * and Y coordinates that indicate the offset within a tile. If the BO is
1003 * untiled, the masks are set to 0.
1006 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1007 uint32_t *mask_x
, uint32_t *mask_y
,
1008 bool map_stencil_as_y_tiled
)
1011 uint32_t tiling
= mt
->tiling
;
1013 if (map_stencil_as_y_tiled
)
1014 tiling
= I915_TILING_Y
;
1018 unreachable("not reached");
1019 case I915_TILING_NONE
:
1020 *mask_x
= *mask_y
= 0;
1023 *mask_x
= 512 / cpp
- 1;
1027 *mask_x
= 128 / cpp
- 1;
1034 * Compute the offset (in bytes) from the start of the BO to the given x
1035 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1036 * multiples of the tile size.
1039 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1040 uint32_t x
, uint32_t y
,
1041 bool map_stencil_as_y_tiled
)
1044 uint32_t pitch
= mt
->pitch
;
1045 uint32_t tiling
= mt
->tiling
;
1047 if (map_stencil_as_y_tiled
) {
1048 tiling
= I915_TILING_Y
;
1050 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1051 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1052 * the resulting surface is twice the pitch of the original miptree,
1053 * since each row in the Y-tiled view corresponds to two rows in the
1054 * actual W-tiled surface. So we need to correct the pitch before
1055 * computing the offsets.
1062 unreachable("not reached");
1063 case I915_TILING_NONE
:
1064 return y
* pitch
+ x
* cpp
;
1066 assert((x
% (512 / cpp
)) == 0);
1067 assert((y
% 8) == 0);
1068 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1070 assert((x
% (128 / cpp
)) == 0);
1071 assert((y
% 32) == 0);
1072 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1077 * Rendering with tiled buffers requires that the base address of the buffer
1078 * be aligned to a page boundary. For renderbuffers, and sometimes with
1079 * textures, we may want the surface to point at a texture image level that
1080 * isn't at a page boundary.
1082 * This function returns an appropriately-aligned base offset
1083 * according to the tiling restrictions, plus any required x/y offset
1087 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1088 GLuint level
, GLuint slice
,
1093 uint32_t mask_x
, mask_y
;
1095 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1096 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1098 *tile_x
= x
& mask_x
;
1099 *tile_y
= y
& mask_y
;
1101 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1105 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1106 struct intel_mipmap_tree
*dst_mt
,
1107 struct intel_mipmap_tree
*src_mt
,
1114 int src_stride
, dst_stride
;
1115 int cpp
= dst_mt
->cpp
;
1117 intel_miptree_map(brw
, src_mt
,
1121 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1124 intel_miptree_map(brw
, dst_mt
,
1128 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1132 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1133 _mesa_get_format_name(src_mt
->format
),
1134 src_mt
, src
, src_stride
,
1135 _mesa_get_format_name(dst_mt
->format
),
1136 dst_mt
, dst
, dst_stride
,
1139 int row_size
= cpp
* width
;
1140 if (src_stride
== row_size
&&
1141 dst_stride
== row_size
) {
1142 memcpy(dst
, src
, row_size
* height
);
1144 for (int i
= 0; i
< height
; i
++) {
1145 memcpy(dst
, src
, row_size
);
1151 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1152 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1154 /* Don't forget to copy the stencil data over, too. We could have skipped
1155 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1156 * shuffling the two data sources in/out of temporary storage instead of
1157 * the direct mapping we get this way.
1159 if (dst_mt
->stencil_mt
) {
1160 assert(src_mt
->stencil_mt
);
1161 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1162 level
, slice
, width
, height
);
1167 intel_miptree_copy_slice(struct brw_context
*brw
,
1168 struct intel_mipmap_tree
*dst_mt
,
1169 struct intel_mipmap_tree
*src_mt
,
1175 mesa_format format
= src_mt
->format
;
1176 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1177 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1185 assert(depth
< src_mt
->level
[level
].depth
);
1186 assert(src_mt
->format
== dst_mt
->format
);
1188 if (dst_mt
->compressed
) {
1189 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1190 width
= ALIGN(width
, dst_mt
->align_w
);
1193 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1194 * below won't apply since we can't do the depth's Y tiling or the
1195 * stencil's W tiling in the blitter.
1197 if (src_mt
->stencil_mt
) {
1198 intel_miptree_copy_slice_sw(brw
,
1205 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1206 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1207 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1209 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1210 _mesa_get_format_name(src_mt
->format
),
1211 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1212 _mesa_get_format_name(dst_mt
->format
),
1213 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1216 if (!intel_miptree_blit(brw
,
1217 src_mt
, level
, slice
, 0, 0, false,
1218 dst_mt
, level
, slice
, 0, 0, false,
1219 width
, height
, GL_COPY
)) {
1220 perf_debug("miptree validate blit for %s failed\n",
1221 _mesa_get_format_name(format
));
1223 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1229 * Copies the image's current data to the given miptree, and associates that
1230 * miptree with the image.
1232 * If \c invalidate is true, then the actual image data does not need to be
1233 * copied, but the image still needs to be associated to the new miptree (this
1234 * is set to true if we're about to clear the image).
1237 intel_miptree_copy_teximage(struct brw_context
*brw
,
1238 struct intel_texture_image
*intelImage
,
1239 struct intel_mipmap_tree
*dst_mt
,
1242 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1243 struct intel_texture_object
*intel_obj
=
1244 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1245 int level
= intelImage
->base
.Base
.Level
;
1246 int face
= intelImage
->base
.Base
.Face
;
1247 GLuint depth
= intelImage
->base
.Base
.Depth
;
1250 for (int slice
= 0; slice
< depth
; slice
++) {
1251 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1255 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1256 intel_obj
->needs_validate
= true;
1260 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1261 struct intel_mipmap_tree
*mt
,
1264 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1265 assert(mt
->mcs_mt
== NULL
);
1267 /* Choose the correct format for the MCS buffer. All that really matters
1268 * is that we allocate the right buffer size, since we'll always be
1269 * accessing this miptree using MCS-specific hardware mechanisms, which
1270 * infer the correct format based on num_samples.
1273 switch (num_samples
) {
1276 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1279 format
= MESA_FORMAT_R_UNORM8
;
1282 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1283 * for each sample, plus 8 padding bits).
1285 format
= MESA_FORMAT_R_UINT32
;
1288 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1291 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1293 * "The MCS surface must be stored as Tile Y."
1295 mt
->mcs_mt
= intel_miptree_create(brw
,
1301 mt
->logical_height0
,
1304 0 /* num_samples */,
1305 INTEL_MIPTREE_TILING_Y
,
1308 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1310 * When MCS buffer is enabled and bound to MSRT, it is required that it
1311 * is cleared prior to any rendering.
1313 * Since we don't use the MCS buffer for any purpose other than rendering,
1314 * it makes sense to just clear it immediately upon allocation.
1316 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1318 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1319 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1320 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1321 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1328 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1329 struct intel_mipmap_tree
*mt
)
1331 assert(mt
->mcs_mt
== NULL
);
1333 /* The format of the MCS buffer is opaque to the driver; all that matters
1334 * is that we get its size and pitch right. We'll pretend that the format
1335 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1336 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1337 * the block width and then a further factor of 4. Since an MCS tile
1338 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1339 * we'll need to scale the height down by the block height and then a
1340 * further factor of 8.
1342 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1343 unsigned block_width_px
;
1344 unsigned block_height
;
1345 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1346 unsigned width_divisor
= block_width_px
* 4;
1347 unsigned height_divisor
= block_height
* 8;
1348 unsigned mcs_width
=
1349 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1350 unsigned mcs_height
=
1351 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1352 assert(mt
->logical_depth0
== 1);
1353 mt
->mcs_mt
= intel_miptree_create(brw
,
1362 0 /* num_samples */,
1363 INTEL_MIPTREE_TILING_Y
,
1371 * Helper for intel_miptree_alloc_hiz() that sets
1372 * \c mt->level[level].has_hiz. Return true if and only if
1373 * \c has_hiz was set.
1376 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1377 struct intel_mipmap_tree
*mt
,
1382 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1383 uint32_t width
= minify(mt
->physical_width0
, level
);
1384 uint32_t height
= minify(mt
->physical_height0
, level
);
1386 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1387 * and the height is 4 aligned. This allows our HiZ support
1388 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1389 * we can grow the width & height to allow the HiZ op to
1390 * force the proper size alignments.
1392 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1393 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1398 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1399 mt
->level
[level
].has_hiz
= true;
1406 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1407 struct intel_mipmap_tree
*mt
)
1409 assert(mt
->hiz_mt
== NULL
);
1410 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1411 mt
->hiz_mt
= intel_miptree_create(brw
,
1417 mt
->logical_height0
,
1421 INTEL_MIPTREE_TILING_ANY
,
1422 force_all_slices_at_each_lod
);
1427 /* Mark that all slices need a HiZ resolve. */
1428 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1429 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1432 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1433 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1434 exec_node_init(&m
->link
);
1437 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1439 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1447 * Does the miptree slice have hiz enabled?
1450 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1452 intel_miptree_check_level_layer(mt
, level
, 0);
1453 return mt
->level
[level
].has_hiz
;
1457 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1461 if (!intel_miptree_level_has_hiz(mt
, level
))
1464 intel_resolve_map_set(&mt
->hiz_map
,
1465 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1470 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1474 if (!intel_miptree_level_has_hiz(mt
, level
))
1477 intel_resolve_map_set(&mt
->hiz_map
,
1478 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1482 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1486 uint32_t end_layer
= mt
->level
[level
].depth
;
1488 for (layer
= 0; layer
< end_layer
; layer
++) {
1489 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1494 intel_miptree_slice_resolve(struct brw_context
*brw
,
1495 struct intel_mipmap_tree
*mt
,
1498 enum gen6_hiz_op need
)
1500 intel_miptree_check_level_layer(mt
, level
, layer
);
1502 struct intel_resolve_map
*item
=
1503 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1505 if (!item
|| item
->need
!= need
)
1508 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1509 intel_resolve_map_remove(item
);
1514 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1515 struct intel_mipmap_tree
*mt
,
1519 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1520 GEN6_HIZ_OP_HIZ_RESOLVE
);
1524 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1525 struct intel_mipmap_tree
*mt
,
1529 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1530 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1534 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1535 struct intel_mipmap_tree
*mt
,
1536 enum gen6_hiz_op need
)
1538 bool did_resolve
= false;
1540 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1541 if (map
->need
!= need
)
1544 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1545 intel_resolve_map_remove(map
);
1553 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1554 struct intel_mipmap_tree
*mt
)
1556 return intel_miptree_all_slices_resolve(brw
, mt
,
1557 GEN6_HIZ_OP_HIZ_RESOLVE
);
1561 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1562 struct intel_mipmap_tree
*mt
)
1564 return intel_miptree_all_slices_resolve(brw
, mt
,
1565 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1570 intel_miptree_resolve_color(struct brw_context
*brw
,
1571 struct intel_mipmap_tree
*mt
)
1573 switch (mt
->fast_clear_state
) {
1574 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1575 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1576 /* No resolve needed */
1578 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1579 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1580 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1581 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1582 brw_meta_resolve_color(brw
, mt
);
1589 * Make it possible to share the BO backing the given miptree with another
1590 * process or another miptree.
1592 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1593 * then discard the MCS buffer, if present. We also set the fast_clear_state
1594 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1595 * allocated in the future.
1598 intel_miptree_make_shareable(struct brw_context
*brw
,
1599 struct intel_mipmap_tree
*mt
)
1601 /* MCS buffers are also used for multisample buffers, but we can't resolve
1602 * away a multisample MCS buffer because it's an integral part of how the
1603 * pixel data is stored. Fortunately this code path should never be
1604 * reached for multisample buffers.
1606 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1609 intel_miptree_resolve_color(brw
, mt
);
1610 intel_miptree_release(&mt
->mcs_mt
);
1611 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1617 * \brief Get pointer offset into stencil buffer.
1619 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1620 * must decode the tile's layout in software.
1623 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1625 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1627 * Even though the returned offset is always positive, the return type is
1629 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1630 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1633 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1635 uint32_t tile_size
= 4096;
1636 uint32_t tile_width
= 64;
1637 uint32_t tile_height
= 64;
1638 uint32_t row_size
= 64 * stride
;
1640 uint32_t tile_x
= x
/ tile_width
;
1641 uint32_t tile_y
= y
/ tile_height
;
1643 /* The byte's address relative to the tile's base addres. */
1644 uint32_t byte_x
= x
% tile_width
;
1645 uint32_t byte_y
= y
% tile_height
;
1647 uintptr_t u
= tile_y
* row_size
1648 + tile_x
* tile_size
1649 + 512 * (byte_x
/ 8)
1651 + 32 * ((byte_y
/ 4) % 2)
1652 + 16 * ((byte_x
/ 4) % 2)
1653 + 8 * ((byte_y
/ 2) % 2)
1654 + 4 * ((byte_x
/ 2) % 2)
1659 /* adjust for bit6 swizzling */
1660 if (((byte_x
/ 8) % 2) == 1) {
1661 if (((byte_y
/ 8) % 2) == 0) {
1673 intel_miptree_updownsample(struct brw_context
*brw
,
1674 struct intel_mipmap_tree
*src
,
1675 struct intel_mipmap_tree
*dst
)
1678 brw_blorp_blit_miptrees(brw
,
1679 src
, 0 /* level */, 0 /* layer */, src
->format
,
1680 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
1682 src
->logical_width0
, src
->logical_height0
,
1684 dst
->logical_width0
, dst
->logical_height0
,
1685 GL_NEAREST
, false, false /*mirror x, y*/);
1686 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1687 brw_meta_stencil_updownsample(brw
, src
, dst
);
1689 brw_meta_updownsample(brw
, src
, dst
);
1692 if (src
->stencil_mt
) {
1693 if (brw
->gen
>= 8) {
1694 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1698 brw_blorp_blit_miptrees(brw
,
1699 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1700 src
->stencil_mt
->format
,
1701 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1702 dst
->stencil_mt
->format
,
1704 src
->logical_width0
, src
->logical_height0
,
1706 dst
->logical_width0
, dst
->logical_height0
,
1707 GL_NEAREST
, false, false /*mirror x, y*/);
1712 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1714 /* CPU accesses to color buffers don't understand fast color clears, so
1715 * resolve any pending fast color clears before we map.
1717 intel_miptree_resolve_color(brw
, mt
);
1719 drm_intel_bo
*bo
= mt
->bo
;
1721 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1722 intel_batchbuffer_flush(brw
);
1724 if (mt
->tiling
!= I915_TILING_NONE
)
1725 brw_bo_map_gtt(brw
, bo
, "miptree");
1727 brw_bo_map(brw
, bo
, true, "miptree");
1733 intel_miptree_unmap_raw(struct brw_context
*brw
,
1734 struct intel_mipmap_tree
*mt
)
1736 drm_intel_bo_unmap(mt
->bo
);
1740 intel_miptree_map_gtt(struct brw_context
*brw
,
1741 struct intel_mipmap_tree
*mt
,
1742 struct intel_miptree_map
*map
,
1743 unsigned int level
, unsigned int slice
)
1745 unsigned int bw
, bh
;
1747 unsigned int image_x
, image_y
;
1751 /* For compressed formats, the stride is the number of bytes per
1752 * row of blocks. intel_miptree_get_image_offset() already does
1755 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1756 assert(y
% bh
== 0);
1759 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1764 /* Note that in the case of cube maps, the caller must have passed the
1765 * slice number referencing the face.
1767 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1771 map
->stride
= mt
->pitch
;
1772 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1775 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1776 map
->x
, map
->y
, map
->w
, map
->h
,
1777 mt
, _mesa_get_format_name(mt
->format
),
1778 x
, y
, map
->ptr
, map
->stride
);
1782 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1783 struct intel_mipmap_tree
*mt
,
1784 struct intel_miptree_map
*map
,
1788 intel_miptree_unmap_raw(brw
, mt
);
1792 intel_miptree_map_blit(struct brw_context
*brw
,
1793 struct intel_mipmap_tree
*mt
,
1794 struct intel_miptree_map
*map
,
1795 unsigned int level
, unsigned int slice
)
1797 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1801 INTEL_MIPTREE_TILING_NONE
,
1804 fprintf(stderr
, "Failed to allocate blit temporary\n");
1807 map
->stride
= map
->mt
->pitch
;
1809 if (!intel_miptree_blit(brw
,
1811 map
->x
, map
->y
, false,
1814 map
->w
, map
->h
, GL_COPY
)) {
1815 fprintf(stderr
, "Failed to blit\n");
1819 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1821 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1822 map
->x
, map
->y
, map
->w
, map
->h
,
1823 mt
, _mesa_get_format_name(mt
->format
),
1824 level
, slice
, map
->ptr
, map
->stride
);
1829 intel_miptree_release(&map
->mt
);
1835 intel_miptree_unmap_blit(struct brw_context
*brw
,
1836 struct intel_mipmap_tree
*mt
,
1837 struct intel_miptree_map
*map
,
1841 struct gl_context
*ctx
= &brw
->ctx
;
1843 intel_miptree_unmap_raw(brw
, map
->mt
);
1845 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1846 bool ok
= intel_miptree_blit(brw
,
1850 map
->x
, map
->y
, false,
1851 map
->w
, map
->h
, GL_COPY
);
1852 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1855 intel_miptree_release(&map
->mt
);
1859 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1861 #if defined(USE_SSE41)
1863 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1864 struct intel_mipmap_tree
*mt
,
1865 struct intel_miptree_map
*map
,
1866 unsigned int level
, unsigned int slice
)
1868 assert(map
->mode
& GL_MAP_READ_BIT
);
1869 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1871 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1872 map
->x
, map
->y
, map
->w
, map
->h
,
1873 mt
, _mesa_get_format_name(mt
->format
),
1874 level
, slice
, map
->ptr
, map
->stride
);
1876 /* Map the original image */
1879 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1883 void *src
= intel_miptree_map_raw(brw
, mt
);
1886 src
+= image_y
* mt
->pitch
;
1887 src
+= image_x
* mt
->cpp
;
1889 /* Due to the pixel offsets for the particular image being mapped, our
1890 * src pointer may not be 16-byte aligned. However, if the pitch is
1891 * divisible by 16, then the amount by which it's misaligned will remain
1892 * consistent from row to row.
1894 assert((mt
->pitch
% 16) == 0);
1895 const int misalignment
= ((uintptr_t) src
) & 15;
1897 /* Create an untiled temporary buffer for the mapping. */
1898 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1900 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1902 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
1903 /* Offset the destination so it has the same misalignment as src. */
1904 map
->ptr
= map
->buffer
+ misalignment
;
1906 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1908 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1909 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1910 void *src_ptr
= src
+ y
* mt
->pitch
;
1912 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1915 intel_miptree_unmap_raw(brw
, mt
);
1919 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1920 struct intel_mipmap_tree
*mt
,
1921 struct intel_miptree_map
*map
,
1925 _mesa_align_free(map
->buffer
);
1932 intel_miptree_map_s8(struct brw_context
*brw
,
1933 struct intel_mipmap_tree
*mt
,
1934 struct intel_miptree_map
*map
,
1935 unsigned int level
, unsigned int slice
)
1937 map
->stride
= map
->w
;
1938 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1942 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1943 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1944 * invalidate is set, since we'll be writing the whole rectangle from our
1945 * temporary buffer back out.
1947 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1948 uint8_t *untiled_s8_map
= map
->ptr
;
1949 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1950 unsigned int image_x
, image_y
;
1952 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1954 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1955 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1956 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1957 x
+ image_x
+ map
->x
,
1958 y
+ image_y
+ map
->y
,
1959 brw
->has_swizzling
);
1960 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1964 intel_miptree_unmap_raw(brw
, mt
);
1966 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1967 map
->x
, map
->y
, map
->w
, map
->h
,
1968 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1970 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1971 map
->x
, map
->y
, map
->w
, map
->h
,
1972 mt
, map
->ptr
, map
->stride
);
1977 intel_miptree_unmap_s8(struct brw_context
*brw
,
1978 struct intel_mipmap_tree
*mt
,
1979 struct intel_miptree_map
*map
,
1983 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1984 unsigned int image_x
, image_y
;
1985 uint8_t *untiled_s8_map
= map
->ptr
;
1986 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1988 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1990 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1991 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1992 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1995 brw
->has_swizzling
);
1996 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2000 intel_miptree_unmap_raw(brw
, mt
);
2007 intel_miptree_map_etc(struct brw_context
*brw
,
2008 struct intel_mipmap_tree
*mt
,
2009 struct intel_miptree_map
*map
,
2013 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2014 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2015 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2018 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2019 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2021 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2022 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2023 map
->w
, map
->h
, 1));
2024 map
->ptr
= map
->buffer
;
2028 intel_miptree_unmap_etc(struct brw_context
*brw
,
2029 struct intel_mipmap_tree
*mt
,
2030 struct intel_miptree_map
*map
,
2036 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2041 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2042 + image_y
* mt
->pitch
2043 + image_x
* mt
->cpp
;
2045 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2046 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2047 map
->ptr
, map
->stride
,
2050 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2051 map
->ptr
, map
->stride
,
2052 map
->w
, map
->h
, mt
->etc_format
);
2054 intel_miptree_unmap_raw(brw
, mt
);
2059 * Mapping function for packed depth/stencil miptrees backed by real separate
2060 * miptrees for depth and stencil.
2062 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2063 * separate from the depth buffer. Yet at the GL API level, we have to expose
2064 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2065 * be able to map that memory for texture storage and glReadPixels-type
2066 * operations. We give Mesa core that access by mallocing a temporary and
2067 * copying the data between the actual backing store and the temporary.
2070 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2071 struct intel_mipmap_tree
*mt
,
2072 struct intel_miptree_map
*map
,
2073 unsigned int level
, unsigned int slice
)
2075 struct intel_mipmap_tree
*z_mt
= mt
;
2076 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2077 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2078 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2080 map
->stride
= map
->w
* packed_bpp
;
2081 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2085 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2086 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2087 * invalidate is set, since we'll be writing the whole rectangle from our
2088 * temporary buffer back out.
2090 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2091 uint32_t *packed_map
= map
->ptr
;
2092 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2093 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2094 unsigned int s_image_x
, s_image_y
;
2095 unsigned int z_image_x
, z_image_y
;
2097 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2098 &s_image_x
, &s_image_y
);
2099 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2100 &z_image_x
, &z_image_y
);
2102 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2103 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2104 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2105 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2108 brw
->has_swizzling
);
2109 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2111 (map_x
+ z_image_x
));
2112 uint8_t s
= s_map
[s_offset
];
2113 uint32_t z
= z_map
[z_offset
];
2115 if (map_z32f_x24s8
) {
2116 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2117 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2119 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2124 intel_miptree_unmap_raw(brw
, s_mt
);
2125 intel_miptree_unmap_raw(brw
, z_mt
);
2127 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2129 map
->x
, map
->y
, map
->w
, map
->h
,
2130 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2131 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2132 map
->ptr
, map
->stride
);
2134 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2135 map
->x
, map
->y
, map
->w
, map
->h
,
2136 mt
, map
->ptr
, map
->stride
);
2141 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2142 struct intel_mipmap_tree
*mt
,
2143 struct intel_miptree_map
*map
,
2147 struct intel_mipmap_tree
*z_mt
= mt
;
2148 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2149 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2151 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2152 uint32_t *packed_map
= map
->ptr
;
2153 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2154 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2155 unsigned int s_image_x
, s_image_y
;
2156 unsigned int z_image_x
, z_image_y
;
2158 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2159 &s_image_x
, &s_image_y
);
2160 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2161 &z_image_x
, &z_image_y
);
2163 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2164 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2165 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2166 x
+ s_image_x
+ map
->x
,
2167 y
+ s_image_y
+ map
->y
,
2168 brw
->has_swizzling
);
2169 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2171 (x
+ z_image_x
+ map
->x
));
2173 if (map_z32f_x24s8
) {
2174 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2175 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2177 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2178 s_map
[s_offset
] = packed
>> 24;
2179 z_map
[z_offset
] = packed
;
2184 intel_miptree_unmap_raw(brw
, s_mt
);
2185 intel_miptree_unmap_raw(brw
, z_mt
);
2187 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2189 map
->x
, map
->y
, map
->w
, map
->h
,
2190 z_mt
, _mesa_get_format_name(z_mt
->format
),
2191 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2192 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2193 map
->ptr
, map
->stride
);
2200 * Create and attach a map to the miptree at (level, slice). Return the
2203 static struct intel_miptree_map
*
2204 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2213 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2218 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2219 mt
->level
[level
].slice
[slice
].map
= map
;
2231 * Release the map at (level, slice).
2234 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2238 struct intel_miptree_map
**map
;
2240 map
= &mt
->level
[level
].slice
[slice
].map
;
2246 can_blit_slice(struct intel_mipmap_tree
*mt
,
2247 unsigned int level
, unsigned int slice
)
2251 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2252 if (image_x
>= 32768 || image_y
>= 32768)
2255 if (mt
->pitch
>= 32768)
2262 intel_miptree_map(struct brw_context
*brw
,
2263 struct intel_mipmap_tree
*mt
,
2274 struct intel_miptree_map
*map
;
2276 assert(mt
->num_samples
<= 1);
2278 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2285 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2286 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2287 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2290 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2291 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2292 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2293 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2294 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2295 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2296 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2298 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2299 else if (brw
->has_llc
&&
2300 !(mode
& GL_MAP_WRITE_BIT
) &&
2302 (mt
->tiling
== I915_TILING_X
||
2303 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2304 can_blit_slice(mt
, level
, slice
)) {
2305 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2306 } else if (mt
->tiling
!= I915_TILING_NONE
&&
2307 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2308 assert(can_blit_slice(mt
, level
, slice
));
2309 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2310 #if defined(USE_SSE41)
2311 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2312 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2315 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2318 *out_ptr
= map
->ptr
;
2319 *out_stride
= map
->stride
;
2321 if (map
->ptr
== NULL
)
2322 intel_miptree_release_map(mt
, level
, slice
);
2326 intel_miptree_unmap(struct brw_context
*brw
,
2327 struct intel_mipmap_tree
*mt
,
2331 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2333 assert(mt
->num_samples
<= 1);
2338 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2339 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2341 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2342 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2343 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2344 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2345 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2346 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2347 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2348 } else if (map
->mt
) {
2349 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2350 #if defined(USE_SSE41)
2351 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2352 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2355 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2358 intel_miptree_release_map(mt
, level
, slice
);