2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_meta_util.h"
40 #include "brw_state.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
50 #include "util/format_srgb.h"
52 #include "x86/common_x86_asm.h"
54 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
56 static void *intel_miptree_map_raw(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*mt
,
60 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* See isl_surf_get_mcs_surf for details. */
77 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
80 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
81 switch (_mesa_get_format_base_format(mt
->format
)) {
82 case GL_DEPTH_COMPONENT
:
83 case GL_STENCIL_INDEX
:
84 case GL_DEPTH_STENCIL
:
87 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
89 * This field must be set to 0 for all SINT MSRTs when all RT channels
92 * In practice this means that we have to disable MCS for all signed
93 * integer MSAA buffers. The alternative, to disable MCS only when one
94 * of the render target channels is disabled, is impractical because it
95 * would require converting between CMS and UMS MSAA layouts on the fly,
98 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
107 intel_tiling_supports_ccs(const struct brw_context
*brw
,
108 enum isl_tiling tiling
)
110 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
112 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
113 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
115 * - Support is limited to tiled render targets.
117 * Gen9 changes the restriction to Y-tile only.
119 if (devinfo
->gen
>= 9)
120 return tiling
== ISL_TILING_Y0
;
121 else if (devinfo
->gen
>= 7)
122 return tiling
!= ISL_TILING_LINEAR
;
128 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
129 * can be used. This doesn't (and should not) inspect any of the properties of
132 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
133 * beneath the "Fast Color Clear" bullet (p326):
135 * - Support is for non-mip-mapped and non-array surface types only.
137 * And then later, on p327:
139 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
142 * From the Skylake documentation, it is made clear that X-tiling is no longer
145 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
149 intel_miptree_supports_ccs(struct brw_context
*brw
,
150 const struct intel_mipmap_tree
*mt
)
152 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
154 /* MCS support does not exist prior to Gen7 */
155 if (devinfo
->gen
< 7)
158 /* This function applies only to non-multisampled render targets. */
159 if (mt
->surf
.samples
> 1)
162 /* MCS is only supported for color buffers */
163 switch (_mesa_get_format_base_format(mt
->format
)) {
164 case GL_DEPTH_COMPONENT
:
165 case GL_DEPTH_STENCIL
:
166 case GL_STENCIL_INDEX
:
170 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
173 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
174 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
175 mt
->surf
.logical_level0_px
.depth
> 1;
178 /* Multisample surfaces with the CMS layout are not layered surfaces,
179 * yet still have physical_depth0 > 1. Assert that we don't
180 * accidentally reject a multisampled surface here. We should have
181 * rejected it earlier by explicitly checking the sample count.
183 assert(mt
->surf
.samples
== 1);
186 /* Handle the hardware restrictions...
188 * All GENs have the following restriction: "MCS buffer for non-MSRT is
189 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
191 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
192 * Non-MultiSampler Render Target Restrictions) Support is for
193 * non-mip-mapped and non-array surface types only.
195 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
200 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
201 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
202 * surfaces are supported with MCS buffer layout with these alignments in
203 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
205 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
208 /* There's no point in using an MCS buffer if the surface isn't in a
211 if (!brw
->mesa_format_supports_render
[mt
->format
])
218 intel_tiling_supports_hiz(const struct brw_context
*brw
,
219 enum isl_tiling tiling
)
221 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
223 if (devinfo
->gen
< 6)
226 return tiling
== ISL_TILING_Y0
;
230 intel_miptree_supports_hiz(const struct brw_context
*brw
,
231 const struct intel_mipmap_tree
*mt
)
236 switch (mt
->format
) {
237 case MESA_FORMAT_Z_FLOAT32
:
238 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
239 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
240 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
241 case MESA_FORMAT_Z_UNORM16
:
249 * Return true if the format that will be used to access the miptree is
250 * CCS_E-compatible with the miptree's linear/non-sRGB format.
252 * Why use the linear format? Well, although the miptree may be specified with
253 * an sRGB format, the usage of that color space/format can be toggled. Since
254 * our HW tends to support more linear formats than sRGB ones, we use this
255 * format variant for check for CCS_E compatibility.
258 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
259 const struct intel_mipmap_tree
*mt
,
260 enum isl_format access_format
)
262 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
264 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
265 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
266 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
270 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
271 const struct intel_mipmap_tree
*mt
)
273 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
275 if (devinfo
->gen
< 9)
278 /* For now compression is only enabled for integer formats even though
279 * there exist supported floating point formats also. This is a heuristic
280 * decision based on current public benchmarks. In none of the cases these
281 * formats provided any improvement but a few cases were seen to regress.
282 * Hence these are left to to be enabled in the future when they are known
285 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
288 if (!intel_miptree_supports_ccs(brw
, mt
))
291 /* Many window system buffers are sRGB even if they are never rendered as
292 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
293 * surface is used as sRGB, we fall back to CCS_D.
295 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
296 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
297 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
301 * Determine depth format corresponding to a depth+stencil format,
302 * for separate stencil.
305 intel_depth_format_for_depthstencil_format(mesa_format format
) {
307 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
308 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
309 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
310 return MESA_FORMAT_Z_FLOAT32
;
317 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
318 unsigned depth0
, struct intel_mipmap_level
*table
)
320 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
322 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
324 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
325 if (!table
[level
].slice
)
332 for (unsigned level
= first_level
; level
<= last_level
; level
++)
333 free(table
[level
].slice
);
339 needs_separate_stencil(const struct brw_context
*brw
,
340 struct intel_mipmap_tree
*mt
,
343 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
345 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
348 if (devinfo
->must_use_separate_stencil
)
351 return brw
->has_separate_stencil
&&
352 intel_miptree_supports_hiz(brw
, mt
);
356 * Choose the aux usage for this miptree. This function must be called fairly
357 * late in the miptree create process after we have a tiling.
360 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
361 struct intel_mipmap_tree
*mt
)
363 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
365 if (intel_miptree_supports_mcs(brw
, mt
)) {
366 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
367 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
368 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
369 intel_miptree_supports_ccs(brw
, mt
)) {
370 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
371 intel_miptree_supports_ccs_e(brw
, mt
)) {
372 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
376 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
377 intel_miptree_supports_hiz(brw
, mt
)) {
378 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
381 /* We can do fast-clear on all auxiliary surface types that are
382 * allocated through the normal texture creation paths.
384 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
385 mt
->supports_fast_clear
= true;
390 * Choose an appropriate uncompressed format for a requested
391 * compressed format, if unsupported.
394 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
396 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
398 /* No need to lower ETC formats on these platforms,
399 * they are supported natively.
401 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
405 case MESA_FORMAT_ETC1_RGB8
:
406 return MESA_FORMAT_R8G8B8X8_UNORM
;
407 case MESA_FORMAT_ETC2_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_SRGB8
:
410 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
411 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
412 return MESA_FORMAT_B8G8R8A8_SRGB
;
413 case MESA_FORMAT_ETC2_RGBA8_EAC
:
414 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
415 return MESA_FORMAT_R8G8B8A8_UNORM
;
416 case MESA_FORMAT_ETC2_R11_EAC
:
417 return MESA_FORMAT_R_UNORM16
;
418 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
419 return MESA_FORMAT_R_SNORM16
;
420 case MESA_FORMAT_ETC2_RG11_EAC
:
421 return MESA_FORMAT_R16G16_UNORM
;
422 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
423 return MESA_FORMAT_R16G16_SNORM
;
425 /* Non ETC1 / ETC2 format */
431 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
433 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
434 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
436 return mt
->surf
.logical_level0_px
.array_len
;
439 UNUSED
static unsigned
440 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
442 /* In case of physical dimensions one needs to consider also the layout.
443 * See isl_calc_phys_level0_extent_sa().
445 if (surf
->dim
!= ISL_SURF_DIM_3D
)
446 return surf
->phys_level0_sa
.array_len
;
448 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
449 return minify(surf
->phys_level0_sa
.array_len
, level
);
451 return minify(surf
->phys_level0_sa
.depth
, level
);
454 /** \brief Assert that the level and layer are valid for the miptree. */
456 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
464 assert(level
>= mt
->first_level
);
465 assert(level
<= mt
->last_level
);
466 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
469 static enum isl_aux_state
**
470 create_aux_state_map(struct intel_mipmap_tree
*mt
,
471 enum isl_aux_state initial
)
473 const uint32_t levels
= mt
->last_level
+ 1;
475 uint32_t total_slices
= 0;
476 for (uint32_t level
= 0; level
< levels
; level
++)
477 total_slices
+= brw_get_num_logical_layers(mt
, level
);
479 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
481 /* We're going to allocate a single chunk of data for both the per-level
482 * reference array and the arrays of aux_state. This makes cleanup
483 * significantly easier.
485 const size_t total_size
= per_level_array_size
+
486 total_slices
* sizeof(enum isl_aux_state
);
487 void *data
= malloc(total_size
);
491 enum isl_aux_state
**per_level_arr
= data
;
492 enum isl_aux_state
*s
= data
+ per_level_array_size
;
493 for (uint32_t level
= 0; level
< levels
; level
++) {
494 per_level_arr
[level
] = s
;
495 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
496 for (uint32_t a
= 0; a
< level_layers
; a
++)
499 assert((void *)s
== data
+ total_size
);
501 return per_level_arr
;
505 free_aux_state_map(enum isl_aux_state
**state
)
511 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
512 enum isl_tiling tiling
, unsigned samples
)
517 if (tiling
== ISL_TILING_LINEAR
)
520 /* If the width is much smaller than a tile, don't bother tiling. */
524 if (ALIGN(row_pitch
, 512) >= 32768) {
525 perf_debug("row pitch %u too large to blit, falling back to untiled",
534 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
535 enum isl_tiling tiling
)
537 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
539 /* If the BO is too large to fit in the aperture, we need to use the
540 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
541 * handle Y-tiling, so we need to fall back to X.
543 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
544 tiling
== ISL_TILING_Y0
)
550 static struct intel_mipmap_tree
*
551 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
552 unsigned first_level
, unsigned last_level
,
553 unsigned width0
, unsigned height0
, unsigned depth0
,
554 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
555 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
556 unsigned row_pitch
, struct brw_bo
*bo
)
558 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
562 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
570 if (target
== GL_TEXTURE_CUBE_MAP
||
571 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
572 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
574 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
576 _mesa_enum_to_string(target
),
577 _mesa_get_format_name(format
),
578 num_samples
, width0
, height0
, depth0
,
579 first_level
, last_level
, mt
);
581 struct isl_surf_init_info init_info
= {
582 .dim
= get_isl_surf_dim(target
),
583 .format
= translate_tex_format(brw
, format
, false),
586 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
587 .levels
= last_level
- first_level
+ 1,
588 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
589 .samples
= num_samples
,
590 .row_pitch
= row_pitch
,
591 .usage
= isl_usage_flags
,
592 .tiling_flags
= tiling_flags
,
595 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
598 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
599 * on gen7 platforms we also need to create Y-tiled copies of stencil for
600 * texturing since the hardware can't sample from W-tiled surfaces. For
601 * everything else, check for corner cases needing special treatment.
603 bool is_depth_stencil
=
604 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
605 if (!is_depth_stencil
) {
606 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
607 mt
->surf
.tiling
, mt
->surf
.samples
)) {
608 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
609 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
611 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
612 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
613 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
618 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
619 * the size may not be multiple of row_pitch.
620 * See isl_apply_surface_padding().
622 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
623 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
626 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
628 isl_tiling_to_i915_tiling(
630 mt
->surf
.row_pitch
, alloc_flags
);
637 mt
->first_level
= first_level
;
638 mt
->last_level
= last_level
;
641 mt
->aux_state
= NULL
;
642 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
643 mt
->compressed
= _mesa_is_format_compressed(format
);
644 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
649 intel_miptree_release(&mt
);
654 make_separate_stencil_surface(struct brw_context
*brw
,
655 struct intel_mipmap_tree
*mt
)
657 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
658 0, mt
->surf
.levels
- 1,
659 mt
->surf
.logical_level0_px
.width
,
660 mt
->surf
.logical_level0_px
.height
,
661 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
662 mt
->surf
.logical_level0_px
.depth
:
663 mt
->surf
.logical_level0_px
.array_len
,
664 mt
->surf
.samples
, ISL_TILING_W_BIT
,
665 ISL_SURF_USAGE_STENCIL_BIT
|
666 ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_BUSY
, 0, NULL
);
672 mt
->stencil_mt
->r8stencil_needs_update
= true;
677 static struct intel_mipmap_tree
*
678 miptree_create(struct brw_context
*brw
,
687 enum intel_miptree_create_flags flags
)
689 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
691 if (format
== MESA_FORMAT_S_UINT8
)
692 return make_surface(brw
, target
, format
, first_level
, last_level
,
693 width0
, height0
, depth0
, num_samples
,
695 ISL_SURF_USAGE_STENCIL_BIT
|
696 ISL_SURF_USAGE_TEXTURE_BIT
,
701 const GLenum base_format
= _mesa_get_format_base_format(format
);
702 if ((base_format
== GL_DEPTH_COMPONENT
||
703 base_format
== GL_DEPTH_STENCIL
) &&
704 !(flags
& MIPTREE_CREATE_LINEAR
)) {
705 /* Fix up the Z miptree format for how we're splitting out separate
706 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
708 const mesa_format depth_only_format
=
709 intel_depth_format_for_depthstencil_format(format
);
710 struct intel_mipmap_tree
*mt
= make_surface(
711 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
712 first_level
, last_level
,
713 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
714 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
715 BO_ALLOC_BUSY
, 0, NULL
);
717 if (needs_separate_stencil(brw
, mt
, format
) &&
718 !make_separate_stencil_surface(brw
, mt
)) {
719 intel_miptree_release(&mt
);
723 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
724 intel_miptree_choose_aux_usage(brw
, mt
);
729 mesa_format tex_format
= format
;
730 mesa_format etc_format
= MESA_FORMAT_NONE
;
731 uint32_t alloc_flags
= 0;
733 format
= intel_lower_compressed_format(brw
, format
);
735 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
737 if (flags
& MIPTREE_CREATE_BUSY
)
738 alloc_flags
|= BO_ALLOC_BUSY
;
740 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
741 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
743 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
744 if (devinfo
->gen
< 6)
745 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
747 struct intel_mipmap_tree
*mt
= make_surface(
749 first_level
, last_level
,
750 width0
, height0
, depth0
,
751 num_samples
, tiling_flags
,
752 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
753 ISL_SURF_USAGE_TEXTURE_BIT
,
754 alloc_flags
, 0, NULL
);
758 mt
->etc_format
= etc_format
;
760 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
761 intel_miptree_choose_aux_usage(brw
, mt
);
766 struct intel_mipmap_tree
*
767 intel_miptree_create(struct brw_context
*brw
,
776 enum intel_miptree_create_flags flags
)
778 assert(num_samples
> 0);
780 struct intel_mipmap_tree
*mt
= miptree_create(
782 first_level
, last_level
,
783 width0
, height0
, depth0
, num_samples
,
790 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
791 * compress clear color so we wait until an actual fast-clear to allocate
794 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
795 !intel_miptree_alloc_aux(brw
, mt
)) {
796 intel_miptree_release(&mt
);
803 struct intel_mipmap_tree
*
804 intel_miptree_create_for_bo(struct brw_context
*brw
,
812 enum isl_tiling tiling
,
813 enum intel_miptree_create_flags flags
)
815 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
816 struct intel_mipmap_tree
*mt
;
817 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
818 const GLenum base_format
= _mesa_get_format_base_format(format
);
820 if ((base_format
== GL_DEPTH_COMPONENT
||
821 base_format
== GL_DEPTH_STENCIL
)) {
822 const mesa_format depth_only_format
=
823 intel_depth_format_for_depthstencil_format(format
);
824 mt
= make_surface(brw
, target
,
825 devinfo
->gen
>= 6 ? depth_only_format
: format
,
826 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
827 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
832 brw_bo_reference(bo
);
834 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
835 intel_miptree_choose_aux_usage(brw
, mt
);
838 } else if (format
== MESA_FORMAT_S_UINT8
) {
839 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
840 0, 0, width
, height
, depth
, 1,
842 ISL_SURF_USAGE_STENCIL_BIT
|
843 ISL_SURF_USAGE_TEXTURE_BIT
,
848 assert(bo
->size
>= mt
->surf
.size
);
850 brw_bo_reference(bo
);
854 /* Nothing will be able to use this miptree with the BO if the offset isn't
857 if (tiling
!= ISL_TILING_LINEAR
)
858 assert(offset
% 4096 == 0);
860 /* miptrees can't handle negative pitch. If you need flipping of images,
861 * that's outside of the scope of the mt.
865 /* The BO already has a tiling format and we shouldn't confuse the lower
866 * layers by making it try to find a tiling format again.
868 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
870 mt
= make_surface(brw
, target
, format
,
871 0, 0, width
, height
, depth
, 1,
873 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
874 ISL_SURF_USAGE_TEXTURE_BIT
,
879 brw_bo_reference(bo
);
883 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
884 intel_miptree_choose_aux_usage(brw
, mt
);
886 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
887 * only compress clear color so we wait until an actual fast-clear to
890 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
891 !intel_miptree_alloc_aux(brw
, mt
)) {
892 intel_miptree_release(&mt
);
900 static struct intel_mipmap_tree
*
901 miptree_create_for_planar_image(struct brw_context
*brw
,
902 __DRIimage
*image
, GLenum target
,
903 enum isl_tiling tiling
)
905 const struct intel_image_format
*f
= image
->planar_format
;
906 struct intel_mipmap_tree
*planar_mt
= NULL
;
908 for (int i
= 0; i
< f
->nplanes
; i
++) {
909 const int index
= f
->planes
[i
].buffer_index
;
910 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
911 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
912 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
913 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
915 /* Disable creation of the texture's aux buffers because the driver
916 * exposes no EGL API to manage them. That is, there is no API for
917 * resolving the aux buffer's content to the main buffer nor for
918 * invalidating the aux buffer's content.
920 struct intel_mipmap_tree
*mt
=
921 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
922 image
->offsets
[index
],
924 image
->strides
[index
],
926 MIPTREE_CREATE_NO_AUX
);
935 planar_mt
->plane
[i
- 1] = mt
;
938 planar_mt
->drm_modifier
= image
->modifier
;
944 create_ccs_buf_for_image(struct brw_context
*brw
,
946 struct intel_mipmap_tree
*mt
,
947 enum isl_aux_state initial_state
)
949 struct isl_surf temp_ccs_surf
;
951 /* CCS is only supported for very simple miptrees */
952 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
953 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
954 assert(mt
->surf
.samples
== 1);
955 assert(mt
->surf
.levels
== 1);
956 assert(mt
->surf
.logical_level0_px
.depth
== 1);
957 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
958 assert(mt
->first_level
== 0);
959 assert(mt
->last_level
== 0);
961 /* We shouldn't already have a CCS */
962 assert(!mt
->aux_buf
);
964 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
968 assert(image
->aux_offset
< image
->bo
->size
);
969 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
971 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
972 if (mt
->aux_buf
== NULL
)
975 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
976 if (!mt
->aux_state
) {
982 /* On gen10+ we start using an extra space in the aux buffer to store the
983 * indirect clear color. However, if we imported an image from the window
984 * system with CCS, we don't have the extra space at the end of the aux
985 * buffer. So create a new bo here that will store that clear color.
987 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
988 mt
->aux_buf
->clear_color_bo
=
989 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
990 brw
->isl_dev
.ss
.clear_color_state_size
,
991 I915_TILING_NONE
, 0, BO_ALLOC_ZEROED
);
992 if (!mt
->aux_buf
->clear_color_bo
) {
999 mt
->aux_buf
->bo
= image
->bo
;
1000 brw_bo_reference(image
->bo
);
1002 mt
->aux_buf
->offset
= image
->aux_offset
;
1003 mt
->aux_buf
->surf
= temp_ccs_surf
;
1008 struct intel_mipmap_tree
*
1009 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1010 __DRIimage
*image
, GLenum target
,
1012 bool is_winsys_image
)
1014 uint32_t bo_tiling
, bo_swizzle
;
1015 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1017 const struct isl_drm_modifier_info
*mod_info
=
1018 isl_drm_modifier_get_info(image
->modifier
);
1020 const enum isl_tiling tiling
=
1021 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1023 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1024 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1026 if (image
->planar_format
)
1027 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1029 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1030 /* The texture storage paths in core Mesa detect if the driver does not
1031 * support the user-requested format, and then searches for a
1032 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1033 * do the fallbacks here for important formats.
1035 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1036 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1037 * the Chrome OS compositor consumes as dma_buf EGLImages.
1039 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1042 if (!brw
->ctx
.TextureFormatSupported
[format
])
1045 enum intel_miptree_create_flags mt_create_flags
= 0;
1047 /* If this image comes in from a window system, we have different
1048 * requirements than if it comes in via an EGL import operation. Window
1049 * system images can use any form of auxiliary compression we wish because
1050 * they get "flushed" before being handed off to the window system and we
1051 * have the opportunity to do resolves. Non window-system images, on the
1052 * other hand, have no resolve point so we can't have aux without a
1055 if (!is_winsys_image
)
1056 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1058 /* If we have a modifier which specifies aux, don't create one yet */
1059 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1060 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1062 /* Disable creation of the texture's aux buffers because the driver exposes
1063 * no EGL API to manage them. That is, there is no API for resolving the aux
1064 * buffer's content to the main buffer nor for invalidating the aux buffer's
1067 struct intel_mipmap_tree
*mt
=
1068 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1069 image
->offset
, image
->width
, image
->height
, 1,
1070 image
->pitch
, tiling
, mt_create_flags
);
1074 mt
->target
= target
;
1075 mt
->level
[0].level_x
= image
->tile_x
;
1076 mt
->level
[0].level_y
= image
->tile_y
;
1077 mt
->drm_modifier
= image
->modifier
;
1079 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1080 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1081 * trouble resolving back to destination image due to alignment issues.
1083 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1084 if (!devinfo
->has_surface_tile_offset
) {
1085 uint32_t draw_x
, draw_y
;
1086 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1088 if (draw_x
!= 0 || draw_y
!= 0) {
1089 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1090 intel_miptree_release(&mt
);
1095 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1096 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1098 mt
->aux_usage
= mod_info
->aux_usage
;
1099 /* If we are a window system buffer, then we can support fast-clears
1100 * even if the modifier doesn't support them by doing a partial resolve
1101 * as part of the flush operation.
1103 mt
->supports_fast_clear
=
1104 is_winsys_image
|| mod_info
->supports_clear_color
;
1106 /* We don't know the actual state of the surface when we get it but we
1107 * can make a pretty good guess based on the modifier. What we do know
1108 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1109 * a worst case of compression.
1111 enum isl_aux_state initial_state
=
1112 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1114 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1115 intel_miptree_release(&mt
);
1120 /* Don't assume coherency for imported EGLimages. We don't know what
1121 * external clients are going to do with it. They may scan it out.
1123 image
->bo
->cache_coherent
= false;
1129 * For a singlesample renderbuffer, this simply wraps the given BO with a
1132 * For a multisample renderbuffer, this wraps the window system's
1133 * (singlesample) BO with a singlesample miptree attached to the
1134 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1135 * that will contain the actual rendering (which is lazily resolved to
1136 * irb->singlesample_mt).
1139 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1140 struct intel_renderbuffer
*irb
,
1141 struct intel_mipmap_tree
*singlesample_mt
,
1142 uint32_t width
, uint32_t height
,
1145 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1146 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1147 mesa_format format
= rb
->Format
;
1148 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1150 /* Only the front and back buffers, which are color buffers, are allocated
1151 * through the image loader.
1153 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1154 _mesa_get_format_base_format(format
) == GL_RGBA
);
1156 assert(singlesample_mt
);
1158 if (num_samples
== 1) {
1159 intel_miptree_release(&irb
->mt
);
1160 irb
->mt
= singlesample_mt
;
1162 assert(!irb
->singlesample_mt
);
1164 intel_miptree_release(&irb
->singlesample_mt
);
1165 irb
->singlesample_mt
= singlesample_mt
;
1168 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1169 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1170 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1175 if (!multisample_mt
)
1178 irb
->need_downsample
= false;
1179 intel_miptree_release(&irb
->mt
);
1180 irb
->mt
= multisample_mt
;
1186 intel_miptree_release(&irb
->mt
);
1190 struct intel_mipmap_tree
*
1191 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1195 uint32_t num_samples
)
1197 struct intel_mipmap_tree
*mt
;
1199 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1201 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1202 width
, height
, depth
, num_samples
,
1203 MIPTREE_CREATE_BUSY
);
1210 intel_miptree_release(&mt
);
1215 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1216 struct intel_mipmap_tree
*src
)
1221 intel_miptree_release(dst
);
1225 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1232 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1234 if (aux_buf
== NULL
)
1237 brw_bo_unreference(aux_buf
->bo
);
1238 brw_bo_unreference(aux_buf
->clear_color_bo
);
1244 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1249 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1250 if (--(*mt
)->refcount
<= 0) {
1253 DBG("%s deleting %p\n", __func__
, *mt
);
1255 brw_bo_unreference((*mt
)->bo
);
1256 intel_miptree_release(&(*mt
)->stencil_mt
);
1257 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1258 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1259 free_aux_state_map((*mt
)->aux_state
);
1261 intel_miptree_release(&(*mt
)->plane
[0]);
1262 intel_miptree_release(&(*mt
)->plane
[1]);
1264 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1265 free((*mt
)->level
[i
].slice
);
1275 intel_get_image_dims(struct gl_texture_image
*image
,
1276 int *width
, int *height
, int *depth
)
1278 switch (image
->TexObject
->Target
) {
1279 case GL_TEXTURE_1D_ARRAY
:
1280 /* For a 1D Array texture the OpenGL API will treat the image height as
1281 * the number of array slices. For Intel hardware, we treat the 1D array
1282 * as a 2D Array with a height of 1. So, here we want to swap image
1285 assert(image
->Depth
== 1);
1286 *width
= image
->Width
;
1288 *depth
= image
->Height
;
1290 case GL_TEXTURE_CUBE_MAP
:
1291 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1292 * though we really have 6 slices.
1294 assert(image
->Depth
== 1);
1295 *width
= image
->Width
;
1296 *height
= image
->Height
;
1300 *width
= image
->Width
;
1301 *height
= image
->Height
;
1302 *depth
= image
->Depth
;
1308 * Can the image be pulled into a unified mipmap tree? This mirrors
1309 * the completeness test in a lot of ways.
1311 * Not sure whether I want to pass gl_texture_image here.
1314 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1315 struct gl_texture_image
*image
)
1317 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1318 GLuint level
= intelImage
->base
.Base
.Level
;
1319 int width
, height
, depth
;
1321 /* glTexImage* choose the texture object based on the target passed in, and
1322 * objects can't change targets over their lifetimes, so this should be
1325 assert(image
->TexObject
->Target
== mt
->target
);
1327 mesa_format mt_format
= mt
->format
;
1328 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1329 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1330 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1331 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1332 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1333 mt_format
= mt
->etc_format
;
1335 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1336 _mesa_get_srgb_format_linear(mt_format
))
1339 intel_get_image_dims(image
, &width
, &height
, &depth
);
1341 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1344 if (level
>= mt
->surf
.levels
)
1347 const unsigned level_depth
=
1348 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1349 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1350 mt
->surf
.logical_level0_px
.array_len
;
1352 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1353 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1354 depth
== level_depth
&&
1355 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1359 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1360 GLuint level
, GLuint slice
,
1361 GLuint
*x
, GLuint
*y
)
1363 if (level
== 0 && slice
== 0) {
1364 *x
= mt
->level
[0].level_x
;
1365 *y
= mt
->level
[0].level_y
;
1369 uint32_t x_offset_sa
, y_offset_sa
;
1371 /* Miptree itself can have an offset only if it represents a single
1372 * slice in an imported buffer object.
1373 * See intel_miptree_create_for_dri_image().
1375 assert(mt
->level
[0].level_x
== 0);
1376 assert(mt
->level
[0].level_y
== 0);
1378 /* Given level is relative to level zero while the miptree may be
1379 * represent just a subset of all levels starting from 'first_level'.
1381 assert(level
>= mt
->first_level
);
1382 level
-= mt
->first_level
;
1384 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1385 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1386 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1387 &x_offset_sa
, &y_offset_sa
);
1395 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1396 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1397 * and tile_h is set to 1.
1400 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1401 uint32_t *tile_w
, uint32_t *tile_h
)
1412 case ISL_TILING_LINEAR
:
1417 unreachable("not reached");
1423 * This function computes masks that may be used to select the bits of the X
1424 * and Y coordinates that indicate the offset within a tile. If the BO is
1425 * untiled, the masks are set to 0.
1428 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1429 uint32_t *mask_x
, uint32_t *mask_y
)
1431 uint32_t tile_w_bytes
, tile_h
;
1433 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1435 *mask_x
= tile_w_bytes
/ cpp
- 1;
1436 *mask_y
= tile_h
- 1;
1440 * Compute the offset (in bytes) from the start of the BO to the given x
1441 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1442 * multiples of the tile size.
1445 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1446 uint32_t x
, uint32_t y
)
1449 uint32_t pitch
= mt
->surf
.row_pitch
;
1451 switch (mt
->surf
.tiling
) {
1453 unreachable("not reached");
1454 case ISL_TILING_LINEAR
:
1455 return y
* pitch
+ x
* cpp
;
1457 assert((x
% (512 / cpp
)) == 0);
1458 assert((y
% 8) == 0);
1459 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1461 assert((x
% (128 / cpp
)) == 0);
1462 assert((y
% 32) == 0);
1463 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1468 * Rendering with tiled buffers requires that the base address of the buffer
1469 * be aligned to a page boundary. For renderbuffers, and sometimes with
1470 * textures, we may want the surface to point at a texture image level that
1471 * isn't at a page boundary.
1473 * This function returns an appropriately-aligned base offset
1474 * according to the tiling restrictions, plus any required x/y offset
1478 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1479 GLuint level
, GLuint slice
,
1484 uint32_t mask_x
, mask_y
;
1486 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1487 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1489 *tile_x
= x
& mask_x
;
1490 *tile_y
= y
& mask_y
;
1492 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1496 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1497 struct intel_mipmap_tree
*src_mt
,
1498 unsigned src_level
, unsigned src_layer
,
1499 struct intel_mipmap_tree
*dst_mt
,
1500 unsigned dst_level
, unsigned dst_layer
,
1501 unsigned width
, unsigned height
)
1504 ptrdiff_t src_stride
, dst_stride
;
1505 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1507 intel_miptree_map(brw
, src_mt
,
1508 src_level
, src_layer
,
1511 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1514 intel_miptree_map(brw
, dst_mt
,
1515 dst_level
, dst_layer
,
1518 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1522 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1523 _mesa_get_format_name(src_mt
->format
),
1524 src_mt
, src
, src_stride
,
1525 _mesa_get_format_name(dst_mt
->format
),
1526 dst_mt
, dst
, dst_stride
,
1529 int row_size
= cpp
* width
;
1530 if (src_stride
== row_size
&&
1531 dst_stride
== row_size
) {
1532 memcpy(dst
, src
, row_size
* height
);
1534 for (int i
= 0; i
< height
; i
++) {
1535 memcpy(dst
, src
, row_size
);
1541 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1542 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1544 /* Don't forget to copy the stencil data over, too. We could have skipped
1545 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1546 * shuffling the two data sources in/out of temporary storage instead of
1547 * the direct mapping we get this way.
1549 if (dst_mt
->stencil_mt
) {
1550 assert(src_mt
->stencil_mt
);
1551 intel_miptree_copy_slice_sw(brw
,
1552 src_mt
->stencil_mt
, src_level
, src_layer
,
1553 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1559 intel_miptree_copy_slice(struct brw_context
*brw
,
1560 struct intel_mipmap_tree
*src_mt
,
1561 unsigned src_level
, unsigned src_layer
,
1562 struct intel_mipmap_tree
*dst_mt
,
1563 unsigned dst_level
, unsigned dst_layer
)
1566 mesa_format format
= src_mt
->format
;
1567 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1568 src_level
- src_mt
->first_level
);
1569 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1570 src_level
- src_mt
->first_level
);
1572 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1573 src_level
- src_mt
->first_level
));
1575 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1576 _mesa_get_srgb_format_linear(dst_mt
->format
));
1578 if (dst_mt
->compressed
) {
1580 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1581 height
= ALIGN_NPOT(height
, j
) / j
;
1582 width
= ALIGN_NPOT(width
, i
) / i
;
1585 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1586 * below won't apply since we can't do the depth's Y tiling or the
1587 * stencil's W tiling in the blitter.
1589 if (src_mt
->stencil_mt
) {
1590 intel_miptree_copy_slice_sw(brw
,
1591 src_mt
, src_level
, src_layer
,
1592 dst_mt
, dst_level
, dst_layer
,
1597 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1598 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1600 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1603 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1604 _mesa_get_format_name(src_mt
->format
),
1605 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1606 _mesa_get_format_name(dst_mt
->format
),
1607 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1610 if (!intel_miptree_blit(brw
,
1611 src_mt
, src_level
, src_layer
, 0, 0, false,
1612 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1613 width
, height
, COLOR_LOGICOP_COPY
)) {
1614 perf_debug("miptree validate blit for %s failed\n",
1615 _mesa_get_format_name(format
));
1617 intel_miptree_copy_slice_sw(brw
,
1618 src_mt
, src_level
, src_layer
,
1619 dst_mt
, dst_level
, dst_layer
,
1625 * Copies the image's current data to the given miptree, and associates that
1626 * miptree with the image.
1629 intel_miptree_copy_teximage(struct brw_context
*brw
,
1630 struct intel_texture_image
*intelImage
,
1631 struct intel_mipmap_tree
*dst_mt
)
1633 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1634 struct intel_texture_object
*intel_obj
=
1635 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1636 int level
= intelImage
->base
.Base
.Level
;
1637 const unsigned face
= intelImage
->base
.Base
.Face
;
1638 unsigned start_layer
, end_layer
;
1640 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1642 assert(intelImage
->base
.Base
.Height
);
1644 end_layer
= intelImage
->base
.Base
.Height
- 1;
1645 } else if (face
> 0) {
1649 assert(intelImage
->base
.Base
.Depth
);
1651 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1654 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1655 intel_miptree_copy_slice(brw
,
1660 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1661 intel_obj
->needs_validate
= true;
1664 static struct intel_miptree_aux_buffer
*
1665 intel_alloc_aux_buffer(struct brw_context
*brw
,
1666 const struct isl_surf
*aux_surf
,
1668 uint8_t memset_value
)
1670 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1674 uint64_t size
= aux_surf
->size
;
1676 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1677 if (has_indirect_clear
) {
1678 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1679 * will set a pointer to a dword somewhere that contains the color. So,
1680 * allocate the space for the clear color value here on the aux buffer.
1682 buf
->clear_color_offset
= size
;
1683 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1686 /* If the buffer needs to be initialised (requiring the buffer to be
1687 * immediately mapped to cpu space for writing), do not use the gpu access
1688 * flag which can cause an unnecessary delay if the backing pages happened
1689 * to be just used by the GPU.
1691 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1692 const bool needs_memset
=
1693 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1694 const uint32_t alloc_flags
=
1695 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1697 /* ISL has stricter set of alignment rules then the drm allocator.
1698 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1699 * trying to recalculate based on different format block sizes.
1701 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1702 I915_TILING_Y
, aux_surf
->row_pitch
,
1709 /* Initialize the bo to the desired value */
1711 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1713 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1715 intel_miptree_aux_buffer_free(buf
);
1719 /* Memset the aux_surf portion of the BO. */
1721 memset(map
, memset_value
, aux_surf
->size
);
1723 /* Zero the indirect clear color to match ::fast_clear_color. */
1724 if (has_indirect_clear
) {
1725 memset((char *)map
+ buf
->clear_color_offset
, 0,
1726 brw
->isl_dev
.ss
.clear_color_state_size
);
1729 brw_bo_unmap(buf
->bo
);
1732 if (has_indirect_clear
) {
1733 buf
->clear_color_bo
= buf
->bo
;
1734 brw_bo_reference(buf
->clear_color_bo
);
1737 buf
->surf
= *aux_surf
;
1743 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1744 struct intel_mipmap_tree
*mt
,
1747 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1748 assert(mt
->aux_buf
== NULL
);
1749 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1751 /* Multisampled miptrees are only supported for single level. */
1752 assert(mt
->first_level
== 0);
1753 enum isl_aux_state
**aux_state
=
1754 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1758 struct isl_surf temp_mcs_surf
;
1760 MAYBE_UNUSED
bool ok
=
1761 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1764 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1766 * When MCS buffer is enabled and bound to MSRT, it is required that it
1767 * is cleared prior to any rendering.
1769 * Since we don't use the MCS buffer for any purpose other than rendering,
1770 * it makes sense to just clear it immediately upon allocation.
1772 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1774 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &temp_mcs_surf
, true, 0xFF);
1780 mt
->aux_state
= aux_state
;
1786 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1787 struct intel_mipmap_tree
*mt
)
1789 assert(mt
->aux_buf
== NULL
);
1790 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1791 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1793 struct isl_surf temp_ccs_surf
;
1795 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1798 assert(temp_ccs_surf
.size
&&
1799 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1801 enum isl_aux_state
**aux_state
=
1802 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1806 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1807 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1809 * "If Software wants to enable Color Compression without Fast clear,
1810 * Software needs to initialize MCS with zeros."
1812 * A CCS value of 0 indicates that the corresponding block is in the
1813 * pass-through state which is what we want.
1815 * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
1816 * bits in the aux buffer.
1818 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &temp_ccs_surf
, true, 0);
1824 mt
->aux_state
= aux_state
;
1830 * Helper for intel_miptree_alloc_hiz() that sets
1831 * \c mt->level[level].has_hiz. Return true if and only if
1832 * \c has_hiz was set.
1835 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1836 struct intel_mipmap_tree
*mt
,
1839 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1841 assert(mt
->aux_buf
);
1842 assert(mt
->surf
.size
> 0);
1844 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1845 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1846 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1848 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1849 * and the height is 4 aligned. This allows our HiZ support
1850 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1851 * we can grow the width & height to allow the HiZ op to
1852 * force the proper size alignments.
1854 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1855 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1860 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1861 mt
->level
[level
].has_hiz
= true;
1866 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1867 struct intel_mipmap_tree
*mt
)
1869 assert(mt
->aux_buf
== NULL
);
1870 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1872 enum isl_aux_state
**aux_state
=
1873 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1877 struct isl_surf temp_hiz_surf
;
1879 MAYBE_UNUSED
bool ok
=
1880 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1883 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &temp_hiz_surf
, false, 0);
1890 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1891 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1893 mt
->aux_state
= aux_state
;
1900 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1902 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1903 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1904 * compress clear color so we wait until an actual fast-clear to allocate it.
1907 intel_miptree_alloc_aux(struct brw_context
*brw
,
1908 struct intel_mipmap_tree
*mt
)
1910 switch (mt
->aux_usage
) {
1911 case ISL_AUX_USAGE_NONE
:
1914 case ISL_AUX_USAGE_HIZ
:
1915 assert(!_mesa_is_format_color_format(mt
->format
));
1916 if (!intel_miptree_alloc_hiz(brw
, mt
))
1920 case ISL_AUX_USAGE_MCS
:
1921 assert(_mesa_is_format_color_format(mt
->format
));
1922 assert(mt
->surf
.samples
> 1);
1923 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1927 case ISL_AUX_USAGE_CCS_D
:
1928 case ISL_AUX_USAGE_CCS_E
:
1929 assert(_mesa_is_format_color_format(mt
->format
));
1930 assert(mt
->surf
.samples
== 1);
1931 if (!intel_miptree_alloc_ccs(brw
, mt
))
1936 unreachable("Invalid aux usage");
1941 * Can the miptree sample using the hiz buffer?
1944 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1945 struct intel_mipmap_tree
*mt
)
1947 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1949 if (!devinfo
->has_sample_with_hiz
) {
1957 /* It seems the hardware won't fallback to the depth buffer if some of the
1958 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1959 * of the texture to be HiZ enabled.
1961 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1962 if (!intel_miptree_level_has_hiz(mt
, level
))
1966 /* If compressed multisampling is enabled, then we use it for the auxiliary
1969 * From the BDW PRM (Volume 2d: Command Reference: Structures
1970 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1972 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1973 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1975 * There is no such blurb for 1D textures, but there is sufficient evidence
1976 * that this is broken on SKL+.
1978 return (mt
->surf
.samples
== 1 &&
1979 mt
->target
!= GL_TEXTURE_3D
&&
1980 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1984 * Does the miptree slice have hiz enabled?
1987 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1989 intel_miptree_check_level_layer(mt
, level
, 0);
1990 return mt
->level
[level
].has_hiz
;
1993 static inline uint32_t
1994 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1995 uint32_t start_level
, uint32_t num_levels
)
1997 assert(start_level
>= mt
->first_level
);
1998 assert(start_level
<= mt
->last_level
);
2000 if (num_levels
== INTEL_REMAINING_LAYERS
)
2001 num_levels
= mt
->last_level
- start_level
+ 1;
2002 /* Check for overflow */
2003 assert(start_level
+ num_levels
>= start_level
);
2004 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2009 static inline uint32_t
2010 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2011 uint32_t start_layer
, uint32_t num_layers
)
2013 assert(level
<= mt
->last_level
);
2015 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
2016 assert(start_layer
< total_num_layers
);
2017 if (num_layers
== INTEL_REMAINING_LAYERS
)
2018 num_layers
= total_num_layers
- start_layer
;
2019 /* Check for overflow */
2020 assert(start_layer
+ num_layers
>= start_layer
);
2021 assert(start_layer
+ num_layers
<= total_num_layers
);
2027 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2028 unsigned start_level
, unsigned num_levels
,
2029 unsigned start_layer
, unsigned num_layers
)
2031 assert(_mesa_is_format_color_format(mt
->format
));
2036 /* Clamp the level range to fit the miptree */
2037 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2039 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2040 const uint32_t level
= start_level
+ l
;
2041 const uint32_t level_layers
=
2042 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2043 for (unsigned a
= 0; a
< level_layers
; a
++) {
2044 enum isl_aux_state aux_state
=
2045 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2046 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2047 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2056 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2057 const struct intel_mipmap_tree
*mt
,
2058 unsigned level
, unsigned layer
)
2063 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2064 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2065 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2067 /* Compression of arrayed msaa surfaces is supported. */
2068 if (mt
->surf
.samples
> 1)
2071 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2072 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2074 mt
->surf
.logical_level0_px
.depth
== 1 &&
2075 mt
->surf
.logical_level0_px
.array_len
== 1));
2081 static enum isl_aux_op
2082 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2083 enum isl_aux_usage aux_usage
,
2084 bool fast_clear_supported
)
2086 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2088 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2090 assert(ccs_supported
== fast_clear_supported
);
2092 switch (aux_state
) {
2093 case ISL_AUX_STATE_CLEAR
:
2094 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2096 return ISL_AUX_OP_FULL_RESOLVE
;
2098 return ISL_AUX_OP_NONE
;
2100 case ISL_AUX_STATE_PASS_THROUGH
:
2101 return ISL_AUX_OP_NONE
;
2103 case ISL_AUX_STATE_RESOLVED
:
2104 case ISL_AUX_STATE_AUX_INVALID
:
2105 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2106 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2110 unreachable("Invalid aux state for CCS_D");
2113 static enum isl_aux_op
2114 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2115 enum isl_aux_usage aux_usage
,
2116 bool fast_clear_supported
)
2118 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2119 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2120 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2121 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2123 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2124 assert(fast_clear_supported
);
2126 switch (aux_state
) {
2127 case ISL_AUX_STATE_CLEAR
:
2128 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2129 if (fast_clear_supported
)
2130 return ISL_AUX_OP_NONE
;
2131 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2132 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2134 return ISL_AUX_OP_FULL_RESOLVE
;
2136 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2137 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2138 return ISL_AUX_OP_FULL_RESOLVE
;
2139 else if (!fast_clear_supported
)
2140 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2142 return ISL_AUX_OP_NONE
;
2144 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2145 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2146 return ISL_AUX_OP_FULL_RESOLVE
;
2148 return ISL_AUX_OP_NONE
;
2150 case ISL_AUX_STATE_PASS_THROUGH
:
2151 return ISL_AUX_OP_NONE
;
2153 case ISL_AUX_STATE_RESOLVED
:
2154 case ISL_AUX_STATE_AUX_INVALID
:
2158 unreachable("Invalid aux state for CCS_E");
2162 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2163 struct intel_mipmap_tree
*mt
,
2164 uint32_t level
, uint32_t layer
,
2165 enum isl_aux_usage aux_usage
,
2166 bool fast_clear_supported
)
2168 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2170 enum isl_aux_op resolve_op
;
2171 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2172 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2173 fast_clear_supported
);
2175 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2176 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2177 fast_clear_supported
);
2180 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2181 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2182 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2184 switch (resolve_op
) {
2185 case ISL_AUX_OP_FULL_RESOLVE
:
2186 /* The CCS full resolve operation destroys the CCS and sets it to the
2187 * pass-through state. (You can also think of this as being both a
2188 * resolve and an ambiguate in one operation.)
2190 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2191 ISL_AUX_STATE_PASS_THROUGH
);
2194 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2195 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2196 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2200 unreachable("Invalid resolve op");
2206 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2207 struct intel_mipmap_tree
*mt
,
2208 uint32_t level
, uint32_t layer
,
2209 enum isl_aux_usage aux_usage
)
2211 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2212 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2213 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2215 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2217 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2218 switch (aux_state
) {
2219 case ISL_AUX_STATE_CLEAR
:
2220 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2221 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2222 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2224 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2225 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2226 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2227 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2228 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2229 ISL_AUX_STATE_PARTIAL_CLEAR
);
2233 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2234 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2235 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2236 break; /* Nothing to do */
2238 case ISL_AUX_STATE_PASS_THROUGH
:
2239 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2240 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2241 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2247 case ISL_AUX_STATE_RESOLVED
:
2248 case ISL_AUX_STATE_AUX_INVALID
:
2249 unreachable("Invalid aux state for CCS_E");
2252 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2253 /* CCS_D is a bit simpler */
2254 switch (aux_state
) {
2255 case ISL_AUX_STATE_CLEAR
:
2256 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2257 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2258 ISL_AUX_STATE_PARTIAL_CLEAR
);
2261 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2262 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2263 break; /* Nothing to do */
2265 case ISL_AUX_STATE_PASS_THROUGH
:
2269 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2270 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2271 case ISL_AUX_STATE_RESOLVED
:
2272 case ISL_AUX_STATE_AUX_INVALID
:
2273 unreachable("Invalid aux state for CCS_D");
2279 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2280 struct intel_mipmap_tree
*mt
,
2282 enum isl_aux_usage aux_usage
,
2283 bool fast_clear_supported
)
2285 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2287 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2288 case ISL_AUX_STATE_CLEAR
:
2289 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2290 if (!fast_clear_supported
) {
2291 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2292 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2293 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2297 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2298 break; /* Nothing to do */
2300 case ISL_AUX_STATE_RESOLVED
:
2301 case ISL_AUX_STATE_PASS_THROUGH
:
2302 case ISL_AUX_STATE_AUX_INVALID
:
2303 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2304 unreachable("Invalid aux state for MCS");
2309 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2310 struct intel_mipmap_tree
*mt
,
2312 enum isl_aux_usage aux_usage
)
2314 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2316 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2317 case ISL_AUX_STATE_CLEAR
:
2318 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2319 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2322 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2323 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2324 break; /* Nothing to do */
2326 case ISL_AUX_STATE_RESOLVED
:
2327 case ISL_AUX_STATE_PASS_THROUGH
:
2328 case ISL_AUX_STATE_AUX_INVALID
:
2329 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2330 unreachable("Invalid aux state for MCS");
2335 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2336 struct intel_mipmap_tree
*mt
,
2337 uint32_t level
, uint32_t layer
,
2338 enum isl_aux_usage aux_usage
,
2339 bool fast_clear_supported
)
2341 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2343 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2344 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2345 case ISL_AUX_STATE_CLEAR
:
2346 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2347 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2348 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2351 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2352 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2353 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2356 case ISL_AUX_STATE_PASS_THROUGH
:
2357 case ISL_AUX_STATE_RESOLVED
:
2360 case ISL_AUX_STATE_AUX_INVALID
:
2361 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2362 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2365 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2366 unreachable("Invalid HiZ state");
2369 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2370 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2373 case ISL_AUX_OP_FULL_RESOLVE
:
2374 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2375 ISL_AUX_STATE_RESOLVED
);
2378 case ISL_AUX_OP_AMBIGUATE
:
2379 /* The HiZ resolve operation is actually an ambiguate */
2380 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2381 ISL_AUX_STATE_PASS_THROUGH
);
2385 unreachable("Invalid HiZ op");
2391 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2392 struct intel_mipmap_tree
*mt
,
2393 uint32_t level
, uint32_t layer
,
2394 enum isl_aux_usage aux_usage
)
2396 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2398 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2399 case ISL_AUX_STATE_CLEAR
:
2400 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2401 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2402 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2405 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2406 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2407 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2408 break; /* Nothing to do */
2410 case ISL_AUX_STATE_RESOLVED
:
2411 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2412 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2413 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2415 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2416 ISL_AUX_STATE_AUX_INVALID
);
2420 case ISL_AUX_STATE_PASS_THROUGH
:
2421 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2422 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2423 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2427 case ISL_AUX_STATE_AUX_INVALID
:
2428 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2431 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2432 unreachable("Invalid HiZ state");
2437 intel_miptree_prepare_access(struct brw_context
*brw
,
2438 struct intel_mipmap_tree
*mt
,
2439 uint32_t start_level
, uint32_t num_levels
,
2440 uint32_t start_layer
, uint32_t num_layers
,
2441 enum isl_aux_usage aux_usage
,
2442 bool fast_clear_supported
)
2444 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2446 switch (mt
->aux_usage
) {
2447 case ISL_AUX_USAGE_NONE
:
2451 case ISL_AUX_USAGE_MCS
:
2452 assert(mt
->aux_buf
);
2453 assert(start_level
== 0 && num_levels
== 1);
2454 const uint32_t level_layers
=
2455 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2456 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2457 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2458 aux_usage
, fast_clear_supported
);
2462 case ISL_AUX_USAGE_CCS_D
:
2463 case ISL_AUX_USAGE_CCS_E
:
2467 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2468 const uint32_t level
= start_level
+ l
;
2469 const uint32_t level_layers
=
2470 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2471 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2472 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2474 aux_usage
, fast_clear_supported
);
2479 case ISL_AUX_USAGE_HIZ
:
2480 assert(mt
->aux_buf
);
2481 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2482 const uint32_t level
= start_level
+ l
;
2483 if (!intel_miptree_level_has_hiz(mt
, level
))
2486 const uint32_t level_layers
=
2487 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2488 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2489 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2490 aux_usage
, fast_clear_supported
);
2496 unreachable("Invalid aux usage");
2501 intel_miptree_finish_write(struct brw_context
*brw
,
2502 struct intel_mipmap_tree
*mt
, uint32_t level
,
2503 uint32_t start_layer
, uint32_t num_layers
,
2504 enum isl_aux_usage aux_usage
)
2506 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2508 switch (mt
->aux_usage
) {
2509 case ISL_AUX_USAGE_NONE
:
2513 case ISL_AUX_USAGE_MCS
:
2514 assert(mt
->aux_buf
);
2515 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2516 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2521 case ISL_AUX_USAGE_CCS_D
:
2522 case ISL_AUX_USAGE_CCS_E
:
2526 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2527 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2532 case ISL_AUX_USAGE_HIZ
:
2533 if (!intel_miptree_level_has_hiz(mt
, level
))
2536 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2537 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2543 unreachable("Invavlid aux usage");
2548 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2549 uint32_t level
, uint32_t layer
)
2551 intel_miptree_check_level_layer(mt
, level
, layer
);
2553 if (_mesa_is_format_color_format(mt
->format
)) {
2554 assert(mt
->aux_buf
!= NULL
);
2555 assert(mt
->surf
.samples
== 1 ||
2556 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2557 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2558 unreachable("Cannot get aux state for stencil");
2560 assert(intel_miptree_level_has_hiz(mt
, level
));
2563 return mt
->aux_state
[level
][layer
];
2567 intel_miptree_set_aux_state(struct brw_context
*brw
,
2568 struct intel_mipmap_tree
*mt
, uint32_t level
,
2569 uint32_t start_layer
, uint32_t num_layers
,
2570 enum isl_aux_state aux_state
)
2572 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2574 if (_mesa_is_format_color_format(mt
->format
)) {
2575 assert(mt
->aux_buf
!= NULL
);
2576 assert(mt
->surf
.samples
== 1 ||
2577 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2578 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2579 unreachable("Cannot get aux state for stencil");
2581 assert(intel_miptree_level_has_hiz(mt
, level
));
2584 for (unsigned a
= 0; a
< num_layers
; a
++) {
2585 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2586 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2587 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2592 /* On Gen9 color buffers may be compressed by the hardware (lossless
2593 * compression). There are, however, format restrictions and care needs to be
2594 * taken that the sampler engine is capable for re-interpreting a buffer with
2595 * format different the buffer was originally written with.
2597 * For example, SRGB formats are not compressible and the sampler engine isn't
2598 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2599 * color buffer needs to be resolved so that the sampling surface can be
2600 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2604 can_texture_with_ccs(struct brw_context
*brw
,
2605 struct intel_mipmap_tree
*mt
,
2606 enum isl_format view_format
)
2608 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2611 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2613 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2614 isl_format_get_layout(view_format
)->name
,
2615 _mesa_get_format_name(mt
->format
));
2623 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2624 struct intel_mipmap_tree
*mt
,
2625 enum isl_format view_format
)
2627 switch (mt
->aux_usage
) {
2628 case ISL_AUX_USAGE_HIZ
:
2629 if (intel_miptree_sample_with_hiz(brw
, mt
))
2630 return ISL_AUX_USAGE_HIZ
;
2633 case ISL_AUX_USAGE_MCS
:
2634 return ISL_AUX_USAGE_MCS
;
2636 case ISL_AUX_USAGE_CCS_D
:
2637 case ISL_AUX_USAGE_CCS_E
:
2639 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2640 return ISL_AUX_USAGE_NONE
;
2643 /* If we don't have any unresolved color, report an aux usage of
2644 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2645 * aux surface and we can save some bandwidth.
2647 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2648 0, INTEL_REMAINING_LAYERS
))
2649 return ISL_AUX_USAGE_NONE
;
2651 if (can_texture_with_ccs(brw
, mt
, view_format
))
2652 return ISL_AUX_USAGE_CCS_E
;
2659 return ISL_AUX_USAGE_NONE
;
2663 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2665 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2666 * values so sRGB curve application was a no-op for all fast-clearable
2669 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2670 * values, the hardware interprets the floats, not as what would be
2671 * returned from the sampler (or written by the shader), but as being
2672 * between format conversion and sRGB curve application. This means that
2673 * we can switch between sRGB and UNORM without having to whack the clear
2676 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2680 intel_miptree_prepare_texture(struct brw_context
*brw
,
2681 struct intel_mipmap_tree
*mt
,
2682 enum isl_format view_format
,
2683 uint32_t start_level
, uint32_t num_levels
,
2684 uint32_t start_layer
, uint32_t num_layers
)
2686 enum isl_aux_usage aux_usage
=
2687 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2688 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2690 /* Clear color is specified as ints or floats and the conversion is done by
2691 * the sampler. If we have a texture view, we would have to perform the
2692 * clear color conversion manually. Just disable clear color.
2694 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2695 clear_supported
= false;
2697 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2698 start_layer
, num_layers
,
2699 aux_usage
, clear_supported
);
2703 intel_miptree_prepare_image(struct brw_context
*brw
,
2704 struct intel_mipmap_tree
*mt
)
2706 /* The data port doesn't understand any compression */
2707 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2708 0, INTEL_REMAINING_LAYERS
,
2709 ISL_AUX_USAGE_NONE
, false);
2713 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2714 struct intel_mipmap_tree
*mt
,
2715 enum isl_format render_format
,
2717 bool draw_aux_disabled
)
2719 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2721 if (draw_aux_disabled
)
2722 return ISL_AUX_USAGE_NONE
;
2724 switch (mt
->aux_usage
) {
2725 case ISL_AUX_USAGE_MCS
:
2726 assert(mt
->aux_buf
);
2727 return ISL_AUX_USAGE_MCS
;
2729 case ISL_AUX_USAGE_CCS_D
:
2730 case ISL_AUX_USAGE_CCS_E
:
2732 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2733 return ISL_AUX_USAGE_NONE
;
2736 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2737 * formats. However, there are issues with blending where it doesn't
2738 * properly apply the sRGB curve to the clear color when blending.
2740 if (devinfo
->gen
>= 9 && blend_enabled
&&
2741 isl_format_is_srgb(render_format
) &&
2742 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2743 return ISL_AUX_USAGE_NONE
;
2745 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2746 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2748 return ISL_AUX_USAGE_CCS_E
;
2750 /* Otherwise, we have to fall back to CCS_D */
2751 return ISL_AUX_USAGE_CCS_D
;
2754 return ISL_AUX_USAGE_NONE
;
2759 intel_miptree_prepare_render(struct brw_context
*brw
,
2760 struct intel_mipmap_tree
*mt
, uint32_t level
,
2761 uint32_t start_layer
, uint32_t layer_count
,
2762 enum isl_aux_usage aux_usage
)
2764 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2765 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2769 intel_miptree_finish_render(struct brw_context
*brw
,
2770 struct intel_mipmap_tree
*mt
, uint32_t level
,
2771 uint32_t start_layer
, uint32_t layer_count
,
2772 enum isl_aux_usage aux_usage
)
2774 assert(_mesa_is_format_color_format(mt
->format
));
2776 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2781 intel_miptree_prepare_depth(struct brw_context
*brw
,
2782 struct intel_mipmap_tree
*mt
, uint32_t level
,
2783 uint32_t start_layer
, uint32_t layer_count
)
2785 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2786 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2790 intel_miptree_finish_depth(struct brw_context
*brw
,
2791 struct intel_mipmap_tree
*mt
, uint32_t level
,
2792 uint32_t start_layer
, uint32_t layer_count
,
2795 if (depth_written
) {
2796 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2797 mt
->aux_buf
!= NULL
);
2802 intel_miptree_prepare_external(struct brw_context
*brw
,
2803 struct intel_mipmap_tree
*mt
)
2805 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2806 bool supports_fast_clear
= false;
2808 const struct isl_drm_modifier_info
*mod_info
=
2809 isl_drm_modifier_get_info(mt
->drm_modifier
);
2811 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2812 /* CCS_E is the only supported aux for external images and it's only
2813 * supported on very simple images.
2815 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2816 assert(_mesa_is_format_color_format(mt
->format
));
2817 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2818 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2819 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2820 assert(mt
->surf
.samples
== 1);
2821 assert(mt
->aux_buf
!= NULL
);
2823 aux_usage
= mod_info
->aux_usage
;
2824 supports_fast_clear
= mod_info
->supports_clear_color
;
2827 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2828 0, INTEL_REMAINING_LAYERS
,
2829 aux_usage
, supports_fast_clear
);
2833 intel_miptree_finish_external(struct brw_context
*brw
,
2834 struct intel_mipmap_tree
*mt
)
2839 /* We don't know the actual aux state of the aux surface. The previous
2840 * owner could have given it to us in a number of different states.
2841 * Because we don't know the aux state, we reset the aux state to the
2842 * least common denominator of possible valid states.
2844 enum isl_aux_state default_aux_state
=
2845 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2846 assert(mt
->last_level
== mt
->first_level
);
2847 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2852 * Make it possible to share the BO backing the given miptree with another
2853 * process or another miptree.
2855 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2856 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2857 * ensure that no MCS buffer gets allocated in the future.
2859 * HiZ is similarly unsafe with shared buffers.
2862 intel_miptree_make_shareable(struct brw_context
*brw
,
2863 struct intel_mipmap_tree
*mt
)
2865 /* MCS buffers are also used for multisample buffers, but we can't resolve
2866 * away a multisample MCS buffer because it's an integral part of how the
2867 * pixel data is stored. Fortunately this code path should never be
2868 * reached for multisample buffers.
2870 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2871 mt
->surf
.samples
== 1);
2873 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2874 0, INTEL_REMAINING_LAYERS
,
2875 ISL_AUX_USAGE_NONE
, false);
2878 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2881 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2882 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2883 mt
->level
[l
].has_hiz
= false;
2886 free(mt
->aux_state
);
2887 mt
->aux_state
= NULL
;
2888 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2891 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2892 mt
->supports_fast_clear
= false;
2897 * \brief Get pointer offset into stencil buffer.
2899 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2900 * must decode the tile's layout in software.
2903 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2905 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2907 * Even though the returned offset is always positive, the return type is
2909 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2910 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2913 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2915 uint32_t tile_size
= 4096;
2916 uint32_t tile_width
= 64;
2917 uint32_t tile_height
= 64;
2918 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2920 uint32_t tile_x
= x
/ tile_width
;
2921 uint32_t tile_y
= y
/ tile_height
;
2923 /* The byte's address relative to the tile's base addres. */
2924 uint32_t byte_x
= x
% tile_width
;
2925 uint32_t byte_y
= y
% tile_height
;
2927 uintptr_t u
= tile_y
* row_size
2928 + tile_x
* tile_size
2929 + 512 * (byte_x
/ 8)
2931 + 32 * ((byte_y
/ 4) % 2)
2932 + 16 * ((byte_x
/ 4) % 2)
2933 + 8 * ((byte_y
/ 2) % 2)
2934 + 4 * ((byte_x
/ 2) % 2)
2939 /* adjust for bit6 swizzling */
2940 if (((byte_x
/ 8) % 2) == 1) {
2941 if (((byte_y
/ 8) % 2) == 0) {
2953 intel_miptree_updownsample(struct brw_context
*brw
,
2954 struct intel_mipmap_tree
*src
,
2955 struct intel_mipmap_tree
*dst
)
2957 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2958 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2959 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2960 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2962 brw_blorp_blit_miptrees(brw
,
2963 src
, 0 /* level */, 0 /* layer */,
2964 src
->format
, SWIZZLE_XYZW
,
2965 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2968 GL_NEAREST
, false, false /*mirror x, y*/,
2971 if (src
->stencil_mt
) {
2972 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2973 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2974 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2975 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2977 brw_blorp_blit_miptrees(brw
,
2978 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2979 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2980 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2981 dst
->stencil_mt
->format
,
2984 GL_NEAREST
, false, false /*mirror x, y*/,
2985 false, false /* decode/encode srgb */);
2990 intel_update_r8stencil(struct brw_context
*brw
,
2991 struct intel_mipmap_tree
*mt
)
2993 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2995 assert(devinfo
->gen
>= 7);
2996 struct intel_mipmap_tree
*src
=
2997 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2998 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
3001 assert(src
->surf
.size
> 0);
3003 if (!mt
->r8stencil_mt
) {
3004 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3005 mt
->r8stencil_mt
= make_surface(
3008 MESA_FORMAT_R_UINT8
,
3009 src
->first_level
, src
->last_level
,
3010 src
->surf
.logical_level0_px
.width
,
3011 src
->surf
.logical_level0_px
.height
,
3012 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3013 src
->surf
.logical_level0_px
.depth
:
3014 src
->surf
.logical_level0_px
.array_len
,
3017 ISL_SURF_USAGE_TEXTURE_BIT
,
3018 BO_ALLOC_BUSY
, 0, NULL
);
3019 assert(mt
->r8stencil_mt
);
3022 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3024 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3025 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3026 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3027 src
->surf
.phys_level0_sa
.array_len
;
3029 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3030 brw_blorp_copy_miptrees(brw
,
3034 minify(src
->surf
.logical_level0_px
.width
,
3036 minify(src
->surf
.logical_level0_px
.height
,
3041 brw_cache_flush_for_read(brw
, dst
->bo
);
3042 src
->r8stencil_needs_update
= false;
3046 intel_miptree_map_raw(struct brw_context
*brw
,
3047 struct intel_mipmap_tree
*mt
,
3050 struct brw_bo
*bo
= mt
->bo
;
3052 if (brw_batch_references(&brw
->batch
, bo
))
3053 intel_batchbuffer_flush(brw
);
3055 return brw_bo_map(brw
, bo
, mode
);
3059 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3061 brw_bo_unmap(mt
->bo
);
3065 intel_miptree_unmap_gtt(struct brw_context
*brw
,
3066 struct intel_mipmap_tree
*mt
,
3067 struct intel_miptree_map
*map
,
3068 unsigned int level
, unsigned int slice
)
3070 intel_miptree_unmap_raw(mt
);
3074 intel_miptree_map_gtt(struct brw_context
*brw
,
3075 struct intel_mipmap_tree
*mt
,
3076 struct intel_miptree_map
*map
,
3077 unsigned int level
, unsigned int slice
)
3079 unsigned int bw
, bh
;
3081 unsigned int image_x
, image_y
;
3082 intptr_t x
= map
->x
;
3083 intptr_t y
= map
->y
;
3085 /* For compressed formats, the stride is the number of bytes per
3086 * row of blocks. intel_miptree_get_image_offset() already does
3089 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3090 assert(y
% bh
== 0);
3091 assert(x
% bw
== 0);
3095 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3102 /* Note that in the case of cube maps, the caller must have passed the
3103 * slice number referencing the face.
3105 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3109 map
->stride
= mt
->surf
.row_pitch
;
3110 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3113 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3114 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3115 map
->x
, map
->y
, map
->w
, map
->h
,
3116 mt
, _mesa_get_format_name(mt
->format
),
3117 x
, y
, map
->ptr
, map
->stride
);
3119 map
->unmap
= intel_miptree_unmap_gtt
;
3123 intel_miptree_unmap_blit(struct brw_context
*brw
,
3124 struct intel_mipmap_tree
*mt
,
3125 struct intel_miptree_map
*map
,
3129 struct gl_context
*ctx
= &brw
->ctx
;
3131 intel_miptree_unmap_raw(map
->linear_mt
);
3133 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3134 bool ok
= intel_miptree_copy(brw
,
3135 map
->linear_mt
, 0, 0, 0, 0,
3136 mt
, level
, slice
, map
->x
, map
->y
,
3138 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3141 intel_miptree_release(&map
->linear_mt
);
3145 intel_miptree_map_blit(struct brw_context
*brw
,
3146 struct intel_mipmap_tree
*mt
,
3147 struct intel_miptree_map
*map
,
3148 unsigned int level
, unsigned int slice
)
3150 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3151 /* first_level */ 0,
3155 MIPTREE_CREATE_LINEAR
);
3157 if (!map
->linear_mt
) {
3158 fprintf(stderr
, "Failed to allocate blit temporary\n");
3161 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3163 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3164 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3165 * invalidate is set, since we'll be writing the whole rectangle from our
3166 * temporary buffer back out.
3168 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3169 if (!intel_miptree_copy(brw
,
3170 mt
, level
, slice
, map
->x
, map
->y
,
3171 map
->linear_mt
, 0, 0, 0, 0,
3173 fprintf(stderr
, "Failed to blit\n");
3178 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3180 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3181 map
->x
, map
->y
, map
->w
, map
->h
,
3182 mt
, _mesa_get_format_name(mt
->format
),
3183 level
, slice
, map
->ptr
, map
->stride
);
3185 map
->unmap
= intel_miptree_unmap_blit
;
3189 intel_miptree_release(&map
->linear_mt
);
3195 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3197 #if defined(USE_SSE41)
3199 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3200 struct intel_mipmap_tree
*mt
,
3201 struct intel_miptree_map
*map
,
3205 _mesa_align_free(map
->buffer
);
3211 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3212 struct intel_mipmap_tree
*mt
,
3213 struct intel_miptree_map
*map
,
3214 unsigned int level
, unsigned int slice
)
3216 assert(map
->mode
& GL_MAP_READ_BIT
);
3217 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3219 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3220 map
->x
, map
->y
, map
->w
, map
->h
,
3221 mt
, _mesa_get_format_name(mt
->format
),
3222 level
, slice
, map
->ptr
, map
->stride
);
3224 /* Map the original image */
3227 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3231 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3237 src
+= image_y
* mt
->surf
.row_pitch
;
3238 src
+= image_x
* mt
->cpp
;
3240 /* Due to the pixel offsets for the particular image being mapped, our
3241 * src pointer may not be 16-byte aligned. However, if the pitch is
3242 * divisible by 16, then the amount by which it's misaligned will remain
3243 * consistent from row to row.
3245 assert((mt
->surf
.row_pitch
% 16) == 0);
3246 const int misalignment
= ((uintptr_t) src
) & 15;
3248 /* Create an untiled temporary buffer for the mapping. */
3249 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3251 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3253 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3254 /* Offset the destination so it has the same misalignment as src. */
3255 map
->ptr
= map
->buffer
+ misalignment
;
3257 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3259 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3260 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3261 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3263 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3266 intel_miptree_unmap_raw(mt
);
3268 map
->unmap
= intel_miptree_unmap_movntdqa
;
3273 intel_miptree_unmap_s8(struct brw_context
*brw
,
3274 struct intel_mipmap_tree
*mt
,
3275 struct intel_miptree_map
*map
,
3279 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3280 unsigned int image_x
, image_y
;
3281 uint8_t *untiled_s8_map
= map
->ptr
;
3282 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3284 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3286 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3287 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3288 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3289 image_x
+ x
+ map
->x
,
3290 image_y
+ y
+ map
->y
,
3291 brw
->has_swizzling
);
3292 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3296 intel_miptree_unmap_raw(mt
);
3303 intel_miptree_map_s8(struct brw_context
*brw
,
3304 struct intel_mipmap_tree
*mt
,
3305 struct intel_miptree_map
*map
,
3306 unsigned int level
, unsigned int slice
)
3308 map
->stride
= map
->w
;
3309 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3313 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3314 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3315 * invalidate is set, since we'll be writing the whole rectangle from our
3316 * temporary buffer back out.
3318 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3319 uint8_t *untiled_s8_map
= map
->ptr
;
3320 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3321 unsigned int image_x
, image_y
;
3323 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3325 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3326 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3327 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3328 x
+ image_x
+ map
->x
,
3329 y
+ image_y
+ map
->y
,
3330 brw
->has_swizzling
);
3331 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3335 intel_miptree_unmap_raw(mt
);
3337 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3338 map
->x
, map
->y
, map
->w
, map
->h
,
3339 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3341 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3342 map
->x
, map
->y
, map
->w
, map
->h
,
3343 mt
, map
->ptr
, map
->stride
);
3346 map
->unmap
= intel_miptree_unmap_s8
;
3350 intel_miptree_unmap_etc(struct brw_context
*brw
,
3351 struct intel_mipmap_tree
*mt
,
3352 struct intel_miptree_map
*map
,
3358 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3363 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3364 + image_y
* mt
->surf
.row_pitch
3365 + image_x
* mt
->cpp
;
3367 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3368 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3369 map
->ptr
, map
->stride
,
3372 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3373 map
->ptr
, map
->stride
,
3374 map
->w
, map
->h
, mt
->etc_format
);
3376 intel_miptree_unmap_raw(mt
);
3381 intel_miptree_map_etc(struct brw_context
*brw
,
3382 struct intel_mipmap_tree
*mt
,
3383 struct intel_miptree_map
*map
,
3387 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3388 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3389 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3392 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3393 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3395 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3396 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3397 map
->w
, map
->h
, 1));
3398 map
->ptr
= map
->buffer
;
3399 map
->unmap
= intel_miptree_unmap_etc
;
3403 * Mapping functions for packed depth/stencil miptrees backed by real separate
3404 * miptrees for depth and stencil.
3406 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3407 * separate from the depth buffer. Yet at the GL API level, we have to expose
3408 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3409 * be able to map that memory for texture storage and glReadPixels-type
3410 * operations. We give Mesa core that access by mallocing a temporary and
3411 * copying the data between the actual backing store and the temporary.
3414 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3415 struct intel_mipmap_tree
*mt
,
3416 struct intel_miptree_map
*map
,
3420 struct intel_mipmap_tree
*z_mt
= mt
;
3421 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3422 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3424 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3425 uint32_t *packed_map
= map
->ptr
;
3426 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3427 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3428 unsigned int s_image_x
, s_image_y
;
3429 unsigned int z_image_x
, z_image_y
;
3431 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3432 &s_image_x
, &s_image_y
);
3433 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3434 &z_image_x
, &z_image_y
);
3436 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3437 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3438 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3439 x
+ s_image_x
+ map
->x
,
3440 y
+ s_image_y
+ map
->y
,
3441 brw
->has_swizzling
);
3442 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3443 (z_mt
->surf
.row_pitch
/ 4) +
3444 (x
+ z_image_x
+ map
->x
));
3446 if (map_z32f_x24s8
) {
3447 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3448 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3450 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3451 s_map
[s_offset
] = packed
>> 24;
3452 z_map
[z_offset
] = packed
;
3457 intel_miptree_unmap_raw(s_mt
);
3458 intel_miptree_unmap_raw(z_mt
);
3460 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3462 map
->x
, map
->y
, map
->w
, map
->h
,
3463 z_mt
, _mesa_get_format_name(z_mt
->format
),
3464 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3465 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3466 map
->ptr
, map
->stride
);
3473 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3474 struct intel_mipmap_tree
*mt
,
3475 struct intel_miptree_map
*map
,
3476 unsigned int level
, unsigned int slice
)
3478 struct intel_mipmap_tree
*z_mt
= mt
;
3479 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3480 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3481 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3483 map
->stride
= map
->w
* packed_bpp
;
3484 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3488 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3489 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3490 * invalidate is set, since we'll be writing the whole rectangle from our
3491 * temporary buffer back out.
3493 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3494 uint32_t *packed_map
= map
->ptr
;
3495 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3496 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3497 unsigned int s_image_x
, s_image_y
;
3498 unsigned int z_image_x
, z_image_y
;
3500 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3501 &s_image_x
, &s_image_y
);
3502 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3503 &z_image_x
, &z_image_y
);
3505 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3506 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3507 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3508 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3511 brw
->has_swizzling
);
3512 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3513 (z_mt
->surf
.row_pitch
/ 4) +
3514 (map_x
+ z_image_x
));
3515 uint8_t s
= s_map
[s_offset
];
3516 uint32_t z
= z_map
[z_offset
];
3518 if (map_z32f_x24s8
) {
3519 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3520 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3522 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3527 intel_miptree_unmap_raw(s_mt
);
3528 intel_miptree_unmap_raw(z_mt
);
3530 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3532 map
->x
, map
->y
, map
->w
, map
->h
,
3533 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3534 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3535 map
->ptr
, map
->stride
);
3537 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3538 map
->x
, map
->y
, map
->w
, map
->h
,
3539 mt
, map
->ptr
, map
->stride
);
3542 map
->unmap
= intel_miptree_unmap_depthstencil
;
3546 * Create and attach a map to the miptree at (level, slice). Return the
3549 static struct intel_miptree_map
*
3550 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3559 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3564 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3565 mt
->level
[level
].slice
[slice
].map
= map
;
3577 * Release the map at (level, slice).
3580 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3584 struct intel_miptree_map
**map
;
3586 map
= &mt
->level
[level
].slice
[slice
].map
;
3592 can_blit_slice(struct intel_mipmap_tree
*mt
,
3593 unsigned int level
, unsigned int slice
)
3595 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3596 if (mt
->surf
.row_pitch
>= 32768)
3603 use_intel_mipree_map_blit(struct brw_context
*brw
,
3604 struct intel_mipmap_tree
*mt
,
3609 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3611 if (devinfo
->has_llc
&&
3612 /* It's probably not worth swapping to the blit ring because of
3613 * all the overhead involved.
3615 !(mode
& GL_MAP_WRITE_BIT
) &&
3617 (mt
->surf
.tiling
== ISL_TILING_X
||
3618 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3619 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3620 /* Fast copy blit on skl+ supports all tiling formats. */
3621 devinfo
->gen
>= 9) &&
3622 can_blit_slice(mt
, level
, slice
))
3625 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3626 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3627 assert(can_blit_slice(mt
, level
, slice
));
3635 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3636 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3637 * arithmetic overflow.
3639 * If you call this function and use \a out_stride, then you're doing pointer
3640 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3641 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3642 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3643 * which usually have type uint32_t or GLuint.
3646 intel_miptree_map(struct brw_context
*brw
,
3647 struct intel_mipmap_tree
*mt
,
3656 ptrdiff_t *out_stride
)
3658 struct intel_miptree_map
*map
;
3660 assert(mt
->surf
.samples
== 1);
3662 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3669 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3670 map
->mode
& GL_MAP_WRITE_BIT
);
3672 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3673 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3674 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3675 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3676 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3677 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3678 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3679 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3680 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3681 #if defined(USE_SSE41)
3682 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3683 !mt
->compressed
&& cpu_has_sse4_1
&&
3684 (mt
->surf
.row_pitch
% 16 == 0)) {
3685 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3688 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3691 *out_ptr
= map
->ptr
;
3692 *out_stride
= map
->stride
;
3694 if (map
->ptr
== NULL
)
3695 intel_miptree_release_map(mt
, level
, slice
);
3699 intel_miptree_unmap(struct brw_context
*brw
,
3700 struct intel_mipmap_tree
*mt
,
3704 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3706 assert(mt
->surf
.samples
== 1);
3711 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3712 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3715 map
->unmap(brw
, mt
, map
, level
, slice
);
3717 intel_miptree_release_map(mt
, level
, slice
);
3721 get_isl_surf_dim(GLenum target
)
3725 case GL_TEXTURE_1D_ARRAY
:
3726 return ISL_SURF_DIM_1D
;
3729 case GL_TEXTURE_2D_ARRAY
:
3730 case GL_TEXTURE_RECTANGLE
:
3731 case GL_TEXTURE_CUBE_MAP
:
3732 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3733 case GL_TEXTURE_2D_MULTISAMPLE
:
3734 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3735 case GL_TEXTURE_EXTERNAL_OES
:
3736 return ISL_SURF_DIM_2D
;
3739 return ISL_SURF_DIM_3D
;
3742 unreachable("Invalid texture target");
3746 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3747 enum isl_tiling tiling
, GLenum target
)
3751 case GL_TEXTURE_1D_ARRAY
:
3752 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3753 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3756 case GL_TEXTURE_2D_ARRAY
:
3757 case GL_TEXTURE_RECTANGLE
:
3758 case GL_TEXTURE_2D_MULTISAMPLE
:
3759 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3760 case GL_TEXTURE_EXTERNAL_OES
:
3761 return ISL_DIM_LAYOUT_GEN4_2D
;
3763 case GL_TEXTURE_CUBE_MAP
:
3764 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3765 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3766 ISL_DIM_LAYOUT_GEN4_2D
);
3769 return (devinfo
->gen
>= 9 ?
3770 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3773 unreachable("Invalid texture target");
3777 intel_miptree_set_clear_color(struct brw_context
*brw
,
3778 struct intel_mipmap_tree
*mt
,
3779 const union gl_color_union
*color
)
3781 const union isl_color_value clear_color
=
3782 brw_meta_convert_fast_clear_color(brw
, mt
, color
);
3784 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3785 mt
->fast_clear_color
= clear_color
;
3786 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3793 intel_miptree_set_depth_clear_value(struct brw_context
*brw
,
3794 struct intel_mipmap_tree
*mt
,
3797 if (mt
->fast_clear_color
.f32
[0] != clear_value
) {
3798 mt
->fast_clear_color
.f32
[0] = clear_value
;
3799 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3805 union isl_color_value
3806 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3807 const struct intel_mipmap_tree
*mt
,
3808 enum isl_format view_format
, bool sampling
,
3809 struct brw_bo
**clear_color_bo
,
3810 uint32_t *clear_color_offset
)
3812 assert(mt
->aux_buf
);
3814 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3815 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3816 * we switch to using the inline clear color and do the sRGB color
3817 * conversion process defined in the OpenGL spec. The red, green, and
3818 * blue channels take part in gamma correction, while the alpha channel
3821 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3822 for (unsigned i
= 0; i
< 3; i
++) {
3823 srgb_decoded_value
.f32
[i
] =
3824 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3826 *clear_color_bo
= 0;
3827 *clear_color_offset
= 0;
3828 return srgb_decoded_value
;
3830 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3831 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3832 return mt
->fast_clear_color
;