2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
,
125 enum isl_tiling tiling
)
127 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
128 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
130 * - Support is limited to tiled render targets.
132 * Gen9 changes the restriction to Y-tile only.
135 return tiling
== ISL_TILING_Y0
;
136 else if (brw
->gen
>= 7)
137 return tiling
!= ISL_TILING_LINEAR
;
143 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
144 * can be used. This doesn't (and should not) inspect any of the properties of
147 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
148 * beneath the "Fast Color Clear" bullet (p326):
150 * - Support is for non-mip-mapped and non-array surface types only.
152 * And then later, on p327:
154 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
157 * From the Skylake documentation, it is made clear that X-tiling is no longer
160 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
164 intel_miptree_supports_ccs(struct brw_context
*brw
,
165 const struct intel_mipmap_tree
*mt
)
167 /* MCS support does not exist prior to Gen7 */
171 /* This function applies only to non-multisampled render targets. */
172 if (mt
->surf
.samples
> 1)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
186 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
187 const bool arrayed
= mt
->physical_depth0
!= 1;
190 /* Multisample surfaces with the CMS layout are not layered surfaces,
191 * yet still have physical_depth0 > 1. Assert that we don't
192 * accidentally reject a multisampled surface here. We should have
193 * rejected it earlier by explicitly checking the sample count.
195 assert(mt
->surf
.samples
== 1);
198 /* Handle the hardware restrictions...
200 * All GENs have the following restriction: "MCS buffer for non-MSRT is
201 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
203 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
204 * Non-MultiSampler Render Target Restrictions) Support is for
205 * non-mip-mapped and non-array surface types only.
207 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
208 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
209 * surfaces are supported with MCS buffer layout with these alignments in
210 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
212 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
213 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
214 * surfaces are supported with MCS buffer layout with these alignments in
215 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
217 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
220 /* There's no point in using an MCS buffer if the surface isn't in a
223 if (!brw
->mesa_format_supports_render
[mt
->format
])
227 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
228 const enum isl_format isl_format
=
229 brw_isl_format_for_mesa_format(linear_format
);
230 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
236 intel_tiling_supports_hiz(const struct brw_context
*brw
,
237 enum isl_tiling tiling
)
242 return tiling
== ISL_TILING_Y0
;
246 intel_miptree_supports_hiz(const struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
252 switch (mt
->format
) {
253 case MESA_FORMAT_Z_FLOAT32
:
254 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
255 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
256 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
257 case MESA_FORMAT_Z_UNORM16
:
265 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
266 const struct intel_mipmap_tree
*mt
)
268 /* For now compression is only enabled for integer formats even though
269 * there exist supported floating point formats also. This is a heuristic
270 * decision based on current public benchmarks. In none of the cases these
271 * formats provided any improvement but a few cases were seen to regress.
272 * Hence these are left to to be enabled in the future when they are known
275 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
278 if (!intel_miptree_supports_ccs(brw
, mt
))
281 /* Fast clear can be also used to clear srgb surfaces by using equivalent
282 * linear format. This trick, however, can't be extended to be used with
283 * lossless compression and therefore a check is needed to see if the format
286 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
290 * Determine depth format corresponding to a depth+stencil format,
291 * for separate stencil.
294 intel_depth_format_for_depthstencil_format(mesa_format format
) {
296 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
297 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
298 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
299 return MESA_FORMAT_Z_FLOAT32
;
306 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
307 unsigned depth0
, struct intel_mipmap_level
*table
)
309 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
311 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
313 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
314 if (!table
[level
].slice
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++)
322 free(table
[level
].slice
);
328 needs_separate_stencil(const struct brw_context
*brw
,
329 struct intel_mipmap_tree
*mt
,
330 mesa_format format
, uint32_t layout_flags
)
333 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
336 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
339 if (brw
->must_use_separate_stencil
)
342 return brw
->has_separate_stencil
&&
343 intel_miptree_supports_hiz(brw
, mt
);
347 * @param for_bo Indicates that the caller is
348 * intel_miptree_create_for_bo(). If true, then do not create
351 static struct intel_mipmap_tree
*
352 intel_miptree_create_layout(struct brw_context
*brw
,
361 uint32_t layout_flags
)
363 assert(num_samples
> 0);
365 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
369 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
370 _mesa_enum_to_string(target
),
371 _mesa_get_format_name(format
),
372 first_level
, last_level
, depth0
, mt
);
374 if (target
== GL_TEXTURE_1D_ARRAY
)
375 assert(height0
== 1);
379 mt
->first_level
= first_level
;
380 mt
->last_level
= last_level
;
381 mt
->logical_width0
= width0
;
382 mt
->logical_height0
= height0
;
383 mt
->logical_depth0
= depth0
;
384 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
385 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
386 mt
->supports_fast_clear
= false;
387 mt
->aux_state
= NULL
;
388 mt
->cpp
= _mesa_get_format_bytes(format
);
389 mt
->surf
.samples
= num_samples
;
390 mt
->compressed
= _mesa_is_format_compressed(format
);
391 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
394 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
395 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
397 int depth_multiply
= 1;
398 if (num_samples
> 1) {
399 /* Adjust width/height/depth for MSAA */
400 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
401 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
402 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
403 * "If the surface is multisampled and it is a depth or stencil
404 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
405 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
408 * +----------------------------------------------------------------+
409 * | Num Multisamples | W_l = | H_l = |
410 * +----------------------------------------------------------------+
411 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
412 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
413 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
414 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
415 * +----------------------------------------------------------------+
418 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
419 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
420 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
422 * Another more complicated explanation for these adjustments comes
423 * from the Sandybridge PRM, volume 4, part 1, page 31:
425 * "Any of the other messages (sample*, LOD, load4) used with a
426 * (4x) multisampled surface will in-effect sample a surface with
427 * double the height and width as that indicated in the surface
428 * state. Each pixel position on the original-sized surface is
429 * replaced with a 2x2 of samples with the following arrangement:
434 * Thus, when sampling from a multisampled texture, it behaves as
435 * though the layout in memory for (x,y,sample) is:
437 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
438 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
440 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
441 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
443 * However, the actual layout of multisampled data in memory is:
445 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
446 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
448 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
449 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
451 * This pattern repeats for each 2x2 pixel block.
453 * As a result, when calculating the size of our 4-sample buffer for
454 * an odd width or height, we have to align before scaling up because
455 * sample 3 is in that bottom right 2x2 block.
457 switch (num_samples
) {
459 assert(brw
->gen
>= 8);
460 width0
= ALIGN(width0
, 2) * 2;
461 height0
= ALIGN(height0
, 2);
464 width0
= ALIGN(width0
, 2) * 2;
465 height0
= ALIGN(height0
, 2) * 2;
468 width0
= ALIGN(width0
, 2) * 4;
469 height0
= ALIGN(height0
, 2) * 2;
472 width0
= ALIGN(width0
, 2) * 4;
473 height0
= ALIGN(height0
, 2) * 4;
476 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
479 unreachable("not reached");
482 /* Non-interleaved */
483 depth_multiply
= num_samples
;
484 depth0
*= depth_multiply
;
488 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->surf
.msaa_layout
) {
508 case ISL_MSAA_LAYOUT_NONE
:
509 case ISL_MSAA_LAYOUT_INTERLEAVED
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case ISL_MSAA_LAYOUT_ARRAY
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
519 assert(depth0
== 6 * depth_multiply
);
521 mt
->physical_width0
= width0
;
522 mt
->physical_height0
= height0
;
523 mt
->physical_depth0
= depth0
;
525 assert(!needs_separate_stencil(brw
, mt
, format
, layout_flags
));
528 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
529 * multisampled or have an AUX buffer attached to it.
531 * GEN | MSRT | AUX_CCS_* or AUX_MCS
532 * -------------------------------------------
533 * 9 | HALIGN_16 | HALIGN_16
534 * 8 | HALIGN_ANY | HALIGN_16
538 if (intel_miptree_supports_ccs(brw
, mt
)) {
539 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
540 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
541 } else if (brw
->gen
>= 9 && num_samples
> 1) {
542 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
544 const UNUSED
bool is_lossless_compressed_aux
=
545 brw
->gen
>= 9 && num_samples
== 1 &&
546 mt
->format
== MESA_FORMAT_R_UINT32
;
548 /* For now, nothing else has this requirement */
549 assert(is_lossless_compressed_aux
||
550 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
553 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
554 intel_miptree_release(&mt
);
563 * Choose the aux usage for this miptree. This function must be called fairly
564 * late in the miptree create process after we have a tiling.
567 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
568 struct intel_mipmap_tree
*mt
)
570 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
572 const unsigned no_flags
= 0;
573 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
574 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
575 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
576 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
577 intel_miptree_supports_ccs(brw
, mt
)) {
578 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
579 brw
->gen
>= 9 && !mt
->is_scanout
&&
580 intel_miptree_supports_ccs_e(brw
, mt
)) {
581 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
583 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
585 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
586 intel_miptree_supports_hiz(brw
, mt
)) {
587 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
590 /* We can do fast-clear on all auxiliary surface types that are
591 * allocated through the normal texture creation paths.
593 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
594 mt
->supports_fast_clear
= true;
599 * Choose an appropriate uncompressed format for a requested
600 * compressed format, if unsupported.
603 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
605 /* No need to lower ETC formats on these platforms,
606 * they are supported natively.
608 if (brw
->gen
>= 8 || brw
->is_baytrail
)
612 case MESA_FORMAT_ETC1_RGB8
:
613 return MESA_FORMAT_R8G8B8X8_UNORM
;
614 case MESA_FORMAT_ETC2_RGB8
:
615 return MESA_FORMAT_R8G8B8X8_UNORM
;
616 case MESA_FORMAT_ETC2_SRGB8
:
617 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
618 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
619 return MESA_FORMAT_B8G8R8A8_SRGB
;
620 case MESA_FORMAT_ETC2_RGBA8_EAC
:
621 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
622 return MESA_FORMAT_R8G8B8A8_UNORM
;
623 case MESA_FORMAT_ETC2_R11_EAC
:
624 return MESA_FORMAT_R_UNORM16
;
625 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
626 return MESA_FORMAT_R_SNORM16
;
627 case MESA_FORMAT_ETC2_RG11_EAC
:
628 return MESA_FORMAT_R16G16_UNORM
;
629 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
630 return MESA_FORMAT_R16G16_SNORM
;
632 /* Non ETC1 / ETC2 format */
638 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
640 /* In case of physical dimensions one needs to consider also the layout.
641 * See isl_calc_phys_level0_extent_sa().
643 if (surf
->dim
!= ISL_SURF_DIM_3D
)
644 return surf
->phys_level0_sa
.array_len
;
646 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
647 return minify(surf
->phys_level0_sa
.array_len
, level
);
649 return minify(surf
->phys_level0_sa
.depth
, level
);
652 /** \brief Assert that the level and layer are valid for the miptree. */
654 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
662 assert(level
>= mt
->first_level
);
663 assert(level
<= mt
->last_level
);
665 if (mt
->surf
.size
> 0)
666 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
668 assert(layer
< mt
->level
[level
].depth
);
671 static enum isl_aux_state
**
672 create_aux_state_map(struct intel_mipmap_tree
*mt
,
673 enum isl_aux_state initial
)
675 const uint32_t levels
= mt
->last_level
+ 1;
677 uint32_t total_slices
= 0;
678 for (uint32_t level
= 0; level
< levels
; level
++) {
679 if (mt
->surf
.size
> 0)
680 total_slices
+= get_num_phys_layers(&mt
->surf
, level
);
682 total_slices
+= mt
->level
[level
].depth
;
685 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
687 /* We're going to allocate a single chunk of data for both the per-level
688 * reference array and the arrays of aux_state. This makes cleanup
689 * significantly easier.
691 const size_t total_size
= per_level_array_size
+
692 total_slices
* sizeof(enum isl_aux_state
);
693 void *data
= malloc(total_size
);
697 enum isl_aux_state
**per_level_arr
= data
;
698 enum isl_aux_state
*s
= data
+ per_level_array_size
;
699 for (uint32_t level
= 0; level
< levels
; level
++) {
700 per_level_arr
[level
] = s
;
702 unsigned level_depth
;
703 if (mt
->surf
.size
> 0)
704 level_depth
= get_num_phys_layers(&mt
->surf
, level
);
706 level_depth
= mt
->level
[level
].depth
;
708 for (uint32_t a
= 0; a
< level_depth
; a
++)
711 assert((void *)s
== data
+ total_size
);
713 return per_level_arr
;
717 free_aux_state_map(enum isl_aux_state
**state
)
723 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
724 enum isl_tiling tiling
, unsigned samples
)
729 if (tiling
== ISL_TILING_LINEAR
)
732 /* If the width is much smaller than a tile, don't bother tiling. */
736 if (ALIGN(row_pitch
, 512) >= 32768) {
737 perf_debug("row pitch %u too large to blit, falling back to untiled",
746 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
747 enum isl_tiling tiling
)
749 /* If the BO is too large to fit in the aperture, we need to use the
750 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
751 * handle Y-tiling, so we need to fall back to X.
753 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
754 tiling
== ISL_TILING_Y0
)
760 static struct intel_mipmap_tree
*
761 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
762 unsigned first_level
, unsigned last_level
,
763 unsigned width0
, unsigned height0
, unsigned depth0
,
764 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
765 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
766 unsigned row_pitch
, struct brw_bo
*bo
)
768 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
772 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
780 if (target
== GL_TEXTURE_CUBE_MAP
||
781 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
782 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
784 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
786 _mesa_enum_to_string(target
),
787 _mesa_get_format_name(format
),
788 num_samples
, width0
, height0
, depth0
,
789 first_level
, last_level
, mt
);
791 struct isl_surf_init_info init_info
= {
792 .dim
= get_isl_surf_dim(target
),
793 .format
= translate_tex_format(brw
, format
, false),
796 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
797 .levels
= last_level
- first_level
+ 1,
798 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
799 .samples
= num_samples
,
800 .row_pitch
= row_pitch
,
801 .usage
= isl_usage_flags
,
802 .tiling_flags
= tiling_flags
,
805 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
808 /* In case caller doesn't specifically request Y-tiling (needed
809 * unconditionally for depth), check for corner cases needing special
812 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
813 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
814 mt
->surf
.tiling
, mt
->surf
.samples
)) {
815 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
816 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
818 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
819 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
820 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
825 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
828 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
830 isl_tiling_to_i915_tiling(
832 mt
->surf
.row_pitch
, alloc_flags
);
839 mt
->first_level
= first_level
;
840 mt
->last_level
= last_level
;
843 mt
->aux_state
= NULL
;
844 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
849 intel_miptree_release(&mt
);
854 make_separate_stencil_surface(struct brw_context
*brw
,
855 struct intel_mipmap_tree
*mt
)
857 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
858 0, mt
->surf
.levels
- 1,
859 mt
->surf
.logical_level0_px
.width
,
860 mt
->surf
.logical_level0_px
.height
,
861 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
862 mt
->surf
.logical_level0_px
.depth
:
863 mt
->surf
.logical_level0_px
.array_len
,
864 mt
->surf
.samples
, ISL_TILING_W_BIT
,
865 ISL_SURF_USAGE_STENCIL_BIT
|
866 ISL_SURF_USAGE_TEXTURE_BIT
,
867 BO_ALLOC_FOR_RENDER
, 0, NULL
);
872 mt
->stencil_mt
->r8stencil_needs_update
= true;
878 force_linear_tiling(uint32_t layout_flags
)
880 /* ANY includes NONE and Y bit. */
881 if (layout_flags
& MIPTREE_LAYOUT_TILING_Y
)
884 return layout_flags
& MIPTREE_LAYOUT_TILING_NONE
;
887 static struct intel_mipmap_tree
*
888 miptree_create(struct brw_context
*brw
,
897 uint32_t layout_flags
)
899 if (format
== MESA_FORMAT_S_UINT8
)
900 return make_surface(brw
, target
, format
, first_level
, last_level
,
901 width0
, height0
, depth0
, num_samples
,
903 ISL_SURF_USAGE_STENCIL_BIT
|
904 ISL_SURF_USAGE_TEXTURE_BIT
,
909 const GLenum base_format
= _mesa_get_format_base_format(format
);
910 if ((base_format
== GL_DEPTH_COMPONENT
||
911 base_format
== GL_DEPTH_STENCIL
) &&
912 !force_linear_tiling(layout_flags
)) {
913 /* Fix up the Z miptree format for how we're splitting out separate
914 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
916 const mesa_format depth_only_format
=
917 intel_depth_format_for_depthstencil_format(format
);
918 struct intel_mipmap_tree
*mt
= make_surface(
919 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
920 first_level
, last_level
,
921 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
922 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
923 BO_ALLOC_FOR_RENDER
, 0, NULL
);
925 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
) &&
926 !make_separate_stencil_surface(brw
, mt
)) {
927 intel_miptree_release(&mt
);
931 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
932 intel_miptree_choose_aux_usage(brw
, mt
);
937 struct intel_mipmap_tree
*mt
;
938 mesa_format tex_format
= format
;
939 mesa_format etc_format
= MESA_FORMAT_NONE
;
940 uint32_t alloc_flags
= 0;
942 format
= intel_lower_compressed_format(brw
, format
);
944 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
946 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
947 mt
= intel_miptree_create_layout(brw
, target
, format
,
948 first_level
, last_level
, width0
,
949 height0
, depth0
, num_samples
,
954 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
955 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
957 mt
->etc_format
= etc_format
;
959 if (format
== MESA_FORMAT_S_UINT8
) {
960 /* Align to size of W tile, 64x64. */
961 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
962 ALIGN(mt
->total_width
, 64),
963 ALIGN(mt
->total_height
, 64),
965 isl_tiling_to_i915_tiling(
970 /* The stencil buffer has quirky pitch requirements. From the
971 * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
972 * dword 1 bits 16:0 - Surface Pitch):
974 * The pitch must be set to 2x the value computed based on width, as
975 * the stencil buffer is stored with two rows interleaved.
977 * While the Ivybridge PRM lacks this comment, the BSpec contains the
978 * same text, and experiments indicate that this is necessary.
980 mt
->surf
.row_pitch
*= 2;
982 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
983 mt
->total_width
, mt
->total_height
,
985 isl_tiling_to_i915_tiling(
991 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
992 mt
->bo
->cache_coherent
= false;
994 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
995 intel_miptree_choose_aux_usage(brw
, mt
);
1000 struct intel_mipmap_tree
*
1001 intel_miptree_create(struct brw_context
*brw
,
1010 uint32_t layout_flags
)
1012 assert(num_samples
> 0);
1014 struct intel_mipmap_tree
*mt
= miptree_create(
1015 brw
, target
, format
,
1016 first_level
, last_level
,
1017 width0
, height0
, depth0
, num_samples
,
1022 if (need_to_retile_as_x(brw
, mt
->bo
->size
, mt
->surf
.tiling
)) {
1023 const uint32_t alloc_flags
=
1024 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
1025 BO_ALLOC_FOR_RENDER
: 0;
1026 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
1027 mt
->total_width
, mt
->total_height
);
1029 mt
->surf
.tiling
= ISL_TILING_X
;
1030 brw_bo_unreference(mt
->bo
);
1031 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
1032 mt
->total_width
, mt
->total_height
, mt
->cpp
,
1033 isl_tiling_to_i915_tiling(
1035 &mt
->surf
.row_pitch
, alloc_flags
);
1041 intel_miptree_release(&mt
);
1045 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1046 intel_miptree_release(&mt
);
1053 struct intel_mipmap_tree
*
1054 intel_miptree_create_for_bo(struct brw_context
*brw
,
1062 uint32_t layout_flags
)
1064 struct intel_mipmap_tree
*mt
;
1065 uint32_t tiling
, swizzle
;
1066 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
1067 const GLenum base_format
= _mesa_get_format_base_format(format
);
1069 if ((base_format
== GL_DEPTH_COMPONENT
||
1070 base_format
== GL_DEPTH_STENCIL
)) {
1071 const mesa_format depth_only_format
=
1072 intel_depth_format_for_depthstencil_format(format
);
1073 mt
= make_surface(brw
, target
,
1074 brw
->gen
>= 6 ? depth_only_format
: format
,
1075 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
1076 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
1077 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1079 brw_bo_reference(bo
);
1081 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1082 intel_miptree_choose_aux_usage(brw
, mt
);
1085 } else if (format
== MESA_FORMAT_S_UINT8
) {
1086 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
1087 0, 0, width
, height
, depth
, 1,
1089 ISL_SURF_USAGE_STENCIL_BIT
|
1090 ISL_SURF_USAGE_TEXTURE_BIT
,
1091 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
1095 assert(bo
->size
>= mt
->surf
.size
);
1097 brw_bo_reference(bo
);
1101 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
1103 /* Nothing will be able to use this miptree with the BO if the offset isn't
1106 if (tiling
!= I915_TILING_NONE
)
1107 assert(offset
% 4096 == 0);
1109 /* miptrees can't handle negative pitch. If you need flipping of images,
1110 * that's outside of the scope of the mt.
1114 /* The BO already has a tiling format and we shouldn't confuse the lower
1115 * layers by making it try to find a tiling format again.
1117 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
1118 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
1120 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
1121 mt
= intel_miptree_create_layout(brw
, target
, format
,
1123 width
, height
, depth
,
1124 1 /* num_samples */,
1129 brw_bo_reference(bo
);
1131 mt
->surf
.row_pitch
= pitch
;
1132 mt
->offset
= offset
;
1133 mt
->surf
.tiling
= isl_tiling_from_i915_tiling(tiling
);
1135 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
1136 intel_miptree_choose_aux_usage(brw
, mt
);
1141 static struct intel_mipmap_tree
*
1142 miptree_create_for_planar_image(struct brw_context
*brw
,
1143 __DRIimage
*image
, GLenum target
)
1145 struct intel_image_format
*f
= image
->planar_format
;
1146 struct intel_mipmap_tree
*planar_mt
= NULL
;
1148 for (int i
= 0; i
< f
->nplanes
; i
++) {
1149 const int index
= f
->planes
[i
].buffer_index
;
1150 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1151 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1152 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1153 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1155 /* Disable creation of the texture's aux buffers because the driver
1156 * exposes no EGL API to manage them. That is, there is no API for
1157 * resolving the aux buffer's content to the main buffer nor for
1158 * invalidating the aux buffer's content.
1160 struct intel_mipmap_tree
*mt
=
1161 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1162 image
->offsets
[index
],
1164 image
->strides
[index
],
1165 MIPTREE_LAYOUT_DISABLE_AUX
);
1169 mt
->target
= target
;
1174 planar_mt
->plane
[i
- 1] = mt
;
1180 struct intel_mipmap_tree
*
1181 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1182 __DRIimage
*image
, GLenum target
,
1183 enum isl_colorspace colorspace
,
1184 bool is_winsys_image
)
1186 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1187 assert(colorspace
== ISL_COLORSPACE_NONE
||
1188 colorspace
== ISL_COLORSPACE_YUV
);
1189 return miptree_create_for_planar_image(brw
, image
, target
);
1192 mesa_format format
= image
->format
;
1193 switch (colorspace
) {
1194 case ISL_COLORSPACE_NONE
:
1195 /* Keep the image format unmodified */
1198 case ISL_COLORSPACE_LINEAR
:
1199 format
=_mesa_get_srgb_format_linear(format
);
1202 case ISL_COLORSPACE_SRGB
:
1203 format
=_mesa_get_linear_format_srgb(format
);
1207 unreachable("Inalid colorspace for non-planar image");
1210 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1211 /* The texture storage paths in core Mesa detect if the driver does not
1212 * support the user-requested format, and then searches for a
1213 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1214 * do the fallbacks here for important formats.
1216 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1217 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1218 * the Chrome OS compositor consumes as dma_buf EGLImages.
1220 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1223 if (!brw
->ctx
.TextureFormatSupported
[format
])
1226 /* If this image comes in from a window system, we have different
1227 * requirements than if it comes in via an EGL import operation. Window
1228 * system images can use any form of auxiliary compression we wish because
1229 * they get "flushed" before being handed off to the window system and we
1230 * have the opportunity to do resolves. Window system buffers also may be
1231 * used for scanout so we need to flag that appropriately.
1233 const uint32_t mt_layout_flags
=
1234 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1236 /* Disable creation of the texture's aux buffers because the driver exposes
1237 * no EGL API to manage them. That is, there is no API for resolving the aux
1238 * buffer's content to the main buffer nor for invalidating the aux buffer's
1241 struct intel_mipmap_tree
*mt
=
1242 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1243 image
->offset
, image
->width
, image
->height
, 1,
1244 image
->pitch
, mt_layout_flags
);
1248 mt
->target
= target
;
1249 mt
->level
[0].level_x
= image
->tile_x
;
1250 mt
->level
[0].level_y
= image
->tile_y
;
1251 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1252 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1254 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1255 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1256 * trouble resolving back to destination image due to alignment issues.
1258 if (!brw
->has_surface_tile_offset
) {
1259 uint32_t draw_x
, draw_y
;
1260 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1262 if (draw_x
!= 0 || draw_y
!= 0) {
1263 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1264 intel_miptree_release(&mt
);
1269 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1270 intel_miptree_release(&mt
);
1278 * For a singlesample renderbuffer, this simply wraps the given BO with a
1281 * For a multisample renderbuffer, this wraps the window system's
1282 * (singlesample) BO with a singlesample miptree attached to the
1283 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1284 * that will contain the actual rendering (which is lazily resolved to
1285 * irb->singlesample_mt).
1288 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1289 struct intel_renderbuffer
*irb
,
1290 struct intel_mipmap_tree
*singlesample_mt
,
1291 uint32_t width
, uint32_t height
,
1294 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1295 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1296 mesa_format format
= rb
->Format
;
1297 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1299 /* Only the front and back buffers, which are color buffers, are allocated
1300 * through the image loader.
1302 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1303 _mesa_get_format_base_format(format
) == GL_RGBA
);
1305 assert(singlesample_mt
);
1307 if (num_samples
== 1) {
1308 intel_miptree_release(&irb
->mt
);
1309 irb
->mt
= singlesample_mt
;
1311 assert(!irb
->singlesample_mt
);
1313 intel_miptree_release(&irb
->singlesample_mt
);
1314 irb
->singlesample_mt
= singlesample_mt
;
1317 irb
->mt
->logical_width0
!= width
||
1318 irb
->mt
->logical_height0
!= height
) {
1319 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1324 if (!multisample_mt
)
1327 irb
->need_downsample
= false;
1328 intel_miptree_release(&irb
->mt
);
1329 irb
->mt
= multisample_mt
;
1335 intel_miptree_release(&irb
->mt
);
1339 struct intel_mipmap_tree
*
1340 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1344 uint32_t num_samples
)
1346 struct intel_mipmap_tree
*mt
;
1348 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1349 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1350 MIPTREE_LAYOUT_TILING_ANY
|
1351 MIPTREE_LAYOUT_FOR_SCANOUT
;
1353 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1354 width
, height
, depth
, num_samples
,
1362 intel_miptree_release(&mt
);
1367 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1368 struct intel_mipmap_tree
*src
)
1373 intel_miptree_release(dst
);
1377 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1384 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1386 if (aux_buf
== NULL
)
1389 brw_bo_unreference(aux_buf
->bo
);
1395 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1400 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1401 if (--(*mt
)->refcount
<= 0) {
1404 DBG("%s deleting %p\n", __func__
, *mt
);
1406 brw_bo_unreference((*mt
)->bo
);
1407 intel_miptree_release(&(*mt
)->stencil_mt
);
1408 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1409 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1410 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1411 free_aux_state_map((*mt
)->aux_state
);
1413 intel_miptree_release(&(*mt
)->plane
[0]);
1414 intel_miptree_release(&(*mt
)->plane
[1]);
1416 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1417 free((*mt
)->level
[i
].slice
);
1427 intel_get_image_dims(struct gl_texture_image
*image
,
1428 int *width
, int *height
, int *depth
)
1430 switch (image
->TexObject
->Target
) {
1431 case GL_TEXTURE_1D_ARRAY
:
1432 /* For a 1D Array texture the OpenGL API will treat the image height as
1433 * the number of array slices. For Intel hardware, we treat the 1D array
1434 * as a 2D Array with a height of 1. So, here we want to swap image
1437 assert(image
->Depth
== 1);
1438 *width
= image
->Width
;
1440 *depth
= image
->Height
;
1442 case GL_TEXTURE_CUBE_MAP
:
1443 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1444 * though we really have 6 slices.
1446 assert(image
->Depth
== 1);
1447 *width
= image
->Width
;
1448 *height
= image
->Height
;
1452 *width
= image
->Width
;
1453 *height
= image
->Height
;
1454 *depth
= image
->Depth
;
1460 * Can the image be pulled into a unified mipmap tree? This mirrors
1461 * the completeness test in a lot of ways.
1463 * Not sure whether I want to pass gl_texture_image here.
1466 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1467 struct gl_texture_image
*image
)
1469 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1470 GLuint level
= intelImage
->base
.Base
.Level
;
1471 int width
, height
, depth
;
1473 /* glTexImage* choose the texture object based on the target passed in, and
1474 * objects can't change targets over their lifetimes, so this should be
1477 assert(image
->TexObject
->Target
== mt
->target
);
1479 mesa_format mt_format
= mt
->format
;
1480 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1481 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1482 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1483 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1484 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1485 mt_format
= mt
->etc_format
;
1487 if (image
->TexFormat
!= mt_format
)
1490 intel_get_image_dims(image
, &width
, &height
, &depth
);
1492 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1495 if (mt
->surf
.size
> 0) {
1496 if (level
>= mt
->surf
.levels
)
1499 const unsigned level_depth
=
1500 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1501 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1502 mt
->surf
.logical_level0_px
.array_len
;
1504 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1505 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1506 depth
== level_depth
&&
1507 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1510 int level_depth
= mt
->level
[level
].depth
;
1511 if (mt
->surf
.samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1512 level_depth
/= mt
->surf
.samples
;
1514 /* Test image dimensions against the base level image adjusted for
1515 * minification. This will also catch images not present in the
1516 * tree, changed targets, etc.
1518 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1519 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1520 depth
!= level_depth
) {
1524 /* Core uses sample number of zero to indicate single-sampled. */
1525 if (MAX2(image
->NumSamples
, 1) != mt
->surf
.samples
)
1533 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1535 GLuint x
, GLuint y
, GLuint d
)
1537 mt
->level
[level
].depth
= d
;
1538 mt
->level
[level
].level_x
= x
;
1539 mt
->level
[level
].level_y
= y
;
1541 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1544 assert(mt
->level
[level
].slice
);
1546 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1547 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1552 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1553 GLuint level
, GLuint img
,
1556 if (img
== 0 && level
== 0)
1557 assert(x
== 0 && y
== 0);
1559 assert(img
< mt
->level
[level
].depth
);
1561 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1562 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1564 DBG("%s level %d img %d pos %d,%d\n",
1565 __func__
, level
, img
,
1566 mt
->level
[level
].slice
[img
].x_offset
,
1567 mt
->level
[level
].slice
[img
].y_offset
);
1571 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1572 GLuint level
, GLuint slice
,
1573 GLuint
*x
, GLuint
*y
)
1575 if (level
== 0 && slice
== 0) {
1576 *x
= mt
->level
[0].level_x
;
1577 *y
= mt
->level
[0].level_y
;
1581 if (mt
->surf
.size
> 0) {
1582 uint32_t x_offset_sa
, y_offset_sa
;
1584 /* Miptree itself can have an offset only if it represents a single
1585 * slice in an imported buffer object.
1586 * See intel_miptree_create_for_dri_image().
1588 assert(mt
->level
[0].level_x
== 0);
1589 assert(mt
->level
[0].level_y
== 0);
1591 /* Given level is relative to level zero while the miptree may be
1592 * represent just a subset of all levels starting from 'first_level'.
1594 assert(level
>= mt
->first_level
);
1595 level
-= mt
->first_level
;
1597 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1598 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1599 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1600 &x_offset_sa
, &y_offset_sa
);
1607 assert(slice
< mt
->level
[level
].depth
);
1609 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1610 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1615 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1616 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1617 * and tile_h is set to 1.
1620 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1621 uint32_t *tile_w
, uint32_t *tile_h
)
1632 case ISL_TILING_LINEAR
:
1637 unreachable("not reached");
1643 * This function computes masks that may be used to select the bits of the X
1644 * and Y coordinates that indicate the offset within a tile. If the BO is
1645 * untiled, the masks are set to 0.
1648 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1649 uint32_t *mask_x
, uint32_t *mask_y
)
1651 uint32_t tile_w_bytes
, tile_h
;
1653 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1655 *mask_x
= tile_w_bytes
/ cpp
- 1;
1656 *mask_y
= tile_h
- 1;
1660 * Compute the offset (in bytes) from the start of the BO to the given x
1661 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1662 * multiples of the tile size.
1665 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1666 uint32_t x
, uint32_t y
)
1669 uint32_t pitch
= mt
->surf
.row_pitch
;
1671 switch (mt
->surf
.tiling
) {
1673 unreachable("not reached");
1674 case ISL_TILING_LINEAR
:
1675 return y
* pitch
+ x
* cpp
;
1677 assert((x
% (512 / cpp
)) == 0);
1678 assert((y
% 8) == 0);
1679 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1681 assert((x
% (128 / cpp
)) == 0);
1682 assert((y
% 32) == 0);
1683 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1688 * Rendering with tiled buffers requires that the base address of the buffer
1689 * be aligned to a page boundary. For renderbuffers, and sometimes with
1690 * textures, we may want the surface to point at a texture image level that
1691 * isn't at a page boundary.
1693 * This function returns an appropriately-aligned base offset
1694 * according to the tiling restrictions, plus any required x/y offset
1698 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1699 GLuint level
, GLuint slice
,
1704 uint32_t mask_x
, mask_y
;
1706 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1707 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1709 *tile_x
= x
& mask_x
;
1710 *tile_y
= y
& mask_y
;
1712 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1716 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1717 struct intel_mipmap_tree
*src_mt
,
1718 unsigned src_level
, unsigned src_layer
,
1719 struct intel_mipmap_tree
*dst_mt
,
1720 unsigned dst_level
, unsigned dst_layer
,
1721 unsigned width
, unsigned height
)
1724 ptrdiff_t src_stride
, dst_stride
;
1725 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1726 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1728 intel_miptree_map(brw
, src_mt
,
1729 src_level
, src_layer
,
1732 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1735 intel_miptree_map(brw
, dst_mt
,
1736 dst_level
, dst_layer
,
1739 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1743 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1744 _mesa_get_format_name(src_mt
->format
),
1745 src_mt
, src
, src_stride
,
1746 _mesa_get_format_name(dst_mt
->format
),
1747 dst_mt
, dst
, dst_stride
,
1750 int row_size
= cpp
* width
;
1751 if (src_stride
== row_size
&&
1752 dst_stride
== row_size
) {
1753 memcpy(dst
, src
, row_size
* height
);
1755 for (int i
= 0; i
< height
; i
++) {
1756 memcpy(dst
, src
, row_size
);
1762 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1763 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1765 /* Don't forget to copy the stencil data over, too. We could have skipped
1766 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1767 * shuffling the two data sources in/out of temporary storage instead of
1768 * the direct mapping we get this way.
1770 if (dst_mt
->stencil_mt
) {
1771 assert(src_mt
->stencil_mt
);
1772 intel_miptree_copy_slice_sw(brw
,
1773 src_mt
->stencil_mt
, src_level
, src_layer
,
1774 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1780 intel_miptree_copy_slice(struct brw_context
*brw
,
1781 struct intel_mipmap_tree
*src_mt
,
1782 unsigned src_level
, unsigned src_layer
,
1783 struct intel_mipmap_tree
*dst_mt
,
1784 unsigned dst_level
, unsigned dst_layer
)
1787 mesa_format format
= src_mt
->format
;
1788 uint32_t width
, height
;
1790 if (src_mt
->surf
.size
> 0) {
1791 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1792 src_level
- src_mt
->first_level
);
1793 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1794 src_level
- src_mt
->first_level
);
1797 get_num_phys_layers(&src_mt
->surf
,
1798 src_level
- src_mt
->first_level
));
1800 width
= minify(src_mt
->physical_width0
,
1801 src_level
- src_mt
->first_level
);
1802 height
= minify(src_mt
->physical_height0
,
1803 src_level
- src_mt
->first_level
);
1804 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1807 assert(src_mt
->format
== dst_mt
->format
);
1809 if (dst_mt
->compressed
) {
1811 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1812 height
= ALIGN_NPOT(height
, j
) / j
;
1813 width
= ALIGN_NPOT(width
, i
) / i
;
1816 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1817 * below won't apply since we can't do the depth's Y tiling or the
1818 * stencil's W tiling in the blitter.
1820 if (src_mt
->stencil_mt
) {
1821 intel_miptree_copy_slice_sw(brw
,
1822 src_mt
, src_level
, src_layer
,
1823 dst_mt
, dst_level
, dst_layer
,
1828 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1829 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1831 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1834 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1835 _mesa_get_format_name(src_mt
->format
),
1836 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1837 _mesa_get_format_name(dst_mt
->format
),
1838 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1841 if (!intel_miptree_blit(brw
,
1842 src_mt
, src_level
, src_layer
, 0, 0, false,
1843 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1844 width
, height
, GL_COPY
)) {
1845 perf_debug("miptree validate blit for %s failed\n",
1846 _mesa_get_format_name(format
));
1848 intel_miptree_copy_slice_sw(brw
,
1849 src_mt
, src_level
, src_layer
,
1850 dst_mt
, dst_level
, dst_layer
,
1856 * Copies the image's current data to the given miptree, and associates that
1857 * miptree with the image.
1859 * If \c invalidate is true, then the actual image data does not need to be
1860 * copied, but the image still needs to be associated to the new miptree (this
1861 * is set to true if we're about to clear the image).
1864 intel_miptree_copy_teximage(struct brw_context
*brw
,
1865 struct intel_texture_image
*intelImage
,
1866 struct intel_mipmap_tree
*dst_mt
,
1869 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1870 struct intel_texture_object
*intel_obj
=
1871 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1872 int level
= intelImage
->base
.Base
.Level
;
1873 const unsigned face
= intelImage
->base
.Base
.Face
;
1874 unsigned start_layer
, end_layer
;
1876 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1878 assert(intelImage
->base
.Base
.Height
);
1880 end_layer
= intelImage
->base
.Base
.Height
- 1;
1881 } else if (face
> 0) {
1885 assert(intelImage
->base
.Base
.Depth
);
1887 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1891 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1892 intel_miptree_copy_slice(brw
,
1898 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1899 intel_obj
->needs_validate
= true;
1903 intel_miptree_init_mcs(struct brw_context
*brw
,
1904 struct intel_mipmap_tree
*mt
,
1907 assert(mt
->mcs_buf
!= NULL
);
1909 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1911 * When MCS buffer is enabled and bound to MSRT, it is required that it
1912 * is cleared prior to any rendering.
1914 * Since we don't use the MCS buffer for any purpose other than rendering,
1915 * it makes sense to just clear it immediately upon allocation.
1917 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1919 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1920 if (unlikely(map
== NULL
)) {
1921 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1922 brw_bo_unreference(mt
->mcs_buf
->bo
);
1927 memset(data
, init_value
, mt
->mcs_buf
->size
);
1928 brw_bo_unmap(mt
->mcs_buf
->bo
);
1931 static struct intel_miptree_aux_buffer
*
1932 intel_alloc_aux_buffer(struct brw_context
*brw
,
1934 const struct isl_surf
*aux_surf
,
1935 uint32_t alloc_flags
,
1936 struct intel_mipmap_tree
*mt
)
1938 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1942 buf
->size
= aux_surf
->size
;
1943 buf
->pitch
= aux_surf
->row_pitch
;
1944 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1946 /* ISL has stricter set of alignment rules then the drm allocator.
1947 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1948 * trying to recalculate based on different format block sizes.
1950 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1951 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1957 buf
->surf
= *aux_surf
;
1963 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1964 struct intel_mipmap_tree
*mt
,
1967 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1968 assert(mt
->mcs_buf
== NULL
);
1969 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1971 /* Multisampled miptrees are only supported for single level. */
1972 assert(mt
->first_level
== 0);
1973 enum isl_aux_state
**aux_state
=
1974 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1978 struct isl_surf temp_main_surf
;
1979 struct isl_surf temp_mcs_surf
;
1981 /* Create first an ISL presentation for the main color surface and let ISL
1982 * calculate equivalent MCS surface against it.
1984 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1985 MAYBE_UNUSED
bool ok
=
1986 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1989 /* Buffer needs to be initialised requiring the buffer to be immediately
1990 * mapped to cpu space for writing. Therefore do not use the gpu access
1991 * flag which can cause an unnecessary delay if the backing pages happened
1992 * to be just used by the GPU.
1994 const uint32_t alloc_flags
= 0;
1995 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1996 &temp_mcs_surf
, alloc_flags
, mt
);
2002 mt
->aux_state
= aux_state
;
2004 intel_miptree_init_mcs(brw
, mt
, 0xFF);
2010 intel_miptree_alloc_ccs(struct brw_context
*brw
,
2011 struct intel_mipmap_tree
*mt
)
2013 assert(mt
->mcs_buf
== NULL
);
2014 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
2015 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2017 struct isl_surf temp_main_surf
;
2018 struct isl_surf temp_ccs_surf
;
2020 /* Create first an ISL presentation for the main color surface and let ISL
2021 * calculate equivalent CCS surface against it.
2023 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
2024 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
2028 assert(temp_ccs_surf
.size
&&
2029 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
2031 enum isl_aux_state
**aux_state
=
2032 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
2036 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
2037 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
2039 * "If Software wants to enable Color Compression without Fast clear,
2040 * Software needs to initialize MCS with zeros."
2042 * A CCS value of 0 indicates that the corresponding block is in the
2043 * pass-through state which is what we want.
2045 * For CCS_D, on the other hand, we don't care as we're about to perform a
2046 * fast-clear operation. In that case, being hot in caches more useful.
2048 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
2049 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
2050 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
2051 &temp_ccs_surf
, alloc_flags
, mt
);
2057 mt
->aux_state
= aux_state
;
2063 * Helper for intel_miptree_alloc_hiz() that sets
2064 * \c mt->level[level].has_hiz. Return true if and only if
2065 * \c has_hiz was set.
2068 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
2069 struct intel_mipmap_tree
*mt
,
2072 assert(mt
->hiz_buf
);
2073 assert(mt
->surf
.size
> 0);
2075 if (brw
->gen
>= 8 || brw
->is_haswell
) {
2076 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
2077 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
2079 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
2080 * and the height is 4 aligned. This allows our HiZ support
2081 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
2082 * we can grow the width & height to allow the HiZ op to
2083 * force the proper size alignments.
2085 if (level
> 0 && ((width
& 7) || (height
& 3))) {
2086 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
2091 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
2092 mt
->level
[level
].has_hiz
= true;
2097 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2098 struct intel_mipmap_tree
*mt
)
2100 assert(mt
->hiz_buf
== NULL
);
2101 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
2103 enum isl_aux_state
**aux_state
=
2104 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
2108 struct isl_surf temp_hiz_surf
;
2110 MAYBE_UNUSED
bool ok
=
2111 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
2114 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
2115 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
2116 &temp_hiz_surf
, alloc_flags
, mt
);
2123 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
2124 intel_miptree_level_enable_hiz(brw
, mt
, level
);
2126 mt
->aux_state
= aux_state
;
2133 * Allocate the initial aux surface for a miptree based on mt->aux_usage
2135 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
2136 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
2137 * compress clear color so we wait until an actual fast-clear to allocate it.
2140 intel_miptree_alloc_aux(struct brw_context
*brw
,
2141 struct intel_mipmap_tree
*mt
)
2143 switch (mt
->aux_usage
) {
2144 case ISL_AUX_USAGE_NONE
:
2147 case ISL_AUX_USAGE_HIZ
:
2148 assert(!_mesa_is_format_color_format(mt
->format
));
2149 if (!intel_miptree_alloc_hiz(brw
, mt
))
2153 case ISL_AUX_USAGE_MCS
:
2154 assert(_mesa_is_format_color_format(mt
->format
));
2155 assert(mt
->surf
.samples
> 1);
2156 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
2160 case ISL_AUX_USAGE_CCS_D
:
2161 /* Since CCS_D can only compress clear color so we wait until an actual
2162 * fast-clear to allocate it.
2166 case ISL_AUX_USAGE_CCS_E
:
2167 assert(_mesa_is_format_color_format(mt
->format
));
2168 assert(mt
->surf
.samples
== 1);
2169 if (!intel_miptree_alloc_ccs(brw
, mt
))
2174 unreachable("Invalid aux usage");
2179 * Can the miptree sample using the hiz buffer?
2182 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2183 struct intel_mipmap_tree
*mt
)
2185 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2186 * so keep things conservative for now and never enable it unless we're SKL+.
2196 /* It seems the hardware won't fallback to the depth buffer if some of the
2197 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2198 * of the texture to be HiZ enabled.
2200 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
2201 if (!intel_miptree_level_has_hiz(mt
, level
))
2205 /* If compressed multisampling is enabled, then we use it for the auxiliary
2208 * From the BDW PRM (Volume 2d: Command Reference: Structures
2209 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2211 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2212 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2214 * There is no such blurb for 1D textures, but there is sufficient evidence
2215 * that this is broken on SKL+.
2217 return (mt
->surf
.samples
== 1 &&
2218 mt
->target
!= GL_TEXTURE_3D
&&
2219 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2223 * Does the miptree slice have hiz enabled?
2226 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2228 intel_miptree_check_level_layer(mt
, level
, 0);
2229 return mt
->level
[level
].has_hiz
;
2233 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2234 unsigned start_level
, unsigned num_levels
,
2235 unsigned start_layer
, unsigned num_layers
)
2237 assert(_mesa_is_format_color_format(mt
->format
));
2242 /* Clamp the level range to fit the miptree */
2243 assert(start_level
+ num_levels
>= start_level
);
2244 const uint32_t last_level
=
2245 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2246 start_level
= MAX2(mt
->first_level
, start_level
);
2247 num_levels
= last_level
- start_level
+ 1;
2249 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2250 uint32_t level_layers
= mt
->surf
.size
> 0 ?
2251 get_num_phys_layers(&mt
->surf
, level
) : mt
->level
[level
].depth
;
2253 level_layers
= MIN2(num_layers
, level_layers
);
2255 for (unsigned a
= 0; a
< level_layers
; a
++) {
2256 enum isl_aux_state aux_state
=
2257 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2258 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2259 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2268 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2269 const struct intel_mipmap_tree
*mt
,
2270 unsigned level
, unsigned layer
)
2276 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2277 assert(brw
->gen
>= 8 ||
2278 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2280 /* Compression of arrayed msaa surfaces is supported. */
2281 if (mt
->surf
.samples
> 1)
2284 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2285 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2291 static enum blorp_fast_clear_op
2292 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2293 bool ccs_supported
, bool fast_clear_supported
)
2295 assert(ccs_supported
== fast_clear_supported
);
2297 switch (aux_state
) {
2298 case ISL_AUX_STATE_CLEAR
:
2299 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2301 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2303 return BLORP_FAST_CLEAR_OP_NONE
;
2305 case ISL_AUX_STATE_PASS_THROUGH
:
2306 return BLORP_FAST_CLEAR_OP_NONE
;
2308 case ISL_AUX_STATE_RESOLVED
:
2309 case ISL_AUX_STATE_AUX_INVALID
:
2310 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2314 unreachable("Invalid aux state for CCS_D");
2317 static enum blorp_fast_clear_op
2318 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2319 bool ccs_supported
, bool fast_clear_supported
)
2321 switch (aux_state
) {
2322 case ISL_AUX_STATE_CLEAR
:
2323 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2325 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2326 else if (!fast_clear_supported
)
2327 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2329 return BLORP_FAST_CLEAR_OP_NONE
;
2331 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2333 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2335 return BLORP_FAST_CLEAR_OP_NONE
;
2337 case ISL_AUX_STATE_PASS_THROUGH
:
2338 return BLORP_FAST_CLEAR_OP_NONE
;
2340 case ISL_AUX_STATE_RESOLVED
:
2341 case ISL_AUX_STATE_AUX_INVALID
:
2345 unreachable("Invalid aux state for CCS_E");
2349 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2350 struct intel_mipmap_tree
*mt
,
2351 uint32_t level
, uint32_t layer
,
2353 bool fast_clear_supported
)
2355 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2357 enum blorp_fast_clear_op resolve_op
;
2358 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2359 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2360 fast_clear_supported
);
2362 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2363 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2364 fast_clear_supported
);
2367 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2368 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2369 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2371 switch (resolve_op
) {
2372 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2373 /* The CCS full resolve operation destroys the CCS and sets it to the
2374 * pass-through state. (You can also think of this as being both a
2375 * resolve and an ambiguate in one operation.)
2377 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2378 ISL_AUX_STATE_PASS_THROUGH
);
2381 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2382 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2383 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2387 unreachable("Invalid resolve op");
2393 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2394 struct intel_mipmap_tree
*mt
,
2395 uint32_t level
, uint32_t layer
,
2396 bool written_with_ccs
)
2398 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2400 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2401 switch (aux_state
) {
2402 case ISL_AUX_STATE_CLEAR
:
2403 assert(written_with_ccs
);
2404 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2405 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2408 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2409 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2410 assert(written_with_ccs
);
2411 break; /* Nothing to do */
2413 case ISL_AUX_STATE_PASS_THROUGH
:
2414 if (written_with_ccs
) {
2415 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2416 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2422 case ISL_AUX_STATE_RESOLVED
:
2423 case ISL_AUX_STATE_AUX_INVALID
:
2424 unreachable("Invalid aux state for CCS_E");
2427 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2428 /* CCS_D is a bit simpler */
2429 switch (aux_state
) {
2430 case ISL_AUX_STATE_CLEAR
:
2431 assert(written_with_ccs
);
2432 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2433 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2436 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2437 assert(written_with_ccs
);
2438 break; /* Nothing to do */
2440 case ISL_AUX_STATE_PASS_THROUGH
:
2444 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2445 case ISL_AUX_STATE_RESOLVED
:
2446 case ISL_AUX_STATE_AUX_INVALID
:
2447 unreachable("Invalid aux state for CCS_D");
2453 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2454 struct intel_mipmap_tree
*mt
,
2455 uint32_t level
, uint32_t layer
,
2456 bool written_with_aux
)
2458 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2459 case ISL_AUX_STATE_CLEAR
:
2460 assert(written_with_aux
);
2461 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2462 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2465 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2466 assert(written_with_aux
);
2467 break; /* Nothing to do */
2469 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2470 case ISL_AUX_STATE_RESOLVED
:
2471 case ISL_AUX_STATE_PASS_THROUGH
:
2472 case ISL_AUX_STATE_AUX_INVALID
:
2473 unreachable("Invalid aux state for MCS");
2478 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2479 struct intel_mipmap_tree
*mt
,
2480 uint32_t level
, uint32_t layer
,
2481 bool hiz_supported
, bool fast_clear_supported
)
2483 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2484 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2485 case ISL_AUX_STATE_CLEAR
:
2486 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2487 if (!hiz_supported
|| !fast_clear_supported
)
2488 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2491 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2493 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2496 case ISL_AUX_STATE_PASS_THROUGH
:
2497 case ISL_AUX_STATE_RESOLVED
:
2500 case ISL_AUX_STATE_AUX_INVALID
:
2502 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2506 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2507 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2510 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2511 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2512 ISL_AUX_STATE_RESOLVED
);
2515 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2516 /* The HiZ resolve operation is actually an ambiguate */
2517 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2518 ISL_AUX_STATE_PASS_THROUGH
);
2522 unreachable("Invalid HiZ op");
2528 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2529 struct intel_mipmap_tree
*mt
,
2530 uint32_t level
, uint32_t layer
,
2531 bool written_with_hiz
)
2533 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2534 case ISL_AUX_STATE_CLEAR
:
2535 assert(written_with_hiz
);
2536 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2537 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2540 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2541 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2542 assert(written_with_hiz
);
2543 break; /* Nothing to do */
2545 case ISL_AUX_STATE_RESOLVED
:
2546 if (written_with_hiz
) {
2547 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2548 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2550 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2551 ISL_AUX_STATE_AUX_INVALID
);
2555 case ISL_AUX_STATE_PASS_THROUGH
:
2556 if (written_with_hiz
) {
2557 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2558 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2562 case ISL_AUX_STATE_AUX_INVALID
:
2563 assert(!written_with_hiz
);
2568 static inline uint32_t
2569 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2570 uint32_t start_level
, uint32_t num_levels
)
2572 assert(start_level
>= mt
->first_level
);
2573 assert(start_level
<= mt
->last_level
);
2575 if (num_levels
== INTEL_REMAINING_LAYERS
)
2576 num_levels
= mt
->last_level
- start_level
+ 1;
2577 /* Check for overflow */
2578 assert(start_level
+ num_levels
>= start_level
);
2579 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2584 static inline uint32_t
2585 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2586 uint32_t start_layer
, uint32_t num_layers
)
2588 assert(level
<= mt
->last_level
);
2589 uint32_t total_num_layers
;
2591 if (mt
->surf
.size
> 0)
2592 total_num_layers
= get_num_phys_layers(&mt
->surf
, level
);
2594 total_num_layers
= mt
->level
[level
].depth
;
2596 assert(start_layer
< total_num_layers
);
2597 if (num_layers
== INTEL_REMAINING_LAYERS
)
2598 num_layers
= total_num_layers
- start_layer
;
2599 /* Check for overflow */
2600 assert(start_layer
+ num_layers
>= start_layer
);
2601 assert(start_layer
+ num_layers
<= total_num_layers
);
2607 intel_miptree_prepare_access(struct brw_context
*brw
,
2608 struct intel_mipmap_tree
*mt
,
2609 uint32_t start_level
, uint32_t num_levels
,
2610 uint32_t start_layer
, uint32_t num_layers
,
2611 bool aux_supported
, bool fast_clear_supported
)
2613 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2615 if (_mesa_is_format_color_format(mt
->format
)) {
2619 if (mt
->surf
.samples
> 1) {
2620 /* Nothing to do for MSAA */
2621 assert(aux_supported
&& fast_clear_supported
);
2623 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2624 const uint32_t level
= start_level
+ l
;
2625 const uint32_t level_layers
=
2626 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2627 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2628 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2629 start_layer
+ a
, aux_supported
,
2630 fast_clear_supported
);
2634 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2635 /* Nothing to do for stencil */
2640 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2641 const uint32_t level
= start_level
+ l
;
2642 if (!intel_miptree_level_has_hiz(mt
, level
))
2645 const uint32_t level_layers
=
2646 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2647 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2648 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2650 fast_clear_supported
);
2657 intel_miptree_finish_write(struct brw_context
*brw
,
2658 struct intel_mipmap_tree
*mt
, uint32_t level
,
2659 uint32_t start_layer
, uint32_t num_layers
,
2660 bool written_with_aux
)
2662 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2664 if (_mesa_is_format_color_format(mt
->format
)) {
2668 if (mt
->surf
.samples
> 1) {
2669 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2670 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2674 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2675 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2679 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2680 /* Nothing to do for stencil */
2682 if (!intel_miptree_level_has_hiz(mt
, level
))
2685 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2686 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2693 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2694 uint32_t level
, uint32_t layer
)
2696 intel_miptree_check_level_layer(mt
, level
, layer
);
2698 if (_mesa_is_format_color_format(mt
->format
)) {
2699 assert(mt
->mcs_buf
!= NULL
);
2700 assert(mt
->surf
.samples
== 1 ||
2701 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2702 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2703 unreachable("Cannot get aux state for stencil");
2705 assert(intel_miptree_level_has_hiz(mt
, level
));
2708 return mt
->aux_state
[level
][layer
];
2712 intel_miptree_set_aux_state(struct brw_context
*brw
,
2713 struct intel_mipmap_tree
*mt
, uint32_t level
,
2714 uint32_t start_layer
, uint32_t num_layers
,
2715 enum isl_aux_state aux_state
)
2717 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2719 if (_mesa_is_format_color_format(mt
->format
)) {
2720 assert(mt
->mcs_buf
!= NULL
);
2721 assert(mt
->surf
.samples
== 1 ||
2722 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2723 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2724 unreachable("Cannot get aux state for stencil");
2726 assert(intel_miptree_level_has_hiz(mt
, level
));
2729 for (unsigned a
= 0; a
< num_layers
; a
++)
2730 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2733 /* On Gen9 color buffers may be compressed by the hardware (lossless
2734 * compression). There are, however, format restrictions and care needs to be
2735 * taken that the sampler engine is capable for re-interpreting a buffer with
2736 * format different the buffer was originally written with.
2738 * For example, SRGB formats are not compressible and the sampler engine isn't
2739 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2740 * color buffer needs to be resolved so that the sampling surface can be
2741 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2745 can_texture_with_ccs(struct brw_context
*brw
,
2746 struct intel_mipmap_tree
*mt
,
2747 mesa_format view_format
)
2749 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2752 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2753 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2755 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2756 isl_mt_format
, isl_view_format
)) {
2757 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2758 _mesa_get_format_name(view_format
),
2759 _mesa_get_format_name(mt
->format
));
2767 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2768 struct intel_mipmap_tree
*mt
,
2769 mesa_format view_format
,
2770 uint32_t start_level
, uint32_t num_levels
,
2771 uint32_t start_layer
, uint32_t num_layers
,
2772 bool *aux_supported_out
)
2774 bool aux_supported
, clear_supported
;
2775 if (_mesa_is_format_color_format(mt
->format
)) {
2776 if (mt
->surf
.samples
> 1) {
2777 aux_supported
= clear_supported
= true;
2779 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2781 /* Clear color is specified as ints or floats and the conversion is
2782 * done by the sampler. If we have a texture view, we would have to
2783 * perform the clear color conversion manually. Just disable clear
2786 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2788 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2789 aux_supported
= clear_supported
= false;
2791 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2794 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2795 start_layer
, num_layers
,
2796 aux_supported
, clear_supported
);
2797 if (aux_supported_out
)
2798 *aux_supported_out
= aux_supported
;
2802 intel_miptree_prepare_texture(struct brw_context
*brw
,
2803 struct intel_mipmap_tree
*mt
,
2804 mesa_format view_format
,
2805 bool *aux_supported_out
)
2807 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2808 0, INTEL_REMAINING_LEVELS
,
2809 0, INTEL_REMAINING_LAYERS
,
2814 intel_miptree_prepare_image(struct brw_context
*brw
,
2815 struct intel_mipmap_tree
*mt
)
2817 /* The data port doesn't understand any compression */
2818 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2819 0, INTEL_REMAINING_LAYERS
, false, false);
2823 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2824 struct intel_mipmap_tree
*mt
, uint32_t level
,
2825 uint32_t start_layer
, uint32_t num_layers
)
2827 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2828 start_layer
, num_layers
, NULL
);
2832 intel_miptree_prepare_render(struct brw_context
*brw
,
2833 struct intel_mipmap_tree
*mt
, uint32_t level
,
2834 uint32_t start_layer
, uint32_t layer_count
,
2837 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2838 * the single-sampled color renderbuffers because the CCS buffer isn't
2839 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2840 * enabled because otherwise the surface state will be programmed with
2841 * the linear equivalent format anyway.
2843 if (brw
->gen
== 9 && srgb_enabled
&& mt
->surf
.samples
== 1 &&
2844 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2846 /* Lossless compression is not supported for SRGB formats, it
2847 * should be impossible to get here with such surfaces.
2849 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2850 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2856 intel_miptree_finish_render(struct brw_context
*brw
,
2857 struct intel_mipmap_tree
*mt
, uint32_t level
,
2858 uint32_t start_layer
, uint32_t layer_count
)
2860 assert(_mesa_is_format_color_format(mt
->format
));
2861 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2862 mt
->mcs_buf
!= NULL
);
2866 intel_miptree_prepare_depth(struct brw_context
*brw
,
2867 struct intel_mipmap_tree
*mt
, uint32_t level
,
2868 uint32_t start_layer
, uint32_t layer_count
)
2870 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2871 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2875 intel_miptree_finish_depth(struct brw_context
*brw
,
2876 struct intel_mipmap_tree
*mt
, uint32_t level
,
2877 uint32_t start_layer
, uint32_t layer_count
,
2880 if (depth_written
) {
2881 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2882 mt
->hiz_buf
!= NULL
);
2887 * Make it possible to share the BO backing the given miptree with another
2888 * process or another miptree.
2890 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2891 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2892 * ensure that no MCS buffer gets allocated in the future.
2894 * HiZ is similarly unsafe with shared buffers.
2897 intel_miptree_make_shareable(struct brw_context
*brw
,
2898 struct intel_mipmap_tree
*mt
)
2900 /* MCS buffers are also used for multisample buffers, but we can't resolve
2901 * away a multisample MCS buffer because it's an integral part of how the
2902 * pixel data is stored. Fortunately this code path should never be
2903 * reached for multisample buffers.
2905 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2906 mt
->surf
.samples
== 1);
2908 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2909 0, INTEL_REMAINING_LAYERS
, false, false);
2912 brw_bo_unreference(mt
->mcs_buf
->bo
);
2916 /* Any pending MCS/CCS operations are no longer needed. Trying to
2917 * execute any will likely crash due to the missing aux buffer. So let's
2918 * delete all pending ops.
2920 free(mt
->aux_state
);
2921 mt
->aux_state
= NULL
;
2925 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2928 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2929 mt
->level
[l
].has_hiz
= false;
2932 /* Any pending HiZ operations are no longer needed. Trying to execute
2933 * any will likely crash due to the missing aux buffer. So let's delete
2936 free(mt
->aux_state
);
2937 mt
->aux_state
= NULL
;
2940 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2945 * \brief Get pointer offset into stencil buffer.
2947 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2948 * must decode the tile's layout in software.
2951 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2953 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2955 * Even though the returned offset is always positive, the return type is
2957 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2958 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2961 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2963 uint32_t tile_size
= 4096;
2964 uint32_t tile_width
= 64;
2965 uint32_t tile_height
= 64;
2966 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2968 uint32_t tile_x
= x
/ tile_width
;
2969 uint32_t tile_y
= y
/ tile_height
;
2971 /* The byte's address relative to the tile's base addres. */
2972 uint32_t byte_x
= x
% tile_width
;
2973 uint32_t byte_y
= y
% tile_height
;
2975 uintptr_t u
= tile_y
* row_size
2976 + tile_x
* tile_size
2977 + 512 * (byte_x
/ 8)
2979 + 32 * ((byte_y
/ 4) % 2)
2980 + 16 * ((byte_x
/ 4) % 2)
2981 + 8 * ((byte_y
/ 2) % 2)
2982 + 4 * ((byte_x
/ 2) % 2)
2987 /* adjust for bit6 swizzling */
2988 if (((byte_x
/ 8) % 2) == 1) {
2989 if (((byte_y
/ 8) % 2) == 0) {
3001 intel_miptree_updownsample(struct brw_context
*brw
,
3002 struct intel_mipmap_tree
*src
,
3003 struct intel_mipmap_tree
*dst
)
3005 unsigned src_w
, src_h
, dst_w
, dst_h
;
3007 if (src
->surf
.size
> 0) {
3008 src_w
= src
->surf
.logical_level0_px
.width
;
3009 src_h
= src
->surf
.logical_level0_px
.height
;
3011 src_w
= src
->logical_width0
;
3012 src_h
= src
->logical_height0
;
3015 if (dst
->surf
.size
> 0) {
3016 dst_w
= dst
->surf
.logical_level0_px
.width
;
3017 dst_h
= dst
->surf
.logical_level0_px
.height
;
3019 dst_w
= dst
->logical_width0
;
3020 dst_h
= dst
->logical_height0
;
3023 brw_blorp_blit_miptrees(brw
,
3024 src
, 0 /* level */, 0 /* layer */,
3025 src
->format
, SWIZZLE_XYZW
,
3026 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
3029 GL_NEAREST
, false, false /*mirror x, y*/,
3032 if (src
->stencil_mt
) {
3033 if (src
->stencil_mt
->surf
.size
> 0) {
3034 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
3035 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
3037 src_w
= src
->stencil_mt
->logical_width0
;
3038 src_h
= src
->stencil_mt
->logical_height0
;
3041 if (dst
->stencil_mt
->surf
.size
> 0) {
3042 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
3043 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
3045 dst_w
= dst
->stencil_mt
->logical_width0
;
3046 dst_h
= dst
->stencil_mt
->logical_height0
;
3049 brw_blorp_blit_miptrees(brw
,
3050 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
3051 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
3052 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
3053 dst
->stencil_mt
->format
,
3056 GL_NEAREST
, false, false /*mirror x, y*/,
3057 false, false /* decode/encode srgb */);
3062 intel_update_r8stencil(struct brw_context
*brw
,
3063 struct intel_mipmap_tree
*mt
)
3065 assert(brw
->gen
>= 7);
3066 struct intel_mipmap_tree
*src
=
3067 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3068 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
3071 assert(src
->surf
.size
> 0);
3073 if (!mt
->r8stencil_mt
) {
3074 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3075 mt
->r8stencil_mt
= make_surface(
3078 MESA_FORMAT_R_UINT8
,
3079 src
->first_level
, src
->last_level
,
3080 src
->surf
.logical_level0_px
.width
,
3081 src
->surf
.logical_level0_px
.height
,
3082 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3083 src
->surf
.logical_level0_px
.depth
:
3084 src
->surf
.logical_level0_px
.array_len
,
3087 ISL_SURF_USAGE_TEXTURE_BIT
,
3088 BO_ALLOC_FOR_RENDER
, 0, NULL
);
3089 assert(mt
->r8stencil_mt
);
3092 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3094 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3095 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3096 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3097 src
->surf
.phys_level0_sa
.array_len
;
3099 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3100 brw_blorp_copy_miptrees(brw
,
3104 minify(src
->surf
.logical_level0_px
.width
,
3106 minify(src
->surf
.logical_level0_px
.height
,
3111 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3112 src
->r8stencil_needs_update
= false;
3116 intel_miptree_map_raw(struct brw_context
*brw
,
3117 struct intel_mipmap_tree
*mt
,
3120 struct brw_bo
*bo
= mt
->bo
;
3122 if (brw_batch_references(&brw
->batch
, bo
))
3123 intel_batchbuffer_flush(brw
);
3125 return brw_bo_map(brw
, bo
, mode
);
3129 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3131 brw_bo_unmap(mt
->bo
);
3135 intel_miptree_map_gtt(struct brw_context
*brw
,
3136 struct intel_mipmap_tree
*mt
,
3137 struct intel_miptree_map
*map
,
3138 unsigned int level
, unsigned int slice
)
3140 unsigned int bw
, bh
;
3142 unsigned int image_x
, image_y
;
3143 intptr_t x
= map
->x
;
3144 intptr_t y
= map
->y
;
3146 /* For compressed formats, the stride is the number of bytes per
3147 * row of blocks. intel_miptree_get_image_offset() already does
3150 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3151 assert(y
% bh
== 0);
3152 assert(x
% bw
== 0);
3156 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3163 /* Note that in the case of cube maps, the caller must have passed the
3164 * slice number referencing the face.
3166 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3170 map
->stride
= mt
->surf
.row_pitch
;
3171 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3174 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3175 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3176 map
->x
, map
->y
, map
->w
, map
->h
,
3177 mt
, _mesa_get_format_name(mt
->format
),
3178 x
, y
, map
->ptr
, map
->stride
);
3182 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3184 intel_miptree_unmap_raw(mt
);
3188 intel_miptree_map_blit(struct brw_context
*brw
,
3189 struct intel_mipmap_tree
*mt
,
3190 struct intel_miptree_map
*map
,
3191 unsigned int level
, unsigned int slice
)
3193 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3194 /* first_level */ 0,
3198 MIPTREE_LAYOUT_TILING_NONE
);
3200 if (!map
->linear_mt
) {
3201 fprintf(stderr
, "Failed to allocate blit temporary\n");
3204 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3206 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3207 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3208 * invalidate is set, since we'll be writing the whole rectangle from our
3209 * temporary buffer back out.
3211 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3212 if (!intel_miptree_copy(brw
,
3213 mt
, level
, slice
, map
->x
, map
->y
,
3214 map
->linear_mt
, 0, 0, 0, 0,
3216 fprintf(stderr
, "Failed to blit\n");
3221 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3223 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3224 map
->x
, map
->y
, map
->w
, map
->h
,
3225 mt
, _mesa_get_format_name(mt
->format
),
3226 level
, slice
, map
->ptr
, map
->stride
);
3231 intel_miptree_release(&map
->linear_mt
);
3237 intel_miptree_unmap_blit(struct brw_context
*brw
,
3238 struct intel_mipmap_tree
*mt
,
3239 struct intel_miptree_map
*map
,
3243 struct gl_context
*ctx
= &brw
->ctx
;
3245 intel_miptree_unmap_raw(map
->linear_mt
);
3247 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3248 bool ok
= intel_miptree_copy(brw
,
3249 map
->linear_mt
, 0, 0, 0, 0,
3250 mt
, level
, slice
, map
->x
, map
->y
,
3252 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3255 intel_miptree_release(&map
->linear_mt
);
3259 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3261 #if defined(USE_SSE41)
3263 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3264 struct intel_mipmap_tree
*mt
,
3265 struct intel_miptree_map
*map
,
3266 unsigned int level
, unsigned int slice
)
3268 assert(map
->mode
& GL_MAP_READ_BIT
);
3269 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3271 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3272 map
->x
, map
->y
, map
->w
, map
->h
,
3273 mt
, _mesa_get_format_name(mt
->format
),
3274 level
, slice
, map
->ptr
, map
->stride
);
3276 /* Map the original image */
3279 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3283 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3289 src
+= image_y
* mt
->surf
.row_pitch
;
3290 src
+= image_x
* mt
->cpp
;
3292 /* Due to the pixel offsets for the particular image being mapped, our
3293 * src pointer may not be 16-byte aligned. However, if the pitch is
3294 * divisible by 16, then the amount by which it's misaligned will remain
3295 * consistent from row to row.
3297 assert((mt
->surf
.row_pitch
% 16) == 0);
3298 const int misalignment
= ((uintptr_t) src
) & 15;
3300 /* Create an untiled temporary buffer for the mapping. */
3301 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3303 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3305 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3306 /* Offset the destination so it has the same misalignment as src. */
3307 map
->ptr
= map
->buffer
+ misalignment
;
3309 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3311 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3312 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3313 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3315 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3318 intel_miptree_unmap_raw(mt
);
3322 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3323 struct intel_mipmap_tree
*mt
,
3324 struct intel_miptree_map
*map
,
3328 _mesa_align_free(map
->buffer
);
3335 intel_miptree_map_s8(struct brw_context
*brw
,
3336 struct intel_mipmap_tree
*mt
,
3337 struct intel_miptree_map
*map
,
3338 unsigned int level
, unsigned int slice
)
3340 map
->stride
= map
->w
;
3341 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3345 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3346 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3347 * invalidate is set, since we'll be writing the whole rectangle from our
3348 * temporary buffer back out.
3350 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3351 uint8_t *untiled_s8_map
= map
->ptr
;
3352 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3353 unsigned int image_x
, image_y
;
3355 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3357 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3358 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3359 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3360 x
+ image_x
+ map
->x
,
3361 y
+ image_y
+ map
->y
,
3362 brw
->has_swizzling
);
3363 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3367 intel_miptree_unmap_raw(mt
);
3369 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3370 map
->x
, map
->y
, map
->w
, map
->h
,
3371 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3373 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3374 map
->x
, map
->y
, map
->w
, map
->h
,
3375 mt
, map
->ptr
, map
->stride
);
3380 intel_miptree_unmap_s8(struct brw_context
*brw
,
3381 struct intel_mipmap_tree
*mt
,
3382 struct intel_miptree_map
*map
,
3386 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3387 unsigned int image_x
, image_y
;
3388 uint8_t *untiled_s8_map
= map
->ptr
;
3389 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3391 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3393 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3394 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3395 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3396 image_x
+ x
+ map
->x
,
3397 image_y
+ y
+ map
->y
,
3398 brw
->has_swizzling
);
3399 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3403 intel_miptree_unmap_raw(mt
);
3410 intel_miptree_map_etc(struct brw_context
*brw
,
3411 struct intel_mipmap_tree
*mt
,
3412 struct intel_miptree_map
*map
,
3416 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3417 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3418 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3421 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3422 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3424 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3425 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3426 map
->w
, map
->h
, 1));
3427 map
->ptr
= map
->buffer
;
3431 intel_miptree_unmap_etc(struct brw_context
*brw
,
3432 struct intel_mipmap_tree
*mt
,
3433 struct intel_miptree_map
*map
,
3439 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3444 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3445 + image_y
* mt
->surf
.row_pitch
3446 + image_x
* mt
->cpp
;
3448 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3449 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3450 map
->ptr
, map
->stride
,
3453 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3454 map
->ptr
, map
->stride
,
3455 map
->w
, map
->h
, mt
->etc_format
);
3457 intel_miptree_unmap_raw(mt
);
3462 * Mapping function for packed depth/stencil miptrees backed by real separate
3463 * miptrees for depth and stencil.
3465 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3466 * separate from the depth buffer. Yet at the GL API level, we have to expose
3467 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3468 * be able to map that memory for texture storage and glReadPixels-type
3469 * operations. We give Mesa core that access by mallocing a temporary and
3470 * copying the data between the actual backing store and the temporary.
3473 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3474 struct intel_mipmap_tree
*mt
,
3475 struct intel_miptree_map
*map
,
3476 unsigned int level
, unsigned int slice
)
3478 struct intel_mipmap_tree
*z_mt
= mt
;
3479 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3480 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3481 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3483 map
->stride
= map
->w
* packed_bpp
;
3484 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3488 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3489 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3490 * invalidate is set, since we'll be writing the whole rectangle from our
3491 * temporary buffer back out.
3493 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3494 uint32_t *packed_map
= map
->ptr
;
3495 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3496 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3497 unsigned int s_image_x
, s_image_y
;
3498 unsigned int z_image_x
, z_image_y
;
3500 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3501 &s_image_x
, &s_image_y
);
3502 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3503 &z_image_x
, &z_image_y
);
3505 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3506 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3507 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3508 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3511 brw
->has_swizzling
);
3512 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3513 (z_mt
->surf
.row_pitch
/ 4) +
3514 (map_x
+ z_image_x
));
3515 uint8_t s
= s_map
[s_offset
];
3516 uint32_t z
= z_map
[z_offset
];
3518 if (map_z32f_x24s8
) {
3519 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3520 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3522 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3527 intel_miptree_unmap_raw(s_mt
);
3528 intel_miptree_unmap_raw(z_mt
);
3530 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3532 map
->x
, map
->y
, map
->w
, map
->h
,
3533 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3534 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3535 map
->ptr
, map
->stride
);
3537 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3538 map
->x
, map
->y
, map
->w
, map
->h
,
3539 mt
, map
->ptr
, map
->stride
);
3544 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3545 struct intel_mipmap_tree
*mt
,
3546 struct intel_miptree_map
*map
,
3550 struct intel_mipmap_tree
*z_mt
= mt
;
3551 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3552 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3554 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3555 uint32_t *packed_map
= map
->ptr
;
3556 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3557 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3558 unsigned int s_image_x
, s_image_y
;
3559 unsigned int z_image_x
, z_image_y
;
3561 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3562 &s_image_x
, &s_image_y
);
3563 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3564 &z_image_x
, &z_image_y
);
3566 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3567 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3568 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3569 x
+ s_image_x
+ map
->x
,
3570 y
+ s_image_y
+ map
->y
,
3571 brw
->has_swizzling
);
3572 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3573 (z_mt
->surf
.row_pitch
/ 4) +
3574 (x
+ z_image_x
+ map
->x
));
3576 if (map_z32f_x24s8
) {
3577 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3578 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3580 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3581 s_map
[s_offset
] = packed
>> 24;
3582 z_map
[z_offset
] = packed
;
3587 intel_miptree_unmap_raw(s_mt
);
3588 intel_miptree_unmap_raw(z_mt
);
3590 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3592 map
->x
, map
->y
, map
->w
, map
->h
,
3593 z_mt
, _mesa_get_format_name(z_mt
->format
),
3594 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3595 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3596 map
->ptr
, map
->stride
);
3603 * Create and attach a map to the miptree at (level, slice). Return the
3606 static struct intel_miptree_map
*
3607 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3616 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3621 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3622 mt
->level
[level
].slice
[slice
].map
= map
;
3634 * Release the map at (level, slice).
3637 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3641 struct intel_miptree_map
**map
;
3643 map
= &mt
->level
[level
].slice
[slice
].map
;
3649 can_blit_slice(struct intel_mipmap_tree
*mt
,
3650 unsigned int level
, unsigned int slice
)
3652 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3653 if (mt
->surf
.row_pitch
>= 32768)
3660 use_intel_mipree_map_blit(struct brw_context
*brw
,
3661 struct intel_mipmap_tree
*mt
,
3667 /* It's probably not worth swapping to the blit ring because of
3668 * all the overhead involved.
3670 !(mode
& GL_MAP_WRITE_BIT
) &&
3672 (mt
->surf
.tiling
== ISL_TILING_X
||
3673 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3674 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3675 /* Fast copy blit on skl+ supports all tiling formats. */
3677 can_blit_slice(mt
, level
, slice
))
3680 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3681 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3682 assert(can_blit_slice(mt
, level
, slice
));
3690 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3691 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3692 * arithmetic overflow.
3694 * If you call this function and use \a out_stride, then you're doing pointer
3695 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3696 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3697 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3698 * which usually have type uint32_t or GLuint.
3701 intel_miptree_map(struct brw_context
*brw
,
3702 struct intel_mipmap_tree
*mt
,
3711 ptrdiff_t *out_stride
)
3713 struct intel_miptree_map
*map
;
3715 assert(mt
->surf
.samples
== 1);
3717 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3724 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3725 map
->mode
& GL_MAP_WRITE_BIT
);
3727 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3728 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3729 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3730 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3731 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3732 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3733 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3734 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3735 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3736 #if defined(USE_SSE41)
3737 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3738 !mt
->compressed
&& cpu_has_sse4_1
&&
3739 (mt
->surf
.row_pitch
% 16 == 0)) {
3740 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3743 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3746 *out_ptr
= map
->ptr
;
3747 *out_stride
= map
->stride
;
3749 if (map
->ptr
== NULL
)
3750 intel_miptree_release_map(mt
, level
, slice
);
3754 intel_miptree_unmap(struct brw_context
*brw
,
3755 struct intel_mipmap_tree
*mt
,
3759 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3761 assert(mt
->surf
.samples
== 1);
3766 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3767 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3769 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3770 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3771 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3772 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3773 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3774 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3775 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3776 } else if (map
->linear_mt
) {
3777 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3778 #if defined(USE_SSE41)
3779 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3780 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3783 intel_miptree_unmap_gtt(mt
);
3786 intel_miptree_release_map(mt
, level
, slice
);
3790 get_isl_surf_dim(GLenum target
)
3794 case GL_TEXTURE_1D_ARRAY
:
3795 return ISL_SURF_DIM_1D
;
3798 case GL_TEXTURE_2D_ARRAY
:
3799 case GL_TEXTURE_RECTANGLE
:
3800 case GL_TEXTURE_CUBE_MAP
:
3801 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3802 case GL_TEXTURE_2D_MULTISAMPLE
:
3803 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3804 case GL_TEXTURE_EXTERNAL_OES
:
3805 return ISL_SURF_DIM_2D
;
3808 return ISL_SURF_DIM_3D
;
3811 unreachable("Invalid texture target");
3815 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3816 enum isl_tiling tiling
, GLenum target
,
3817 enum miptree_array_layout array_layout
)
3819 if (array_layout
== GEN6_HIZ_STENCIL
)
3820 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3824 case GL_TEXTURE_1D_ARRAY
:
3825 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3826 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3829 case GL_TEXTURE_2D_ARRAY
:
3830 case GL_TEXTURE_RECTANGLE
:
3831 case GL_TEXTURE_2D_MULTISAMPLE
:
3832 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3833 case GL_TEXTURE_EXTERNAL_OES
:
3834 return ISL_DIM_LAYOUT_GEN4_2D
;
3836 case GL_TEXTURE_CUBE_MAP
:
3837 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3838 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3839 ISL_DIM_LAYOUT_GEN4_2D
);
3842 return (devinfo
->gen
>= 9 ?
3843 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3846 unreachable("Invalid texture target");
3850 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3852 if (mt
->format
== MESA_FORMAT_S_UINT8
)
3853 return ISL_TILING_W
;
3854 return mt
->surf
.tiling
;
3858 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3859 const struct intel_mipmap_tree
*mt
,
3860 struct isl_surf
*surf
)
3862 surf
->dim
= get_isl_surf_dim(mt
->target
);
3863 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3864 mt
->surf
.tiling
, mt
->target
,
3866 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3867 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3868 surf
->row_pitch
= mt
->surf
.row_pitch
;
3869 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3871 if (brw
->gen
>= 9) {
3872 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3873 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3874 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3876 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3877 * alignment in terms of surface elements like we want.
3879 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3882 /* On earlier gens it's stored in pixels. */
3884 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3885 surf
->image_alignment_el
=
3886 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3889 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3890 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3891 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3892 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3893 surf
->logical_level0_px
.array_len
= 1;
3895 surf
->logical_level0_px
.depth
= 1;
3896 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3899 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3900 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3901 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3902 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3903 surf
->phys_level0_sa
.array_len
= 1;
3905 surf
->phys_level0_sa
.depth
= 1;
3906 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3909 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3910 surf
->samples
= mt
->surf
.samples
;
3912 surf
->size
= 0; /* TODO */
3913 surf
->alignment
= 0; /* TODO */
3915 switch (surf
->dim_layout
) {
3916 case ISL_DIM_LAYOUT_GEN4_2D
:
3917 case ISL_DIM_LAYOUT_GEN4_3D
:
3918 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3919 if (brw
->gen
>= 9) {
3920 surf
->array_pitch_el_rows
= mt
->qpitch
;
3923 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3924 assert(mt
->qpitch
% bh
== 0);
3925 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3928 case ISL_DIM_LAYOUT_GEN9_1D
:
3929 surf
->array_pitch_el_rows
= 1;
3933 switch (mt
->array_layout
) {
3934 case ALL_LOD_IN_EACH_SLICE
:
3935 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3937 case ALL_SLICES_AT_EACH_LOD
:
3938 case GEN6_HIZ_STENCIL
:
3939 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3942 unreachable("Invalid array layout");
3945 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3946 switch (base_format
) {
3947 case GL_DEPTH_COMPONENT
:
3948 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3950 case GL_STENCIL_INDEX
:
3951 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3953 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3955 case GL_DEPTH_STENCIL
:
3956 /* In this case we only texture from the depth part */
3957 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3958 ISL_SURF_USAGE_TEXTURE_BIT
;
3961 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3962 if (brw
->mesa_format_supports_render
[mt
->format
])
3963 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3967 if (_mesa_is_cube_map_texture(mt
->target
))
3968 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3972 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3973 const struct intel_mipmap_tree
*mt
)
3976 return ISL_AUX_USAGE_HIZ
;
3979 return ISL_AUX_USAGE_NONE
;
3981 return mt
->aux_usage
;