2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
107 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
108 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
110 * - Support is limited to tiled render targets.
112 * Gen9 changes the restriction to Y-tile only.
115 return tiling
== I915_TILING_Y
;
116 else if (brw
->gen
>= 7)
117 return tiling
!= I915_TILING_NONE
;
123 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
124 * can be used. This doesn't (and should not) inspect any of the properties of
127 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
128 * beneath the "Fast Color Clear" bullet (p326):
130 * - Support is for non-mip-mapped and non-array surface types only.
132 * And then later, on p327:
134 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
137 * From the Skylake documentation, it is made clear that X-tiling is no longer
140 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
144 intel_miptree_supports_ccs(struct brw_context
*brw
,
145 const struct intel_mipmap_tree
*mt
)
147 /* MCS support does not exist prior to Gen7 */
151 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
154 /* This function applies only to non-multisampled render targets. */
155 if (mt
->num_samples
> 1)
158 /* MCS is only supported for color buffers */
159 switch (_mesa_get_format_base_format(mt
->format
)) {
160 case GL_DEPTH_COMPONENT
:
161 case GL_DEPTH_STENCIL
:
162 case GL_STENCIL_INDEX
:
166 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
169 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
170 const bool arrayed
= mt
->physical_depth0
!= 1;
173 /* Multisample surfaces with the CMS layout are not layered surfaces,
174 * yet still have physical_depth0 > 1. Assert that we don't
175 * accidentally reject a multisampled surface here. We should have
176 * rejected it earlier by explicitly checking the sample count.
178 assert(mt
->num_samples
<= 1);
181 /* Handle the hardware restrictions...
183 * All GENs have the following restriction: "MCS buffer for non-MSRT is
184 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
186 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
187 * Non-MultiSampler Render Target Restrictions) Support is for
188 * non-mip-mapped and non-array surface types only.
190 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
195 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
200 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
203 /* There's no point in using an MCS buffer if the surface isn't in a
206 if (!brw
->mesa_format_supports_render
[mt
->format
])
210 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
211 const enum isl_format isl_format
=
212 brw_isl_format_for_mesa_format(linear_format
);
213 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
218 /* On Gen9 support for color buffer compression was extended to single
219 * sampled surfaces. This is a helper considering both auxiliary buffer
220 * type and number of samples telling if the given miptree represents
221 * the new single sampled case - also called lossless compression.
224 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
225 const struct intel_mipmap_tree
*mt
)
227 /* Only available from Gen9 onwards. */
231 /* Compression always requires auxiliary buffer. */
235 /* Single sample compression is represented re-using msaa compression
236 * layout type: "Compressed Multisampled Surfaces".
238 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
241 /* And finally distinguish between msaa and single sample case. */
242 return mt
->num_samples
<= 1;
246 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
249 /* For now compression is only enabled for integer formats even though
250 * there exist supported floating point formats also. This is a heuristic
251 * decision based on current public benchmarks. In none of the cases these
252 * formats provided any improvement but a few cases were seen to regress.
253 * Hence these are left to to be enabled in the future when they are known
256 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
259 if (!intel_miptree_supports_ccs(brw
, mt
))
262 /* Fast clear can be also used to clear srgb surfaces by using equivalent
263 * linear format. This trick, however, can't be extended to be used with
264 * lossless compression and therefore a check is needed to see if the format
267 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
271 * Determine depth format corresponding to a depth+stencil format,
272 * for separate stencil.
275 intel_depth_format_for_depthstencil_format(mesa_format format
) {
277 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
278 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
279 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
280 return MESA_FORMAT_Z_FLOAT32
;
287 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
288 unsigned depth0
, struct intel_mipmap_level
*table
)
290 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
292 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
294 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
295 if (!table
[level
].slice
)
302 for (unsigned level
= first_level
; level
<= last_level
; level
++)
303 free(table
[level
].slice
);
309 * @param for_bo Indicates that the caller is
310 * intel_miptree_create_for_bo(). If true, then do not create
313 static struct intel_mipmap_tree
*
314 intel_miptree_create_layout(struct brw_context
*brw
,
323 uint32_t layout_flags
)
325 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
329 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
330 _mesa_enum_to_string(target
),
331 _mesa_get_format_name(format
),
332 first_level
, last_level
, depth0
, mt
);
334 if (target
== GL_TEXTURE_1D_ARRAY
)
335 assert(height0
== 1);
339 mt
->first_level
= first_level
;
340 mt
->last_level
= last_level
;
341 mt
->logical_width0
= width0
;
342 mt
->logical_height0
= height0
;
343 mt
->logical_depth0
= depth0
;
344 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
345 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
346 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
347 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
348 mt
->aux_state
= NULL
;
349 mt
->cpp
= _mesa_get_format_bytes(format
);
350 mt
->num_samples
= num_samples
;
351 mt
->compressed
= _mesa_is_format_compressed(format
);
352 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
355 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
356 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
358 int depth_multiply
= 1;
359 if (num_samples
> 1) {
360 /* Adjust width/height/depth for MSAA */
361 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
362 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
363 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
364 * "If the surface is multisampled and it is a depth or stencil
365 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
366 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
369 * +----------------------------------------------------------------+
370 * | Num Multisamples | W_l = | H_l = |
371 * +----------------------------------------------------------------+
372 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
373 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
374 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
375 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
376 * +----------------------------------------------------------------+
379 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
380 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
381 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
383 * Another more complicated explanation for these adjustments comes
384 * from the Sandybridge PRM, volume 4, part 1, page 31:
386 * "Any of the other messages (sample*, LOD, load4) used with a
387 * (4x) multisampled surface will in-effect sample a surface with
388 * double the height and width as that indicated in the surface
389 * state. Each pixel position on the original-sized surface is
390 * replaced with a 2x2 of samples with the following arrangement:
395 * Thus, when sampling from a multisampled texture, it behaves as
396 * though the layout in memory for (x,y,sample) is:
398 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
399 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
401 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
402 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
404 * However, the actual layout of multisampled data in memory is:
406 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
407 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
409 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
410 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
412 * This pattern repeats for each 2x2 pixel block.
414 * As a result, when calculating the size of our 4-sample buffer for
415 * an odd width or height, we have to align before scaling up because
416 * sample 3 is in that bottom right 2x2 block.
418 switch (num_samples
) {
420 assert(brw
->gen
>= 8);
421 width0
= ALIGN(width0
, 2) * 2;
422 height0
= ALIGN(height0
, 2);
425 width0
= ALIGN(width0
, 2) * 2;
426 height0
= ALIGN(height0
, 2) * 2;
429 width0
= ALIGN(width0
, 2) * 4;
430 height0
= ALIGN(height0
, 2) * 2;
433 width0
= ALIGN(width0
, 2) * 4;
434 height0
= ALIGN(height0
, 2) * 4;
437 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
440 unreachable("not reached");
443 /* Non-interleaved */
444 depth_multiply
= num_samples
;
445 depth0
*= depth_multiply
;
449 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
455 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
456 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
457 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
458 * used on Gen8 to make it pick a qpitch value which doesn't include space
459 * for the mipmaps. On Gen9 this is not necessary because it will
460 * automatically pick a packed qpitch value whenever mt->first_level ==
462 * TODO: can we use it elsewhere?
463 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
466 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
468 switch (mt
->msaa_layout
) {
469 case INTEL_MSAA_LAYOUT_NONE
:
470 case INTEL_MSAA_LAYOUT_IMS
:
471 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
473 case INTEL_MSAA_LAYOUT_UMS
:
474 case INTEL_MSAA_LAYOUT_CMS
:
475 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
480 if (target
== GL_TEXTURE_CUBE_MAP
)
481 assert(depth0
== 6 * depth_multiply
);
483 mt
->physical_width0
= width0
;
484 mt
->physical_height0
= height0
;
485 mt
->physical_depth0
= depth0
;
487 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
488 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
489 (brw
->must_use_separate_stencil
||
490 (brw
->has_separate_stencil
&&
491 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
492 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
494 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
497 mt
->stencil_mt
= intel_miptree_create(brw
,
508 if (!mt
->stencil_mt
) {
509 intel_miptree_release(&mt
);
512 mt
->stencil_mt
->r8stencil_needs_update
= true;
514 /* Fix up the Z miptree format for how we're splitting out separate
515 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
517 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
520 if (format
== mt
->format
) {
521 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
522 _mesa_get_format_name(mt
->format
));
526 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
527 mt
->array_layout
= GEN6_HIZ_STENCIL
;
530 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
531 * multisampled or have an AUX buffer attached to it.
533 * GEN | MSRT | AUX_CCS_* or AUX_MCS
534 * -------------------------------------------
535 * 9 | HALIGN_16 | HALIGN_16
536 * 8 | HALIGN_ANY | HALIGN_16
540 if (intel_miptree_supports_ccs(brw
, mt
)) {
541 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
542 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
543 } else if (brw
->gen
>= 9 && num_samples
> 1) {
544 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
546 const UNUSED
bool is_lossless_compressed_aux
=
547 brw
->gen
>= 9 && num_samples
== 1 &&
548 mt
->format
== MESA_FORMAT_R_UINT32
;
550 /* For now, nothing else has this requirement */
551 assert(is_lossless_compressed_aux
||
552 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
555 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
556 intel_miptree_release(&mt
);
560 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
561 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
568 * Choose an appropriate uncompressed format for a requested
569 * compressed format, if unsupported.
572 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
574 /* No need to lower ETC formats on these platforms,
575 * they are supported natively.
577 if (brw
->gen
>= 8 || brw
->is_baytrail
)
581 case MESA_FORMAT_ETC1_RGB8
:
582 return MESA_FORMAT_R8G8B8X8_UNORM
;
583 case MESA_FORMAT_ETC2_RGB8
:
584 return MESA_FORMAT_R8G8B8X8_UNORM
;
585 case MESA_FORMAT_ETC2_SRGB8
:
586 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
587 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
588 return MESA_FORMAT_B8G8R8A8_SRGB
;
589 case MESA_FORMAT_ETC2_RGBA8_EAC
:
590 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
591 return MESA_FORMAT_R8G8B8A8_UNORM
;
592 case MESA_FORMAT_ETC2_R11_EAC
:
593 return MESA_FORMAT_R_UNORM16
;
594 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
595 return MESA_FORMAT_R_SNORM16
;
596 case MESA_FORMAT_ETC2_RG11_EAC
:
597 return MESA_FORMAT_R16G16_UNORM
;
598 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
599 return MESA_FORMAT_R16G16_SNORM
;
601 /* Non ETC1 / ETC2 format */
606 /** \brief Assert that the level and layer are valid for the miptree. */
608 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
616 assert(level
>= mt
->first_level
);
617 assert(level
<= mt
->last_level
);
619 if (mt
->surf
.size
> 0)
620 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
621 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
622 mt
->surf
.phys_level0_sa
.array_len
));
624 assert(layer
< mt
->level
[level
].depth
);
627 static enum isl_aux_state
**
628 create_aux_state_map(struct intel_mipmap_tree
*mt
,
629 enum isl_aux_state initial
)
631 const uint32_t levels
= mt
->last_level
+ 1;
633 uint32_t total_slices
= 0;
634 for (uint32_t level
= 0; level
< levels
; level
++)
635 total_slices
+= mt
->level
[level
].depth
;
637 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
639 /* We're going to allocate a single chunk of data for both the per-level
640 * reference array and the arrays of aux_state. This makes cleanup
641 * significantly easier.
643 const size_t total_size
= per_level_array_size
+
644 total_slices
* sizeof(enum isl_aux_state
);
645 void *data
= malloc(total_size
);
649 enum isl_aux_state
**per_level_arr
= data
;
650 enum isl_aux_state
*s
= data
+ per_level_array_size
;
651 for (uint32_t level
= 0; level
< levels
; level
++) {
652 per_level_arr
[level
] = s
;
653 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
656 assert((void *)s
== data
+ total_size
);
658 return per_level_arr
;
662 free_aux_state_map(enum isl_aux_state
**state
)
667 static struct intel_mipmap_tree
*
668 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
669 unsigned first_level
, unsigned last_level
,
670 unsigned width0
, unsigned height0
, unsigned depth0
,
671 unsigned num_samples
, enum isl_tiling isl_tiling
,
672 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
675 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
679 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
685 if (target
== GL_TEXTURE_CUBE_MAP
||
686 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
687 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
689 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
691 _mesa_enum_to_string(target
),
692 _mesa_get_format_name(format
),
693 num_samples
, width0
, height0
, depth0
,
694 first_level
, last_level
, mt
);
696 struct isl_surf_init_info init_info
= {
697 .dim
= get_isl_surf_dim(target
),
698 .format
= translate_tex_format(brw
, format
, false),
701 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
702 .levels
= last_level
- first_level
+ 1,
703 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
704 .samples
= MAX2(num_samples
, 1),
705 .usage
= isl_usage_flags
,
706 .tiling_flags
= 1u << isl_tiling
709 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
712 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
715 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
717 isl_tiling_to_bufmgr_tiling(isl_tiling
),
718 mt
->surf
.row_pitch
, alloc_flags
);
725 mt
->first_level
= first_level
;
726 mt
->last_level
= last_level
;
730 mt
->aux_state
= NULL
;
735 intel_miptree_release(&mt
);
739 static struct intel_mipmap_tree
*
740 miptree_create(struct brw_context
*brw
,
749 uint32_t layout_flags
)
751 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
752 return make_surface(brw
, target
, format
, first_level
, last_level
,
753 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
754 ISL_SURF_USAGE_STENCIL_BIT
|
755 ISL_SURF_USAGE_TEXTURE_BIT
,
756 BO_ALLOC_FOR_RENDER
, NULL
);
758 struct intel_mipmap_tree
*mt
;
759 mesa_format tex_format
= format
;
760 mesa_format etc_format
= MESA_FORMAT_NONE
;
761 uint32_t alloc_flags
= 0;
763 format
= intel_lower_compressed_format(brw
, format
);
765 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
767 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
768 mt
= intel_miptree_create_layout(brw
, target
, format
,
769 first_level
, last_level
, width0
,
770 height0
, depth0
, num_samples
,
775 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
776 mt
->tiling
= I915_TILING_Y
;
778 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
779 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
781 mt
->etc_format
= etc_format
;
783 if (format
== MESA_FORMAT_S_UINT8
) {
784 /* Align to size of W tile, 64x64. */
785 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
786 ALIGN(mt
->total_width
, 64),
787 ALIGN(mt
->total_height
, 64),
788 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
791 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
792 mt
->total_width
, mt
->total_height
,
793 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
797 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
798 mt
->bo
->cache_coherent
= false;
803 struct intel_mipmap_tree
*
804 intel_miptree_create(struct brw_context
*brw
,
813 uint32_t layout_flags
)
815 struct intel_mipmap_tree
*mt
= miptree_create(
817 first_level
, last_level
,
818 width0
, height0
, depth0
, num_samples
,
821 /* If the BO is too large to fit in the aperture, we need to use the
822 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
823 * handle Y-tiling, so we need to fall back to X.
825 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
826 mt
->tiling
== I915_TILING_Y
) {
827 const uint32_t alloc_flags
=
828 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
829 BO_ALLOC_FOR_RENDER
: 0;
830 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
831 mt
->total_width
, mt
->total_height
);
833 mt
->tiling
= I915_TILING_X
;
834 brw_bo_unreference(mt
->bo
);
835 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
836 mt
->total_width
, mt
->total_height
, mt
->cpp
,
837 mt
->tiling
, &mt
->pitch
, alloc_flags
);
843 intel_miptree_release(&mt
);
848 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
849 assert(mt
->num_samples
> 1);
850 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
851 intel_miptree_release(&mt
);
856 /* If this miptree is capable of supporting fast color clears, set
857 * fast_clear_state appropriately to ensure that fast clears will occur.
858 * Allocation of the MCS miptree will be deferred until the first fast
859 * clear actually occurs or when compressed single sampled buffer is
860 * written by the GPU for the first time.
862 if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
863 intel_miptree_supports_ccs(brw
, mt
)) {
864 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
865 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
867 /* On Gen9+ clients are not currently capable of consuming compressed
868 * single-sampled buffers. Disabling compression allows us to skip
871 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
872 const bool is_lossless_compressed
=
873 unlikely(!lossless_compression_disabled
) &&
874 brw
->gen
>= 9 && !mt
->is_scanout
&&
875 intel_miptree_supports_ccs_e(brw
, mt
);
877 if (is_lossless_compressed
) {
878 intel_miptree_alloc_ccs(brw
, mt
, is_lossless_compressed
);
885 struct intel_mipmap_tree
*
886 intel_miptree_create_for_bo(struct brw_context
*brw
,
894 uint32_t layout_flags
)
896 struct intel_mipmap_tree
*mt
;
897 uint32_t tiling
, swizzle
;
898 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
900 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
901 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
902 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
903 ISL_SURF_USAGE_STENCIL_BIT
|
904 ISL_SURF_USAGE_TEXTURE_BIT
,
905 BO_ALLOC_FOR_RENDER
, bo
);
909 assert(bo
->size
>= mt
->surf
.size
);
911 brw_bo_reference(bo
);
915 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
917 /* Nothing will be able to use this miptree with the BO if the offset isn't
920 if (tiling
!= I915_TILING_NONE
)
921 assert(offset
% 4096 == 0);
923 /* miptrees can't handle negative pitch. If you need flipping of images,
924 * that's outside of the scope of the mt.
928 /* The BO already has a tiling format and we shouldn't confuse the lower
929 * layers by making it try to find a tiling format again.
931 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
932 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
934 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
935 mt
= intel_miptree_create_layout(brw
, target
, format
,
937 width
, height
, depth
, 0,
942 brw_bo_reference(bo
);
952 * For a singlesample renderbuffer, this simply wraps the given BO with a
955 * For a multisample renderbuffer, this wraps the window system's
956 * (singlesample) BO with a singlesample miptree attached to the
957 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
958 * that will contain the actual rendering (which is lazily resolved to
959 * irb->singlesample_mt).
962 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
963 struct intel_renderbuffer
*irb
,
965 uint32_t width
, uint32_t height
,
968 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
969 struct intel_mipmap_tree
*multisample_mt
= NULL
;
970 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
971 mesa_format format
= rb
->Format
;
972 int num_samples
= rb
->NumSamples
;
974 /* Only the front and back buffers, which are color buffers, are allocated
975 * through the image loader.
977 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
978 _mesa_get_format_base_format(format
) == GL_RGBA
);
980 singlesample_mt
= intel_miptree_create_for_bo(intel
,
988 MIPTREE_LAYOUT_FOR_SCANOUT
);
989 if (!singlesample_mt
)
992 /* If this miptree is capable of supporting fast color clears, set
993 * mcs_state appropriately to ensure that fast clears will occur.
994 * Allocation of the MCS miptree will be deferred until the first fast
995 * clear actually occurs.
997 if (intel_tiling_supports_ccs(intel
, singlesample_mt
->tiling
) &&
998 intel_miptree_supports_ccs(intel
, singlesample_mt
)) {
999 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
1002 if (num_samples
== 0) {
1003 intel_miptree_release(&irb
->mt
);
1004 irb
->mt
= singlesample_mt
;
1006 assert(!irb
->singlesample_mt
);
1008 intel_miptree_release(&irb
->singlesample_mt
);
1009 irb
->singlesample_mt
= singlesample_mt
;
1012 irb
->mt
->logical_width0
!= width
||
1013 irb
->mt
->logical_height0
!= height
) {
1014 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1019 if (!multisample_mt
)
1022 irb
->need_downsample
= false;
1023 intel_miptree_release(&irb
->mt
);
1024 irb
->mt
= multisample_mt
;
1030 intel_miptree_release(&irb
->singlesample_mt
);
1031 intel_miptree_release(&irb
->mt
);
1035 struct intel_mipmap_tree
*
1036 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1040 uint32_t num_samples
)
1042 struct intel_mipmap_tree
*mt
;
1045 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1046 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1047 MIPTREE_LAYOUT_TILING_ANY
|
1048 MIPTREE_LAYOUT_FOR_SCANOUT
;
1050 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1051 width
, height
, depth
, num_samples
,
1056 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
1057 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1065 intel_miptree_release(&mt
);
1070 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1071 struct intel_mipmap_tree
*src
)
1076 intel_miptree_release(dst
);
1080 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1087 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1089 if (aux_buf
== NULL
)
1092 brw_bo_unreference(aux_buf
->bo
);
1098 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1103 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1104 if (--(*mt
)->refcount
<= 0) {
1107 DBG("%s deleting %p\n", __func__
, *mt
);
1109 brw_bo_unreference((*mt
)->bo
);
1110 intel_miptree_release(&(*mt
)->stencil_mt
);
1111 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1112 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1113 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1114 free_aux_state_map((*mt
)->aux_state
);
1116 intel_miptree_release(&(*mt
)->plane
[0]);
1117 intel_miptree_release(&(*mt
)->plane
[1]);
1119 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1120 free((*mt
)->level
[i
].slice
);
1130 intel_get_image_dims(struct gl_texture_image
*image
,
1131 int *width
, int *height
, int *depth
)
1133 switch (image
->TexObject
->Target
) {
1134 case GL_TEXTURE_1D_ARRAY
:
1135 /* For a 1D Array texture the OpenGL API will treat the image height as
1136 * the number of array slices. For Intel hardware, we treat the 1D array
1137 * as a 2D Array with a height of 1. So, here we want to swap image
1140 assert(image
->Depth
== 1);
1141 *width
= image
->Width
;
1143 *depth
= image
->Height
;
1145 case GL_TEXTURE_CUBE_MAP
:
1146 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1147 * though we really have 6 slices.
1149 assert(image
->Depth
== 1);
1150 *width
= image
->Width
;
1151 *height
= image
->Height
;
1155 *width
= image
->Width
;
1156 *height
= image
->Height
;
1157 *depth
= image
->Depth
;
1163 * Can the image be pulled into a unified mipmap tree? This mirrors
1164 * the completeness test in a lot of ways.
1166 * Not sure whether I want to pass gl_texture_image here.
1169 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1170 struct gl_texture_image
*image
)
1172 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1173 GLuint level
= intelImage
->base
.Base
.Level
;
1174 int width
, height
, depth
;
1176 /* glTexImage* choose the texture object based on the target passed in, and
1177 * objects can't change targets over their lifetimes, so this should be
1180 assert(image
->TexObject
->Target
== mt
->target
);
1182 mesa_format mt_format
= mt
->format
;
1183 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1184 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1185 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1186 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1187 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1188 mt_format
= mt
->etc_format
;
1190 if (image
->TexFormat
!= mt_format
)
1193 intel_get_image_dims(image
, &width
, &height
, &depth
);
1195 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1198 if (mt
->surf
.size
> 0) {
1199 if (level
>= mt
->surf
.levels
)
1202 const unsigned level_depth
=
1203 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1204 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1205 mt
->surf
.logical_level0_px
.array_len
;
1207 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1208 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1209 depth
== level_depth
&&
1210 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1213 int level_depth
= mt
->level
[level
].depth
;
1214 if (mt
->num_samples
> 1) {
1215 switch (mt
->msaa_layout
) {
1216 case INTEL_MSAA_LAYOUT_NONE
:
1217 case INTEL_MSAA_LAYOUT_IMS
:
1219 case INTEL_MSAA_LAYOUT_UMS
:
1220 case INTEL_MSAA_LAYOUT_CMS
:
1221 level_depth
/= mt
->num_samples
;
1226 /* Test image dimensions against the base level image adjusted for
1227 * minification. This will also catch images not present in the
1228 * tree, changed targets, etc.
1230 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1231 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1232 depth
!= level_depth
) {
1236 if (image
->NumSamples
!= mt
->num_samples
)
1244 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1246 GLuint x
, GLuint y
, GLuint d
)
1248 mt
->level
[level
].depth
= d
;
1249 mt
->level
[level
].level_x
= x
;
1250 mt
->level
[level
].level_y
= y
;
1252 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1255 assert(mt
->level
[level
].slice
);
1257 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1258 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1263 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1264 GLuint level
, GLuint img
,
1267 if (img
== 0 && level
== 0)
1268 assert(x
== 0 && y
== 0);
1270 assert(img
< mt
->level
[level
].depth
);
1272 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1273 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1275 DBG("%s level %d img %d pos %d,%d\n",
1276 __func__
, level
, img
,
1277 mt
->level
[level
].slice
[img
].x_offset
,
1278 mt
->level
[level
].slice
[img
].y_offset
);
1282 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1283 GLuint level
, GLuint slice
,
1284 GLuint
*x
, GLuint
*y
)
1286 if (mt
->surf
.size
> 0) {
1287 uint32_t x_offset_sa
, y_offset_sa
;
1289 /* Given level is relative to level zero while the miptree may be
1290 * represent just a subset of all levels starting from 'first_level'.
1292 assert(level
>= mt
->first_level
);
1293 level
-= mt
->first_level
;
1295 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1296 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1297 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1298 &x_offset_sa
, &y_offset_sa
);
1305 assert(slice
< mt
->level
[level
].depth
);
1307 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1308 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1313 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1314 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1315 * and tile_h is set to 1.
1318 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1319 uint32_t *tile_w
, uint32_t *tile_h
)
1330 case I915_TILING_NONE
:
1335 unreachable("not reached");
1341 * This function computes masks that may be used to select the bits of the X
1342 * and Y coordinates that indicate the offset within a tile. If the BO is
1343 * untiled, the masks are set to 0.
1346 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1347 uint32_t *mask_x
, uint32_t *mask_y
)
1349 uint32_t tile_w_bytes
, tile_h
;
1351 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1353 *mask_x
= tile_w_bytes
/ cpp
- 1;
1354 *mask_y
= tile_h
- 1;
1358 * Compute the offset (in bytes) from the start of the BO to the given x
1359 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1360 * multiples of the tile size.
1363 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1364 uint32_t x
, uint32_t y
)
1367 uint32_t pitch
= mt
->pitch
;
1368 uint32_t tiling
= mt
->tiling
;
1372 unreachable("not reached");
1373 case I915_TILING_NONE
:
1374 return y
* pitch
+ x
* cpp
;
1376 assert((x
% (512 / cpp
)) == 0);
1377 assert((y
% 8) == 0);
1378 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1380 assert((x
% (128 / cpp
)) == 0);
1381 assert((y
% 32) == 0);
1382 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1387 * Rendering with tiled buffers requires that the base address of the buffer
1388 * be aligned to a page boundary. For renderbuffers, and sometimes with
1389 * textures, we may want the surface to point at a texture image level that
1390 * isn't at a page boundary.
1392 * This function returns an appropriately-aligned base offset
1393 * according to the tiling restrictions, plus any required x/y offset
1397 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1398 GLuint level
, GLuint slice
,
1403 uint32_t mask_x
, mask_y
;
1405 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1406 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1408 *tile_x
= x
& mask_x
;
1409 *tile_y
= y
& mask_y
;
1411 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1415 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1416 struct intel_mipmap_tree
*src_mt
,
1417 unsigned src_level
, unsigned src_layer
,
1418 struct intel_mipmap_tree
*dst_mt
,
1419 unsigned dst_level
, unsigned dst_layer
,
1420 unsigned width
, unsigned height
)
1423 ptrdiff_t src_stride
, dst_stride
;
1424 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1425 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1427 intel_miptree_map(brw
, src_mt
,
1428 src_level
, src_layer
,
1431 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1434 intel_miptree_map(brw
, dst_mt
,
1435 dst_level
, dst_layer
,
1438 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1442 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1443 _mesa_get_format_name(src_mt
->format
),
1444 src_mt
, src
, src_stride
,
1445 _mesa_get_format_name(dst_mt
->format
),
1446 dst_mt
, dst
, dst_stride
,
1449 int row_size
= cpp
* width
;
1450 if (src_stride
== row_size
&&
1451 dst_stride
== row_size
) {
1452 memcpy(dst
, src
, row_size
* height
);
1454 for (int i
= 0; i
< height
; i
++) {
1455 memcpy(dst
, src
, row_size
);
1461 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1462 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1464 /* Don't forget to copy the stencil data over, too. We could have skipped
1465 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1466 * shuffling the two data sources in/out of temporary storage instead of
1467 * the direct mapping we get this way.
1469 if (dst_mt
->stencil_mt
) {
1470 assert(src_mt
->stencil_mt
);
1471 intel_miptree_copy_slice_sw(brw
,
1472 src_mt
->stencil_mt
, src_level
, src_layer
,
1473 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1479 intel_miptree_copy_slice(struct brw_context
*brw
,
1480 struct intel_mipmap_tree
*src_mt
,
1481 unsigned src_level
, unsigned src_layer
,
1482 struct intel_mipmap_tree
*dst_mt
,
1483 unsigned dst_level
, unsigned dst_layer
)
1486 mesa_format format
= src_mt
->format
;
1487 uint32_t width
, height
;
1489 if (src_mt
->surf
.size
> 0) {
1490 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1491 src_level
- src_mt
->first_level
);
1492 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1493 src_level
- src_mt
->first_level
);
1495 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1496 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1497 src_level
- src_mt
->first_level
));
1499 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1501 width
= minify(src_mt
->physical_width0
,
1502 src_level
- src_mt
->first_level
);
1503 height
= minify(src_mt
->physical_height0
,
1504 src_level
- src_mt
->first_level
);
1505 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1508 assert(src_mt
->format
== dst_mt
->format
);
1510 if (dst_mt
->compressed
) {
1512 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1513 height
= ALIGN_NPOT(height
, j
) / j
;
1514 width
= ALIGN_NPOT(width
, i
) / i
;
1517 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1518 * below won't apply since we can't do the depth's Y tiling or the
1519 * stencil's W tiling in the blitter.
1521 if (src_mt
->stencil_mt
) {
1522 intel_miptree_copy_slice_sw(brw
,
1523 src_mt
, src_level
, src_layer
,
1524 dst_mt
, dst_level
, dst_layer
,
1529 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1530 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1532 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1535 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1536 _mesa_get_format_name(src_mt
->format
),
1537 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1538 _mesa_get_format_name(dst_mt
->format
),
1539 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1542 if (!intel_miptree_blit(brw
,
1543 src_mt
, src_level
, src_layer
, 0, 0, false,
1544 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1545 width
, height
, GL_COPY
)) {
1546 perf_debug("miptree validate blit for %s failed\n",
1547 _mesa_get_format_name(format
));
1549 intel_miptree_copy_slice_sw(brw
,
1550 src_mt
, src_level
, src_layer
,
1551 dst_mt
, dst_level
, dst_layer
,
1557 * Copies the image's current data to the given miptree, and associates that
1558 * miptree with the image.
1560 * If \c invalidate is true, then the actual image data does not need to be
1561 * copied, but the image still needs to be associated to the new miptree (this
1562 * is set to true if we're about to clear the image).
1565 intel_miptree_copy_teximage(struct brw_context
*brw
,
1566 struct intel_texture_image
*intelImage
,
1567 struct intel_mipmap_tree
*dst_mt
,
1570 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1571 struct intel_texture_object
*intel_obj
=
1572 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1573 int level
= intelImage
->base
.Base
.Level
;
1574 const unsigned face
= intelImage
->base
.Base
.Face
;
1575 unsigned start_layer
, end_layer
;
1577 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1579 assert(intelImage
->base
.Base
.Height
);
1581 end_layer
= intelImage
->base
.Base
.Height
- 1;
1582 } else if (face
> 0) {
1586 assert(intelImage
->base
.Base
.Depth
);
1588 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1592 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1593 intel_miptree_copy_slice(brw
,
1599 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1600 intel_obj
->needs_validate
= true;
1604 intel_miptree_init_mcs(struct brw_context
*brw
,
1605 struct intel_mipmap_tree
*mt
,
1608 assert(mt
->mcs_buf
!= NULL
);
1610 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1612 * When MCS buffer is enabled and bound to MSRT, it is required that it
1613 * is cleared prior to any rendering.
1615 * Since we don't use the MCS buffer for any purpose other than rendering,
1616 * it makes sense to just clear it immediately upon allocation.
1618 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1620 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1621 if (unlikely(map
== NULL
)) {
1622 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1623 brw_bo_unreference(mt
->mcs_buf
->bo
);
1628 memset(data
, init_value
, mt
->mcs_buf
->size
);
1629 brw_bo_unmap(mt
->mcs_buf
->bo
);
1632 static struct intel_miptree_aux_buffer
*
1633 intel_alloc_aux_buffer(struct brw_context
*brw
,
1635 const struct isl_surf
*aux_surf
,
1636 uint32_t alloc_flags
,
1637 struct intel_mipmap_tree
*mt
)
1639 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1643 buf
->size
= aux_surf
->size
;
1644 buf
->pitch
= aux_surf
->row_pitch
;
1645 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1647 /* ISL has stricter set of alignment rules then the drm allocator.
1648 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1649 * trying to recalculate based on different format block sizes.
1651 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1652 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1658 buf
->surf
= *aux_surf
;
1664 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1665 struct intel_mipmap_tree
*mt
,
1668 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1669 assert(mt
->mcs_buf
== NULL
);
1670 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1672 /* Multisampled miptrees are only supported for single level. */
1673 assert(mt
->first_level
== 0);
1674 enum isl_aux_state
**aux_state
=
1675 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1679 struct isl_surf temp_main_surf
;
1680 struct isl_surf temp_mcs_surf
;
1682 /* Create first an ISL presentation for the main color surface and let ISL
1683 * calculate equivalent MCS surface against it.
1685 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1686 MAYBE_UNUSED
bool ok
=
1687 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1690 /* Buffer needs to be initialised requiring the buffer to be immediately
1691 * mapped to cpu space for writing. Therefore do not use the gpu access
1692 * flag which can cause an unnecessary delay if the backing pages happened
1693 * to be just used by the GPU.
1695 const uint32_t alloc_flags
= 0;
1696 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1697 &temp_mcs_surf
, alloc_flags
, mt
);
1703 mt
->aux_state
= aux_state
;
1705 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1711 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1712 struct intel_mipmap_tree
*mt
,
1715 assert(mt
->mcs_buf
== NULL
);
1716 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1718 struct isl_surf temp_main_surf
;
1719 struct isl_surf temp_ccs_surf
;
1721 /* Create first an ISL presentation for the main color surface and let ISL
1722 * calculate equivalent CCS surface against it.
1724 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1725 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1728 assert(temp_ccs_surf
.size
&&
1729 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1731 enum isl_aux_state
**aux_state
=
1732 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1736 /* In case of compression mcs buffer needs to be initialised requiring the
1737 * buffer to be immediately mapped to cpu space for writing. Therefore do
1738 * not use the gpu access flag which can cause an unnecessary delay if the
1739 * backing pages happened to be just used by the GPU.
1741 const uint32_t alloc_flags
= is_ccs_e
? 0 : BO_ALLOC_FOR_RENDER
;
1742 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1743 &temp_ccs_surf
, alloc_flags
, mt
);
1749 mt
->aux_state
= aux_state
;
1751 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1752 * used for lossless compression which requires similar initialisation
1753 * as multi-sample compression.
1756 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1757 * resolve. Initialize it accordingly in case the first renderer is
1758 * cpu (or other none compression aware party).
1760 * This is also explicitly stated in the spec (MCS Buffer for Render
1762 * "If Software wants to enable Color Compression without Fast clear,
1763 * Software needs to initialize MCS with zeros."
1765 intel_miptree_init_mcs(brw
, mt
, 0);
1766 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1773 * Helper for intel_miptree_alloc_hiz() that sets
1774 * \c mt->level[level].has_hiz. Return true if and only if
1775 * \c has_hiz was set.
1778 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1779 struct intel_mipmap_tree
*mt
,
1782 assert(mt
->hiz_buf
);
1784 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1785 uint32_t width
= minify(mt
->physical_width0
, level
);
1786 uint32_t height
= minify(mt
->physical_height0
, level
);
1788 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1789 * and the height is 4 aligned. This allows our HiZ support
1790 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1791 * we can grow the width & height to allow the HiZ op to
1792 * force the proper size alignments.
1794 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1795 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1800 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1801 mt
->level
[level
].has_hiz
= true;
1806 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1807 struct intel_mipmap_tree
*mt
)
1812 if (mt
->hiz_buf
!= NULL
)
1815 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1818 switch (mt
->format
) {
1819 case MESA_FORMAT_Z_FLOAT32
:
1820 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1821 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1822 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1823 case MESA_FORMAT_Z_UNORM16
:
1831 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1832 struct intel_mipmap_tree
*mt
)
1834 assert(mt
->hiz_buf
== NULL
);
1835 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1837 enum isl_aux_state
**aux_state
=
1838 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1842 struct isl_surf temp_main_surf
;
1843 struct isl_surf temp_hiz_surf
;
1845 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1846 MAYBE_UNUSED
bool ok
=
1847 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1850 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1851 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1852 &temp_hiz_surf
, alloc_flags
, mt
);
1859 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1860 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1862 mt
->aux_state
= aux_state
;
1868 * Can the miptree sample using the hiz buffer?
1871 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1872 struct intel_mipmap_tree
*mt
)
1874 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1875 * so keep things conservative for now and never enable it unless we're SKL+.
1885 /* It seems the hardware won't fallback to the depth buffer if some of the
1886 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1887 * of the texture to be HiZ enabled.
1889 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1890 if (!intel_miptree_level_has_hiz(mt
, level
))
1894 /* If compressed multisampling is enabled, then we use it for the auxiliary
1897 * From the BDW PRM (Volume 2d: Command Reference: Structures
1898 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1900 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1901 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1903 * There is no such blurb for 1D textures, but there is sufficient evidence
1904 * that this is broken on SKL+.
1906 return (mt
->num_samples
<= 1 &&
1907 mt
->target
!= GL_TEXTURE_3D
&&
1908 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1912 * Does the miptree slice have hiz enabled?
1915 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1917 intel_miptree_check_level_layer(mt
, level
, 0);
1918 return mt
->level
[level
].has_hiz
;
1922 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1923 unsigned start_level
, unsigned num_levels
,
1924 unsigned start_layer
, unsigned num_layers
)
1926 assert(_mesa_is_format_color_format(mt
->format
));
1931 /* Clamp the level range to fit the miptree */
1932 assert(start_level
+ num_levels
>= start_level
);
1933 const uint32_t last_level
=
1934 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
1935 start_level
= MAX2(mt
->first_level
, start_level
);
1936 num_levels
= last_level
- start_level
+ 1;
1938 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
1939 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
1940 for (unsigned a
= 0; a
< level_layers
; a
++) {
1941 enum isl_aux_state aux_state
=
1942 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1943 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1944 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1953 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1954 const struct intel_mipmap_tree
*mt
,
1955 unsigned level
, unsigned layer
)
1958 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
1961 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1962 assert(brw
->gen
>= 8 ||
1963 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1965 /* Compression of arrayed msaa surfaces is supported. */
1966 if (mt
->num_samples
> 1)
1969 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1970 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
1976 static enum blorp_fast_clear_op
1977 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1978 bool ccs_supported
, bool fast_clear_supported
)
1980 assert(ccs_supported
== fast_clear_supported
);
1982 switch (aux_state
) {
1983 case ISL_AUX_STATE_CLEAR
:
1984 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1986 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1988 return BLORP_FAST_CLEAR_OP_NONE
;
1990 case ISL_AUX_STATE_PASS_THROUGH
:
1991 return BLORP_FAST_CLEAR_OP_NONE
;
1993 case ISL_AUX_STATE_RESOLVED
:
1994 case ISL_AUX_STATE_AUX_INVALID
:
1995 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1999 unreachable("Invalid aux state for CCS_D");
2002 static enum blorp_fast_clear_op
2003 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2004 bool ccs_supported
, bool fast_clear_supported
)
2006 switch (aux_state
) {
2007 case ISL_AUX_STATE_CLEAR
:
2008 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2010 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2011 else if (!fast_clear_supported
)
2012 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2014 return BLORP_FAST_CLEAR_OP_NONE
;
2016 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2018 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2020 return BLORP_FAST_CLEAR_OP_NONE
;
2022 case ISL_AUX_STATE_PASS_THROUGH
:
2023 return BLORP_FAST_CLEAR_OP_NONE
;
2025 case ISL_AUX_STATE_RESOLVED
:
2026 case ISL_AUX_STATE_AUX_INVALID
:
2030 unreachable("Invalid aux state for CCS_E");
2034 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2035 struct intel_mipmap_tree
*mt
,
2036 uint32_t level
, uint32_t layer
,
2038 bool fast_clear_supported
)
2040 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2042 enum blorp_fast_clear_op resolve_op
;
2043 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2044 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2045 fast_clear_supported
);
2047 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2048 fast_clear_supported
);
2051 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2052 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2053 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2055 switch (resolve_op
) {
2056 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2057 /* The CCS full resolve operation destroys the CCS and sets it to the
2058 * pass-through state. (You can also think of this as being both a
2059 * resolve and an ambiguate in one operation.)
2061 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2062 ISL_AUX_STATE_PASS_THROUGH
);
2065 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2066 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2067 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2071 unreachable("Invalid resolve op");
2077 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2078 struct intel_mipmap_tree
*mt
,
2079 uint32_t level
, uint32_t layer
,
2080 bool written_with_ccs
)
2082 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2084 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2085 switch (aux_state
) {
2086 case ISL_AUX_STATE_CLEAR
:
2087 assert(written_with_ccs
);
2088 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2089 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2092 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2093 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2094 assert(written_with_ccs
);
2095 break; /* Nothing to do */
2097 case ISL_AUX_STATE_PASS_THROUGH
:
2098 if (written_with_ccs
) {
2099 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2100 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2106 case ISL_AUX_STATE_RESOLVED
:
2107 case ISL_AUX_STATE_AUX_INVALID
:
2108 unreachable("Invalid aux state for CCS_E");
2111 /* CCS_D is a bit simpler */
2112 switch (aux_state
) {
2113 case ISL_AUX_STATE_CLEAR
:
2114 assert(written_with_ccs
);
2115 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2116 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2119 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2120 assert(written_with_ccs
);
2121 break; /* Nothing to do */
2123 case ISL_AUX_STATE_PASS_THROUGH
:
2127 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2128 case ISL_AUX_STATE_RESOLVED
:
2129 case ISL_AUX_STATE_AUX_INVALID
:
2130 unreachable("Invalid aux state for CCS_D");
2136 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2137 struct intel_mipmap_tree
*mt
,
2138 uint32_t level
, uint32_t layer
,
2139 bool written_with_aux
)
2141 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2142 case ISL_AUX_STATE_CLEAR
:
2143 assert(written_with_aux
);
2144 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2145 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2148 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2149 assert(written_with_aux
);
2150 break; /* Nothing to do */
2152 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2153 case ISL_AUX_STATE_RESOLVED
:
2154 case ISL_AUX_STATE_PASS_THROUGH
:
2155 case ISL_AUX_STATE_AUX_INVALID
:
2156 unreachable("Invalid aux state for MCS");
2161 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2162 struct intel_mipmap_tree
*mt
,
2163 uint32_t level
, uint32_t layer
,
2164 bool hiz_supported
, bool fast_clear_supported
)
2166 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2167 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2168 case ISL_AUX_STATE_CLEAR
:
2169 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2170 if (!hiz_supported
|| !fast_clear_supported
)
2171 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2174 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2176 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2179 case ISL_AUX_STATE_PASS_THROUGH
:
2180 case ISL_AUX_STATE_RESOLVED
:
2183 case ISL_AUX_STATE_AUX_INVALID
:
2185 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2189 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2190 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2193 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2194 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2195 ISL_AUX_STATE_RESOLVED
);
2198 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2199 /* The HiZ resolve operation is actually an ambiguate */
2200 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2201 ISL_AUX_STATE_PASS_THROUGH
);
2205 unreachable("Invalid HiZ op");
2211 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2212 struct intel_mipmap_tree
*mt
,
2213 uint32_t level
, uint32_t layer
,
2214 bool written_with_hiz
)
2216 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2217 case ISL_AUX_STATE_CLEAR
:
2218 assert(written_with_hiz
);
2219 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2220 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2223 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2224 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2225 assert(written_with_hiz
);
2226 break; /* Nothing to do */
2228 case ISL_AUX_STATE_RESOLVED
:
2229 if (written_with_hiz
) {
2230 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2231 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2233 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2234 ISL_AUX_STATE_AUX_INVALID
);
2238 case ISL_AUX_STATE_PASS_THROUGH
:
2239 if (written_with_hiz
) {
2240 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2241 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2245 case ISL_AUX_STATE_AUX_INVALID
:
2246 assert(!written_with_hiz
);
2251 static inline uint32_t
2252 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2253 uint32_t start_level
, uint32_t num_levels
)
2255 assert(start_level
>= mt
->first_level
);
2256 assert(start_level
<= mt
->last_level
);
2258 if (num_levels
== INTEL_REMAINING_LAYERS
)
2259 num_levels
= mt
->last_level
- start_level
+ 1;
2260 /* Check for overflow */
2261 assert(start_level
+ num_levels
>= start_level
);
2262 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2267 static inline uint32_t
2268 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2269 uint32_t start_layer
, uint32_t num_layers
)
2271 assert(level
<= mt
->last_level
);
2272 uint32_t total_num_layers
;
2274 if (mt
->surf
.size
> 0)
2275 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2276 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2277 mt
->surf
.phys_level0_sa
.array_len
;
2279 total_num_layers
= mt
->level
[level
].depth
;
2281 assert(start_layer
< total_num_layers
);
2282 if (num_layers
== INTEL_REMAINING_LAYERS
)
2283 num_layers
= total_num_layers
- start_layer
;
2284 /* Check for overflow */
2285 assert(start_layer
+ num_layers
>= start_layer
);
2286 assert(start_layer
+ num_layers
<= total_num_layers
);
2292 intel_miptree_prepare_access(struct brw_context
*brw
,
2293 struct intel_mipmap_tree
*mt
,
2294 uint32_t start_level
, uint32_t num_levels
,
2295 uint32_t start_layer
, uint32_t num_layers
,
2296 bool aux_supported
, bool fast_clear_supported
)
2298 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2300 if (_mesa_is_format_color_format(mt
->format
)) {
2304 if (mt
->num_samples
> 1) {
2305 /* Nothing to do for MSAA */
2306 assert(aux_supported
&& fast_clear_supported
);
2308 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2309 const uint32_t level
= start_level
+ l
;
2310 const uint32_t level_layers
=
2311 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2312 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2313 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2314 start_layer
+ a
, aux_supported
,
2315 fast_clear_supported
);
2319 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2320 /* Nothing to do for stencil */
2325 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2326 const uint32_t level
= start_level
+ l
;
2327 if (!intel_miptree_level_has_hiz(mt
, level
))
2330 const uint32_t level_layers
=
2331 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2332 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2333 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2335 fast_clear_supported
);
2342 intel_miptree_finish_write(struct brw_context
*brw
,
2343 struct intel_mipmap_tree
*mt
, uint32_t level
,
2344 uint32_t start_layer
, uint32_t num_layers
,
2345 bool written_with_aux
)
2347 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2349 if (_mesa_is_format_color_format(mt
->format
)) {
2353 if (mt
->num_samples
> 1) {
2354 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2355 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2359 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2360 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2364 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2365 /* Nothing to do for stencil */
2367 if (!intel_miptree_level_has_hiz(mt
, level
))
2370 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2371 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2378 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2379 uint32_t level
, uint32_t layer
)
2381 intel_miptree_check_level_layer(mt
, level
, layer
);
2383 if (_mesa_is_format_color_format(mt
->format
)) {
2384 assert(mt
->mcs_buf
!= NULL
);
2385 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2386 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2387 unreachable("Cannot get aux state for stencil");
2389 assert(intel_miptree_level_has_hiz(mt
, level
));
2392 return mt
->aux_state
[level
][layer
];
2396 intel_miptree_set_aux_state(struct brw_context
*brw
,
2397 struct intel_mipmap_tree
*mt
, uint32_t level
,
2398 uint32_t start_layer
, uint32_t num_layers
,
2399 enum isl_aux_state aux_state
)
2401 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2403 if (_mesa_is_format_color_format(mt
->format
)) {
2404 assert(mt
->mcs_buf
!= NULL
);
2405 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2406 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2407 unreachable("Cannot get aux state for stencil");
2409 assert(intel_miptree_level_has_hiz(mt
, level
));
2412 for (unsigned a
= 0; a
< num_layers
; a
++)
2413 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2416 /* On Gen9 color buffers may be compressed by the hardware (lossless
2417 * compression). There are, however, format restrictions and care needs to be
2418 * taken that the sampler engine is capable for re-interpreting a buffer with
2419 * format different the buffer was originally written with.
2421 * For example, SRGB formats are not compressible and the sampler engine isn't
2422 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2423 * color buffer needs to be resolved so that the sampling surface can be
2424 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2428 can_texture_with_ccs(struct brw_context
*brw
,
2429 struct intel_mipmap_tree
*mt
,
2430 mesa_format view_format
)
2432 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2435 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2436 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2438 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2439 isl_mt_format
, isl_view_format
)) {
2440 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2441 _mesa_get_format_name(view_format
),
2442 _mesa_get_format_name(mt
->format
));
2450 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2451 struct intel_mipmap_tree
*mt
,
2452 mesa_format view_format
,
2453 uint32_t start_level
, uint32_t num_levels
,
2454 uint32_t start_layer
, uint32_t num_layers
,
2455 bool *aux_supported_out
)
2457 bool aux_supported
, clear_supported
;
2458 if (_mesa_is_format_color_format(mt
->format
)) {
2459 if (mt
->num_samples
> 1) {
2460 aux_supported
= clear_supported
= true;
2462 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2464 /* Clear color is specified as ints or floats and the conversion is
2465 * done by the sampler. If we have a texture view, we would have to
2466 * perform the clear color conversion manually. Just disable clear
2469 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2471 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2472 aux_supported
= clear_supported
= false;
2474 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2477 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2478 start_layer
, num_layers
,
2479 aux_supported
, clear_supported
);
2480 if (aux_supported_out
)
2481 *aux_supported_out
= aux_supported
;
2485 intel_miptree_prepare_texture(struct brw_context
*brw
,
2486 struct intel_mipmap_tree
*mt
,
2487 mesa_format view_format
,
2488 bool *aux_supported_out
)
2490 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2491 0, INTEL_REMAINING_LEVELS
,
2492 0, INTEL_REMAINING_LAYERS
,
2497 intel_miptree_prepare_image(struct brw_context
*brw
,
2498 struct intel_mipmap_tree
*mt
)
2500 /* The data port doesn't understand any compression */
2501 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2502 0, INTEL_REMAINING_LAYERS
, false, false);
2506 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2507 struct intel_mipmap_tree
*mt
, uint32_t level
,
2508 uint32_t start_layer
, uint32_t num_layers
)
2510 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2511 start_layer
, num_layers
, NULL
);
2515 intel_miptree_prepare_render(struct brw_context
*brw
,
2516 struct intel_mipmap_tree
*mt
, uint32_t level
,
2517 uint32_t start_layer
, uint32_t layer_count
,
2520 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2521 * the single-sampled color renderbuffers because the CCS buffer isn't
2522 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2523 * enabled because otherwise the surface state will be programmed with
2524 * the linear equivalent format anyway.
2526 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2527 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2529 /* Lossless compression is not supported for SRGB formats, it
2530 * should be impossible to get here with such surfaces.
2532 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2533 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2539 intel_miptree_finish_render(struct brw_context
*brw
,
2540 struct intel_mipmap_tree
*mt
, uint32_t level
,
2541 uint32_t start_layer
, uint32_t layer_count
)
2543 assert(_mesa_is_format_color_format(mt
->format
));
2544 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2545 mt
->mcs_buf
!= NULL
);
2549 intel_miptree_prepare_depth(struct brw_context
*brw
,
2550 struct intel_mipmap_tree
*mt
, uint32_t level
,
2551 uint32_t start_layer
, uint32_t layer_count
)
2553 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2554 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2558 intel_miptree_finish_depth(struct brw_context
*brw
,
2559 struct intel_mipmap_tree
*mt
, uint32_t level
,
2560 uint32_t start_layer
, uint32_t layer_count
,
2563 if (depth_written
) {
2564 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2565 mt
->hiz_buf
!= NULL
);
2570 * Make it possible to share the BO backing the given miptree with another
2571 * process or another miptree.
2573 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2574 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2575 * ensure that no MCS buffer gets allocated in the future.
2577 * HiZ is similarly unsafe with shared buffers.
2580 intel_miptree_make_shareable(struct brw_context
*brw
,
2581 struct intel_mipmap_tree
*mt
)
2583 /* MCS buffers are also used for multisample buffers, but we can't resolve
2584 * away a multisample MCS buffer because it's an integral part of how the
2585 * pixel data is stored. Fortunately this code path should never be
2586 * reached for multisample buffers.
2588 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2590 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2591 0, INTEL_REMAINING_LAYERS
, false, false);
2594 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2595 brw_bo_unreference(mt
->mcs_buf
->bo
);
2599 /* Any pending MCS/CCS operations are no longer needed. Trying to
2600 * execute any will likely crash due to the missing aux buffer. So let's
2601 * delete all pending ops.
2603 free(mt
->aux_state
);
2604 mt
->aux_state
= NULL
;
2608 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2609 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2612 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2613 mt
->level
[l
].has_hiz
= false;
2616 /* Any pending HiZ operations are no longer needed. Trying to execute
2617 * any will likely crash due to the missing aux buffer. So let's delete
2620 free(mt
->aux_state
);
2621 mt
->aux_state
= NULL
;
2627 * \brief Get pointer offset into stencil buffer.
2629 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2630 * must decode the tile's layout in software.
2633 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2635 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2637 * Even though the returned offset is always positive, the return type is
2639 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2640 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2643 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2645 uint32_t tile_size
= 4096;
2646 uint32_t tile_width
= 64;
2647 uint32_t tile_height
= 64;
2648 uint32_t row_size
= 64 * stride
;
2650 uint32_t tile_x
= x
/ tile_width
;
2651 uint32_t tile_y
= y
/ tile_height
;
2653 /* The byte's address relative to the tile's base addres. */
2654 uint32_t byte_x
= x
% tile_width
;
2655 uint32_t byte_y
= y
% tile_height
;
2657 uintptr_t u
= tile_y
* row_size
2658 + tile_x
* tile_size
2659 + 512 * (byte_x
/ 8)
2661 + 32 * ((byte_y
/ 4) % 2)
2662 + 16 * ((byte_x
/ 4) % 2)
2663 + 8 * ((byte_y
/ 2) % 2)
2664 + 4 * ((byte_x
/ 2) % 2)
2669 /* adjust for bit6 swizzling */
2670 if (((byte_x
/ 8) % 2) == 1) {
2671 if (((byte_y
/ 8) % 2) == 0) {
2683 intel_miptree_updownsample(struct brw_context
*brw
,
2684 struct intel_mipmap_tree
*src
,
2685 struct intel_mipmap_tree
*dst
)
2687 unsigned src_w
, src_h
, dst_w
, dst_h
;
2689 if (src
->surf
.size
> 0) {
2690 src_w
= src
->surf
.logical_level0_px
.width
;
2691 src_h
= src
->surf
.logical_level0_px
.height
;
2693 src_w
= src
->logical_width0
;
2694 src_h
= src
->logical_height0
;
2697 if (dst
->surf
.size
> 0) {
2698 dst_w
= dst
->surf
.logical_level0_px
.width
;
2699 dst_h
= dst
->surf
.logical_level0_px
.height
;
2701 dst_w
= dst
->logical_width0
;
2702 dst_h
= dst
->logical_height0
;
2705 brw_blorp_blit_miptrees(brw
,
2706 src
, 0 /* level */, 0 /* layer */,
2707 src
->format
, SWIZZLE_XYZW
,
2708 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2711 GL_NEAREST
, false, false /*mirror x, y*/,
2714 if (src
->stencil_mt
) {
2715 if (src
->stencil_mt
->surf
.size
> 0) {
2716 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2717 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2719 src_w
= src
->stencil_mt
->logical_width0
;
2720 src_h
= src
->stencil_mt
->logical_height0
;
2723 if (dst
->stencil_mt
->surf
.size
> 0) {
2724 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2725 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2727 dst_w
= dst
->stencil_mt
->logical_width0
;
2728 dst_h
= dst
->stencil_mt
->logical_height0
;
2731 brw_blorp_blit_miptrees(brw
,
2732 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2733 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2734 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2735 dst
->stencil_mt
->format
,
2738 GL_NEAREST
, false, false /*mirror x, y*/,
2739 false, false /* decode/encode srgb */);
2744 intel_update_r8stencil(struct brw_context
*brw
,
2745 struct intel_mipmap_tree
*mt
)
2747 assert(brw
->gen
>= 7);
2748 struct intel_mipmap_tree
*src
=
2749 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2750 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2753 if (!mt
->r8stencil_mt
) {
2754 const uint32_t r8stencil_flags
=
2755 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2756 MIPTREE_LAYOUT_DISABLE_AUX
;
2757 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2758 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2760 MESA_FORMAT_R_UINT8
,
2763 src
->logical_width0
,
2764 src
->logical_height0
,
2765 src
->logical_depth0
,
2768 assert(mt
->r8stencil_mt
);
2771 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2773 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2774 const unsigned depth
= src
->level
[level
].depth
;
2776 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2777 brw_blorp_copy_miptrees(brw
,
2781 minify(src
->logical_width0
, level
),
2782 minify(src
->logical_height0
, level
));
2786 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2787 src
->r8stencil_needs_update
= false;
2791 intel_miptree_map_raw(struct brw_context
*brw
,
2792 struct intel_mipmap_tree
*mt
,
2795 struct brw_bo
*bo
= mt
->bo
;
2797 if (brw_batch_references(&brw
->batch
, bo
))
2798 intel_batchbuffer_flush(brw
);
2800 return brw_bo_map(brw
, bo
, mode
);
2804 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2806 brw_bo_unmap(mt
->bo
);
2810 intel_miptree_map_gtt(struct brw_context
*brw
,
2811 struct intel_mipmap_tree
*mt
,
2812 struct intel_miptree_map
*map
,
2813 unsigned int level
, unsigned int slice
)
2815 unsigned int bw
, bh
;
2817 unsigned int image_x
, image_y
;
2818 intptr_t x
= map
->x
;
2819 intptr_t y
= map
->y
;
2821 /* For compressed formats, the stride is the number of bytes per
2822 * row of blocks. intel_miptree_get_image_offset() already does
2825 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2826 assert(y
% bh
== 0);
2827 assert(x
% bw
== 0);
2831 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2836 /* Note that in the case of cube maps, the caller must have passed the
2837 * slice number referencing the face.
2839 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2843 map
->stride
= mt
->pitch
;
2844 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2847 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2848 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2849 map
->x
, map
->y
, map
->w
, map
->h
,
2850 mt
, _mesa_get_format_name(mt
->format
),
2851 x
, y
, map
->ptr
, map
->stride
);
2855 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2857 intel_miptree_unmap_raw(mt
);
2861 intel_miptree_map_blit(struct brw_context
*brw
,
2862 struct intel_mipmap_tree
*mt
,
2863 struct intel_miptree_map
*map
,
2864 unsigned int level
, unsigned int slice
)
2866 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2867 /* first_level */ 0,
2871 MIPTREE_LAYOUT_TILING_NONE
);
2873 if (!map
->linear_mt
) {
2874 fprintf(stderr
, "Failed to allocate blit temporary\n");
2877 map
->stride
= map
->linear_mt
->pitch
;
2879 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2880 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2881 * invalidate is set, since we'll be writing the whole rectangle from our
2882 * temporary buffer back out.
2884 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2885 if (!intel_miptree_copy(brw
,
2886 mt
, level
, slice
, map
->x
, map
->y
,
2887 map
->linear_mt
, 0, 0, 0, 0,
2889 fprintf(stderr
, "Failed to blit\n");
2894 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2896 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2897 map
->x
, map
->y
, map
->w
, map
->h
,
2898 mt
, _mesa_get_format_name(mt
->format
),
2899 level
, slice
, map
->ptr
, map
->stride
);
2904 intel_miptree_release(&map
->linear_mt
);
2910 intel_miptree_unmap_blit(struct brw_context
*brw
,
2911 struct intel_mipmap_tree
*mt
,
2912 struct intel_miptree_map
*map
,
2916 struct gl_context
*ctx
= &brw
->ctx
;
2918 intel_miptree_unmap_raw(map
->linear_mt
);
2920 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2921 bool ok
= intel_miptree_copy(brw
,
2922 map
->linear_mt
, 0, 0, 0, 0,
2923 mt
, level
, slice
, map
->x
, map
->y
,
2925 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2928 intel_miptree_release(&map
->linear_mt
);
2932 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2934 #if defined(USE_SSE41)
2936 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2937 struct intel_mipmap_tree
*mt
,
2938 struct intel_miptree_map
*map
,
2939 unsigned int level
, unsigned int slice
)
2941 assert(map
->mode
& GL_MAP_READ_BIT
);
2942 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2944 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2945 map
->x
, map
->y
, map
->w
, map
->h
,
2946 mt
, _mesa_get_format_name(mt
->format
),
2947 level
, slice
, map
->ptr
, map
->stride
);
2949 /* Map the original image */
2952 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2956 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2962 src
+= image_y
* mt
->pitch
;
2963 src
+= image_x
* mt
->cpp
;
2965 /* Due to the pixel offsets for the particular image being mapped, our
2966 * src pointer may not be 16-byte aligned. However, if the pitch is
2967 * divisible by 16, then the amount by which it's misaligned will remain
2968 * consistent from row to row.
2970 assert((mt
->pitch
% 16) == 0);
2971 const int misalignment
= ((uintptr_t) src
) & 15;
2973 /* Create an untiled temporary buffer for the mapping. */
2974 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2976 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2978 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2979 /* Offset the destination so it has the same misalignment as src. */
2980 map
->ptr
= map
->buffer
+ misalignment
;
2982 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2984 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2985 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2986 void *src_ptr
= src
+ y
* mt
->pitch
;
2988 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2991 intel_miptree_unmap_raw(mt
);
2995 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2996 struct intel_mipmap_tree
*mt
,
2997 struct intel_miptree_map
*map
,
3001 _mesa_align_free(map
->buffer
);
3008 intel_miptree_map_s8(struct brw_context
*brw
,
3009 struct intel_mipmap_tree
*mt
,
3010 struct intel_miptree_map
*map
,
3011 unsigned int level
, unsigned int slice
)
3013 map
->stride
= map
->w
;
3014 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3018 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3019 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3020 * invalidate is set, since we'll be writing the whole rectangle from our
3021 * temporary buffer back out.
3023 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3024 /* ISL uses a stencil pitch value that is expected by hardware whereas
3025 * traditional miptree uses half of that. Below the value gets supplied
3026 * to intel_offset_S8() which expects the legacy interpretation.
3028 const unsigned pitch
= mt
->surf
.size
> 0 ?
3029 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3030 uint8_t *untiled_s8_map
= map
->ptr
;
3031 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3032 unsigned int image_x
, image_y
;
3034 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3036 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3037 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3038 ptrdiff_t offset
= intel_offset_S8(pitch
,
3039 x
+ image_x
+ map
->x
,
3040 y
+ image_y
+ map
->y
,
3041 brw
->has_swizzling
);
3042 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3046 intel_miptree_unmap_raw(mt
);
3048 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3049 map
->x
, map
->y
, map
->w
, map
->h
,
3050 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3052 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3053 map
->x
, map
->y
, map
->w
, map
->h
,
3054 mt
, map
->ptr
, map
->stride
);
3059 intel_miptree_unmap_s8(struct brw_context
*brw
,
3060 struct intel_mipmap_tree
*mt
,
3061 struct intel_miptree_map
*map
,
3065 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3066 /* ISL uses a stencil pitch value that is expected by hardware whereas
3067 * traditional miptree uses half of that. Below the value gets supplied
3068 * to intel_offset_S8() which expects the legacy interpretation.
3070 const unsigned pitch
= mt
->surf
.size
> 0 ?
3071 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3072 unsigned int image_x
, image_y
;
3073 uint8_t *untiled_s8_map
= map
->ptr
;
3074 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3076 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3078 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3079 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3080 ptrdiff_t offset
= intel_offset_S8(pitch
,
3081 image_x
+ x
+ map
->x
,
3082 image_y
+ y
+ map
->y
,
3083 brw
->has_swizzling
);
3084 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3088 intel_miptree_unmap_raw(mt
);
3095 intel_miptree_map_etc(struct brw_context
*brw
,
3096 struct intel_mipmap_tree
*mt
,
3097 struct intel_miptree_map
*map
,
3101 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3102 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3103 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3106 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3107 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3109 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3110 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3111 map
->w
, map
->h
, 1));
3112 map
->ptr
= map
->buffer
;
3116 intel_miptree_unmap_etc(struct brw_context
*brw
,
3117 struct intel_mipmap_tree
*mt
,
3118 struct intel_miptree_map
*map
,
3124 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3129 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3130 + image_y
* mt
->pitch
3131 + image_x
* mt
->cpp
;
3133 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3134 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3135 map
->ptr
, map
->stride
,
3138 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3139 map
->ptr
, map
->stride
,
3140 map
->w
, map
->h
, mt
->etc_format
);
3142 intel_miptree_unmap_raw(mt
);
3147 * Mapping function for packed depth/stencil miptrees backed by real separate
3148 * miptrees for depth and stencil.
3150 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3151 * separate from the depth buffer. Yet at the GL API level, we have to expose
3152 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3153 * be able to map that memory for texture storage and glReadPixels-type
3154 * operations. We give Mesa core that access by mallocing a temporary and
3155 * copying the data between the actual backing store and the temporary.
3158 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3159 struct intel_mipmap_tree
*mt
,
3160 struct intel_miptree_map
*map
,
3161 unsigned int level
, unsigned int slice
)
3163 struct intel_mipmap_tree
*z_mt
= mt
;
3164 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3165 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3166 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3168 map
->stride
= map
->w
* packed_bpp
;
3169 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3173 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3174 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3175 * invalidate is set, since we'll be writing the whole rectangle from our
3176 * temporary buffer back out.
3178 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3179 /* ISL uses a stencil pitch value that is expected by hardware whereas
3180 * traditional miptree uses half of that. Below the value gets supplied
3181 * to intel_offset_S8() which expects the legacy interpretation.
3183 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3184 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3185 uint32_t *packed_map
= map
->ptr
;
3186 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3187 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3188 unsigned int s_image_x
, s_image_y
;
3189 unsigned int z_image_x
, z_image_y
;
3191 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3192 &s_image_x
, &s_image_y
);
3193 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3194 &z_image_x
, &z_image_y
);
3196 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3197 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3198 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3199 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3202 brw
->has_swizzling
);
3203 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3205 (map_x
+ z_image_x
));
3206 uint8_t s
= s_map
[s_offset
];
3207 uint32_t z
= z_map
[z_offset
];
3209 if (map_z32f_x24s8
) {
3210 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3211 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3213 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3218 intel_miptree_unmap_raw(s_mt
);
3219 intel_miptree_unmap_raw(z_mt
);
3221 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3223 map
->x
, map
->y
, map
->w
, map
->h
,
3224 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3225 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3226 map
->ptr
, map
->stride
);
3228 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3229 map
->x
, map
->y
, map
->w
, map
->h
,
3230 mt
, map
->ptr
, map
->stride
);
3235 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3236 struct intel_mipmap_tree
*mt
,
3237 struct intel_miptree_map
*map
,
3241 struct intel_mipmap_tree
*z_mt
= mt
;
3242 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3243 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3245 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3246 /* ISL uses a stencil pitch value that is expected by hardware whereas
3247 * traditional miptree uses half of that. Below the value gets supplied
3248 * to intel_offset_S8() which expects the legacy interpretation.
3250 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3251 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3252 uint32_t *packed_map
= map
->ptr
;
3253 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3254 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3255 unsigned int s_image_x
, s_image_y
;
3256 unsigned int z_image_x
, z_image_y
;
3258 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3259 &s_image_x
, &s_image_y
);
3260 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3261 &z_image_x
, &z_image_y
);
3263 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3264 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3265 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3266 x
+ s_image_x
+ map
->x
,
3267 y
+ s_image_y
+ map
->y
,
3268 brw
->has_swizzling
);
3269 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3271 (x
+ z_image_x
+ map
->x
));
3273 if (map_z32f_x24s8
) {
3274 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3275 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3277 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3278 s_map
[s_offset
] = packed
>> 24;
3279 z_map
[z_offset
] = packed
;
3284 intel_miptree_unmap_raw(s_mt
);
3285 intel_miptree_unmap_raw(z_mt
);
3287 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3289 map
->x
, map
->y
, map
->w
, map
->h
,
3290 z_mt
, _mesa_get_format_name(z_mt
->format
),
3291 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3292 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3293 map
->ptr
, map
->stride
);
3300 * Create and attach a map to the miptree at (level, slice). Return the
3303 static struct intel_miptree_map
*
3304 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3313 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3318 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3319 mt
->level
[level
].slice
[slice
].map
= map
;
3331 * Release the map at (level, slice).
3334 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3338 struct intel_miptree_map
**map
;
3340 map
= &mt
->level
[level
].slice
[slice
].map
;
3346 can_blit_slice(struct intel_mipmap_tree
*mt
,
3347 unsigned int level
, unsigned int slice
)
3349 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3350 if (mt
->pitch
>= 32768)
3357 use_intel_mipree_map_blit(struct brw_context
*brw
,
3358 struct intel_mipmap_tree
*mt
,
3364 /* It's probably not worth swapping to the blit ring because of
3365 * all the overhead involved.
3367 !(mode
& GL_MAP_WRITE_BIT
) &&
3369 (mt
->tiling
== I915_TILING_X
||
3370 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3371 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3372 /* Fast copy blit on skl+ supports all tiling formats. */
3374 can_blit_slice(mt
, level
, slice
))
3377 if (mt
->tiling
!= I915_TILING_NONE
&&
3378 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3379 assert(can_blit_slice(mt
, level
, slice
));
3387 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3388 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3389 * arithmetic overflow.
3391 * If you call this function and use \a out_stride, then you're doing pointer
3392 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3393 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3394 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3395 * which usually have type uint32_t or GLuint.
3398 intel_miptree_map(struct brw_context
*brw
,
3399 struct intel_mipmap_tree
*mt
,
3408 ptrdiff_t *out_stride
)
3410 struct intel_miptree_map
*map
;
3412 assert(mt
->num_samples
<= 1);
3414 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3421 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3422 map
->mode
& GL_MAP_WRITE_BIT
);
3424 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3425 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3426 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3427 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3428 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3429 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3430 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3431 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3432 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3433 #if defined(USE_SSE41)
3434 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3435 !mt
->compressed
&& cpu_has_sse4_1
&&
3436 (mt
->pitch
% 16 == 0)) {
3437 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3440 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3443 *out_ptr
= map
->ptr
;
3444 *out_stride
= map
->stride
;
3446 if (map
->ptr
== NULL
)
3447 intel_miptree_release_map(mt
, level
, slice
);
3451 intel_miptree_unmap(struct brw_context
*brw
,
3452 struct intel_mipmap_tree
*mt
,
3456 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3458 assert(mt
->num_samples
<= 1);
3463 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3464 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3466 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3467 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3468 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3469 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3470 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3471 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3472 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3473 } else if (map
->linear_mt
) {
3474 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3475 #if defined(USE_SSE41)
3476 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3477 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3480 intel_miptree_unmap_gtt(mt
);
3483 intel_miptree_release_map(mt
, level
, slice
);
3487 get_isl_surf_dim(GLenum target
)
3491 case GL_TEXTURE_1D_ARRAY
:
3492 return ISL_SURF_DIM_1D
;
3495 case GL_TEXTURE_2D_ARRAY
:
3496 case GL_TEXTURE_RECTANGLE
:
3497 case GL_TEXTURE_CUBE_MAP
:
3498 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3499 case GL_TEXTURE_2D_MULTISAMPLE
:
3500 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3501 case GL_TEXTURE_EXTERNAL_OES
:
3502 return ISL_SURF_DIM_2D
;
3505 return ISL_SURF_DIM_3D
;
3508 unreachable("Invalid texture target");
3512 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3513 GLenum target
, enum miptree_array_layout array_layout
)
3515 if (array_layout
== GEN6_HIZ_STENCIL
)
3516 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3520 case GL_TEXTURE_1D_ARRAY
:
3521 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3522 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3525 case GL_TEXTURE_2D_ARRAY
:
3526 case GL_TEXTURE_RECTANGLE
:
3527 case GL_TEXTURE_2D_MULTISAMPLE
:
3528 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3529 case GL_TEXTURE_EXTERNAL_OES
:
3530 return ISL_DIM_LAYOUT_GEN4_2D
;
3532 case GL_TEXTURE_CUBE_MAP
:
3533 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3534 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3535 ISL_DIM_LAYOUT_GEN4_2D
);
3538 return (devinfo
->gen
>= 9 ?
3539 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3542 unreachable("Invalid texture target");
3546 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3548 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3549 return ISL_TILING_W
;
3551 switch (mt
->tiling
) {
3552 case I915_TILING_NONE
:
3553 return ISL_TILING_LINEAR
;
3555 return ISL_TILING_X
;
3557 return ISL_TILING_Y0
;
3559 unreachable("Invalid tiling mode");
3565 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3566 const struct intel_mipmap_tree
*mt
,
3567 struct isl_surf
*surf
)
3569 surf
->dim
= get_isl_surf_dim(mt
->target
);
3570 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3571 mt
->tiling
, mt
->target
,
3574 if (mt
->num_samples
> 1) {
3575 switch (mt
->msaa_layout
) {
3576 case INTEL_MSAA_LAYOUT_IMS
:
3577 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3579 case INTEL_MSAA_LAYOUT_UMS
:
3580 case INTEL_MSAA_LAYOUT_CMS
:
3581 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3584 unreachable("Invalid MSAA layout");
3587 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3590 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3592 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3593 /* The ISL definition of row_pitch matches the surface state pitch field
3594 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3595 * the factor of 2 for W-tiling in row_pitch.
3597 surf
->row_pitch
= 2 * mt
->pitch
;
3599 surf
->row_pitch
= mt
->pitch
;
3602 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3604 if (brw
->gen
>= 9) {
3605 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3606 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3607 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3609 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3610 * alignment in terms of surface elements like we want.
3612 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3615 /* On earlier gens it's stored in pixels. */
3617 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3618 surf
->image_alignment_el
=
3619 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3622 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3623 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3624 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3625 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3626 surf
->logical_level0_px
.array_len
= 1;
3628 surf
->logical_level0_px
.depth
= 1;
3629 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3632 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3633 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3634 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3635 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3636 surf
->phys_level0_sa
.array_len
= 1;
3638 surf
->phys_level0_sa
.depth
= 1;
3639 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3642 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3643 surf
->samples
= MAX2(mt
->num_samples
, 1);
3645 surf
->size
= 0; /* TODO */
3646 surf
->alignment
= 0; /* TODO */
3648 switch (surf
->dim_layout
) {
3649 case ISL_DIM_LAYOUT_GEN4_2D
:
3650 case ISL_DIM_LAYOUT_GEN4_3D
:
3651 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3652 if (brw
->gen
>= 9) {
3653 surf
->array_pitch_el_rows
= mt
->qpitch
;
3656 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3657 assert(mt
->qpitch
% bh
== 0);
3658 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3661 case ISL_DIM_LAYOUT_GEN9_1D
:
3662 surf
->array_pitch_el_rows
= 1;
3666 switch (mt
->array_layout
) {
3667 case ALL_LOD_IN_EACH_SLICE
:
3668 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3670 case ALL_SLICES_AT_EACH_LOD
:
3671 case GEN6_HIZ_STENCIL
:
3672 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3675 unreachable("Invalid array layout");
3678 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3679 switch (base_format
) {
3680 case GL_DEPTH_COMPONENT
:
3681 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3683 case GL_STENCIL_INDEX
:
3684 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3686 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3688 case GL_DEPTH_STENCIL
:
3689 /* In this case we only texture from the depth part */
3690 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3691 ISL_SURF_USAGE_TEXTURE_BIT
;
3694 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3695 if (brw
->mesa_format_supports_render
[mt
->format
])
3696 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3700 if (_mesa_is_cube_map_texture(mt
->target
))
3701 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3705 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3706 const struct intel_mipmap_tree
*mt
)
3709 return ISL_AUX_USAGE_HIZ
;
3712 return ISL_AUX_USAGE_NONE
;
3714 if (mt
->num_samples
> 1) {
3715 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3716 return ISL_AUX_USAGE_MCS
;
3719 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3720 assert(brw
->gen
>= 9);
3721 return ISL_AUX_USAGE_CCS_E
;
3724 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0)
3725 return ISL_AUX_USAGE_CCS_D
;
3727 unreachable("Invalid MCS miptree");