2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include "drm-uapi/drm_fourcc.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 * Return true if the format that will be used to access the miptree is
63 * CCS_E-compatible with the miptree's linear/non-sRGB format.
65 * Why use the linear format? Well, although the miptree may be specified with
66 * an sRGB format, the usage of that color space/format can be toggled. Since
67 * our HW tends to support more linear formats than sRGB ones, we use this
68 * format variant for check for CCS_E compatibility.
71 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
72 const struct intel_mipmap_tree
*mt
,
73 enum isl_format access_format
)
75 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
77 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
78 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
79 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
82 /* Determine if CCS_E is supported for a given platform and mesa format. */
84 format_supports_ccs_e(const struct brw_context
*brw
, mesa_format format
)
86 /* For now compression is only enabled for integer formats even though
87 * there exist supported floating point formats also. This is a heuristic
88 * decision based on current public benchmarks. In none of the cases these
89 * formats provided any improvement but a few cases were seen to regress.
90 * Hence these are left to to be enabled in the future when they are known
93 if (_mesa_get_format_datatype(format
) == GL_FLOAT
)
96 /* Many window system buffers are sRGB even if they are never rendered as
97 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
98 * surface is used as sRGB, we fall back to CCS_D.
100 mesa_format linear_format
= _mesa_get_srgb_format_linear(format
);
101 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
102 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
106 * Determine depth format corresponding to a depth+stencil format,
107 * for separate stencil.
110 intel_depth_format_for_depthstencil_format(mesa_format format
) {
112 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
113 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
114 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
115 return MESA_FORMAT_Z_FLOAT32
;
122 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
123 unsigned depth0
, struct intel_mipmap_level
*table
)
125 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
127 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
129 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
130 if (!table
[level
].slice
)
137 for (unsigned level
= first_level
; level
<= last_level
; level
++)
138 free(table
[level
].slice
);
144 needs_separate_stencil(const struct brw_context
*brw
,
145 struct intel_mipmap_tree
*mt
,
148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
150 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
153 if (devinfo
->must_use_separate_stencil
)
156 return brw
->has_separate_stencil
&& brw
->has_hiz
;
160 * Choose the aux usage for this miptree. This function must be called fairly
161 * late in the miptree create process after we have a tiling.
164 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
165 struct intel_mipmap_tree
*mt
)
167 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
169 if (_mesa_is_format_color_format(mt
->format
)) {
170 if (mt
->surf
.samples
> 1) {
171 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
172 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
173 format_supports_ccs_e(brw
, mt
->format
)) {
174 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
175 } else if (brw
->mesa_format_supports_render
[mt
->format
]) {
176 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
178 } else if (isl_surf_usage_is_depth(mt
->surf
.usage
) && brw
->has_hiz
) {
179 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
182 /* We can do fast-clear on all auxiliary surface types that are
183 * allocated through the normal texture creation paths.
185 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
186 mt
->supports_fast_clear
= true;
191 * Choose an appropriate uncompressed format for a requested
192 * compressed format, if unsupported.
195 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
197 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
199 /* No need to lower ETC formats on these platforms,
200 * they are supported natively.
202 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
206 case MESA_FORMAT_ETC1_RGB8
:
207 return MESA_FORMAT_R8G8B8X8_UNORM
;
208 case MESA_FORMAT_ETC2_RGB8
:
209 return MESA_FORMAT_R8G8B8X8_UNORM
;
210 case MESA_FORMAT_ETC2_SRGB8
:
211 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
212 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
213 return MESA_FORMAT_B8G8R8A8_SRGB
;
214 case MESA_FORMAT_ETC2_RGBA8_EAC
:
215 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
216 return MESA_FORMAT_R8G8B8A8_UNORM
;
217 case MESA_FORMAT_ETC2_R11_EAC
:
218 return MESA_FORMAT_R_UNORM16
;
219 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
220 return MESA_FORMAT_R_SNORM16
;
221 case MESA_FORMAT_ETC2_RG11_EAC
:
222 return MESA_FORMAT_RG_UNORM16
;
223 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
224 return MESA_FORMAT_RG_SNORM16
;
226 /* Non ETC1 / ETC2 format */
232 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
234 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
235 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
237 return mt
->surf
.logical_level0_px
.array_len
;
240 UNUSED
static unsigned
241 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
243 /* In case of physical dimensions one needs to consider also the layout.
244 * See isl_calc_phys_level0_extent_sa().
246 if (surf
->dim
!= ISL_SURF_DIM_3D
)
247 return surf
->phys_level0_sa
.array_len
;
249 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
250 return minify(surf
->phys_level0_sa
.array_len
, level
);
252 return minify(surf
->phys_level0_sa
.depth
, level
);
255 /** \brief Assert that the level and layer are valid for the miptree. */
257 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
265 assert(level
>= mt
->first_level
);
266 assert(level
<= mt
->last_level
);
267 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
270 static enum isl_aux_state
**
271 create_aux_state_map(struct intel_mipmap_tree
*mt
,
272 enum isl_aux_state initial
)
274 const uint32_t levels
= mt
->last_level
+ 1;
276 uint32_t total_slices
= 0;
277 for (uint32_t level
= 0; level
< levels
; level
++)
278 total_slices
+= brw_get_num_logical_layers(mt
, level
);
280 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
282 /* We're going to allocate a single chunk of data for both the per-level
283 * reference array and the arrays of aux_state. This makes cleanup
284 * significantly easier.
286 const size_t total_size
= per_level_array_size
+
287 total_slices
* sizeof(enum isl_aux_state
);
288 void *data
= malloc(total_size
);
292 enum isl_aux_state
**per_level_arr
= data
;
293 enum isl_aux_state
*s
= data
+ per_level_array_size
;
294 for (uint32_t level
= 0; level
< levels
; level
++) {
295 per_level_arr
[level
] = s
;
296 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
297 for (uint32_t a
= 0; a
< level_layers
; a
++)
300 assert((void *)s
== data
+ total_size
);
302 return per_level_arr
;
306 free_aux_state_map(enum isl_aux_state
**state
)
312 need_to_retile_as_linear(struct brw_context
*brw
, unsigned blt_pitch
,
313 enum isl_tiling tiling
, unsigned samples
)
318 if (tiling
== ISL_TILING_LINEAR
)
321 if (blt_pitch
>= 32768) {
322 perf_debug("blt pitch %u too large to blit, falling back to untiled",
331 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
332 enum isl_tiling tiling
)
334 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
336 /* If the BO is too large to fit in the aperture, we need to use the
337 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
338 * handle Y-tiling, so we need to fall back to X.
340 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
341 tiling
== ISL_TILING_Y0
)
347 static struct intel_mipmap_tree
*
348 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
349 unsigned first_level
, unsigned last_level
,
350 unsigned width0
, unsigned height0
, unsigned depth0
,
351 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
352 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
353 unsigned row_pitch_B
, struct brw_bo
*bo
)
355 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
359 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
367 if (target
== GL_TEXTURE_CUBE_MAP
||
368 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
369 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
371 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
373 _mesa_enum_to_string(target
),
374 _mesa_get_format_name(format
),
375 num_samples
, width0
, height0
, depth0
,
376 first_level
, last_level
, mt
);
378 struct isl_surf_init_info init_info
= {
379 .dim
= get_isl_surf_dim(target
),
380 .format
= translate_tex_format(brw
, format
, false),
383 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
384 .levels
= last_level
- first_level
+ 1,
385 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
386 .samples
= num_samples
,
387 .row_pitch_B
= row_pitch_B
,
388 .usage
= isl_usage_flags
,
389 .tiling_flags
= tiling_flags
,
392 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
395 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
396 * on gen7 platforms we also need to create Y-tiled copies of stencil for
397 * texturing since the hardware can't sample from W-tiled surfaces. For
398 * everything else, check for corner cases needing special treatment.
400 bool is_depth_stencil
=
401 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
402 if (!is_depth_stencil
) {
403 if (need_to_retile_as_linear(brw
, intel_miptree_blt_pitch(mt
),
404 mt
->surf
.tiling
, mt
->surf
.samples
)) {
405 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
406 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
408 } else if (need_to_retile_as_x(brw
, mt
->surf
.size_B
, mt
->surf
.tiling
)) {
409 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
410 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
415 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
416 * the size may not be multiple of row_pitch.
417 * See isl_apply_surface_padding().
419 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
420 assert(mt
->surf
.size_B
% mt
->surf
.row_pitch_B
== 0);
423 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
426 isl_tiling_to_i915_tiling(
428 mt
->surf
.row_pitch_B
, alloc_flags
);
435 mt
->first_level
= first_level
;
436 mt
->last_level
= last_level
;
439 mt
->aux_state
= NULL
;
440 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
441 mt
->compressed
= _mesa_is_format_compressed(format
);
442 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
447 intel_miptree_release(&mt
);
451 /* Return the usual surface usage flags for the given format. */
452 static isl_surf_usage_flags_t
453 mt_surf_usage(mesa_format format
)
455 switch(_mesa_get_format_base_format(format
)) {
456 case GL_DEPTH_COMPONENT
:
457 return ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
458 case GL_DEPTH_STENCIL
:
459 return ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
460 ISL_SURF_USAGE_TEXTURE_BIT
;
461 case GL_STENCIL_INDEX
:
462 return ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
464 return ISL_SURF_USAGE_RENDER_TARGET_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
468 static struct intel_mipmap_tree
*
469 miptree_create(struct brw_context
*brw
,
478 enum intel_miptree_create_flags flags
)
480 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
481 const uint32_t alloc_flags
=
482 (flags
& MIPTREE_CREATE_BUSY
|| num_samples
> 1) ? BO_ALLOC_BUSY
: 0;
483 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
485 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
486 if (devinfo
->gen
< 6 && _mesa_is_format_color_format(format
))
487 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
489 mesa_format mt_fmt
= format
;
490 if (!_mesa_is_format_color_format(format
) && devinfo
->gen
>= 6) {
491 /* Fix up the Z miptree format for how we're splitting out separate
492 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
494 mt_fmt
= intel_depth_format_for_depthstencil_format(format
);
497 struct intel_mipmap_tree
*mt
=
498 make_surface(brw
, target
, mt_fmt
, first_level
, last_level
,
499 width0
, height0
, depth0
, num_samples
,
500 tiling_flags
, mt_surf_usage(mt_fmt
),
501 alloc_flags
, 0, NULL
);
506 if (intel_miptree_needs_fake_etc(brw
, mt
)) {
507 mesa_format decomp_format
= intel_lower_compressed_format(brw
, format
);
508 mt
->shadow_mt
= make_surface(brw
, target
, decomp_format
, first_level
,
509 last_level
, width0
, height0
, depth0
,
510 num_samples
, tiling_flags
,
511 mt_surf_usage(decomp_format
),
512 alloc_flags
, 0, NULL
);
514 if (mt
->shadow_mt
== NULL
) {
515 intel_miptree_release(&mt
);
520 if (needs_separate_stencil(brw
, mt
, format
)) {
522 make_surface(brw
, target
, MESA_FORMAT_S_UINT8
, first_level
, last_level
,
523 width0
, height0
, depth0
, num_samples
,
524 ISL_TILING_W_BIT
, mt_surf_usage(MESA_FORMAT_S_UINT8
),
525 alloc_flags
, 0, NULL
);
526 if (mt
->stencil_mt
== NULL
) {
527 intel_miptree_release(&mt
);
532 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
533 intel_miptree_choose_aux_usage(brw
, mt
);
538 struct intel_mipmap_tree
*
539 intel_miptree_create(struct brw_context
*brw
,
548 enum intel_miptree_create_flags flags
)
550 assert(num_samples
> 0);
552 struct intel_mipmap_tree
*mt
= miptree_create(
554 first_level
, last_level
,
555 width0
, height0
, depth0
, num_samples
,
562 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
563 * compress clear color so we wait until an actual fast-clear to allocate
566 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
567 !intel_miptree_alloc_aux(brw
, mt
)) {
568 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
569 mt
->supports_fast_clear
= false;
575 struct intel_mipmap_tree
*
576 intel_miptree_create_for_bo(struct brw_context
*brw
,
584 enum isl_tiling tiling
,
585 enum intel_miptree_create_flags flags
)
587 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
588 struct intel_mipmap_tree
*mt
;
589 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
590 const GLenum base_format
= _mesa_get_format_base_format(format
);
592 if ((base_format
== GL_DEPTH_COMPONENT
||
593 base_format
== GL_DEPTH_STENCIL
)) {
594 const mesa_format mt_fmt
= (devinfo
->gen
< 6) ? format
:
595 intel_depth_format_for_depthstencil_format(format
);
596 mt
= make_surface(brw
, target
, mt_fmt
,
597 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
598 mt_surf_usage(mt_fmt
),
603 brw_bo_reference(bo
);
605 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
606 intel_miptree_choose_aux_usage(brw
, mt
);
609 } else if (format
== MESA_FORMAT_S_UINT8
) {
610 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
611 0, 0, width
, height
, depth
, 1,
613 mt_surf_usage(MESA_FORMAT_S_UINT8
),
618 assert(bo
->size
>= mt
->surf
.size_B
);
620 brw_bo_reference(bo
);
624 /* Nothing will be able to use this miptree with the BO if the offset isn't
627 if (tiling
!= ISL_TILING_LINEAR
)
628 assert(offset
% 4096 == 0);
630 /* miptrees can't handle negative pitch. If you need flipping of images,
631 * that's outside of the scope of the mt.
635 mt
= make_surface(brw
, target
, format
,
636 0, 0, width
, height
, depth
, 1,
638 mt_surf_usage(format
),
643 brw_bo_reference(bo
);
647 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
648 intel_miptree_choose_aux_usage(brw
, mt
);
650 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
651 * only compress clear color so we wait until an actual fast-clear to
654 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
655 !intel_miptree_alloc_aux(brw
, mt
)) {
656 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
657 mt
->supports_fast_clear
= false;
664 static struct intel_mipmap_tree
*
665 miptree_create_for_planar_image(struct brw_context
*brw
,
666 __DRIimage
*image
, GLenum target
,
667 enum isl_tiling tiling
)
669 const struct intel_image_format
*f
= image
->planar_format
;
670 struct intel_mipmap_tree
*planar_mt
= NULL
;
672 for (int i
= 0; i
< f
->nplanes
; i
++) {
673 const int index
= f
->planes
[i
].buffer_index
;
674 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
675 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
676 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
677 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
679 /* Disable creation of the texture's aux buffers because the driver
680 * exposes no EGL API to manage them. That is, there is no API for
681 * resolving the aux buffer's content to the main buffer nor for
682 * invalidating the aux buffer's content.
684 struct intel_mipmap_tree
*mt
=
685 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
686 image
->offsets
[index
],
688 image
->strides
[index
],
690 MIPTREE_CREATE_NO_AUX
);
692 intel_miptree_release(&planar_mt
);
701 planar_mt
->plane
[i
- 1] = mt
;
704 planar_mt
->drm_modifier
= image
->modifier
;
710 create_ccs_buf_for_image(struct brw_context
*brw
,
712 struct intel_mipmap_tree
*mt
,
713 enum isl_aux_state initial_state
)
715 struct isl_surf temp_ccs_surf
;
717 /* CCS is only supported for very simple miptrees */
718 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
719 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
720 assert(mt
->surf
.samples
== 1);
721 assert(mt
->surf
.levels
== 1);
722 assert(mt
->surf
.logical_level0_px
.depth
== 1);
723 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
724 assert(mt
->first_level
== 0);
725 assert(mt
->last_level
== 0);
727 /* We shouldn't already have a CCS */
728 assert(!mt
->aux_buf
);
730 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
734 assert(image
->aux_offset
< image
->bo
->size
);
735 assert(temp_ccs_surf
.size_B
<= image
->bo
->size
- image
->aux_offset
);
737 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
738 if (mt
->aux_buf
== NULL
)
741 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
742 if (!mt
->aux_state
) {
748 /* On gen10+ we start using an extra space in the aux buffer to store the
749 * indirect clear color. However, if we imported an image from the window
750 * system with CCS, we don't have the extra space at the end of the aux
751 * buffer. So create a new bo here that will store that clear color.
753 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
754 mt
->aux_buf
->clear_color_bo
=
755 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
756 brw
->isl_dev
.ss
.clear_color_state_size
,
757 BRW_MEMZONE_OTHER
, I915_TILING_NONE
, 0,
759 if (!mt
->aux_buf
->clear_color_bo
) {
766 mt
->aux_buf
->bo
= image
->bo
;
767 brw_bo_reference(image
->bo
);
769 mt
->aux_buf
->offset
= image
->aux_offset
;
770 mt
->aux_buf
->surf
= temp_ccs_surf
;
775 struct intel_mipmap_tree
*
776 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
777 __DRIimage
*image
, GLenum target
,
779 bool allow_internal_aux
)
781 uint32_t bo_tiling
, bo_swizzle
;
782 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
784 const struct isl_drm_modifier_info
*mod_info
=
785 isl_drm_modifier_get_info(image
->modifier
);
787 const enum isl_tiling tiling
=
788 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
790 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
791 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
793 if (image
->planar_format
)
794 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
796 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
797 /* The texture storage paths in core Mesa detect if the driver does not
798 * support the user-requested format, and then searches for a
799 * fallback format. The DRIimage code bypasses core Mesa, though. So we
800 * do the fallbacks here for important formats.
802 * We must support DRM_FOURCC_XBGR8888 textures because the Android
803 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
804 * the Chrome OS compositor consumes as dma_buf EGLImages.
806 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
809 if (!brw
->ctx
.TextureFormatSupported
[format
])
812 enum intel_miptree_create_flags mt_create_flags
= 0;
814 /* If this image comes in from a window system, we have different
815 * requirements than if it comes in via an EGL import operation. Window
816 * system images can use any form of auxiliary compression we wish because
817 * they get "flushed" before being handed off to the window system and we
818 * have the opportunity to do resolves. Non window-system images, on the
819 * other hand, have no resolve point so we can't have aux without a
822 if (!allow_internal_aux
)
823 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
825 /* If we have a modifier which specifies aux, don't create one yet */
826 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
827 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
829 /* Disable creation of the texture's aux buffers because the driver exposes
830 * no EGL API to manage them. That is, there is no API for resolving the aux
831 * buffer's content to the main buffer nor for invalidating the aux buffer's
834 struct intel_mipmap_tree
*mt
=
835 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
836 image
->offset
, image
->width
, image
->height
, 1,
837 image
->pitch
, tiling
, mt_create_flags
);
842 mt
->level
[0].level_x
= image
->tile_x
;
843 mt
->level
[0].level_y
= image
->tile_y
;
844 mt
->drm_modifier
= image
->modifier
;
846 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
847 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
848 * trouble resolving back to destination image due to alignment issues.
850 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
851 if (!devinfo
->has_surface_tile_offset
) {
852 uint32_t draw_x
, draw_y
;
853 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
855 if (draw_x
!= 0 || draw_y
!= 0) {
856 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
857 intel_miptree_release(&mt
);
862 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
863 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
865 mt
->aux_usage
= mod_info
->aux_usage
;
866 /* If we are a window system buffer, then we can support fast-clears
867 * even if the modifier doesn't support them by doing a partial resolve
868 * as part of the flush operation.
870 mt
->supports_fast_clear
=
871 allow_internal_aux
|| mod_info
->supports_clear_color
;
873 /* We don't know the actual state of the surface when we get it but we
874 * can make a pretty good guess based on the modifier. What we do know
875 * for sure is that it isn't in the AUX_INVALID state, so we just assume
876 * a worst case of compression.
878 enum isl_aux_state initial_state
=
879 isl_drm_modifier_get_default_aux_state(image
->modifier
);
881 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
882 intel_miptree_release(&mt
);
887 /* Don't assume coherency for imported EGLimages. We don't know what
888 * external clients are going to do with it. They may scan it out.
890 image
->bo
->cache_coherent
= false;
896 * For a singlesample renderbuffer, this simply wraps the given BO with a
899 * For a multisample renderbuffer, this wraps the window system's
900 * (singlesample) BO with a singlesample miptree attached to the
901 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
902 * that will contain the actual rendering (which is lazily resolved to
903 * irb->singlesample_mt).
906 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
907 struct intel_renderbuffer
*irb
,
908 struct intel_mipmap_tree
*singlesample_mt
,
909 uint32_t width
, uint32_t height
,
912 struct intel_mipmap_tree
*multisample_mt
= NULL
;
913 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
914 mesa_format format
= rb
->Format
;
915 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
917 /* Only the front and back buffers, which are color buffers, are allocated
918 * through the image loader.
920 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
921 _mesa_get_format_base_format(format
) == GL_RGBA
);
923 assert(singlesample_mt
);
925 if (num_samples
== 1) {
926 intel_miptree_release(&irb
->mt
);
927 irb
->mt
= singlesample_mt
;
929 assert(!irb
->singlesample_mt
);
931 intel_miptree_release(&irb
->singlesample_mt
);
932 irb
->singlesample_mt
= singlesample_mt
;
935 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
936 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
937 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
945 irb
->need_downsample
= false;
946 intel_miptree_release(&irb
->mt
);
947 irb
->mt
= multisample_mt
;
953 intel_miptree_release(&irb
->mt
);
957 struct intel_mipmap_tree
*
958 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
962 uint32_t num_samples
)
964 struct intel_mipmap_tree
*mt
;
966 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
968 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
969 width
, height
, depth
, num_samples
,
970 MIPTREE_CREATE_BUSY
);
977 intel_miptree_release(&mt
);
982 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
983 struct intel_mipmap_tree
*src
)
988 intel_miptree_release(dst
);
992 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
999 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1001 if (aux_buf
== NULL
)
1004 brw_bo_unreference(aux_buf
->bo
);
1005 brw_bo_unreference(aux_buf
->clear_color_bo
);
1011 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1016 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1017 if (--(*mt
)->refcount
<= 0) {
1020 DBG("%s deleting %p\n", __func__
, *mt
);
1022 brw_bo_unreference((*mt
)->bo
);
1023 intel_miptree_release(&(*mt
)->stencil_mt
);
1024 intel_miptree_release(&(*mt
)->shadow_mt
);
1025 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1026 free_aux_state_map((*mt
)->aux_state
);
1028 intel_miptree_release(&(*mt
)->plane
[0]);
1029 intel_miptree_release(&(*mt
)->plane
[1]);
1031 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1032 free((*mt
)->level
[i
].slice
);
1042 intel_get_image_dims(struct gl_texture_image
*image
,
1043 int *width
, int *height
, int *depth
)
1045 switch (image
->TexObject
->Target
) {
1046 case GL_TEXTURE_1D_ARRAY
:
1047 /* For a 1D Array texture the OpenGL API will treat the image height as
1048 * the number of array slices. For Intel hardware, we treat the 1D array
1049 * as a 2D Array with a height of 1. So, here we want to swap image
1052 assert(image
->Depth
== 1);
1053 *width
= image
->Width
;
1055 *depth
= image
->Height
;
1057 case GL_TEXTURE_CUBE_MAP
:
1058 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1059 * though we really have 6 slices.
1061 assert(image
->Depth
== 1);
1062 *width
= image
->Width
;
1063 *height
= image
->Height
;
1067 *width
= image
->Width
;
1068 *height
= image
->Height
;
1069 *depth
= image
->Depth
;
1075 * Can the image be pulled into a unified mipmap tree? This mirrors
1076 * the completeness test in a lot of ways.
1078 * Not sure whether I want to pass gl_texture_image here.
1081 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1082 struct gl_texture_image
*image
)
1084 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1085 GLuint level
= intelImage
->base
.Base
.Level
;
1086 int width
, height
, depth
;
1088 /* glTexImage* choose the texture object based on the target passed in, and
1089 * objects can't change targets over their lifetimes, so this should be
1092 assert(image
->TexObject
->Target
== mt
->target
);
1094 mesa_format mt_format
= mt
->format
;
1095 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1096 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1097 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1098 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1100 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1101 _mesa_get_srgb_format_linear(mt_format
))
1104 intel_get_image_dims(image
, &width
, &height
, &depth
);
1106 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1109 if (level
>= mt
->surf
.levels
)
1112 const unsigned level_depth
=
1113 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1114 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1115 mt
->surf
.logical_level0_px
.array_len
;
1117 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1118 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1119 depth
== level_depth
&&
1120 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1124 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1125 GLuint level
, GLuint slice
,
1126 GLuint
*x
, GLuint
*y
)
1128 if (level
== 0 && slice
== 0) {
1129 *x
= mt
->level
[0].level_x
;
1130 *y
= mt
->level
[0].level_y
;
1134 uint32_t x_offset_sa
, y_offset_sa
;
1136 /* Miptree itself can have an offset only if it represents a single
1137 * slice in an imported buffer object.
1138 * See intel_miptree_create_for_dri_image().
1140 assert(mt
->level
[0].level_x
== 0);
1141 assert(mt
->level
[0].level_y
== 0);
1143 /* Given level is relative to level zero while the miptree may be
1144 * represent just a subset of all levels starting from 'first_level'.
1146 assert(level
>= mt
->first_level
);
1147 level
-= mt
->first_level
;
1149 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1150 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1151 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1152 &x_offset_sa
, &y_offset_sa
);
1160 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1161 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1162 * and tile_h is set to 1.
1165 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1166 uint32_t *tile_w
, uint32_t *tile_h
)
1177 case ISL_TILING_LINEAR
:
1182 unreachable("not reached");
1188 * This function computes masks that may be used to select the bits of the X
1189 * and Y coordinates that indicate the offset within a tile. If the BO is
1190 * untiled, the masks are set to 0.
1193 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1194 uint32_t *mask_x
, uint32_t *mask_y
)
1196 uint32_t tile_w_bytes
, tile_h
;
1198 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1200 *mask_x
= tile_w_bytes
/ cpp
- 1;
1201 *mask_y
= tile_h
- 1;
1205 * Compute the offset (in bytes) from the start of the BO to the given x
1206 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1207 * multiples of the tile size.
1210 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1211 uint32_t x
, uint32_t y
)
1214 uint32_t pitch
= mt
->surf
.row_pitch_B
;
1216 switch (mt
->surf
.tiling
) {
1218 unreachable("not reached");
1219 case ISL_TILING_LINEAR
:
1220 return y
* pitch
+ x
* cpp
;
1222 assert((x
% (512 / cpp
)) == 0);
1223 assert((y
% 8) == 0);
1224 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1226 assert((x
% (128 / cpp
)) == 0);
1227 assert((y
% 32) == 0);
1228 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1233 * Rendering with tiled buffers requires that the base address of the buffer
1234 * be aligned to a page boundary. For renderbuffers, and sometimes with
1235 * textures, we may want the surface to point at a texture image level that
1236 * isn't at a page boundary.
1238 * This function returns an appropriately-aligned base offset
1239 * according to the tiling restrictions, plus any required x/y offset
1243 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1244 GLuint level
, GLuint slice
,
1249 uint32_t mask_x
, mask_y
;
1251 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1252 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1254 *tile_x
= x
& mask_x
;
1255 *tile_y
= y
& mask_y
;
1257 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1261 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1262 struct intel_mipmap_tree
*src_mt
,
1263 unsigned src_level
, unsigned src_layer
,
1264 struct intel_mipmap_tree
*dst_mt
,
1265 unsigned dst_level
, unsigned dst_layer
,
1266 unsigned width
, unsigned height
)
1269 ptrdiff_t src_stride
, dst_stride
;
1270 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1272 intel_miptree_map(brw
, src_mt
,
1273 src_level
, src_layer
,
1276 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1279 intel_miptree_map(brw
, dst_mt
,
1280 dst_level
, dst_layer
,
1283 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1287 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1288 _mesa_get_format_name(src_mt
->format
),
1289 src_mt
, src
, src_stride
,
1290 _mesa_get_format_name(dst_mt
->format
),
1291 dst_mt
, dst
, dst_stride
,
1294 int row_size
= cpp
* width
;
1295 if (src_stride
== row_size
&&
1296 dst_stride
== row_size
) {
1297 memcpy(dst
, src
, row_size
* height
);
1299 for (int i
= 0; i
< height
; i
++) {
1300 memcpy(dst
, src
, row_size
);
1306 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1307 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1309 /* Don't forget to copy the stencil data over, too. We could have skipped
1310 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1311 * shuffling the two data sources in/out of temporary storage instead of
1312 * the direct mapping we get this way.
1314 if (dst_mt
->stencil_mt
) {
1315 assert(src_mt
->stencil_mt
);
1316 intel_miptree_copy_slice_sw(brw
,
1317 src_mt
->stencil_mt
, src_level
, src_layer
,
1318 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1324 intel_miptree_copy_slice(struct brw_context
*brw
,
1325 struct intel_mipmap_tree
*src_mt
,
1326 unsigned src_level
, unsigned src_layer
,
1327 struct intel_mipmap_tree
*dst_mt
,
1328 unsigned dst_level
, unsigned dst_layer
)
1331 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1332 mesa_format format
= src_mt
->format
;
1333 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1334 src_level
- src_mt
->first_level
);
1335 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1336 src_level
- src_mt
->first_level
);
1338 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1339 src_level
- src_mt
->first_level
));
1341 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1342 _mesa_get_srgb_format_linear(dst_mt
->format
));
1344 DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
1345 _mesa_get_format_name(src_mt
->format
),
1346 src_mt
, src_level
, src_layer
,
1347 _mesa_get_format_name(dst_mt
->format
),
1348 dst_mt
, dst_level
, dst_layer
,
1351 if (devinfo
->gen
>= 6) {
1352 /* On gen6 and above, we just use blorp. It's faster than the blitter
1353 * and can handle everything without software fallbacks.
1355 brw_blorp_copy_miptrees(brw
,
1356 src_mt
, src_level
, src_layer
,
1357 dst_mt
, dst_level
, dst_layer
,
1358 0, 0, 0, 0, width
, height
);
1360 if (src_mt
->stencil_mt
) {
1361 assert(dst_mt
->stencil_mt
);
1362 brw_blorp_copy_miptrees(brw
,
1363 src_mt
->stencil_mt
, src_level
, src_layer
,
1364 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1365 0, 0, 0, 0, width
, height
);
1370 if (dst_mt
->compressed
) {
1372 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1373 height
= ALIGN_NPOT(height
, j
) / j
;
1374 width
= ALIGN_NPOT(width
, i
) / i
;
1377 /* Gen4-5 doesn't support separate stencil */
1378 assert(!src_mt
->stencil_mt
);
1380 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1381 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1383 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1386 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1387 _mesa_get_format_name(src_mt
->format
),
1388 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch_B
,
1389 _mesa_get_format_name(dst_mt
->format
),
1390 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch_B
,
1393 if (!intel_miptree_blit(brw
,
1394 src_mt
, src_level
, src_layer
, 0, 0, false,
1395 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1396 width
, height
, COLOR_LOGICOP_COPY
)) {
1397 perf_debug("miptree validate blit for %s failed\n",
1398 _mesa_get_format_name(format
));
1400 intel_miptree_copy_slice_sw(brw
,
1401 src_mt
, src_level
, src_layer
,
1402 dst_mt
, dst_level
, dst_layer
,
1408 * Copies the image's current data to the given miptree, and associates that
1409 * miptree with the image.
1412 intel_miptree_copy_teximage(struct brw_context
*brw
,
1413 struct intel_texture_image
*intelImage
,
1414 struct intel_mipmap_tree
*dst_mt
)
1416 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1417 struct intel_texture_object
*intel_obj
=
1418 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1419 int level
= intelImage
->base
.Base
.Level
;
1420 const unsigned face
= intelImage
->base
.Base
.Face
;
1421 unsigned start_layer
, end_layer
;
1423 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1425 assert(intelImage
->base
.Base
.Height
);
1427 end_layer
= intelImage
->base
.Base
.Height
- 1;
1428 } else if (face
> 0) {
1432 assert(intelImage
->base
.Base
.Depth
);
1434 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1437 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1438 intel_miptree_copy_slice(brw
,
1443 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1444 intel_obj
->needs_validate
= true;
1447 static struct intel_miptree_aux_buffer
*
1448 intel_alloc_aux_buffer(struct brw_context
*brw
,
1449 const struct isl_surf
*aux_surf
,
1451 uint8_t memset_value
)
1453 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1457 uint64_t size
= aux_surf
->size_B
;
1459 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1460 if (has_indirect_clear
) {
1461 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1462 * will set a pointer to a dword somewhere that contains the color. So,
1463 * allocate the space for the clear color value here on the aux buffer.
1465 buf
->clear_color_offset
= size
;
1466 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1469 /* If the buffer needs to be initialised (requiring the buffer to be
1470 * immediately mapped to cpu space for writing), do not use the gpu access
1471 * flag which can cause an unnecessary delay if the backing pages happened
1472 * to be just used by the GPU.
1474 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1475 const bool needs_memset
=
1476 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1477 const uint32_t alloc_flags
=
1478 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1480 /* ISL has stricter set of alignment rules then the drm allocator.
1481 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1482 * trying to recalculate based on different format block sizes.
1484 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1485 BRW_MEMZONE_OTHER
, I915_TILING_Y
,
1486 aux_surf
->row_pitch_B
, alloc_flags
);
1492 /* Initialize the bo to the desired value */
1494 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1496 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1498 intel_miptree_aux_buffer_free(buf
);
1502 /* Memset the aux_surf portion of the BO. */
1504 memset(map
, memset_value
, aux_surf
->size_B
);
1506 /* Zero the indirect clear color to match ::fast_clear_color. */
1507 if (has_indirect_clear
) {
1508 memset((char *)map
+ buf
->clear_color_offset
, 0,
1509 brw
->isl_dev
.ss
.clear_color_state_size
);
1512 brw_bo_unmap(buf
->bo
);
1515 if (has_indirect_clear
) {
1516 buf
->clear_color_bo
= buf
->bo
;
1517 brw_bo_reference(buf
->clear_color_bo
);
1520 buf
->surf
= *aux_surf
;
1527 * Helper for intel_miptree_alloc_aux() that sets
1528 * \c mt->level[level].has_hiz. Return true if and only if
1529 * \c has_hiz was set.
1532 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1533 struct intel_mipmap_tree
*mt
,
1536 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1538 assert(mt
->aux_buf
);
1539 assert(mt
->surf
.size_B
> 0);
1541 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1542 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1543 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1545 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1546 * and the height is 4 aligned. This allows our HiZ support
1547 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1548 * we can grow the width & height to allow the HiZ op to
1549 * force the proper size alignments.
1551 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1552 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1557 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1558 mt
->level
[level
].has_hiz
= true;
1564 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1566 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1567 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1568 * compress clear color so we wait until an actual fast-clear to allocate it.
1571 intel_miptree_alloc_aux(struct brw_context
*brw
,
1572 struct intel_mipmap_tree
*mt
)
1574 assert(mt
->aux_buf
== NULL
);
1576 /* Get the aux buf allocation parameters for this miptree. */
1577 enum isl_aux_state initial_state
;
1578 uint8_t memset_value
;
1579 struct isl_surf aux_surf
;
1580 bool aux_surf_ok
= false;
1582 switch (mt
->aux_usage
) {
1583 case ISL_AUX_USAGE_NONE
:
1584 aux_surf
.size_B
= 0;
1587 case ISL_AUX_USAGE_HIZ
:
1588 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1590 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1592 case ISL_AUX_USAGE_MCS
:
1593 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1595 * When MCS buffer is enabled and bound to MSRT, it is required that
1596 * it is cleared prior to any rendering.
1598 * Since we don't use the MCS buffer for any purpose other than
1599 * rendering, it makes sense to just clear it immediately upon
1602 * Note: the clear value for MCS buffers is all 1's, so we memset to
1605 initial_state
= ISL_AUX_STATE_CLEAR
;
1606 memset_value
= 0xFF;
1607 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1609 case ISL_AUX_USAGE_CCS_D
:
1610 case ISL_AUX_USAGE_CCS_E
:
1611 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1612 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1615 * "If Software wants to enable Color Compression without Fast
1616 * clear, Software needs to initialize MCS with zeros."
1618 * A CCS value of 0 indicates that the corresponding block is in the
1619 * pass-through state which is what we want.
1621 * For CCS_D, do the same thing. On gen9+, this avoids having any
1622 * undefined bits in the aux buffer.
1624 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1627 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1631 unreachable("Invalid aux usage");
1634 /* We should have a valid aux_surf. */
1638 /* No work is needed for a zero-sized auxiliary buffer. */
1639 if (aux_surf
.size_B
== 0)
1642 /* Create the aux_state for the auxiliary buffer. */
1643 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1644 if (mt
->aux_state
== NULL
)
1647 /* Allocate the auxiliary buffer. */
1648 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1649 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1651 if (mt
->aux_buf
== NULL
) {
1652 free_aux_state_map(mt
->aux_state
);
1653 mt
->aux_state
= NULL
;
1657 /* Perform aux_usage-specific initialization. */
1658 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1659 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1660 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1668 * Can the miptree sample using the hiz buffer?
1671 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1672 struct intel_mipmap_tree
*mt
)
1674 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1676 if (!devinfo
->has_sample_with_hiz
) {
1684 /* It seems the hardware won't fallback to the depth buffer if some of the
1685 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1686 * of the texture to be HiZ enabled.
1688 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1689 if (!intel_miptree_level_has_hiz(mt
, level
))
1693 /* If compressed multisampling is enabled, then we use it for the auxiliary
1696 * From the BDW PRM (Volume 2d: Command Reference: Structures
1697 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1699 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1700 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1702 * There is no such blurb for 1D textures, but there is sufficient evidence
1703 * that this is broken on SKL+.
1705 return (mt
->surf
.samples
== 1 &&
1706 mt
->target
!= GL_TEXTURE_3D
&&
1707 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1711 * Does the miptree slice have hiz enabled?
1714 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1716 intel_miptree_check_level_layer(mt
, level
, 0);
1717 return mt
->level
[level
].has_hiz
;
1720 static inline uint32_t
1721 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1722 uint32_t start_level
, uint32_t num_levels
)
1724 assert(start_level
>= mt
->first_level
);
1725 assert(start_level
<= mt
->last_level
);
1727 if (num_levels
== INTEL_REMAINING_LAYERS
)
1728 num_levels
= mt
->last_level
- start_level
+ 1;
1729 /* Check for overflow */
1730 assert(start_level
+ num_levels
>= start_level
);
1731 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1736 static inline uint32_t
1737 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1738 uint32_t start_layer
, uint32_t num_layers
)
1740 assert(level
<= mt
->last_level
);
1742 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1743 assert(start_layer
< total_num_layers
);
1744 if (num_layers
== INTEL_REMAINING_LAYERS
)
1745 num_layers
= total_num_layers
- start_layer
;
1746 /* Check for overflow */
1747 assert(start_layer
+ num_layers
>= start_layer
);
1748 assert(start_layer
+ num_layers
<= total_num_layers
);
1754 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1755 unsigned start_level
, unsigned num_levels
,
1756 unsigned start_layer
, unsigned num_layers
)
1758 assert(_mesa_is_format_color_format(mt
->format
));
1763 /* Clamp the level range to fit the miptree */
1764 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1766 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1767 const uint32_t level
= start_level
+ l
;
1768 const uint32_t level_layers
=
1769 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1770 for (unsigned a
= 0; a
< level_layers
; a
++) {
1771 enum isl_aux_state aux_state
=
1772 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1773 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1774 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1783 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1784 const struct intel_mipmap_tree
*mt
,
1785 unsigned level
, unsigned layer
)
1790 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1791 assert(brw
->screen
->devinfo
.gen
>= 8 ||
1792 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1794 /* Compression of arrayed msaa surfaces is supported. */
1795 if (mt
->surf
.samples
> 1)
1798 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1799 assert(brw
->screen
->devinfo
.gen
>= 8 ||
1801 mt
->surf
.logical_level0_px
.depth
== 1 &&
1802 mt
->surf
.logical_level0_px
.array_len
== 1));
1808 static enum isl_aux_op
1809 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1810 enum isl_aux_usage aux_usage
,
1811 bool fast_clear_supported
)
1813 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
1815 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
1817 assert(ccs_supported
== fast_clear_supported
);
1819 switch (aux_state
) {
1820 case ISL_AUX_STATE_CLEAR
:
1821 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1823 return ISL_AUX_OP_FULL_RESOLVE
;
1825 return ISL_AUX_OP_NONE
;
1827 case ISL_AUX_STATE_PASS_THROUGH
:
1828 return ISL_AUX_OP_NONE
;
1830 case ISL_AUX_STATE_RESOLVED
:
1831 case ISL_AUX_STATE_AUX_INVALID
:
1832 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1833 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1837 unreachable("Invalid aux state for CCS_D");
1840 static enum isl_aux_op
1841 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
1842 enum isl_aux_usage aux_usage
,
1843 bool fast_clear_supported
)
1845 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
1846 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1847 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1848 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1850 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
1851 assert(fast_clear_supported
);
1853 switch (aux_state
) {
1854 case ISL_AUX_STATE_CLEAR
:
1855 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1856 if (fast_clear_supported
)
1857 return ISL_AUX_OP_NONE
;
1858 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
1859 return ISL_AUX_OP_PARTIAL_RESOLVE
;
1861 return ISL_AUX_OP_FULL_RESOLVE
;
1863 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1864 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1865 return ISL_AUX_OP_FULL_RESOLVE
;
1866 else if (!fast_clear_supported
)
1867 return ISL_AUX_OP_PARTIAL_RESOLVE
;
1869 return ISL_AUX_OP_NONE
;
1871 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1872 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1873 return ISL_AUX_OP_FULL_RESOLVE
;
1875 return ISL_AUX_OP_NONE
;
1877 case ISL_AUX_STATE_PASS_THROUGH
:
1878 return ISL_AUX_OP_NONE
;
1880 case ISL_AUX_STATE_RESOLVED
:
1881 case ISL_AUX_STATE_AUX_INVALID
:
1885 unreachable("Invalid aux state for CCS_E");
1889 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
1890 struct intel_mipmap_tree
*mt
,
1891 uint32_t level
, uint32_t layer
,
1892 enum isl_aux_usage aux_usage
,
1893 bool fast_clear_supported
)
1895 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
1897 enum isl_aux_op resolve_op
;
1898 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1899 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
1900 fast_clear_supported
);
1902 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1903 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
1904 fast_clear_supported
);
1907 if (resolve_op
!= ISL_AUX_OP_NONE
) {
1908 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
1909 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
1911 switch (resolve_op
) {
1912 case ISL_AUX_OP_FULL_RESOLVE
:
1913 /* The CCS full resolve operation destroys the CCS and sets it to the
1914 * pass-through state. (You can also think of this as being both a
1915 * resolve and an ambiguate in one operation.)
1917 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
1918 ISL_AUX_STATE_PASS_THROUGH
);
1921 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1922 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
1923 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1927 unreachable("Invalid resolve op");
1933 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
1934 struct intel_mipmap_tree
*mt
,
1935 uint32_t level
, uint32_t layer
,
1936 enum isl_aux_usage aux_usage
)
1938 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1939 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1940 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1942 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
1944 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1945 switch (aux_state
) {
1946 case ISL_AUX_STATE_CLEAR
:
1947 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1948 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
1949 aux_usage
== ISL_AUX_USAGE_CCS_D
);
1951 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1952 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
1953 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1954 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
1955 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
1956 ISL_AUX_STATE_PARTIAL_CLEAR
);
1960 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1961 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1962 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
1963 break; /* Nothing to do */
1965 case ISL_AUX_STATE_PASS_THROUGH
:
1966 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1967 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
1968 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1974 case ISL_AUX_STATE_RESOLVED
:
1975 case ISL_AUX_STATE_AUX_INVALID
:
1976 unreachable("Invalid aux state for CCS_E");
1979 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1980 /* CCS_D is a bit simpler */
1981 switch (aux_state
) {
1982 case ISL_AUX_STATE_CLEAR
:
1983 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
1984 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
1985 ISL_AUX_STATE_PARTIAL_CLEAR
);
1988 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1989 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
1990 break; /* Nothing to do */
1992 case ISL_AUX_STATE_PASS_THROUGH
:
1996 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1997 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1998 case ISL_AUX_STATE_RESOLVED
:
1999 case ISL_AUX_STATE_AUX_INVALID
:
2000 unreachable("Invalid aux state for CCS_D");
2006 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2007 struct intel_mipmap_tree
*mt
,
2009 enum isl_aux_usage aux_usage
,
2010 bool fast_clear_supported
)
2012 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2014 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2015 case ISL_AUX_STATE_CLEAR
:
2016 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2017 if (!fast_clear_supported
) {
2018 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2019 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2020 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2024 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2025 break; /* Nothing to do */
2027 case ISL_AUX_STATE_RESOLVED
:
2028 case ISL_AUX_STATE_PASS_THROUGH
:
2029 case ISL_AUX_STATE_AUX_INVALID
:
2030 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2031 unreachable("Invalid aux state for MCS");
2036 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2037 struct intel_mipmap_tree
*mt
,
2039 enum isl_aux_usage aux_usage
)
2041 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2043 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2044 case ISL_AUX_STATE_CLEAR
:
2045 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2046 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2049 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2050 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2051 break; /* Nothing to do */
2053 case ISL_AUX_STATE_RESOLVED
:
2054 case ISL_AUX_STATE_PASS_THROUGH
:
2055 case ISL_AUX_STATE_AUX_INVALID
:
2056 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2057 unreachable("Invalid aux state for MCS");
2062 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2063 struct intel_mipmap_tree
*mt
,
2064 uint32_t level
, uint32_t layer
,
2065 enum isl_aux_usage aux_usage
,
2066 bool fast_clear_supported
)
2068 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2070 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2071 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2072 case ISL_AUX_STATE_CLEAR
:
2073 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2074 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2075 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2078 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2079 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2080 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2083 case ISL_AUX_STATE_PASS_THROUGH
:
2084 case ISL_AUX_STATE_RESOLVED
:
2087 case ISL_AUX_STATE_AUX_INVALID
:
2088 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2089 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2092 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2093 unreachable("Invalid HiZ state");
2096 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2097 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2100 case ISL_AUX_OP_FULL_RESOLVE
:
2101 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2102 ISL_AUX_STATE_RESOLVED
);
2105 case ISL_AUX_OP_AMBIGUATE
:
2106 /* The HiZ resolve operation is actually an ambiguate */
2107 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2108 ISL_AUX_STATE_PASS_THROUGH
);
2112 unreachable("Invalid HiZ op");
2118 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2119 struct intel_mipmap_tree
*mt
,
2120 uint32_t level
, uint32_t layer
,
2121 enum isl_aux_usage aux_usage
)
2123 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2125 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2126 case ISL_AUX_STATE_CLEAR
:
2127 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2128 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2129 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2132 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2133 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2134 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2135 break; /* Nothing to do */
2137 case ISL_AUX_STATE_RESOLVED
:
2138 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2139 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2140 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2142 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2143 ISL_AUX_STATE_AUX_INVALID
);
2147 case ISL_AUX_STATE_PASS_THROUGH
:
2148 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2149 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2150 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2154 case ISL_AUX_STATE_AUX_INVALID
:
2155 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2158 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2159 unreachable("Invalid HiZ state");
2164 intel_miptree_prepare_access(struct brw_context
*brw
,
2165 struct intel_mipmap_tree
*mt
,
2166 uint32_t start_level
, uint32_t num_levels
,
2167 uint32_t start_layer
, uint32_t num_layers
,
2168 enum isl_aux_usage aux_usage
,
2169 bool fast_clear_supported
)
2171 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2173 switch (mt
->aux_usage
) {
2174 case ISL_AUX_USAGE_NONE
:
2178 case ISL_AUX_USAGE_MCS
:
2179 assert(mt
->aux_buf
);
2180 assert(start_level
== 0 && num_levels
== 1);
2181 const uint32_t level_layers
=
2182 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2183 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2184 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2185 aux_usage
, fast_clear_supported
);
2189 case ISL_AUX_USAGE_CCS_D
:
2190 case ISL_AUX_USAGE_CCS_E
:
2194 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2195 const uint32_t level
= start_level
+ l
;
2196 const uint32_t level_layers
=
2197 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2198 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2199 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2201 aux_usage
, fast_clear_supported
);
2206 case ISL_AUX_USAGE_HIZ
:
2207 assert(mt
->aux_buf
);
2208 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2209 const uint32_t level
= start_level
+ l
;
2210 if (!intel_miptree_level_has_hiz(mt
, level
))
2213 const uint32_t level_layers
=
2214 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2215 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2216 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2217 aux_usage
, fast_clear_supported
);
2223 unreachable("Invalid aux usage");
2228 intel_miptree_finish_write(struct brw_context
*brw
,
2229 struct intel_mipmap_tree
*mt
, uint32_t level
,
2230 uint32_t start_layer
, uint32_t num_layers
,
2231 enum isl_aux_usage aux_usage
)
2233 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2234 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2236 switch (mt
->aux_usage
) {
2237 case ISL_AUX_USAGE_NONE
:
2238 if (mt
->format
== MESA_FORMAT_S_UINT8
&& devinfo
->gen
<= 7) {
2239 mt
->shadow_needs_update
= true;
2240 } else if (intel_miptree_has_etc_shadow(brw
, mt
)) {
2241 mt
->shadow_needs_update
= true;
2245 case ISL_AUX_USAGE_MCS
:
2246 assert(mt
->aux_buf
);
2247 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2248 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2253 case ISL_AUX_USAGE_CCS_D
:
2254 case ISL_AUX_USAGE_CCS_E
:
2258 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2259 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2264 case ISL_AUX_USAGE_HIZ
:
2265 if (!intel_miptree_level_has_hiz(mt
, level
))
2268 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2269 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2275 unreachable("Invavlid aux usage");
2280 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2281 uint32_t level
, uint32_t layer
)
2283 intel_miptree_check_level_layer(mt
, level
, layer
);
2285 if (_mesa_is_format_color_format(mt
->format
)) {
2286 assert(mt
->aux_buf
!= NULL
);
2287 assert(mt
->surf
.samples
== 1 ||
2288 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2289 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2290 unreachable("Cannot get aux state for stencil");
2292 assert(intel_miptree_level_has_hiz(mt
, level
));
2295 return mt
->aux_state
[level
][layer
];
2299 intel_miptree_set_aux_state(struct brw_context
*brw
,
2300 struct intel_mipmap_tree
*mt
, uint32_t level
,
2301 uint32_t start_layer
, uint32_t num_layers
,
2302 enum isl_aux_state aux_state
)
2304 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2306 if (_mesa_is_format_color_format(mt
->format
)) {
2307 assert(mt
->aux_buf
!= NULL
);
2308 assert(mt
->surf
.samples
== 1 ||
2309 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2310 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2311 unreachable("Cannot get aux state for stencil");
2313 assert(intel_miptree_level_has_hiz(mt
, level
));
2316 for (unsigned a
= 0; a
< num_layers
; a
++) {
2317 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2318 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2319 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2324 /* On Gen9 color buffers may be compressed by the hardware (lossless
2325 * compression). There are, however, format restrictions and care needs to be
2326 * taken that the sampler engine is capable for re-interpreting a buffer with
2327 * format different the buffer was originally written with.
2329 * For example, SRGB formats are not compressible and the sampler engine isn't
2330 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2331 * color buffer needs to be resolved so that the sampling surface can be
2332 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2336 can_texture_with_ccs(struct brw_context
*brw
,
2337 struct intel_mipmap_tree
*mt
,
2338 enum isl_format view_format
)
2340 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2343 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2345 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2346 isl_format_get_layout(view_format
)->name
,
2347 _mesa_get_format_name(mt
->format
));
2355 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 enum isl_format view_format
,
2358 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
2360 assert(brw
->screen
->devinfo
.gen
== 9 || astc5x5_wa_bits
== 0);
2362 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
2363 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
2366 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
2367 mt
->aux_usage
!= ISL_AUX_USAGE_MCS
)
2368 return ISL_AUX_USAGE_NONE
;
2370 switch (mt
->aux_usage
) {
2371 case ISL_AUX_USAGE_HIZ
:
2372 if (intel_miptree_sample_with_hiz(brw
, mt
))
2373 return ISL_AUX_USAGE_HIZ
;
2376 case ISL_AUX_USAGE_MCS
:
2377 return ISL_AUX_USAGE_MCS
;
2379 case ISL_AUX_USAGE_CCS_D
:
2380 case ISL_AUX_USAGE_CCS_E
:
2382 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2383 return ISL_AUX_USAGE_NONE
;
2386 /* If we don't have any unresolved color, report an aux usage of
2387 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2388 * aux surface and we can save some bandwidth.
2390 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2391 0, INTEL_REMAINING_LAYERS
))
2392 return ISL_AUX_USAGE_NONE
;
2394 if (can_texture_with_ccs(brw
, mt
, view_format
))
2395 return ISL_AUX_USAGE_CCS_E
;
2402 return ISL_AUX_USAGE_NONE
;
2406 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2408 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2409 * values so sRGB curve application was a no-op for all fast-clearable
2412 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2413 * values, the hardware interprets the floats, not as what would be
2414 * returned from the sampler (or written by the shader), but as being
2415 * between format conversion and sRGB curve application. This means that
2416 * we can switch between sRGB and UNORM without having to whack the clear
2419 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2423 intel_miptree_prepare_texture(struct brw_context
*brw
,
2424 struct intel_mipmap_tree
*mt
,
2425 enum isl_format view_format
,
2426 uint32_t start_level
, uint32_t num_levels
,
2427 uint32_t start_layer
, uint32_t num_layers
,
2428 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
2430 enum isl_aux_usage aux_usage
=
2431 intel_miptree_texture_aux_usage(brw
, mt
, view_format
, astc5x5_wa_bits
);
2433 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2435 /* Clear color is specified as ints or floats and the conversion is done by
2436 * the sampler. If we have a texture view, we would have to perform the
2437 * clear color conversion manually. Just disable clear color.
2439 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2440 clear_supported
= false;
2442 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2443 start_layer
, num_layers
,
2444 aux_usage
, clear_supported
);
2448 intel_miptree_prepare_image(struct brw_context
*brw
,
2449 struct intel_mipmap_tree
*mt
)
2451 /* The data port doesn't understand any compression */
2452 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2453 0, INTEL_REMAINING_LAYERS
,
2454 ISL_AUX_USAGE_NONE
, false);
2458 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2459 struct intel_mipmap_tree
*mt
,
2460 enum isl_format render_format
,
2462 bool draw_aux_disabled
)
2464 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2466 if (draw_aux_disabled
)
2467 return ISL_AUX_USAGE_NONE
;
2469 switch (mt
->aux_usage
) {
2470 case ISL_AUX_USAGE_MCS
:
2471 assert(mt
->aux_buf
);
2472 return ISL_AUX_USAGE_MCS
;
2474 case ISL_AUX_USAGE_CCS_D
:
2475 case ISL_AUX_USAGE_CCS_E
:
2477 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2478 return ISL_AUX_USAGE_NONE
;
2481 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2482 * formats. However, there are issues with blending where it doesn't
2483 * properly apply the sRGB curve to the clear color when blending.
2485 if (devinfo
->gen
>= 9 && blend_enabled
&&
2486 isl_format_is_srgb(render_format
) &&
2487 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2488 return ISL_AUX_USAGE_NONE
;
2490 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2491 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2493 return ISL_AUX_USAGE_CCS_E
;
2495 /* Otherwise, we have to fall back to CCS_D */
2496 return ISL_AUX_USAGE_CCS_D
;
2499 return ISL_AUX_USAGE_NONE
;
2504 intel_miptree_prepare_render(struct brw_context
*brw
,
2505 struct intel_mipmap_tree
*mt
, uint32_t level
,
2506 uint32_t start_layer
, uint32_t layer_count
,
2507 enum isl_aux_usage aux_usage
)
2509 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2510 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2514 intel_miptree_finish_render(struct brw_context
*brw
,
2515 struct intel_mipmap_tree
*mt
, uint32_t level
,
2516 uint32_t start_layer
, uint32_t layer_count
,
2517 enum isl_aux_usage aux_usage
)
2519 assert(_mesa_is_format_color_format(mt
->format
));
2521 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2526 intel_miptree_prepare_depth(struct brw_context
*brw
,
2527 struct intel_mipmap_tree
*mt
, uint32_t level
,
2528 uint32_t start_layer
, uint32_t layer_count
)
2530 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2531 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2535 intel_miptree_finish_depth(struct brw_context
*brw
,
2536 struct intel_mipmap_tree
*mt
, uint32_t level
,
2537 uint32_t start_layer
, uint32_t layer_count
,
2540 if (depth_written
) {
2541 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2547 intel_miptree_prepare_external(struct brw_context
*brw
,
2548 struct intel_mipmap_tree
*mt
)
2550 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2551 bool supports_fast_clear
= false;
2553 const struct isl_drm_modifier_info
*mod_info
=
2554 isl_drm_modifier_get_info(mt
->drm_modifier
);
2556 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2557 /* CCS_E is the only supported aux for external images and it's only
2558 * supported on very simple images.
2560 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2561 assert(_mesa_is_format_color_format(mt
->format
));
2562 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2563 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2564 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2565 assert(mt
->surf
.samples
== 1);
2566 assert(mt
->aux_buf
!= NULL
);
2568 aux_usage
= mod_info
->aux_usage
;
2569 supports_fast_clear
= mod_info
->supports_clear_color
;
2572 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2573 0, INTEL_REMAINING_LAYERS
,
2574 aux_usage
, supports_fast_clear
);
2578 intel_miptree_finish_external(struct brw_context
*brw
,
2579 struct intel_mipmap_tree
*mt
)
2584 /* We don't know the actual aux state of the aux surface. The previous
2585 * owner could have given it to us in a number of different states.
2586 * Because we don't know the aux state, we reset the aux state to the
2587 * least common denominator of possible valid states.
2589 enum isl_aux_state default_aux_state
=
2590 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2591 assert(mt
->last_level
== mt
->first_level
);
2592 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2597 * Make it possible to share the BO backing the given miptree with another
2598 * process or another miptree.
2600 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2601 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2602 * ensure that no MCS buffer gets allocated in the future.
2604 * HiZ is similarly unsafe with shared buffers.
2607 intel_miptree_make_shareable(struct brw_context
*brw
,
2608 struct intel_mipmap_tree
*mt
)
2610 /* MCS buffers are also used for multisample buffers, but we can't resolve
2611 * away a multisample MCS buffer because it's an integral part of how the
2612 * pixel data is stored. Fortunately this code path should never be
2613 * reached for multisample buffers.
2615 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2616 mt
->surf
.samples
== 1);
2618 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2619 0, INTEL_REMAINING_LAYERS
,
2620 ISL_AUX_USAGE_NONE
, false);
2623 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2626 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2627 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2628 mt
->level
[l
].has_hiz
= false;
2631 free(mt
->aux_state
);
2632 mt
->aux_state
= NULL
;
2633 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2636 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2637 mt
->supports_fast_clear
= false;
2642 * \brief Get pointer offset into stencil buffer.
2644 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2645 * must decode the tile's layout in software.
2648 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2650 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2652 * Even though the returned offset is always positive, the return type is
2654 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2655 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2658 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2660 uint32_t tile_size
= 4096;
2661 uint32_t tile_width
= 64;
2662 uint32_t tile_height
= 64;
2663 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2665 uint32_t tile_x
= x
/ tile_width
;
2666 uint32_t tile_y
= y
/ tile_height
;
2668 /* The byte's address relative to the tile's base addres. */
2669 uint32_t byte_x
= x
% tile_width
;
2670 uint32_t byte_y
= y
% tile_height
;
2672 uintptr_t u
= tile_y
* row_size
2673 + tile_x
* tile_size
2674 + 512 * (byte_x
/ 8)
2676 + 32 * ((byte_y
/ 4) % 2)
2677 + 16 * ((byte_x
/ 4) % 2)
2678 + 8 * ((byte_y
/ 2) % 2)
2679 + 4 * ((byte_x
/ 2) % 2)
2684 /* adjust for bit6 swizzling */
2685 if (((byte_x
/ 8) % 2) == 1) {
2686 if (((byte_y
/ 8) % 2) == 0) {
2698 intel_miptree_updownsample(struct brw_context
*brw
,
2699 struct intel_mipmap_tree
*src
,
2700 struct intel_mipmap_tree
*dst
)
2702 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2703 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2704 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2705 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2707 brw_blorp_blit_miptrees(brw
,
2708 src
, 0 /* level */, 0 /* layer */,
2709 src
->format
, SWIZZLE_XYZW
,
2710 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2713 GL_NEAREST
, false, false /*mirror x, y*/,
2716 if (src
->stencil_mt
) {
2717 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2718 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2719 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2720 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2722 brw_blorp_blit_miptrees(brw
,
2723 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2724 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2725 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2726 dst
->stencil_mt
->format
,
2729 GL_NEAREST
, false, false /*mirror x, y*/,
2730 false, false /* decode/encode srgb */);
2735 intel_update_r8stencil(struct brw_context
*brw
,
2736 struct intel_mipmap_tree
*mt
)
2738 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2740 assert(devinfo
->gen
>= 7);
2741 struct intel_mipmap_tree
*src
=
2742 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2743 if (!src
|| devinfo
->gen
>= 8)
2746 assert(src
->surf
.size_B
> 0);
2748 if (!mt
->shadow_mt
) {
2749 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2750 mt
->shadow_mt
= make_surface(
2753 MESA_FORMAT_R_UINT8
,
2754 src
->first_level
, src
->last_level
,
2755 src
->surf
.logical_level0_px
.width
,
2756 src
->surf
.logical_level0_px
.height
,
2757 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2758 src
->surf
.logical_level0_px
.depth
:
2759 src
->surf
.logical_level0_px
.array_len
,
2762 ISL_SURF_USAGE_TEXTURE_BIT
,
2763 BO_ALLOC_BUSY
, 0, NULL
);
2764 assert(mt
->shadow_mt
);
2767 if (src
->shadow_needs_update
== false)
2770 struct intel_mipmap_tree
*dst
= mt
->shadow_mt
;
2772 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2773 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2774 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2775 src
->surf
.phys_level0_sa
.array_len
;
2777 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2778 brw_blorp_copy_miptrees(brw
,
2782 minify(src
->surf
.logical_level0_px
.width
,
2784 minify(src
->surf
.logical_level0_px
.height
,
2789 brw_cache_flush_for_read(brw
, dst
->bo
);
2790 src
->shadow_needs_update
= false;
2794 intel_miptree_map_raw(struct brw_context
*brw
,
2795 struct intel_mipmap_tree
*mt
,
2798 struct brw_bo
*bo
= mt
->bo
;
2800 if (brw_batch_references(&brw
->batch
, bo
))
2801 intel_batchbuffer_flush(brw
);
2803 return brw_bo_map(brw
, bo
, mode
);
2807 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2809 brw_bo_unmap(mt
->bo
);
2813 intel_miptree_unmap_map(struct brw_context
*brw
,
2814 struct intel_mipmap_tree
*mt
,
2815 struct intel_miptree_map
*map
,
2816 unsigned int level
, unsigned int slice
)
2818 intel_miptree_unmap_raw(mt
);
2822 intel_miptree_map_map(struct brw_context
*brw
,
2823 struct intel_mipmap_tree
*mt
,
2824 struct intel_miptree_map
*map
,
2825 unsigned int level
, unsigned int slice
)
2827 unsigned int bw
, bh
;
2829 unsigned int image_x
, image_y
;
2830 intptr_t x
= map
->x
;
2831 intptr_t y
= map
->y
;
2833 /* For compressed formats, the stride is the number of bytes per
2834 * row of blocks. intel_miptree_get_image_offset() already does
2837 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2838 assert(y
% bh
== 0);
2839 assert(x
% bw
== 0);
2843 intel_miptree_access_raw(brw
, mt
, level
, slice
,
2844 map
->mode
& GL_MAP_WRITE_BIT
);
2846 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2853 /* Note that in the case of cube maps, the caller must have passed the
2854 * slice number referencing the face.
2856 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2860 map
->stride
= mt
->surf
.row_pitch_B
;
2861 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2864 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2865 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2866 map
->x
, map
->y
, map
->w
, map
->h
,
2867 mt
, _mesa_get_format_name(mt
->format
),
2868 x
, y
, map
->ptr
, map
->stride
);
2870 map
->unmap
= intel_miptree_unmap_map
;
2874 intel_miptree_unmap_blit(struct brw_context
*brw
,
2875 struct intel_mipmap_tree
*mt
,
2876 struct intel_miptree_map
*map
,
2880 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2881 struct gl_context
*ctx
= &brw
->ctx
;
2883 intel_miptree_unmap_raw(map
->linear_mt
);
2885 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2886 if (devinfo
->gen
>= 6) {
2887 brw_blorp_copy_miptrees(brw
, map
->linear_mt
, 0, 0,
2889 0, 0, map
->x
, map
->y
, map
->w
, map
->h
);
2891 bool ok
= intel_miptree_copy(brw
,
2892 map
->linear_mt
, 0, 0, 0, 0,
2893 mt
, level
, slice
, map
->x
, map
->y
,
2895 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2899 intel_miptree_release(&map
->linear_mt
);
2902 /* Compute extent parameters for use with tiled_memcpy functions.
2903 * xs are in units of bytes and ys are in units of strides.
2906 tile_extents(struct intel_mipmap_tree
*mt
, struct intel_miptree_map
*map
,
2907 unsigned int level
, unsigned int slice
, unsigned int *x1_B
,
2908 unsigned int *x2_B
, unsigned int *y1_el
, unsigned int *y2_el
)
2910 unsigned int block_width
, block_height
;
2911 unsigned int x0_el
, y0_el
;
2913 _mesa_get_format_block_size(mt
->format
, &block_width
, &block_height
);
2915 assert(map
->x
% block_width
== 0);
2916 assert(map
->y
% block_height
== 0);
2918 intel_miptree_get_image_offset(mt
, level
, slice
, &x0_el
, &y0_el
);
2919 *x1_B
= (map
->x
/ block_width
+ x0_el
) * mt
->cpp
;
2920 *y1_el
= map
->y
/ block_height
+ y0_el
;
2921 *x2_B
= (DIV_ROUND_UP(map
->x
+ map
->w
, block_width
) + x0_el
) * mt
->cpp
;
2922 *y2_el
= DIV_ROUND_UP(map
->y
+ map
->h
, block_height
) + y0_el
;
2926 intel_miptree_unmap_tiled_memcpy(struct brw_context
*brw
,
2927 struct intel_mipmap_tree
*mt
,
2928 struct intel_miptree_map
*map
,
2932 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2933 unsigned int x1
, x2
, y1
, y2
;
2934 tile_extents(mt
, map
, level
, slice
, &x1
, &x2
, &y1
, &y2
);
2936 char *dst
= intel_miptree_map_raw(brw
, mt
, map
->mode
| MAP_RAW
);
2939 isl_memcpy_linear_to_tiled(
2940 x1
, x2
, y1
, y2
, dst
, map
->ptr
, mt
->surf
.row_pitch_B
, map
->stride
,
2941 brw
->has_swizzling
, mt
->surf
.tiling
, ISL_MEMCPY
);
2943 intel_miptree_unmap_raw(mt
);
2945 _mesa_align_free(map
->buffer
);
2946 map
->buffer
= map
->ptr
= NULL
;
2950 * Determine which copy function to use for the given format combination
2952 * The only two possible copy functions which are ever returned are a
2953 * direct memcpy and a RGBA <-> BGRA copy function. Since RGBA -> BGRA and
2954 * BGRA -> RGBA are exactly the same operation (and memcpy is obviously
2955 * symmetric), it doesn't matter whether the copy is from the tiled image
2956 * to the untiled or vice versa. The copy function required is the same in
2957 * either case so this function can be used.
2959 * \param[in] tiledFormat The format of the tiled image
2960 * \param[in] format The GL format of the client data
2961 * \param[in] type The GL type of the client data
2962 * \param[out] mem_copy Will be set to one of either the standard
2963 * library's memcpy or a different copy function
2964 * that performs an RGBA to BGRA conversion
2965 * \param[out] cpp Number of bytes per channel
2967 * \return true if the format and type combination are valid
2970 intel_miptree_get_memcpy_type(mesa_format tiledFormat
, GLenum format
, GLenum type
,
2973 if (type
== GL_UNSIGNED_INT_8_8_8_8_REV
&&
2974 !(format
== GL_RGBA
|| format
== GL_BGRA
))
2975 return ISL_MEMCPY_INVALID
; /* Invalid type/format combination */
2977 if ((tiledFormat
== MESA_FORMAT_L_UNORM8
&& format
== GL_LUMINANCE
) ||
2978 (tiledFormat
== MESA_FORMAT_A_UNORM8
&& format
== GL_ALPHA
)) {
2981 } else if ((tiledFormat
== MESA_FORMAT_B8G8R8A8_UNORM
) ||
2982 (tiledFormat
== MESA_FORMAT_B8G8R8X8_UNORM
) ||
2983 (tiledFormat
== MESA_FORMAT_B8G8R8A8_SRGB
) ||
2984 (tiledFormat
== MESA_FORMAT_B8G8R8X8_SRGB
)) {
2986 if (format
== GL_BGRA
) {
2988 } else if (format
== GL_RGBA
) {
2989 return ISL_MEMCPY_BGRA8
;
2991 } else if ((tiledFormat
== MESA_FORMAT_R8G8B8A8_UNORM
) ||
2992 (tiledFormat
== MESA_FORMAT_R8G8B8X8_UNORM
) ||
2993 (tiledFormat
== MESA_FORMAT_R8G8B8A8_SRGB
) ||
2994 (tiledFormat
== MESA_FORMAT_R8G8B8X8_SRGB
)) {
2996 if (format
== GL_BGRA
) {
2997 /* Copying from RGBA to BGRA is the same as BGRA to RGBA so we can
2998 * use the same function.
3000 return ISL_MEMCPY_BGRA8
;
3001 } else if (format
== GL_RGBA
) {
3006 return ISL_MEMCPY_INVALID
;
3010 intel_miptree_map_tiled_memcpy(struct brw_context
*brw
,
3011 struct intel_mipmap_tree
*mt
,
3012 struct intel_miptree_map
*map
,
3013 unsigned int level
, unsigned int slice
)
3015 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3016 map
->mode
& GL_MAP_WRITE_BIT
);
3018 unsigned int x1
, x2
, y1
, y2
;
3019 tile_extents(mt
, map
, level
, slice
, &x1
, &x2
, &y1
, &y2
);
3020 map
->stride
= ALIGN(_mesa_format_row_stride(mt
->format
, map
->w
), 16);
3022 /* The tiling and detiling functions require that the linear buffer
3023 * has proper 16-byte alignment (that is, its `x0` is 16-byte
3024 * aligned). Here we over-allocate the linear buffer by enough
3025 * bytes to get the proper alignment.
3027 map
->buffer
= _mesa_align_malloc(map
->stride
* (y2
- y1
) + (x1
& 0xf), 16);
3028 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
3029 assert(map
->buffer
);
3031 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3032 char *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
| MAP_RAW
);
3035 const isl_memcpy_type copy_type
=
3036 #if defined(USE_SSE41)
3037 cpu_has_sse4_1
? ISL_MEMCPY_STREAMING_LOAD
:
3041 isl_memcpy_tiled_to_linear(
3042 x1
, x2
, y1
, y2
, map
->ptr
, src
, map
->stride
,
3043 mt
->surf
.row_pitch_B
, brw
->has_swizzling
, mt
->surf
.tiling
,
3046 intel_miptree_unmap_raw(mt
);
3049 map
->unmap
= intel_miptree_unmap_tiled_memcpy
;
3053 intel_miptree_map_blit(struct brw_context
*brw
,
3054 struct intel_mipmap_tree
*mt
,
3055 struct intel_miptree_map
*map
,
3056 unsigned int level
, unsigned int slice
)
3058 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3059 map
->linear_mt
= make_surface(brw
, GL_TEXTURE_2D
, mt
->format
,
3060 0, 0, map
->w
, map
->h
, 1, 1,
3061 ISL_TILING_LINEAR_BIT
,
3062 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
3063 ISL_SURF_USAGE_TEXTURE_BIT
,
3066 if (!map
->linear_mt
) {
3067 fprintf(stderr
, "Failed to allocate blit temporary\n");
3070 map
->stride
= map
->linear_mt
->surf
.row_pitch_B
;
3072 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3073 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3074 * invalidate is set, since we'll be writing the whole rectangle from our
3075 * temporary buffer back out.
3077 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3078 if (devinfo
->gen
>= 6) {
3079 brw_blorp_copy_miptrees(brw
, mt
, level
, slice
,
3080 map
->linear_mt
, 0, 0,
3081 map
->x
, map
->y
, 0, 0, map
->w
, map
->h
);
3083 if (!intel_miptree_copy(brw
,
3084 mt
, level
, slice
, map
->x
, map
->y
,
3085 map
->linear_mt
, 0, 0, 0, 0,
3087 fprintf(stderr
, "Failed to blit\n");
3093 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3095 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3096 map
->x
, map
->y
, map
->w
, map
->h
,
3097 mt
, _mesa_get_format_name(mt
->format
),
3098 level
, slice
, map
->ptr
, map
->stride
);
3100 map
->unmap
= intel_miptree_unmap_blit
;
3104 intel_miptree_release(&map
->linear_mt
);
3110 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3112 #if defined(USE_SSE41)
3114 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3115 struct intel_mipmap_tree
*mt
,
3116 struct intel_miptree_map
*map
,
3120 _mesa_align_free(map
->buffer
);
3126 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3127 struct intel_mipmap_tree
*mt
,
3128 struct intel_miptree_map
*map
,
3129 unsigned int level
, unsigned int slice
)
3131 assert(map
->mode
& GL_MAP_READ_BIT
);
3132 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3134 intel_miptree_access_raw(brw
, mt
, level
, slice
, false);
3136 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3137 map
->x
, map
->y
, map
->w
, map
->h
,
3138 mt
, _mesa_get_format_name(mt
->format
),
3139 level
, slice
, map
->ptr
, map
->stride
);
3141 /* Map the original image */
3144 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3148 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3154 src
+= image_y
* mt
->surf
.row_pitch_B
;
3155 src
+= image_x
* mt
->cpp
;
3157 /* Due to the pixel offsets for the particular image being mapped, our
3158 * src pointer may not be 16-byte aligned. However, if the pitch is
3159 * divisible by 16, then the amount by which it's misaligned will remain
3160 * consistent from row to row.
3162 assert((mt
->surf
.row_pitch_B
% 16) == 0);
3163 const int misalignment
= ((uintptr_t) src
) & 15;
3165 /* Create an untiled temporary buffer for the mapping. */
3166 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3168 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3170 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3171 /* Offset the destination so it has the same misalignment as src. */
3172 map
->ptr
= map
->buffer
+ misalignment
;
3174 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3176 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3177 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3178 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch_B
;
3180 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3183 intel_miptree_unmap_raw(mt
);
3185 map
->unmap
= intel_miptree_unmap_movntdqa
;
3190 intel_miptree_unmap_s8(struct brw_context
*brw
,
3191 struct intel_mipmap_tree
*mt
,
3192 struct intel_miptree_map
*map
,
3196 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3197 unsigned int image_x
, image_y
;
3198 uint8_t *untiled_s8_map
= map
->ptr
;
3199 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3201 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3203 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3204 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3205 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch_B
,
3206 image_x
+ x
+ map
->x
,
3207 image_y
+ y
+ map
->y
,
3208 brw
->has_swizzling
);
3209 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3213 intel_miptree_unmap_raw(mt
);
3220 intel_miptree_map_s8(struct brw_context
*brw
,
3221 struct intel_mipmap_tree
*mt
,
3222 struct intel_miptree_map
*map
,
3223 unsigned int level
, unsigned int slice
)
3225 map
->stride
= map
->w
;
3226 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3230 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3231 map
->mode
& GL_MAP_WRITE_BIT
);
3233 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3234 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3235 * invalidate is set, since we'll be writing the whole rectangle from our
3236 * temporary buffer back out.
3238 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3239 uint8_t *untiled_s8_map
= map
->ptr
;
3240 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3241 unsigned int image_x
, image_y
;
3243 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3245 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3246 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3247 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch_B
,
3248 x
+ image_x
+ map
->x
,
3249 y
+ image_y
+ map
->y
,
3250 brw
->has_swizzling
);
3251 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3255 intel_miptree_unmap_raw(mt
);
3257 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3258 map
->x
, map
->y
, map
->w
, map
->h
,
3259 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3261 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3262 map
->x
, map
->y
, map
->w
, map
->h
,
3263 mt
, map
->ptr
, map
->stride
);
3266 map
->unmap
= intel_miptree_unmap_s8
;
3270 * Mapping functions for packed depth/stencil miptrees backed by real separate
3271 * miptrees for depth and stencil.
3273 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3274 * separate from the depth buffer. Yet at the GL API level, we have to expose
3275 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3276 * be able to map that memory for texture storage and glReadPixels-type
3277 * operations. We give Mesa core that access by mallocing a temporary and
3278 * copying the data between the actual backing store and the temporary.
3281 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3282 struct intel_mipmap_tree
*mt
,
3283 struct intel_miptree_map
*map
,
3287 struct intel_mipmap_tree
*z_mt
= mt
;
3288 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3289 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3291 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3292 uint32_t *packed_map
= map
->ptr
;
3293 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3294 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3295 unsigned int s_image_x
, s_image_y
;
3296 unsigned int z_image_x
, z_image_y
;
3298 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3299 &s_image_x
, &s_image_y
);
3300 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3301 &z_image_x
, &z_image_y
);
3303 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3304 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3305 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch_B
,
3306 x
+ s_image_x
+ map
->x
,
3307 y
+ s_image_y
+ map
->y
,
3308 brw
->has_swizzling
);
3309 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3310 (z_mt
->surf
.row_pitch_B
/ 4) +
3311 (x
+ z_image_x
+ map
->x
));
3313 if (map_z32f_x24s8
) {
3314 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3315 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3317 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3318 s_map
[s_offset
] = packed
>> 24;
3319 z_map
[z_offset
] = packed
;
3324 intel_miptree_unmap_raw(s_mt
);
3325 intel_miptree_unmap_raw(z_mt
);
3327 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3329 map
->x
, map
->y
, map
->w
, map
->h
,
3330 z_mt
, _mesa_get_format_name(z_mt
->format
),
3331 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3332 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3333 map
->ptr
, map
->stride
);
3340 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3341 struct intel_mipmap_tree
*mt
,
3342 struct intel_miptree_map
*map
,
3343 unsigned int level
, unsigned int slice
)
3345 struct intel_mipmap_tree
*z_mt
= mt
;
3346 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3347 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3348 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3350 map
->stride
= map
->w
* packed_bpp
;
3351 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3355 intel_miptree_access_raw(brw
, z_mt
, level
, slice
,
3356 map
->mode
& GL_MAP_WRITE_BIT
);
3357 intel_miptree_access_raw(brw
, s_mt
, level
, slice
,
3358 map
->mode
& GL_MAP_WRITE_BIT
);
3360 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3361 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3362 * invalidate is set, since we'll be writing the whole rectangle from our
3363 * temporary buffer back out.
3365 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3366 uint32_t *packed_map
= map
->ptr
;
3367 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3368 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3369 unsigned int s_image_x
, s_image_y
;
3370 unsigned int z_image_x
, z_image_y
;
3372 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3373 &s_image_x
, &s_image_y
);
3374 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3375 &z_image_x
, &z_image_y
);
3377 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3378 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3379 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3380 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch_B
,
3383 brw
->has_swizzling
);
3384 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3385 (z_mt
->surf
.row_pitch_B
/ 4) +
3386 (map_x
+ z_image_x
));
3387 uint8_t s
= s_map
[s_offset
];
3388 uint32_t z
= z_map
[z_offset
];
3390 if (map_z32f_x24s8
) {
3391 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3392 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3394 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3399 intel_miptree_unmap_raw(s_mt
);
3400 intel_miptree_unmap_raw(z_mt
);
3402 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3404 map
->x
, map
->y
, map
->w
, map
->h
,
3405 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3406 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3407 map
->ptr
, map
->stride
);
3409 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3410 map
->x
, map
->y
, map
->w
, map
->h
,
3411 mt
, map
->ptr
, map
->stride
);
3414 map
->unmap
= intel_miptree_unmap_depthstencil
;
3418 * Create and attach a map to the miptree at (level, slice). Return the
3421 static struct intel_miptree_map
*
3422 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3431 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3436 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3437 mt
->level
[level
].slice
[slice
].map
= map
;
3449 * Release the map at (level, slice).
3452 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3456 struct intel_miptree_map
**map
;
3458 map
= &mt
->level
[level
].slice
[slice
].map
;
3464 can_blit_slice(struct intel_mipmap_tree
*mt
,
3465 const struct intel_miptree_map
*map
)
3467 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3468 const unsigned src_blt_pitch
= intel_miptree_blt_pitch(mt
);
3469 const unsigned dst_blt_pitch
= ALIGN(map
->w
* mt
->cpp
, 64);
3470 return src_blt_pitch
< 32768 && dst_blt_pitch
< 32768;
3474 use_intel_mipree_map_blit(struct brw_context
*brw
,
3475 struct intel_mipmap_tree
*mt
,
3476 const struct intel_miptree_map
*map
)
3478 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3480 if (devinfo
->has_llc
&&
3481 /* It's probably not worth swapping to the blit ring because of
3482 * all the overhead involved.
3484 !(map
->mode
& GL_MAP_WRITE_BIT
) &&
3486 (mt
->surf
.tiling
== ISL_TILING_X
||
3487 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3488 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3489 /* Fast copy blit on skl+ supports all tiling formats. */
3490 devinfo
->gen
>= 9) &&
3491 can_blit_slice(mt
, map
))
3494 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3495 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3496 assert(can_blit_slice(mt
, map
));
3504 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3505 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3506 * arithmetic overflow.
3508 * If you call this function and use \a out_stride, then you're doing pointer
3509 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3510 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3511 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3512 * which usually have type uint32_t or GLuint.
3515 intel_miptree_map(struct brw_context
*brw
,
3516 struct intel_mipmap_tree
*mt
,
3525 ptrdiff_t *out_stride
)
3527 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3528 struct intel_miptree_map
*map
;
3530 assert(mt
->surf
.samples
== 1);
3532 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3539 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3540 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3541 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3542 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3543 } else if (use_intel_mipree_map_blit(brw
, mt
, map
)) {
3544 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3545 } else if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&& devinfo
->gen
> 4) {
3546 intel_miptree_map_tiled_memcpy(brw
, mt
, map
, level
, slice
);
3547 #if defined(USE_SSE41)
3548 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3549 !mt
->compressed
&& cpu_has_sse4_1
&&
3550 (mt
->surf
.row_pitch_B
% 16 == 0)) {
3551 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3554 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
3555 perf_debug("intel_miptree_map: mapping via gtt");
3556 intel_miptree_map_map(brw
, mt
, map
, level
, slice
);
3559 *out_ptr
= map
->ptr
;
3560 *out_stride
= map
->stride
;
3562 if (map
->ptr
== NULL
)
3563 intel_miptree_release_map(mt
, level
, slice
);
3567 intel_miptree_unmap(struct brw_context
*brw
,
3568 struct intel_mipmap_tree
*mt
,
3572 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3574 assert(mt
->surf
.samples
== 1);
3579 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3580 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3583 map
->unmap(brw
, mt
, map
, level
, slice
);
3585 intel_miptree_release_map(mt
, level
, slice
);
3589 get_isl_surf_dim(GLenum target
)
3593 case GL_TEXTURE_1D_ARRAY
:
3594 return ISL_SURF_DIM_1D
;
3597 case GL_TEXTURE_2D_ARRAY
:
3598 case GL_TEXTURE_RECTANGLE
:
3599 case GL_TEXTURE_CUBE_MAP
:
3600 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3601 case GL_TEXTURE_2D_MULTISAMPLE
:
3602 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3603 case GL_TEXTURE_EXTERNAL_OES
:
3604 return ISL_SURF_DIM_2D
;
3607 return ISL_SURF_DIM_3D
;
3610 unreachable("Invalid texture target");
3614 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3615 enum isl_tiling tiling
, GLenum target
)
3619 case GL_TEXTURE_1D_ARRAY
:
3620 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3621 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3624 case GL_TEXTURE_2D_ARRAY
:
3625 case GL_TEXTURE_RECTANGLE
:
3626 case GL_TEXTURE_2D_MULTISAMPLE
:
3627 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3628 case GL_TEXTURE_EXTERNAL_OES
:
3629 return ISL_DIM_LAYOUT_GEN4_2D
;
3631 case GL_TEXTURE_CUBE_MAP
:
3632 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3633 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3634 ISL_DIM_LAYOUT_GEN4_2D
);
3637 return (devinfo
->gen
>= 9 ?
3638 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3641 unreachable("Invalid texture target");
3645 intel_miptree_set_clear_color(struct brw_context
*brw
,
3646 struct intel_mipmap_tree
*mt
,
3647 union isl_color_value clear_color
)
3649 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3650 mt
->fast_clear_color
= clear_color
;
3651 if (mt
->aux_buf
->clear_color_bo
) {
3652 /* We can't update the clear color while the hardware is still using
3653 * the previous one for a resolve or sampling from it. Make sure that
3654 * there are no pending commands at this point.
3656 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3657 for (int i
= 0; i
< 4; i
++) {
3658 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3659 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3660 mt
->fast_clear_color
.u32
[i
]);
3662 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3664 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3670 union isl_color_value
3671 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3672 const struct intel_mipmap_tree
*mt
,
3673 enum isl_format view_format
, bool sampling
,
3674 struct brw_bo
**clear_color_bo
,
3675 uint64_t *clear_color_offset
)
3677 assert(mt
->aux_buf
);
3679 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3680 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3681 * we switch to using the inline clear color and do the sRGB color
3682 * conversion process defined in the OpenGL spec. The red, green, and
3683 * blue channels take part in gamma correction, while the alpha channel
3686 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3687 for (unsigned i
= 0; i
< 3; i
++) {
3688 srgb_decoded_value
.f32
[i
] =
3689 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3691 *clear_color_bo
= 0;
3692 *clear_color_offset
= 0;
3693 return srgb_decoded_value
;
3695 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3696 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3697 return mt
->fast_clear_color
;
3702 intel_miptree_update_etc_shadow(struct brw_context
*brw
,
3703 struct intel_mipmap_tree
*mt
,
3709 ptrdiff_t etc_stride
, shadow_stride
;
3711 struct intel_mipmap_tree
*smt
= mt
->shadow_mt
;
3713 assert(intel_miptree_has_etc_shadow(brw
, mt
));
3715 intel_miptree_map(brw
, mt
, level
, slice
, 0, 0, level_w
, level_h
,
3716 GL_MAP_READ_BIT
, &mptr
, &etc_stride
);
3717 intel_miptree_map(brw
, smt
, level
, slice
, 0, 0, level_w
, level_h
,
3718 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
,
3719 &sptr
, &shadow_stride
);
3721 if (mt
->format
== MESA_FORMAT_ETC1_RGB8
) {
3722 _mesa_etc1_unpack_rgba8888(sptr
, shadow_stride
, mptr
, etc_stride
,
3725 /* destination and source images must have the same swizzle */
3726 bool is_bgra
= (smt
->format
== MESA_FORMAT_B8G8R8A8_SRGB
);
3727 _mesa_unpack_etc2_format(sptr
, shadow_stride
, mptr
, etc_stride
,
3728 level_w
, level_h
, mt
->format
, is_bgra
);
3731 intel_miptree_unmap(brw
, mt
, level
, slice
);
3732 intel_miptree_unmap(brw
, smt
, level
, slice
);
3736 intel_miptree_update_etc_shadow_levels(struct brw_context
*brw
,
3737 struct intel_mipmap_tree
*mt
)
3739 struct intel_mipmap_tree
*smt
;
3743 assert(mt
->surf
.size_B
> 0);
3744 assert(intel_miptree_has_etc_shadow(brw
, mt
));
3746 smt
= mt
->shadow_mt
;
3747 num_slices
= smt
->surf
.logical_level0_px
.array_len
;
3749 for (int level
= smt
->first_level
; level
<= smt
->last_level
; level
++) {
3750 int level_w
= minify(smt
->surf
.logical_level0_px
.width
,
3751 level
- smt
->first_level
);
3752 int level_h
= minify(smt
->surf
.logical_level0_px
.height
,
3753 level
- smt
->first_level
);
3755 for (unsigned int slice
= 0; slice
< num_slices
; slice
++) {
3756 intel_miptree_update_etc_shadow(brw
, mt
, level
, slice
, level_w
,
3761 mt
->shadow_needs_update
= false;