2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_meta_util.h"
40 #include "brw_state.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
50 #include "util/format_srgb.h"
52 #include "x86/common_x86_asm.h"
54 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
56 static void *intel_miptree_map_raw(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*mt
,
60 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
63 intel_miptree_alloc_aux(struct brw_context
*brw
,
64 struct intel_mipmap_tree
*mt
);
67 intel_miptree_supports_mcs(struct brw_context
*brw
,
68 const struct intel_mipmap_tree
*mt
)
70 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
72 /* MCS compression only applies to multisampled miptrees */
73 if (mt
->surf
.samples
<= 1)
76 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
80 /* See isl_surf_get_mcs_surf for details. */
81 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
84 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
85 switch (_mesa_get_format_base_format(mt
->format
)) {
86 case GL_DEPTH_COMPONENT
:
87 case GL_STENCIL_INDEX
:
88 case GL_DEPTH_STENCIL
:
91 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
93 * This field must be set to 0 for all SINT MSRTs when all RT channels
96 * In practice this means that we have to disable MCS for all signed
97 * integer MSAA buffers. The alternative, to disable MCS only when one
98 * of the render target channels is disabled, is impractical because it
99 * would require converting between CMS and UMS MSAA layouts on the fly,
100 * which is expensive.
102 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
111 intel_tiling_supports_ccs(const struct brw_context
*brw
,
112 enum isl_tiling tiling
)
114 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
116 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
117 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
119 * - Support is limited to tiled render targets.
121 * Gen9 changes the restriction to Y-tile only.
123 if (devinfo
->gen
>= 9)
124 return tiling
== ISL_TILING_Y0
;
125 else if (devinfo
->gen
>= 7)
126 return tiling
!= ISL_TILING_LINEAR
;
132 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
133 * can be used. This doesn't (and should not) inspect any of the properties of
136 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
137 * beneath the "Fast Color Clear" bullet (p326):
139 * - Support is for non-mip-mapped and non-array surface types only.
141 * And then later, on p327:
143 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
146 * From the Skylake documentation, it is made clear that X-tiling is no longer
149 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
153 intel_miptree_supports_ccs(struct brw_context
*brw
,
154 const struct intel_mipmap_tree
*mt
)
156 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
158 /* MCS support does not exist prior to Gen7 */
159 if (devinfo
->gen
< 7)
162 /* This function applies only to non-multisampled render targets. */
163 if (mt
->surf
.samples
> 1)
166 /* MCS is only supported for color buffers */
167 switch (_mesa_get_format_base_format(mt
->format
)) {
168 case GL_DEPTH_COMPONENT
:
169 case GL_DEPTH_STENCIL
:
170 case GL_STENCIL_INDEX
:
174 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
177 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
178 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
179 mt
->surf
.logical_level0_px
.depth
> 1;
182 /* Multisample surfaces with the CMS layout are not layered surfaces,
183 * yet still have physical_depth0 > 1. Assert that we don't
184 * accidentally reject a multisampled surface here. We should have
185 * rejected it earlier by explicitly checking the sample count.
187 assert(mt
->surf
.samples
== 1);
190 /* Handle the hardware restrictions...
192 * All GENs have the following restriction: "MCS buffer for non-MSRT is
193 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
195 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
196 * Non-MultiSampler Render Target Restrictions) Support is for
197 * non-mip-mapped and non-array surface types only.
199 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
200 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
201 * surfaces are supported with MCS buffer layout with these alignments in
202 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
204 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
205 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
206 * surfaces are supported with MCS buffer layout with these alignments in
207 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
209 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
212 /* There's no point in using an MCS buffer if the surface isn't in a
215 if (!brw
->mesa_format_supports_render
[mt
->format
])
222 intel_tiling_supports_hiz(const struct brw_context
*brw
,
223 enum isl_tiling tiling
)
225 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
227 if (devinfo
->gen
< 6)
230 return tiling
== ISL_TILING_Y0
;
234 intel_miptree_supports_hiz(const struct brw_context
*brw
,
235 const struct intel_mipmap_tree
*mt
)
240 switch (mt
->format
) {
241 case MESA_FORMAT_Z_FLOAT32
:
242 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
243 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
244 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
245 case MESA_FORMAT_Z_UNORM16
:
253 * Return true if the format that will be used to access the miptree is
254 * CCS_E-compatible with the miptree's linear/non-sRGB format.
256 * Why use the linear format? Well, although the miptree may be specified with
257 * an sRGB format, the usage of that color space/format can be toggled. Since
258 * our HW tends to support more linear formats than sRGB ones, we use this
259 * format variant for check for CCS_E compatibility.
262 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
263 const struct intel_mipmap_tree
*mt
,
264 enum isl_format access_format
)
266 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
268 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
269 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
270 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
274 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
275 const struct intel_mipmap_tree
*mt
)
277 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
279 if (devinfo
->gen
< 9)
282 /* For now compression is only enabled for integer formats even though
283 * there exist supported floating point formats also. This is a heuristic
284 * decision based on current public benchmarks. In none of the cases these
285 * formats provided any improvement but a few cases were seen to regress.
286 * Hence these are left to to be enabled in the future when they are known
289 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
292 if (!intel_miptree_supports_ccs(brw
, mt
))
295 /* Many window system buffers are sRGB even if they are never rendered as
296 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
297 * surface is used as sRGB, we fall back to CCS_D.
299 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
300 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
301 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
305 * Determine depth format corresponding to a depth+stencil format,
306 * for separate stencil.
309 intel_depth_format_for_depthstencil_format(mesa_format format
) {
311 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
312 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
313 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
314 return MESA_FORMAT_Z_FLOAT32
;
321 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
322 unsigned depth0
, struct intel_mipmap_level
*table
)
324 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
326 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
328 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
329 if (!table
[level
].slice
)
336 for (unsigned level
= first_level
; level
<= last_level
; level
++)
337 free(table
[level
].slice
);
343 needs_separate_stencil(const struct brw_context
*brw
,
344 struct intel_mipmap_tree
*mt
,
347 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
349 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
352 if (devinfo
->must_use_separate_stencil
)
355 return brw
->has_separate_stencil
&&
356 intel_miptree_supports_hiz(brw
, mt
);
360 * Choose the aux usage for this miptree. This function must be called fairly
361 * late in the miptree create process after we have a tiling.
364 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
365 struct intel_mipmap_tree
*mt
)
367 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
369 if (intel_miptree_supports_mcs(brw
, mt
)) {
370 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
371 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
372 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
373 intel_miptree_supports_ccs(brw
, mt
)) {
374 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
375 intel_miptree_supports_ccs_e(brw
, mt
)) {
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
378 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
380 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
381 intel_miptree_supports_hiz(brw
, mt
)) {
382 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
385 /* We can do fast-clear on all auxiliary surface types that are
386 * allocated through the normal texture creation paths.
388 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
389 mt
->supports_fast_clear
= true;
394 * Choose an appropriate uncompressed format for a requested
395 * compressed format, if unsupported.
398 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
400 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
402 /* No need to lower ETC formats on these platforms,
403 * they are supported natively.
405 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
409 case MESA_FORMAT_ETC1_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_RGB8
:
412 return MESA_FORMAT_R8G8B8X8_UNORM
;
413 case MESA_FORMAT_ETC2_SRGB8
:
414 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
415 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
416 return MESA_FORMAT_B8G8R8A8_SRGB
;
417 case MESA_FORMAT_ETC2_RGBA8_EAC
:
418 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
419 return MESA_FORMAT_R8G8B8A8_UNORM
;
420 case MESA_FORMAT_ETC2_R11_EAC
:
421 return MESA_FORMAT_R_UNORM16
;
422 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
423 return MESA_FORMAT_R_SNORM16
;
424 case MESA_FORMAT_ETC2_RG11_EAC
:
425 return MESA_FORMAT_R16G16_UNORM
;
426 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
427 return MESA_FORMAT_R16G16_SNORM
;
429 /* Non ETC1 / ETC2 format */
435 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
437 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
438 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
440 return mt
->surf
.logical_level0_px
.array_len
;
443 UNUSED
static unsigned
444 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
446 /* In case of physical dimensions one needs to consider also the layout.
447 * See isl_calc_phys_level0_extent_sa().
449 if (surf
->dim
!= ISL_SURF_DIM_3D
)
450 return surf
->phys_level0_sa
.array_len
;
452 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
453 return minify(surf
->phys_level0_sa
.array_len
, level
);
455 return minify(surf
->phys_level0_sa
.depth
, level
);
458 /** \brief Assert that the level and layer are valid for the miptree. */
460 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
468 assert(level
>= mt
->first_level
);
469 assert(level
<= mt
->last_level
);
470 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
473 static enum isl_aux_state
**
474 create_aux_state_map(struct intel_mipmap_tree
*mt
,
475 enum isl_aux_state initial
)
477 const uint32_t levels
= mt
->last_level
+ 1;
479 uint32_t total_slices
= 0;
480 for (uint32_t level
= 0; level
< levels
; level
++)
481 total_slices
+= brw_get_num_logical_layers(mt
, level
);
483 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
485 /* We're going to allocate a single chunk of data for both the per-level
486 * reference array and the arrays of aux_state. This makes cleanup
487 * significantly easier.
489 const size_t total_size
= per_level_array_size
+
490 total_slices
* sizeof(enum isl_aux_state
);
491 void *data
= malloc(total_size
);
495 enum isl_aux_state
**per_level_arr
= data
;
496 enum isl_aux_state
*s
= data
+ per_level_array_size
;
497 for (uint32_t level
= 0; level
< levels
; level
++) {
498 per_level_arr
[level
] = s
;
499 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
500 for (uint32_t a
= 0; a
< level_layers
; a
++)
503 assert((void *)s
== data
+ total_size
);
505 return per_level_arr
;
509 free_aux_state_map(enum isl_aux_state
**state
)
515 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
516 enum isl_tiling tiling
, unsigned samples
)
521 if (tiling
== ISL_TILING_LINEAR
)
524 /* If the width is much smaller than a tile, don't bother tiling. */
528 if (ALIGN(row_pitch
, 512) >= 32768) {
529 perf_debug("row pitch %u too large to blit, falling back to untiled",
538 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
539 enum isl_tiling tiling
)
541 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
543 /* If the BO is too large to fit in the aperture, we need to use the
544 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
545 * handle Y-tiling, so we need to fall back to X.
547 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
548 tiling
== ISL_TILING_Y0
)
554 static struct intel_mipmap_tree
*
555 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
556 unsigned first_level
, unsigned last_level
,
557 unsigned width0
, unsigned height0
, unsigned depth0
,
558 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
559 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
560 unsigned row_pitch
, struct brw_bo
*bo
)
562 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
566 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
574 if (target
== GL_TEXTURE_CUBE_MAP
||
575 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
576 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
578 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
580 _mesa_enum_to_string(target
),
581 _mesa_get_format_name(format
),
582 num_samples
, width0
, height0
, depth0
,
583 first_level
, last_level
, mt
);
585 struct isl_surf_init_info init_info
= {
586 .dim
= get_isl_surf_dim(target
),
587 .format
= translate_tex_format(brw
, format
, false),
590 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
591 .levels
= last_level
- first_level
+ 1,
592 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
593 .samples
= num_samples
,
594 .row_pitch
= row_pitch
,
595 .usage
= isl_usage_flags
,
596 .tiling_flags
= tiling_flags
,
599 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
602 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
603 * on gen7 platforms we also need to create Y-tiled copies of stencil for
604 * texturing since the hardware can't sample from W-tiled surfaces. For
605 * everything else, check for corner cases needing special treatment.
607 bool is_depth_stencil
=
608 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
609 if (!is_depth_stencil
) {
610 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
611 mt
->surf
.tiling
, mt
->surf
.samples
)) {
612 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
613 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
615 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
616 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
617 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
622 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
623 * the size may not be multiple of row_pitch.
624 * See isl_apply_surface_padding().
626 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
627 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
630 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
632 isl_tiling_to_i915_tiling(
634 mt
->surf
.row_pitch
, alloc_flags
);
641 mt
->first_level
= first_level
;
642 mt
->last_level
= last_level
;
645 mt
->aux_state
= NULL
;
646 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
647 mt
->compressed
= _mesa_is_format_compressed(format
);
648 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
653 intel_miptree_release(&mt
);
658 make_separate_stencil_surface(struct brw_context
*brw
,
659 struct intel_mipmap_tree
*mt
)
661 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
662 0, mt
->surf
.levels
- 1,
663 mt
->surf
.logical_level0_px
.width
,
664 mt
->surf
.logical_level0_px
.height
,
665 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
666 mt
->surf
.logical_level0_px
.depth
:
667 mt
->surf
.logical_level0_px
.array_len
,
668 mt
->surf
.samples
, ISL_TILING_W_BIT
,
669 ISL_SURF_USAGE_STENCIL_BIT
|
670 ISL_SURF_USAGE_TEXTURE_BIT
,
671 BO_ALLOC_BUSY
, 0, NULL
);
676 mt
->stencil_mt
->r8stencil_needs_update
= true;
681 static struct intel_mipmap_tree
*
682 miptree_create(struct brw_context
*brw
,
691 enum intel_miptree_create_flags flags
)
693 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
695 if (format
== MESA_FORMAT_S_UINT8
)
696 return make_surface(brw
, target
, format
, first_level
, last_level
,
697 width0
, height0
, depth0
, num_samples
,
699 ISL_SURF_USAGE_STENCIL_BIT
|
700 ISL_SURF_USAGE_TEXTURE_BIT
,
705 const GLenum base_format
= _mesa_get_format_base_format(format
);
706 if ((base_format
== GL_DEPTH_COMPONENT
||
707 base_format
== GL_DEPTH_STENCIL
) &&
708 !(flags
& MIPTREE_CREATE_LINEAR
)) {
709 /* Fix up the Z miptree format for how we're splitting out separate
710 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
712 const mesa_format depth_only_format
=
713 intel_depth_format_for_depthstencil_format(format
);
714 struct intel_mipmap_tree
*mt
= make_surface(
715 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
716 first_level
, last_level
,
717 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
718 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
719 BO_ALLOC_BUSY
, 0, NULL
);
721 if (needs_separate_stencil(brw
, mt
, format
) &&
722 !make_separate_stencil_surface(brw
, mt
)) {
723 intel_miptree_release(&mt
);
727 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
728 intel_miptree_choose_aux_usage(brw
, mt
);
733 mesa_format tex_format
= format
;
734 mesa_format etc_format
= MESA_FORMAT_NONE
;
735 uint32_t alloc_flags
= 0;
737 format
= intel_lower_compressed_format(brw
, format
);
739 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
741 if (flags
& MIPTREE_CREATE_BUSY
)
742 alloc_flags
|= BO_ALLOC_BUSY
;
744 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
745 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
747 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
748 if (devinfo
->gen
< 6)
749 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
751 struct intel_mipmap_tree
*mt
= make_surface(
753 first_level
, last_level
,
754 width0
, height0
, depth0
,
755 num_samples
, tiling_flags
,
756 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
757 ISL_SURF_USAGE_TEXTURE_BIT
,
758 alloc_flags
, 0, NULL
);
762 mt
->etc_format
= etc_format
;
764 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
765 intel_miptree_choose_aux_usage(brw
, mt
);
770 struct intel_mipmap_tree
*
771 intel_miptree_create(struct brw_context
*brw
,
780 enum intel_miptree_create_flags flags
)
782 assert(num_samples
> 0);
784 struct intel_mipmap_tree
*mt
= miptree_create(
786 first_level
, last_level
,
787 width0
, height0
, depth0
, num_samples
,
794 if (!intel_miptree_alloc_aux(brw
, mt
)) {
795 intel_miptree_release(&mt
);
802 struct intel_mipmap_tree
*
803 intel_miptree_create_for_bo(struct brw_context
*brw
,
811 enum isl_tiling tiling
,
812 enum intel_miptree_create_flags flags
)
814 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
815 struct intel_mipmap_tree
*mt
;
816 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
817 const GLenum base_format
= _mesa_get_format_base_format(format
);
819 if ((base_format
== GL_DEPTH_COMPONENT
||
820 base_format
== GL_DEPTH_STENCIL
)) {
821 const mesa_format depth_only_format
=
822 intel_depth_format_for_depthstencil_format(format
);
823 mt
= make_surface(brw
, target
,
824 devinfo
->gen
>= 6 ? depth_only_format
: format
,
825 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
826 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
831 brw_bo_reference(bo
);
833 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
834 intel_miptree_choose_aux_usage(brw
, mt
);
837 } else if (format
== MESA_FORMAT_S_UINT8
) {
838 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
839 0, 0, width
, height
, depth
, 1,
841 ISL_SURF_USAGE_STENCIL_BIT
|
842 ISL_SURF_USAGE_TEXTURE_BIT
,
847 assert(bo
->size
>= mt
->surf
.size
);
849 brw_bo_reference(bo
);
853 /* Nothing will be able to use this miptree with the BO if the offset isn't
856 if (tiling
!= ISL_TILING_LINEAR
)
857 assert(offset
% 4096 == 0);
859 /* miptrees can't handle negative pitch. If you need flipping of images,
860 * that's outside of the scope of the mt.
864 /* The BO already has a tiling format and we shouldn't confuse the lower
865 * layers by making it try to find a tiling format again.
867 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
869 mt
= make_surface(brw
, target
, format
,
870 0, 0, width
, height
, depth
, 1,
872 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
873 ISL_SURF_USAGE_TEXTURE_BIT
,
878 brw_bo_reference(bo
);
882 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
883 intel_miptree_choose_aux_usage(brw
, mt
);
885 if (!intel_miptree_alloc_aux(brw
, mt
)) {
886 intel_miptree_release(&mt
);
894 static struct intel_mipmap_tree
*
895 miptree_create_for_planar_image(struct brw_context
*brw
,
896 __DRIimage
*image
, GLenum target
,
897 enum isl_tiling tiling
)
899 const struct intel_image_format
*f
= image
->planar_format
;
900 struct intel_mipmap_tree
*planar_mt
= NULL
;
902 for (int i
= 0; i
< f
->nplanes
; i
++) {
903 const int index
= f
->planes
[i
].buffer_index
;
904 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
905 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
906 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
907 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
909 /* Disable creation of the texture's aux buffers because the driver
910 * exposes no EGL API to manage them. That is, there is no API for
911 * resolving the aux buffer's content to the main buffer nor for
912 * invalidating the aux buffer's content.
914 struct intel_mipmap_tree
*mt
=
915 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
916 image
->offsets
[index
],
918 image
->strides
[index
],
920 MIPTREE_CREATE_NO_AUX
);
929 planar_mt
->plane
[i
- 1] = mt
;
932 planar_mt
->drm_modifier
= image
->modifier
;
938 create_ccs_buf_for_image(struct brw_context
*brw
,
940 struct intel_mipmap_tree
*mt
,
941 enum isl_aux_state initial_state
)
943 struct isl_surf temp_ccs_surf
;
945 /* CCS is only supported for very simple miptrees */
946 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
947 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
948 assert(mt
->surf
.samples
== 1);
949 assert(mt
->surf
.levels
== 1);
950 assert(mt
->surf
.logical_level0_px
.depth
== 1);
951 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
952 assert(mt
->first_level
== 0);
953 assert(mt
->last_level
== 0);
955 /* We shouldn't already have a CCS */
956 assert(!mt
->aux_buf
);
958 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
962 assert(image
->aux_offset
< image
->bo
->size
);
963 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
965 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
966 if (mt
->aux_buf
== NULL
)
969 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
970 if (!mt
->aux_state
) {
976 /* On gen10+ we start using an extra space in the aux buffer to store the
977 * indirect clear color. However, if we imported an image from the window
978 * system with CCS, we don't have the extra space at the end of the aux
979 * buffer. So create a new bo here that will store that clear color.
981 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
982 if (devinfo
->gen
>= 10) {
983 mt
->aux_buf
->clear_color_bo
=
984 brw_bo_alloc(brw
->bufmgr
, "clear_color_bo",
985 brw
->isl_dev
.ss
.clear_color_state_size
);
986 if (!mt
->aux_buf
->clear_color_bo
) {
993 mt
->aux_buf
->bo
= image
->bo
;
994 brw_bo_reference(image
->bo
);
996 mt
->aux_buf
->offset
= image
->aux_offset
;
997 mt
->aux_buf
->size
= image
->bo
->size
- image
->aux_offset
;
998 mt
->aux_buf
->pitch
= image
->aux_pitch
;
999 mt
->aux_buf
->qpitch
= 0;
1000 mt
->aux_buf
->surf
= temp_ccs_surf
;
1005 struct intel_mipmap_tree
*
1006 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1007 __DRIimage
*image
, GLenum target
,
1009 bool is_winsys_image
)
1011 uint32_t bo_tiling
, bo_swizzle
;
1012 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1014 const struct isl_drm_modifier_info
*mod_info
=
1015 isl_drm_modifier_get_info(image
->modifier
);
1017 const enum isl_tiling tiling
=
1018 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1020 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1021 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1023 if (image
->planar_format
)
1024 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1026 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1027 /* The texture storage paths in core Mesa detect if the driver does not
1028 * support the user-requested format, and then searches for a
1029 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1030 * do the fallbacks here for important formats.
1032 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1033 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1034 * the Chrome OS compositor consumes as dma_buf EGLImages.
1036 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1039 if (!brw
->ctx
.TextureFormatSupported
[format
])
1042 enum intel_miptree_create_flags mt_create_flags
= 0;
1044 /* If this image comes in from a window system, we have different
1045 * requirements than if it comes in via an EGL import operation. Window
1046 * system images can use any form of auxiliary compression we wish because
1047 * they get "flushed" before being handed off to the window system and we
1048 * have the opportunity to do resolves. Non window-system images, on the
1049 * other hand, have no resolve point so we can't have aux without a
1052 if (!is_winsys_image
)
1053 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1055 /* If we have a modifier which specifies aux, don't create one yet */
1056 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1057 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1059 /* Disable creation of the texture's aux buffers because the driver exposes
1060 * no EGL API to manage them. That is, there is no API for resolving the aux
1061 * buffer's content to the main buffer nor for invalidating the aux buffer's
1064 struct intel_mipmap_tree
*mt
=
1065 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1066 image
->offset
, image
->width
, image
->height
, 1,
1067 image
->pitch
, tiling
, mt_create_flags
);
1071 mt
->target
= target
;
1072 mt
->level
[0].level_x
= image
->tile_x
;
1073 mt
->level
[0].level_y
= image
->tile_y
;
1074 mt
->drm_modifier
= image
->modifier
;
1076 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1077 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1078 * trouble resolving back to destination image due to alignment issues.
1080 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1081 if (!devinfo
->has_surface_tile_offset
) {
1082 uint32_t draw_x
, draw_y
;
1083 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1085 if (draw_x
!= 0 || draw_y
!= 0) {
1086 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1087 intel_miptree_release(&mt
);
1092 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1093 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1095 mt
->aux_usage
= mod_info
->aux_usage
;
1096 /* If we are a window system buffer, then we can support fast-clears
1097 * even if the modifier doesn't support them by doing a partial resolve
1098 * as part of the flush operation.
1100 mt
->supports_fast_clear
=
1101 is_winsys_image
|| mod_info
->supports_clear_color
;
1103 /* We don't know the actual state of the surface when we get it but we
1104 * can make a pretty good guess based on the modifier. What we do know
1105 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1106 * a worst case of compression.
1108 enum isl_aux_state initial_state
=
1109 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1111 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1112 intel_miptree_release(&mt
);
1117 /* Don't assume coherency for imported EGLimages. We don't know what
1118 * external clients are going to do with it. They may scan it out.
1120 image
->bo
->cache_coherent
= false;
1126 * For a singlesample renderbuffer, this simply wraps the given BO with a
1129 * For a multisample renderbuffer, this wraps the window system's
1130 * (singlesample) BO with a singlesample miptree attached to the
1131 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1132 * that will contain the actual rendering (which is lazily resolved to
1133 * irb->singlesample_mt).
1136 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1137 struct intel_renderbuffer
*irb
,
1138 struct intel_mipmap_tree
*singlesample_mt
,
1139 uint32_t width
, uint32_t height
,
1142 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1143 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1144 mesa_format format
= rb
->Format
;
1145 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1147 /* Only the front and back buffers, which are color buffers, are allocated
1148 * through the image loader.
1150 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1151 _mesa_get_format_base_format(format
) == GL_RGBA
);
1153 assert(singlesample_mt
);
1155 if (num_samples
== 1) {
1156 intel_miptree_release(&irb
->mt
);
1157 irb
->mt
= singlesample_mt
;
1159 assert(!irb
->singlesample_mt
);
1161 intel_miptree_release(&irb
->singlesample_mt
);
1162 irb
->singlesample_mt
= singlesample_mt
;
1165 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1166 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1167 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1172 if (!multisample_mt
)
1175 irb
->need_downsample
= false;
1176 intel_miptree_release(&irb
->mt
);
1177 irb
->mt
= multisample_mt
;
1183 intel_miptree_release(&irb
->mt
);
1187 struct intel_mipmap_tree
*
1188 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1192 uint32_t num_samples
)
1194 struct intel_mipmap_tree
*mt
;
1196 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1198 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1199 width
, height
, depth
, num_samples
,
1200 MIPTREE_CREATE_BUSY
);
1207 intel_miptree_release(&mt
);
1212 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1213 struct intel_mipmap_tree
*src
)
1218 intel_miptree_release(dst
);
1222 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1229 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1231 if (aux_buf
== NULL
)
1234 brw_bo_unreference(aux_buf
->bo
);
1235 brw_bo_unreference(aux_buf
->clear_color_bo
);
1241 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1246 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1247 if (--(*mt
)->refcount
<= 0) {
1250 DBG("%s deleting %p\n", __func__
, *mt
);
1252 brw_bo_unreference((*mt
)->bo
);
1253 intel_miptree_release(&(*mt
)->stencil_mt
);
1254 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1255 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1256 free_aux_state_map((*mt
)->aux_state
);
1258 intel_miptree_release(&(*mt
)->plane
[0]);
1259 intel_miptree_release(&(*mt
)->plane
[1]);
1261 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1262 free((*mt
)->level
[i
].slice
);
1272 intel_get_image_dims(struct gl_texture_image
*image
,
1273 int *width
, int *height
, int *depth
)
1275 switch (image
->TexObject
->Target
) {
1276 case GL_TEXTURE_1D_ARRAY
:
1277 /* For a 1D Array texture the OpenGL API will treat the image height as
1278 * the number of array slices. For Intel hardware, we treat the 1D array
1279 * as a 2D Array with a height of 1. So, here we want to swap image
1282 assert(image
->Depth
== 1);
1283 *width
= image
->Width
;
1285 *depth
= image
->Height
;
1287 case GL_TEXTURE_CUBE_MAP
:
1288 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1289 * though we really have 6 slices.
1291 assert(image
->Depth
== 1);
1292 *width
= image
->Width
;
1293 *height
= image
->Height
;
1297 *width
= image
->Width
;
1298 *height
= image
->Height
;
1299 *depth
= image
->Depth
;
1305 * Can the image be pulled into a unified mipmap tree? This mirrors
1306 * the completeness test in a lot of ways.
1308 * Not sure whether I want to pass gl_texture_image here.
1311 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1312 struct gl_texture_image
*image
)
1314 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1315 GLuint level
= intelImage
->base
.Base
.Level
;
1316 int width
, height
, depth
;
1318 /* glTexImage* choose the texture object based on the target passed in, and
1319 * objects can't change targets over their lifetimes, so this should be
1322 assert(image
->TexObject
->Target
== mt
->target
);
1324 mesa_format mt_format
= mt
->format
;
1325 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1326 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1327 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1328 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1329 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1330 mt_format
= mt
->etc_format
;
1332 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1333 _mesa_get_srgb_format_linear(mt_format
))
1336 intel_get_image_dims(image
, &width
, &height
, &depth
);
1338 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1341 if (level
>= mt
->surf
.levels
)
1344 const unsigned level_depth
=
1345 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1346 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1347 mt
->surf
.logical_level0_px
.array_len
;
1349 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1350 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1351 depth
== level_depth
&&
1352 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1356 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1357 GLuint level
, GLuint slice
,
1358 GLuint
*x
, GLuint
*y
)
1360 if (level
== 0 && slice
== 0) {
1361 *x
= mt
->level
[0].level_x
;
1362 *y
= mt
->level
[0].level_y
;
1366 uint32_t x_offset_sa
, y_offset_sa
;
1368 /* Miptree itself can have an offset only if it represents a single
1369 * slice in an imported buffer object.
1370 * See intel_miptree_create_for_dri_image().
1372 assert(mt
->level
[0].level_x
== 0);
1373 assert(mt
->level
[0].level_y
== 0);
1375 /* Given level is relative to level zero while the miptree may be
1376 * represent just a subset of all levels starting from 'first_level'.
1378 assert(level
>= mt
->first_level
);
1379 level
-= mt
->first_level
;
1381 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1382 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1383 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1384 &x_offset_sa
, &y_offset_sa
);
1392 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1393 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1394 * and tile_h is set to 1.
1397 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1398 uint32_t *tile_w
, uint32_t *tile_h
)
1409 case ISL_TILING_LINEAR
:
1414 unreachable("not reached");
1420 * This function computes masks that may be used to select the bits of the X
1421 * and Y coordinates that indicate the offset within a tile. If the BO is
1422 * untiled, the masks are set to 0.
1425 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1426 uint32_t *mask_x
, uint32_t *mask_y
)
1428 uint32_t tile_w_bytes
, tile_h
;
1430 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1432 *mask_x
= tile_w_bytes
/ cpp
- 1;
1433 *mask_y
= tile_h
- 1;
1437 * Compute the offset (in bytes) from the start of the BO to the given x
1438 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1439 * multiples of the tile size.
1442 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1443 uint32_t x
, uint32_t y
)
1446 uint32_t pitch
= mt
->surf
.row_pitch
;
1448 switch (mt
->surf
.tiling
) {
1450 unreachable("not reached");
1451 case ISL_TILING_LINEAR
:
1452 return y
* pitch
+ x
* cpp
;
1454 assert((x
% (512 / cpp
)) == 0);
1455 assert((y
% 8) == 0);
1456 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1458 assert((x
% (128 / cpp
)) == 0);
1459 assert((y
% 32) == 0);
1460 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1465 * Rendering with tiled buffers requires that the base address of the buffer
1466 * be aligned to a page boundary. For renderbuffers, and sometimes with
1467 * textures, we may want the surface to point at a texture image level that
1468 * isn't at a page boundary.
1470 * This function returns an appropriately-aligned base offset
1471 * according to the tiling restrictions, plus any required x/y offset
1475 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1476 GLuint level
, GLuint slice
,
1481 uint32_t mask_x
, mask_y
;
1483 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1484 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1486 *tile_x
= x
& mask_x
;
1487 *tile_y
= y
& mask_y
;
1489 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1493 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1494 struct intel_mipmap_tree
*src_mt
,
1495 unsigned src_level
, unsigned src_layer
,
1496 struct intel_mipmap_tree
*dst_mt
,
1497 unsigned dst_level
, unsigned dst_layer
,
1498 unsigned width
, unsigned height
)
1501 ptrdiff_t src_stride
, dst_stride
;
1502 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1504 intel_miptree_map(brw
, src_mt
,
1505 src_level
, src_layer
,
1508 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1511 intel_miptree_map(brw
, dst_mt
,
1512 dst_level
, dst_layer
,
1515 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1519 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1520 _mesa_get_format_name(src_mt
->format
),
1521 src_mt
, src
, src_stride
,
1522 _mesa_get_format_name(dst_mt
->format
),
1523 dst_mt
, dst
, dst_stride
,
1526 int row_size
= cpp
* width
;
1527 if (src_stride
== row_size
&&
1528 dst_stride
== row_size
) {
1529 memcpy(dst
, src
, row_size
* height
);
1531 for (int i
= 0; i
< height
; i
++) {
1532 memcpy(dst
, src
, row_size
);
1538 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1539 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1541 /* Don't forget to copy the stencil data over, too. We could have skipped
1542 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1543 * shuffling the two data sources in/out of temporary storage instead of
1544 * the direct mapping we get this way.
1546 if (dst_mt
->stencil_mt
) {
1547 assert(src_mt
->stencil_mt
);
1548 intel_miptree_copy_slice_sw(brw
,
1549 src_mt
->stencil_mt
, src_level
, src_layer
,
1550 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1556 intel_miptree_copy_slice(struct brw_context
*brw
,
1557 struct intel_mipmap_tree
*src_mt
,
1558 unsigned src_level
, unsigned src_layer
,
1559 struct intel_mipmap_tree
*dst_mt
,
1560 unsigned dst_level
, unsigned dst_layer
)
1563 mesa_format format
= src_mt
->format
;
1564 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1565 src_level
- src_mt
->first_level
);
1566 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1567 src_level
- src_mt
->first_level
);
1569 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1570 src_level
- src_mt
->first_level
));
1572 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1573 _mesa_get_srgb_format_linear(dst_mt
->format
));
1575 if (dst_mt
->compressed
) {
1577 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1578 height
= ALIGN_NPOT(height
, j
) / j
;
1579 width
= ALIGN_NPOT(width
, i
) / i
;
1582 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1583 * below won't apply since we can't do the depth's Y tiling or the
1584 * stencil's W tiling in the blitter.
1586 if (src_mt
->stencil_mt
) {
1587 intel_miptree_copy_slice_sw(brw
,
1588 src_mt
, src_level
, src_layer
,
1589 dst_mt
, dst_level
, dst_layer
,
1594 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1595 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1597 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1600 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1601 _mesa_get_format_name(src_mt
->format
),
1602 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1603 _mesa_get_format_name(dst_mt
->format
),
1604 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1607 if (!intel_miptree_blit(brw
,
1608 src_mt
, src_level
, src_layer
, 0, 0, false,
1609 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1610 width
, height
, COLOR_LOGICOP_COPY
)) {
1611 perf_debug("miptree validate blit for %s failed\n",
1612 _mesa_get_format_name(format
));
1614 intel_miptree_copy_slice_sw(brw
,
1615 src_mt
, src_level
, src_layer
,
1616 dst_mt
, dst_level
, dst_layer
,
1622 * Copies the image's current data to the given miptree, and associates that
1623 * miptree with the image.
1626 intel_miptree_copy_teximage(struct brw_context
*brw
,
1627 struct intel_texture_image
*intelImage
,
1628 struct intel_mipmap_tree
*dst_mt
)
1630 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1631 struct intel_texture_object
*intel_obj
=
1632 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1633 int level
= intelImage
->base
.Base
.Level
;
1634 const unsigned face
= intelImage
->base
.Base
.Face
;
1635 unsigned start_layer
, end_layer
;
1637 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1639 assert(intelImage
->base
.Base
.Height
);
1641 end_layer
= intelImage
->base
.Base
.Height
- 1;
1642 } else if (face
> 0) {
1646 assert(intelImage
->base
.Base
.Depth
);
1648 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1651 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1652 intel_miptree_copy_slice(brw
,
1657 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1658 intel_obj
->needs_validate
= true;
1662 intel_miptree_init_mcs(struct brw_context
*brw
,
1663 struct intel_mipmap_tree
*mt
,
1666 assert(mt
->aux_buf
!= NULL
);
1668 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1670 * When MCS buffer is enabled and bound to MSRT, it is required that it
1671 * is cleared prior to any rendering.
1673 * Since we don't use the MCS buffer for any purpose other than rendering,
1674 * it makes sense to just clear it immediately upon allocation.
1676 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1678 void *map
= brw_bo_map(brw
, mt
->aux_buf
->bo
, MAP_WRITE
| MAP_RAW
);
1679 if (unlikely(map
== NULL
)) {
1680 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1681 brw_bo_unreference(mt
->aux_buf
->bo
);
1686 memset(data
, init_value
, mt
->aux_buf
->size
);
1687 brw_bo_unmap(mt
->aux_buf
->bo
);
1690 static struct intel_miptree_aux_buffer
*
1691 intel_alloc_aux_buffer(struct brw_context
*brw
,
1693 const struct isl_surf
*aux_surf
,
1694 uint32_t alloc_flags
,
1695 struct intel_mipmap_tree
*mt
)
1697 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1701 buf
->size
= aux_surf
->size
;
1703 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1704 if (devinfo
->gen
>= 10) {
1705 /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
1706 * will set a pointer to a dword somewhere that contains the color. So,
1707 * allocate the space for the clear color value here on the aux buffer.
1709 buf
->clear_color_offset
= buf
->size
;
1710 buf
->size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1713 buf
->pitch
= aux_surf
->row_pitch
;
1714 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1716 /* ISL has stricter set of alignment rules then the drm allocator.
1717 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1718 * trying to recalculate based on different format block sizes.
1720 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1721 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1727 if (devinfo
->gen
>= 10) {
1728 buf
->clear_color_bo
= buf
->bo
;
1729 brw_bo_reference(buf
->clear_color_bo
);
1732 buf
->surf
= *aux_surf
;
1738 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1739 struct intel_mipmap_tree
*mt
,
1742 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1743 assert(mt
->aux_buf
== NULL
);
1744 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1746 /* Multisampled miptrees are only supported for single level. */
1747 assert(mt
->first_level
== 0);
1748 enum isl_aux_state
**aux_state
=
1749 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1753 struct isl_surf temp_mcs_surf
;
1755 MAYBE_UNUSED
bool ok
=
1756 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1759 /* Buffer needs to be initialised requiring the buffer to be immediately
1760 * mapped to cpu space for writing. Therefore do not use the gpu access
1761 * flag which can cause an unnecessary delay if the backing pages happened
1762 * to be just used by the GPU.
1764 const uint32_t alloc_flags
= 0;
1765 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1766 &temp_mcs_surf
, alloc_flags
, mt
);
1772 mt
->aux_state
= aux_state
;
1774 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1780 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1781 struct intel_mipmap_tree
*mt
)
1783 assert(mt
->aux_buf
== NULL
);
1784 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1785 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1787 struct isl_surf temp_ccs_surf
;
1789 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1792 assert(temp_ccs_surf
.size
&&
1793 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1795 enum isl_aux_state
**aux_state
=
1796 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1800 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1801 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1803 * "If Software wants to enable Color Compression without Fast clear,
1804 * Software needs to initialize MCS with zeros."
1806 * A CCS value of 0 indicates that the corresponding block is in the
1807 * pass-through state which is what we want.
1809 * For CCS_D, on the other hand, we don't care as we're about to perform a
1810 * fast-clear operation. In that case, being hot in caches more useful.
1812 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1813 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1814 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1815 &temp_ccs_surf
, alloc_flags
, mt
);
1821 mt
->aux_state
= aux_state
;
1827 * Helper for intel_miptree_alloc_hiz() that sets
1828 * \c mt->level[level].has_hiz. Return true if and only if
1829 * \c has_hiz was set.
1832 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1833 struct intel_mipmap_tree
*mt
,
1836 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1838 assert(mt
->aux_buf
);
1839 assert(mt
->surf
.size
> 0);
1841 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1842 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1843 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1845 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1846 * and the height is 4 aligned. This allows our HiZ support
1847 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1848 * we can grow the width & height to allow the HiZ op to
1849 * force the proper size alignments.
1851 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1852 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1857 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1858 mt
->level
[level
].has_hiz
= true;
1863 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1864 struct intel_mipmap_tree
*mt
)
1866 assert(mt
->aux_buf
== NULL
);
1867 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1869 enum isl_aux_state
**aux_state
=
1870 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1874 struct isl_surf temp_hiz_surf
;
1876 MAYBE_UNUSED
bool ok
=
1877 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1880 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1881 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1882 &temp_hiz_surf
, alloc_flags
, mt
);
1889 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1890 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1892 mt
->aux_state
= aux_state
;
1899 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1901 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1902 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1903 * compress clear color so we wait until an actual fast-clear to allocate it.
1906 intel_miptree_alloc_aux(struct brw_context
*brw
,
1907 struct intel_mipmap_tree
*mt
)
1909 switch (mt
->aux_usage
) {
1910 case ISL_AUX_USAGE_NONE
:
1913 case ISL_AUX_USAGE_HIZ
:
1914 assert(!_mesa_is_format_color_format(mt
->format
));
1915 if (!intel_miptree_alloc_hiz(brw
, mt
))
1919 case ISL_AUX_USAGE_MCS
:
1920 assert(_mesa_is_format_color_format(mt
->format
));
1921 assert(mt
->surf
.samples
> 1);
1922 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1926 case ISL_AUX_USAGE_CCS_D
:
1927 /* Since CCS_D can only compress clear color so we wait until an actual
1928 * fast-clear to allocate it.
1932 case ISL_AUX_USAGE_CCS_E
:
1933 assert(_mesa_is_format_color_format(mt
->format
));
1934 assert(mt
->surf
.samples
== 1);
1935 if (!intel_miptree_alloc_ccs(brw
, mt
))
1940 unreachable("Invalid aux usage");
1945 * Can the miptree sample using the hiz buffer?
1948 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1949 struct intel_mipmap_tree
*mt
)
1951 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1953 if (!devinfo
->has_sample_with_hiz
) {
1961 /* It seems the hardware won't fallback to the depth buffer if some of the
1962 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1963 * of the texture to be HiZ enabled.
1965 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1966 if (!intel_miptree_level_has_hiz(mt
, level
))
1970 /* If compressed multisampling is enabled, then we use it for the auxiliary
1973 * From the BDW PRM (Volume 2d: Command Reference: Structures
1974 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1976 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1977 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1979 * There is no such blurb for 1D textures, but there is sufficient evidence
1980 * that this is broken on SKL+.
1982 return (mt
->surf
.samples
== 1 &&
1983 mt
->target
!= GL_TEXTURE_3D
&&
1984 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1988 * Does the miptree slice have hiz enabled?
1991 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1993 intel_miptree_check_level_layer(mt
, level
, 0);
1994 return mt
->level
[level
].has_hiz
;
1997 static inline uint32_t
1998 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1999 uint32_t start_level
, uint32_t num_levels
)
2001 assert(start_level
>= mt
->first_level
);
2002 assert(start_level
<= mt
->last_level
);
2004 if (num_levels
== INTEL_REMAINING_LAYERS
)
2005 num_levels
= mt
->last_level
- start_level
+ 1;
2006 /* Check for overflow */
2007 assert(start_level
+ num_levels
>= start_level
);
2008 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2013 static inline uint32_t
2014 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2015 uint32_t start_layer
, uint32_t num_layers
)
2017 assert(level
<= mt
->last_level
);
2019 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
2020 assert(start_layer
< total_num_layers
);
2021 if (num_layers
== INTEL_REMAINING_LAYERS
)
2022 num_layers
= total_num_layers
- start_layer
;
2023 /* Check for overflow */
2024 assert(start_layer
+ num_layers
>= start_layer
);
2025 assert(start_layer
+ num_layers
<= total_num_layers
);
2031 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2032 unsigned start_level
, unsigned num_levels
,
2033 unsigned start_layer
, unsigned num_layers
)
2035 assert(_mesa_is_format_color_format(mt
->format
));
2040 /* Clamp the level range to fit the miptree */
2041 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2043 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2044 const uint32_t level
= start_level
+ l
;
2045 const uint32_t level_layers
=
2046 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2047 for (unsigned a
= 0; a
< level_layers
; a
++) {
2048 enum isl_aux_state aux_state
=
2049 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2050 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2051 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2060 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2061 const struct intel_mipmap_tree
*mt
,
2062 unsigned level
, unsigned layer
)
2067 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2068 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2069 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2071 /* Compression of arrayed msaa surfaces is supported. */
2072 if (mt
->surf
.samples
> 1)
2075 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2076 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2078 mt
->surf
.logical_level0_px
.depth
== 1 &&
2079 mt
->surf
.logical_level0_px
.array_len
== 1));
2085 static enum isl_aux_op
2086 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2087 enum isl_aux_usage aux_usage
,
2088 bool fast_clear_supported
)
2090 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2092 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2094 assert(ccs_supported
== fast_clear_supported
);
2096 switch (aux_state
) {
2097 case ISL_AUX_STATE_CLEAR
:
2098 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2100 return ISL_AUX_OP_FULL_RESOLVE
;
2102 return ISL_AUX_OP_NONE
;
2104 case ISL_AUX_STATE_PASS_THROUGH
:
2105 return ISL_AUX_OP_NONE
;
2107 case ISL_AUX_STATE_RESOLVED
:
2108 case ISL_AUX_STATE_AUX_INVALID
:
2109 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2110 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2114 unreachable("Invalid aux state for CCS_D");
2117 static enum isl_aux_op
2118 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2119 enum isl_aux_usage aux_usage
,
2120 bool fast_clear_supported
)
2122 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2123 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2124 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2125 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2127 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2128 assert(fast_clear_supported
);
2130 switch (aux_state
) {
2131 case ISL_AUX_STATE_CLEAR
:
2132 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2133 if (fast_clear_supported
)
2134 return ISL_AUX_OP_NONE
;
2135 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2136 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2138 return ISL_AUX_OP_FULL_RESOLVE
;
2140 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2141 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2142 return ISL_AUX_OP_FULL_RESOLVE
;
2143 else if (!fast_clear_supported
)
2144 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2146 return ISL_AUX_OP_NONE
;
2148 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2149 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2150 return ISL_AUX_OP_FULL_RESOLVE
;
2152 return ISL_AUX_OP_NONE
;
2154 case ISL_AUX_STATE_PASS_THROUGH
:
2155 return ISL_AUX_OP_NONE
;
2157 case ISL_AUX_STATE_RESOLVED
:
2158 case ISL_AUX_STATE_AUX_INVALID
:
2162 unreachable("Invalid aux state for CCS_E");
2166 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2167 struct intel_mipmap_tree
*mt
,
2168 uint32_t level
, uint32_t layer
,
2169 enum isl_aux_usage aux_usage
,
2170 bool fast_clear_supported
)
2172 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2174 enum isl_aux_op resolve_op
;
2175 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2176 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2177 fast_clear_supported
);
2179 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2180 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2181 fast_clear_supported
);
2184 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2185 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2186 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2188 switch (resolve_op
) {
2189 case ISL_AUX_OP_FULL_RESOLVE
:
2190 /* The CCS full resolve operation destroys the CCS and sets it to the
2191 * pass-through state. (You can also think of this as being both a
2192 * resolve and an ambiguate in one operation.)
2194 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2195 ISL_AUX_STATE_PASS_THROUGH
);
2198 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2199 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2200 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2204 unreachable("Invalid resolve op");
2210 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2211 struct intel_mipmap_tree
*mt
,
2212 uint32_t level
, uint32_t layer
,
2213 enum isl_aux_usage aux_usage
)
2215 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2216 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2217 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2219 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2221 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2222 switch (aux_state
) {
2223 case ISL_AUX_STATE_CLEAR
:
2224 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2225 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2226 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2228 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2229 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2230 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2231 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2232 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2233 ISL_AUX_STATE_PARTIAL_CLEAR
);
2237 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2238 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2239 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2240 break; /* Nothing to do */
2242 case ISL_AUX_STATE_PASS_THROUGH
:
2243 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2244 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2245 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2251 case ISL_AUX_STATE_RESOLVED
:
2252 case ISL_AUX_STATE_AUX_INVALID
:
2253 unreachable("Invalid aux state for CCS_E");
2256 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2257 /* CCS_D is a bit simpler */
2258 switch (aux_state
) {
2259 case ISL_AUX_STATE_CLEAR
:
2260 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2261 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2262 ISL_AUX_STATE_PARTIAL_CLEAR
);
2265 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2266 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2267 break; /* Nothing to do */
2269 case ISL_AUX_STATE_PASS_THROUGH
:
2273 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2274 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2275 case ISL_AUX_STATE_RESOLVED
:
2276 case ISL_AUX_STATE_AUX_INVALID
:
2277 unreachable("Invalid aux state for CCS_D");
2283 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2284 struct intel_mipmap_tree
*mt
,
2286 enum isl_aux_usage aux_usage
,
2287 bool fast_clear_supported
)
2289 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2291 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2292 case ISL_AUX_STATE_CLEAR
:
2293 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2294 if (!fast_clear_supported
) {
2295 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2296 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2297 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2301 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2302 break; /* Nothing to do */
2304 case ISL_AUX_STATE_RESOLVED
:
2305 case ISL_AUX_STATE_PASS_THROUGH
:
2306 case ISL_AUX_STATE_AUX_INVALID
:
2307 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2308 unreachable("Invalid aux state for MCS");
2313 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2314 struct intel_mipmap_tree
*mt
,
2316 enum isl_aux_usage aux_usage
)
2318 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2320 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2321 case ISL_AUX_STATE_CLEAR
:
2322 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2323 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2326 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2327 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2328 break; /* Nothing to do */
2330 case ISL_AUX_STATE_RESOLVED
:
2331 case ISL_AUX_STATE_PASS_THROUGH
:
2332 case ISL_AUX_STATE_AUX_INVALID
:
2333 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2334 unreachable("Invalid aux state for MCS");
2339 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2340 struct intel_mipmap_tree
*mt
,
2341 uint32_t level
, uint32_t layer
,
2342 enum isl_aux_usage aux_usage
,
2343 bool fast_clear_supported
)
2345 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2347 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2348 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2349 case ISL_AUX_STATE_CLEAR
:
2350 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2351 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2352 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2355 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2356 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2357 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2360 case ISL_AUX_STATE_PASS_THROUGH
:
2361 case ISL_AUX_STATE_RESOLVED
:
2364 case ISL_AUX_STATE_AUX_INVALID
:
2365 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2366 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2369 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2370 unreachable("Invalid HiZ state");
2373 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2374 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2377 case ISL_AUX_OP_FULL_RESOLVE
:
2378 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2379 ISL_AUX_STATE_RESOLVED
);
2382 case ISL_AUX_OP_AMBIGUATE
:
2383 /* The HiZ resolve operation is actually an ambiguate */
2384 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2385 ISL_AUX_STATE_PASS_THROUGH
);
2389 unreachable("Invalid HiZ op");
2395 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2396 struct intel_mipmap_tree
*mt
,
2397 uint32_t level
, uint32_t layer
,
2398 enum isl_aux_usage aux_usage
)
2400 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2402 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2403 case ISL_AUX_STATE_CLEAR
:
2404 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2405 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2406 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2409 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2410 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2411 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2412 break; /* Nothing to do */
2414 case ISL_AUX_STATE_RESOLVED
:
2415 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2416 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2417 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2419 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2420 ISL_AUX_STATE_AUX_INVALID
);
2424 case ISL_AUX_STATE_PASS_THROUGH
:
2425 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2426 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2427 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2431 case ISL_AUX_STATE_AUX_INVALID
:
2432 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2435 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2436 unreachable("Invalid HiZ state");
2441 intel_miptree_prepare_access(struct brw_context
*brw
,
2442 struct intel_mipmap_tree
*mt
,
2443 uint32_t start_level
, uint32_t num_levels
,
2444 uint32_t start_layer
, uint32_t num_layers
,
2445 enum isl_aux_usage aux_usage
,
2446 bool fast_clear_supported
)
2448 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2450 switch (mt
->aux_usage
) {
2451 case ISL_AUX_USAGE_NONE
:
2455 case ISL_AUX_USAGE_MCS
:
2456 assert(mt
->aux_buf
);
2457 assert(start_level
== 0 && num_levels
== 1);
2458 const uint32_t level_layers
=
2459 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2460 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2461 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2462 aux_usage
, fast_clear_supported
);
2466 case ISL_AUX_USAGE_CCS_D
:
2467 case ISL_AUX_USAGE_CCS_E
:
2471 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2472 const uint32_t level
= start_level
+ l
;
2473 const uint32_t level_layers
=
2474 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2475 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2476 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2478 aux_usage
, fast_clear_supported
);
2483 case ISL_AUX_USAGE_HIZ
:
2484 assert(mt
->aux_buf
);
2485 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2486 const uint32_t level
= start_level
+ l
;
2487 if (!intel_miptree_level_has_hiz(mt
, level
))
2490 const uint32_t level_layers
=
2491 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2492 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2493 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2494 aux_usage
, fast_clear_supported
);
2500 unreachable("Invalid aux usage");
2505 intel_miptree_finish_write(struct brw_context
*brw
,
2506 struct intel_mipmap_tree
*mt
, uint32_t level
,
2507 uint32_t start_layer
, uint32_t num_layers
,
2508 enum isl_aux_usage aux_usage
)
2510 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2512 switch (mt
->aux_usage
) {
2513 case ISL_AUX_USAGE_NONE
:
2517 case ISL_AUX_USAGE_MCS
:
2518 assert(mt
->aux_buf
);
2519 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2520 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2525 case ISL_AUX_USAGE_CCS_D
:
2526 case ISL_AUX_USAGE_CCS_E
:
2530 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2531 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2536 case ISL_AUX_USAGE_HIZ
:
2537 if (!intel_miptree_level_has_hiz(mt
, level
))
2540 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2541 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2547 unreachable("Invavlid aux usage");
2552 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2553 uint32_t level
, uint32_t layer
)
2555 intel_miptree_check_level_layer(mt
, level
, layer
);
2557 if (_mesa_is_format_color_format(mt
->format
)) {
2558 assert(mt
->aux_buf
!= NULL
);
2559 assert(mt
->surf
.samples
== 1 ||
2560 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2561 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2562 unreachable("Cannot get aux state for stencil");
2564 assert(intel_miptree_level_has_hiz(mt
, level
));
2567 return mt
->aux_state
[level
][layer
];
2571 intel_miptree_set_aux_state(struct brw_context
*brw
,
2572 struct intel_mipmap_tree
*mt
, uint32_t level
,
2573 uint32_t start_layer
, uint32_t num_layers
,
2574 enum isl_aux_state aux_state
)
2576 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2578 if (_mesa_is_format_color_format(mt
->format
)) {
2579 assert(mt
->aux_buf
!= NULL
);
2580 assert(mt
->surf
.samples
== 1 ||
2581 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2582 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2583 unreachable("Cannot get aux state for stencil");
2585 assert(intel_miptree_level_has_hiz(mt
, level
));
2588 for (unsigned a
= 0; a
< num_layers
; a
++) {
2589 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2590 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2591 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2596 /* On Gen9 color buffers may be compressed by the hardware (lossless
2597 * compression). There are, however, format restrictions and care needs to be
2598 * taken that the sampler engine is capable for re-interpreting a buffer with
2599 * format different the buffer was originally written with.
2601 * For example, SRGB formats are not compressible and the sampler engine isn't
2602 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2603 * color buffer needs to be resolved so that the sampling surface can be
2604 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2608 can_texture_with_ccs(struct brw_context
*brw
,
2609 struct intel_mipmap_tree
*mt
,
2610 enum isl_format view_format
)
2612 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2615 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2617 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2618 isl_format_get_layout(view_format
)->name
,
2619 _mesa_get_format_name(mt
->format
));
2627 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2628 struct intel_mipmap_tree
*mt
,
2629 enum isl_format view_format
)
2631 switch (mt
->aux_usage
) {
2632 case ISL_AUX_USAGE_HIZ
:
2633 if (intel_miptree_sample_with_hiz(brw
, mt
))
2634 return ISL_AUX_USAGE_HIZ
;
2637 case ISL_AUX_USAGE_MCS
:
2638 return ISL_AUX_USAGE_MCS
;
2640 case ISL_AUX_USAGE_CCS_D
:
2641 case ISL_AUX_USAGE_CCS_E
:
2643 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2644 return ISL_AUX_USAGE_NONE
;
2647 /* If we don't have any unresolved color, report an aux usage of
2648 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2649 * aux surface and we can save some bandwidth.
2651 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2652 0, INTEL_REMAINING_LAYERS
))
2653 return ISL_AUX_USAGE_NONE
;
2655 if (can_texture_with_ccs(brw
, mt
, view_format
))
2656 return ISL_AUX_USAGE_CCS_E
;
2663 return ISL_AUX_USAGE_NONE
;
2667 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2669 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2670 * values so sRGB curve application was a no-op for all fast-clearable
2673 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2674 * values, the hardware interprets the floats, not as what would be
2675 * returned from the sampler (or written by the shader), but as being
2676 * between format conversion and sRGB curve application. This means that
2677 * we can switch between sRGB and UNORM without having to whack the clear
2680 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2684 intel_miptree_prepare_texture(struct brw_context
*brw
,
2685 struct intel_mipmap_tree
*mt
,
2686 enum isl_format view_format
,
2687 uint32_t start_level
, uint32_t num_levels
,
2688 uint32_t start_layer
, uint32_t num_layers
)
2690 enum isl_aux_usage aux_usage
=
2691 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2692 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2694 /* Clear color is specified as ints or floats and the conversion is done by
2695 * the sampler. If we have a texture view, we would have to perform the
2696 * clear color conversion manually. Just disable clear color.
2698 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2699 clear_supported
= false;
2701 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2702 start_layer
, num_layers
,
2703 aux_usage
, clear_supported
);
2707 intel_miptree_prepare_image(struct brw_context
*brw
,
2708 struct intel_mipmap_tree
*mt
)
2710 /* The data port doesn't understand any compression */
2711 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2712 0, INTEL_REMAINING_LAYERS
,
2713 ISL_AUX_USAGE_NONE
, false);
2717 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2718 struct intel_mipmap_tree
*mt
,
2719 enum isl_format render_format
,
2721 bool draw_aux_disabled
)
2723 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2725 if (draw_aux_disabled
)
2726 return ISL_AUX_USAGE_NONE
;
2728 switch (mt
->aux_usage
) {
2729 case ISL_AUX_USAGE_MCS
:
2730 assert(mt
->aux_buf
);
2731 return ISL_AUX_USAGE_MCS
;
2733 case ISL_AUX_USAGE_CCS_D
:
2734 case ISL_AUX_USAGE_CCS_E
:
2736 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2737 return ISL_AUX_USAGE_NONE
;
2740 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2741 * formats. However, there are issues with blending where it doesn't
2742 * properly apply the sRGB curve to the clear color when blending.
2744 if (devinfo
->gen
== 9 && blend_enabled
&&
2745 isl_format_is_srgb(render_format
) &&
2746 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2747 return ISL_AUX_USAGE_NONE
;
2749 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2750 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2752 return ISL_AUX_USAGE_CCS_E
;
2754 /* Otherwise, we have to fall back to CCS_D */
2755 return ISL_AUX_USAGE_CCS_D
;
2758 return ISL_AUX_USAGE_NONE
;
2763 intel_miptree_prepare_render(struct brw_context
*brw
,
2764 struct intel_mipmap_tree
*mt
, uint32_t level
,
2765 uint32_t start_layer
, uint32_t layer_count
,
2766 enum isl_aux_usage aux_usage
)
2768 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2769 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2773 intel_miptree_finish_render(struct brw_context
*brw
,
2774 struct intel_mipmap_tree
*mt
, uint32_t level
,
2775 uint32_t start_layer
, uint32_t layer_count
,
2776 enum isl_aux_usage aux_usage
)
2778 assert(_mesa_is_format_color_format(mt
->format
));
2780 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2785 intel_miptree_prepare_depth(struct brw_context
*brw
,
2786 struct intel_mipmap_tree
*mt
, uint32_t level
,
2787 uint32_t start_layer
, uint32_t layer_count
)
2789 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2790 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2794 intel_miptree_finish_depth(struct brw_context
*brw
,
2795 struct intel_mipmap_tree
*mt
, uint32_t level
,
2796 uint32_t start_layer
, uint32_t layer_count
,
2799 if (depth_written
) {
2800 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2801 mt
->aux_buf
!= NULL
);
2806 intel_miptree_prepare_external(struct brw_context
*brw
,
2807 struct intel_mipmap_tree
*mt
)
2809 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2810 bool supports_fast_clear
= false;
2812 const struct isl_drm_modifier_info
*mod_info
=
2813 isl_drm_modifier_get_info(mt
->drm_modifier
);
2815 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2816 /* CCS_E is the only supported aux for external images and it's only
2817 * supported on very simple images.
2819 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2820 assert(_mesa_is_format_color_format(mt
->format
));
2821 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2822 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2823 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2824 assert(mt
->surf
.samples
== 1);
2825 assert(mt
->aux_buf
!= NULL
);
2827 aux_usage
= mod_info
->aux_usage
;
2828 supports_fast_clear
= mod_info
->supports_clear_color
;
2831 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2832 0, INTEL_REMAINING_LAYERS
,
2833 aux_usage
, supports_fast_clear
);
2837 intel_miptree_finish_external(struct brw_context
*brw
,
2838 struct intel_mipmap_tree
*mt
)
2843 /* We don't know the actual aux state of the aux surface. The previous
2844 * owner could have given it to us in a number of different states.
2845 * Because we don't know the aux state, we reset the aux state to the
2846 * least common denominator of possible valid states.
2848 enum isl_aux_state default_aux_state
=
2849 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2850 assert(mt
->last_level
== mt
->first_level
);
2851 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2856 * Make it possible to share the BO backing the given miptree with another
2857 * process or another miptree.
2859 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2860 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2861 * ensure that no MCS buffer gets allocated in the future.
2863 * HiZ is similarly unsafe with shared buffers.
2866 intel_miptree_make_shareable(struct brw_context
*brw
,
2867 struct intel_mipmap_tree
*mt
)
2869 /* MCS buffers are also used for multisample buffers, but we can't resolve
2870 * away a multisample MCS buffer because it's an integral part of how the
2871 * pixel data is stored. Fortunately this code path should never be
2872 * reached for multisample buffers.
2874 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2875 mt
->surf
.samples
== 1);
2877 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2878 0, INTEL_REMAINING_LAYERS
,
2879 ISL_AUX_USAGE_NONE
, false);
2882 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2885 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2886 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2887 mt
->level
[l
].has_hiz
= false;
2890 free(mt
->aux_state
);
2891 mt
->aux_state
= NULL
;
2892 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2895 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2896 mt
->supports_fast_clear
= false;
2901 * \brief Get pointer offset into stencil buffer.
2903 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2904 * must decode the tile's layout in software.
2907 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2909 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2911 * Even though the returned offset is always positive, the return type is
2913 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2914 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2917 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2919 uint32_t tile_size
= 4096;
2920 uint32_t tile_width
= 64;
2921 uint32_t tile_height
= 64;
2922 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2924 uint32_t tile_x
= x
/ tile_width
;
2925 uint32_t tile_y
= y
/ tile_height
;
2927 /* The byte's address relative to the tile's base addres. */
2928 uint32_t byte_x
= x
% tile_width
;
2929 uint32_t byte_y
= y
% tile_height
;
2931 uintptr_t u
= tile_y
* row_size
2932 + tile_x
* tile_size
2933 + 512 * (byte_x
/ 8)
2935 + 32 * ((byte_y
/ 4) % 2)
2936 + 16 * ((byte_x
/ 4) % 2)
2937 + 8 * ((byte_y
/ 2) % 2)
2938 + 4 * ((byte_x
/ 2) % 2)
2943 /* adjust for bit6 swizzling */
2944 if (((byte_x
/ 8) % 2) == 1) {
2945 if (((byte_y
/ 8) % 2) == 0) {
2957 intel_miptree_updownsample(struct brw_context
*brw
,
2958 struct intel_mipmap_tree
*src
,
2959 struct intel_mipmap_tree
*dst
)
2961 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2962 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2963 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2964 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2966 brw_blorp_blit_miptrees(brw
,
2967 src
, 0 /* level */, 0 /* layer */,
2968 src
->format
, SWIZZLE_XYZW
,
2969 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2972 GL_NEAREST
, false, false /*mirror x, y*/,
2975 if (src
->stencil_mt
) {
2976 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2977 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2978 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2979 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2981 brw_blorp_blit_miptrees(brw
,
2982 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2983 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2984 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2985 dst
->stencil_mt
->format
,
2988 GL_NEAREST
, false, false /*mirror x, y*/,
2989 false, false /* decode/encode srgb */);
2994 intel_update_r8stencil(struct brw_context
*brw
,
2995 struct intel_mipmap_tree
*mt
)
2997 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2999 assert(devinfo
->gen
>= 7);
3000 struct intel_mipmap_tree
*src
=
3001 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3002 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
3005 assert(src
->surf
.size
> 0);
3007 if (!mt
->r8stencil_mt
) {
3008 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3009 mt
->r8stencil_mt
= make_surface(
3012 MESA_FORMAT_R_UINT8
,
3013 src
->first_level
, src
->last_level
,
3014 src
->surf
.logical_level0_px
.width
,
3015 src
->surf
.logical_level0_px
.height
,
3016 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3017 src
->surf
.logical_level0_px
.depth
:
3018 src
->surf
.logical_level0_px
.array_len
,
3021 ISL_SURF_USAGE_TEXTURE_BIT
,
3022 BO_ALLOC_BUSY
, 0, NULL
);
3023 assert(mt
->r8stencil_mt
);
3026 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3028 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3029 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3030 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3031 src
->surf
.phys_level0_sa
.array_len
;
3033 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3034 brw_blorp_copy_miptrees(brw
,
3038 minify(src
->surf
.logical_level0_px
.width
,
3040 minify(src
->surf
.logical_level0_px
.height
,
3045 brw_cache_flush_for_read(brw
, dst
->bo
);
3046 src
->r8stencil_needs_update
= false;
3050 intel_miptree_map_raw(struct brw_context
*brw
,
3051 struct intel_mipmap_tree
*mt
,
3054 struct brw_bo
*bo
= mt
->bo
;
3056 if (brw_batch_references(&brw
->batch
, bo
))
3057 intel_batchbuffer_flush(brw
);
3059 return brw_bo_map(brw
, bo
, mode
);
3063 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3065 brw_bo_unmap(mt
->bo
);
3069 intel_miptree_map_gtt(struct brw_context
*brw
,
3070 struct intel_mipmap_tree
*mt
,
3071 struct intel_miptree_map
*map
,
3072 unsigned int level
, unsigned int slice
)
3074 unsigned int bw
, bh
;
3076 unsigned int image_x
, image_y
;
3077 intptr_t x
= map
->x
;
3078 intptr_t y
= map
->y
;
3080 /* For compressed formats, the stride is the number of bytes per
3081 * row of blocks. intel_miptree_get_image_offset() already does
3084 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3085 assert(y
% bh
== 0);
3086 assert(x
% bw
== 0);
3090 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3097 /* Note that in the case of cube maps, the caller must have passed the
3098 * slice number referencing the face.
3100 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3104 map
->stride
= mt
->surf
.row_pitch
;
3105 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3108 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3109 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3110 map
->x
, map
->y
, map
->w
, map
->h
,
3111 mt
, _mesa_get_format_name(mt
->format
),
3112 x
, y
, map
->ptr
, map
->stride
);
3116 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3118 intel_miptree_unmap_raw(mt
);
3122 intel_miptree_map_blit(struct brw_context
*brw
,
3123 struct intel_mipmap_tree
*mt
,
3124 struct intel_miptree_map
*map
,
3125 unsigned int level
, unsigned int slice
)
3127 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3128 /* first_level */ 0,
3132 MIPTREE_CREATE_LINEAR
);
3134 if (!map
->linear_mt
) {
3135 fprintf(stderr
, "Failed to allocate blit temporary\n");
3138 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3140 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3141 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3142 * invalidate is set, since we'll be writing the whole rectangle from our
3143 * temporary buffer back out.
3145 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3146 if (!intel_miptree_copy(brw
,
3147 mt
, level
, slice
, map
->x
, map
->y
,
3148 map
->linear_mt
, 0, 0, 0, 0,
3150 fprintf(stderr
, "Failed to blit\n");
3155 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3157 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3158 map
->x
, map
->y
, map
->w
, map
->h
,
3159 mt
, _mesa_get_format_name(mt
->format
),
3160 level
, slice
, map
->ptr
, map
->stride
);
3165 intel_miptree_release(&map
->linear_mt
);
3171 intel_miptree_unmap_blit(struct brw_context
*brw
,
3172 struct intel_mipmap_tree
*mt
,
3173 struct intel_miptree_map
*map
,
3177 struct gl_context
*ctx
= &brw
->ctx
;
3179 intel_miptree_unmap_raw(map
->linear_mt
);
3181 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3182 bool ok
= intel_miptree_copy(brw
,
3183 map
->linear_mt
, 0, 0, 0, 0,
3184 mt
, level
, slice
, map
->x
, map
->y
,
3186 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3189 intel_miptree_release(&map
->linear_mt
);
3193 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3195 #if defined(USE_SSE41)
3197 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3198 struct intel_mipmap_tree
*mt
,
3199 struct intel_miptree_map
*map
,
3200 unsigned int level
, unsigned int slice
)
3202 assert(map
->mode
& GL_MAP_READ_BIT
);
3203 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3205 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3206 map
->x
, map
->y
, map
->w
, map
->h
,
3207 mt
, _mesa_get_format_name(mt
->format
),
3208 level
, slice
, map
->ptr
, map
->stride
);
3210 /* Map the original image */
3213 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3217 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3223 src
+= image_y
* mt
->surf
.row_pitch
;
3224 src
+= image_x
* mt
->cpp
;
3226 /* Due to the pixel offsets for the particular image being mapped, our
3227 * src pointer may not be 16-byte aligned. However, if the pitch is
3228 * divisible by 16, then the amount by which it's misaligned will remain
3229 * consistent from row to row.
3231 assert((mt
->surf
.row_pitch
% 16) == 0);
3232 const int misalignment
= ((uintptr_t) src
) & 15;
3234 /* Create an untiled temporary buffer for the mapping. */
3235 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3237 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3239 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3240 /* Offset the destination so it has the same misalignment as src. */
3241 map
->ptr
= map
->buffer
+ misalignment
;
3243 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3245 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3246 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3247 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3249 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3252 intel_miptree_unmap_raw(mt
);
3256 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3257 struct intel_mipmap_tree
*mt
,
3258 struct intel_miptree_map
*map
,
3262 _mesa_align_free(map
->buffer
);
3269 intel_miptree_map_s8(struct brw_context
*brw
,
3270 struct intel_mipmap_tree
*mt
,
3271 struct intel_miptree_map
*map
,
3272 unsigned int level
, unsigned int slice
)
3274 map
->stride
= map
->w
;
3275 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3279 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3280 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3281 * invalidate is set, since we'll be writing the whole rectangle from our
3282 * temporary buffer back out.
3284 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3285 uint8_t *untiled_s8_map
= map
->ptr
;
3286 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3287 unsigned int image_x
, image_y
;
3289 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3291 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3292 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3293 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3294 x
+ image_x
+ map
->x
,
3295 y
+ image_y
+ map
->y
,
3296 brw
->has_swizzling
);
3297 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3301 intel_miptree_unmap_raw(mt
);
3303 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3304 map
->x
, map
->y
, map
->w
, map
->h
,
3305 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3307 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3308 map
->x
, map
->y
, map
->w
, map
->h
,
3309 mt
, map
->ptr
, map
->stride
);
3314 intel_miptree_unmap_s8(struct brw_context
*brw
,
3315 struct intel_mipmap_tree
*mt
,
3316 struct intel_miptree_map
*map
,
3320 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3321 unsigned int image_x
, image_y
;
3322 uint8_t *untiled_s8_map
= map
->ptr
;
3323 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3325 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3327 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3328 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3329 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3330 image_x
+ x
+ map
->x
,
3331 image_y
+ y
+ map
->y
,
3332 brw
->has_swizzling
);
3333 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3337 intel_miptree_unmap_raw(mt
);
3344 intel_miptree_map_etc(struct brw_context
*brw
,
3345 struct intel_mipmap_tree
*mt
,
3346 struct intel_miptree_map
*map
,
3350 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3351 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3352 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3355 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3356 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3358 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3359 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3360 map
->w
, map
->h
, 1));
3361 map
->ptr
= map
->buffer
;
3365 intel_miptree_unmap_etc(struct brw_context
*brw
,
3366 struct intel_mipmap_tree
*mt
,
3367 struct intel_miptree_map
*map
,
3373 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3378 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3379 + image_y
* mt
->surf
.row_pitch
3380 + image_x
* mt
->cpp
;
3382 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3383 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3384 map
->ptr
, map
->stride
,
3387 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3388 map
->ptr
, map
->stride
,
3389 map
->w
, map
->h
, mt
->etc_format
);
3391 intel_miptree_unmap_raw(mt
);
3396 * Mapping function for packed depth/stencil miptrees backed by real separate
3397 * miptrees for depth and stencil.
3399 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3400 * separate from the depth buffer. Yet at the GL API level, we have to expose
3401 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3402 * be able to map that memory for texture storage and glReadPixels-type
3403 * operations. We give Mesa core that access by mallocing a temporary and
3404 * copying the data between the actual backing store and the temporary.
3407 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3408 struct intel_mipmap_tree
*mt
,
3409 struct intel_miptree_map
*map
,
3410 unsigned int level
, unsigned int slice
)
3412 struct intel_mipmap_tree
*z_mt
= mt
;
3413 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3414 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3415 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3417 map
->stride
= map
->w
* packed_bpp
;
3418 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3422 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3423 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3424 * invalidate is set, since we'll be writing the whole rectangle from our
3425 * temporary buffer back out.
3427 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3428 uint32_t *packed_map
= map
->ptr
;
3429 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3430 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3431 unsigned int s_image_x
, s_image_y
;
3432 unsigned int z_image_x
, z_image_y
;
3434 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3435 &s_image_x
, &s_image_y
);
3436 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3437 &z_image_x
, &z_image_y
);
3439 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3440 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3441 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3442 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3445 brw
->has_swizzling
);
3446 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3447 (z_mt
->surf
.row_pitch
/ 4) +
3448 (map_x
+ z_image_x
));
3449 uint8_t s
= s_map
[s_offset
];
3450 uint32_t z
= z_map
[z_offset
];
3452 if (map_z32f_x24s8
) {
3453 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3454 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3456 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3461 intel_miptree_unmap_raw(s_mt
);
3462 intel_miptree_unmap_raw(z_mt
);
3464 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3466 map
->x
, map
->y
, map
->w
, map
->h
,
3467 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3468 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3469 map
->ptr
, map
->stride
);
3471 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3472 map
->x
, map
->y
, map
->w
, map
->h
,
3473 mt
, map
->ptr
, map
->stride
);
3478 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3479 struct intel_mipmap_tree
*mt
,
3480 struct intel_miptree_map
*map
,
3484 struct intel_mipmap_tree
*z_mt
= mt
;
3485 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3486 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3488 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3489 uint32_t *packed_map
= map
->ptr
;
3490 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3491 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3492 unsigned int s_image_x
, s_image_y
;
3493 unsigned int z_image_x
, z_image_y
;
3495 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3496 &s_image_x
, &s_image_y
);
3497 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3498 &z_image_x
, &z_image_y
);
3500 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3501 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3502 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3503 x
+ s_image_x
+ map
->x
,
3504 y
+ s_image_y
+ map
->y
,
3505 brw
->has_swizzling
);
3506 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3507 (z_mt
->surf
.row_pitch
/ 4) +
3508 (x
+ z_image_x
+ map
->x
));
3510 if (map_z32f_x24s8
) {
3511 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3512 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3514 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3515 s_map
[s_offset
] = packed
>> 24;
3516 z_map
[z_offset
] = packed
;
3521 intel_miptree_unmap_raw(s_mt
);
3522 intel_miptree_unmap_raw(z_mt
);
3524 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3526 map
->x
, map
->y
, map
->w
, map
->h
,
3527 z_mt
, _mesa_get_format_name(z_mt
->format
),
3528 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3529 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3530 map
->ptr
, map
->stride
);
3537 * Create and attach a map to the miptree at (level, slice). Return the
3540 static struct intel_miptree_map
*
3541 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3550 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3555 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3556 mt
->level
[level
].slice
[slice
].map
= map
;
3568 * Release the map at (level, slice).
3571 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3575 struct intel_miptree_map
**map
;
3577 map
= &mt
->level
[level
].slice
[slice
].map
;
3583 can_blit_slice(struct intel_mipmap_tree
*mt
,
3584 unsigned int level
, unsigned int slice
)
3586 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3587 if (mt
->surf
.row_pitch
>= 32768)
3594 use_intel_mipree_map_blit(struct brw_context
*brw
,
3595 struct intel_mipmap_tree
*mt
,
3600 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3602 if (devinfo
->has_llc
&&
3603 /* It's probably not worth swapping to the blit ring because of
3604 * all the overhead involved.
3606 !(mode
& GL_MAP_WRITE_BIT
) &&
3608 (mt
->surf
.tiling
== ISL_TILING_X
||
3609 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3610 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3611 /* Fast copy blit on skl+ supports all tiling formats. */
3612 devinfo
->gen
>= 9) &&
3613 can_blit_slice(mt
, level
, slice
))
3616 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3617 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3618 assert(can_blit_slice(mt
, level
, slice
));
3626 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3627 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3628 * arithmetic overflow.
3630 * If you call this function and use \a out_stride, then you're doing pointer
3631 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3632 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3633 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3634 * which usually have type uint32_t or GLuint.
3637 intel_miptree_map(struct brw_context
*brw
,
3638 struct intel_mipmap_tree
*mt
,
3647 ptrdiff_t *out_stride
)
3649 struct intel_miptree_map
*map
;
3651 assert(mt
->surf
.samples
== 1);
3653 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3660 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3661 map
->mode
& GL_MAP_WRITE_BIT
);
3663 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3664 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3665 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3666 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3667 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3668 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3669 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3670 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3671 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3672 #if defined(USE_SSE41)
3673 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3674 !mt
->compressed
&& cpu_has_sse4_1
&&
3675 (mt
->surf
.row_pitch
% 16 == 0)) {
3676 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3679 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3682 *out_ptr
= map
->ptr
;
3683 *out_stride
= map
->stride
;
3685 if (map
->ptr
== NULL
)
3686 intel_miptree_release_map(mt
, level
, slice
);
3690 intel_miptree_unmap(struct brw_context
*brw
,
3691 struct intel_mipmap_tree
*mt
,
3695 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3697 assert(mt
->surf
.samples
== 1);
3702 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3703 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3705 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3706 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3707 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3708 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3709 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3710 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3711 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3712 } else if (map
->linear_mt
) {
3713 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3714 #if defined(USE_SSE41)
3715 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3716 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3719 intel_miptree_unmap_gtt(mt
);
3722 intel_miptree_release_map(mt
, level
, slice
);
3726 get_isl_surf_dim(GLenum target
)
3730 case GL_TEXTURE_1D_ARRAY
:
3731 return ISL_SURF_DIM_1D
;
3734 case GL_TEXTURE_2D_ARRAY
:
3735 case GL_TEXTURE_RECTANGLE
:
3736 case GL_TEXTURE_CUBE_MAP
:
3737 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3738 case GL_TEXTURE_2D_MULTISAMPLE
:
3739 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3740 case GL_TEXTURE_EXTERNAL_OES
:
3741 return ISL_SURF_DIM_2D
;
3744 return ISL_SURF_DIM_3D
;
3747 unreachable("Invalid texture target");
3751 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3752 enum isl_tiling tiling
, GLenum target
)
3756 case GL_TEXTURE_1D_ARRAY
:
3757 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3758 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3761 case GL_TEXTURE_2D_ARRAY
:
3762 case GL_TEXTURE_RECTANGLE
:
3763 case GL_TEXTURE_2D_MULTISAMPLE
:
3764 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3765 case GL_TEXTURE_EXTERNAL_OES
:
3766 return ISL_DIM_LAYOUT_GEN4_2D
;
3768 case GL_TEXTURE_CUBE_MAP
:
3769 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3770 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3771 ISL_DIM_LAYOUT_GEN4_2D
);
3774 return (devinfo
->gen
>= 9 ?
3775 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3778 unreachable("Invalid texture target");
3782 intel_miptree_set_clear_color(struct brw_context
*brw
,
3783 struct intel_mipmap_tree
*mt
,
3784 const union gl_color_union
*color
)
3786 const union isl_color_value clear_color
=
3787 brw_meta_convert_fast_clear_color(brw
, mt
, color
);
3789 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3790 mt
->fast_clear_color
= clear_color
;
3791 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3798 intel_miptree_set_depth_clear_value(struct brw_context
*brw
,
3799 struct intel_mipmap_tree
*mt
,
3802 if (mt
->fast_clear_color
.f32
[0] != clear_value
) {
3803 mt
->fast_clear_color
.f32
[0] = clear_value
;
3804 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3810 union isl_color_value
3811 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3812 const struct intel_mipmap_tree
*mt
,
3813 enum isl_format view_format
, bool sampling
,
3814 struct brw_bo
**clear_color_bo
,
3815 uint32_t *clear_color_offset
)
3817 assert(mt
->aux_buf
);
3819 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3820 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3821 * we switch to using the inline clear color and do the sRGB color
3822 * conversion process defined in the OpenGL spec. The red, green, and
3823 * blue channels take part in gamma correction, while the alpha channel
3826 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3827 for (unsigned i
= 0; i
< 3; i
++) {
3828 srgb_decoded_value
.f32
[i
] =
3829 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3831 *clear_color_bo
= 0;
3832 *clear_color_offset
= 0;
3833 return srgb_decoded_value
;
3835 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3836 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3837 return mt
->fast_clear_color
;