2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
167 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
168 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
170 * - Support is limited to tiled render targets.
172 * Gen9 changes the restriction to Y-tile only.
175 return tiling
== I915_TILING_Y
;
176 else if (brw
->gen
>= 7)
177 return tiling
!= I915_TILING_NONE
;
183 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
184 * can be used. This doesn't (and should not) inspect any of the properties of
187 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
188 * beneath the "Fast Color Clear" bullet (p326):
190 * - Support is for non-mip-mapped and non-array surface types only.
192 * And then later, on p327:
194 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
197 * From the Skylake documentation, it is made clear that X-tiling is no longer
200 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
204 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
205 struct intel_mipmap_tree
*mt
)
207 /* MCS support does not exist prior to Gen7 */
211 if (mt
->disable_aux_buffers
)
214 /* This function applies only to non-multisampled render targets. */
215 if (mt
->num_samples
> 1)
218 /* MCS is only supported for color buffers */
219 switch (_mesa_get_format_base_format(mt
->format
)) {
220 case GL_DEPTH_COMPONENT
:
221 case GL_DEPTH_STENCIL
:
222 case GL_STENCIL_INDEX
:
226 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
228 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
230 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
231 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
237 /* Check for layered surfaces. */
238 if (mt
->physical_depth0
!= 1) {
239 /* Multisample surfaces with the CMS layout are not layered surfaces,
240 * yet still have physical_depth0 > 1. Assert that we don't
241 * accidentally reject a multisampled surface here. We should have
242 * rejected it earlier by explicitly checking the sample count.
244 assert(mt
->num_samples
<= 1);
247 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
248 mt
->logical_width0
, mt
->logical_height0
,
249 mt
->physical_depth0
);
255 /* There's no point in using an MCS buffer if the surface isn't in a
258 if (!brw
->format_supported_as_render_target
[mt
->format
])
262 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
263 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
264 return brw_losslessly_compressible_format(brw
, brw_format
);
271 * Determine depth format corresponding to a depth+stencil format,
272 * for separate stencil.
275 intel_depth_format_for_depthstencil_format(mesa_format format
) {
277 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
278 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
279 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
280 return MESA_FORMAT_Z_FLOAT32
;
288 * @param for_bo Indicates that the caller is
289 * intel_miptree_create_for_bo(). If true, then do not create
292 static struct intel_mipmap_tree
*
293 intel_miptree_create_layout(struct brw_context
*brw
,
302 uint32_t layout_flags
)
304 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
308 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
309 _mesa_enum_to_string(target
),
310 _mesa_get_format_name(format
),
311 first_level
, last_level
, depth0
, mt
);
313 if (target
== GL_TEXTURE_1D_ARRAY
) {
314 /* For a 1D Array texture the OpenGL API will treat the height0
315 * parameter as the number of array slices. For Intel hardware, we treat
316 * the 1D array as a 2D Array with a height of 1.
318 * So, when we first come through this path to create a 1D Array
319 * texture, height0 stores the number of slices, and depth0 is 1. In
320 * this case, we want to swap height0 and depth0.
322 * Since some miptrees will be created based on the base miptree, we may
323 * come through this path and see height0 as 1 and depth0 being the
324 * number of slices. In this case we don't need to do the swap.
326 assert(height0
== 1 || depth0
== 1);
335 mt
->first_level
= first_level
;
336 mt
->last_level
= last_level
;
337 mt
->logical_width0
= width0
;
338 mt
->logical_height0
= height0
;
339 mt
->logical_depth0
= depth0
;
340 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
341 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
342 exec_list_make_empty(&mt
->hiz_map
);
343 mt
->cpp
= _mesa_get_format_bytes(format
);
344 mt
->num_samples
= num_samples
;
345 mt
->compressed
= _mesa_is_format_compressed(format
);
346 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
349 if (num_samples
> 1) {
350 /* Adjust width/height/depth for MSAA */
351 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
352 mt
->disable_aux_buffers
);
353 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
354 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
355 * "If the surface is multisampled and it is a depth or stencil
356 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
357 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
360 * +----------------------------------------------------------------+
361 * | Num Multisamples | W_l = | H_l = |
362 * +----------------------------------------------------------------+
363 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
364 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
365 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
366 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
367 * +----------------------------------------------------------------+
370 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
371 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
372 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
374 * Another more complicated explanation for these adjustments comes
375 * from the Sandybridge PRM, volume 4, part 1, page 31:
377 * "Any of the other messages (sample*, LOD, load4) used with a
378 * (4x) multisampled surface will in-effect sample a surface with
379 * double the height and width as that indicated in the surface
380 * state. Each pixel position on the original-sized surface is
381 * replaced with a 2x2 of samples with the following arrangement:
386 * Thus, when sampling from a multisampled texture, it behaves as
387 * though the layout in memory for (x,y,sample) is:
389 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
390 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
392 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
393 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
395 * However, the actual layout of multisampled data in memory is:
397 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
398 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
400 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
401 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
403 * This pattern repeats for each 2x2 pixel block.
405 * As a result, when calculating the size of our 4-sample buffer for
406 * an odd width or height, we have to align before scaling up because
407 * sample 3 is in that bottom right 2x2 block.
409 switch (num_samples
) {
411 assert(brw
->gen
>= 8);
412 width0
= ALIGN(width0
, 2) * 2;
413 height0
= ALIGN(height0
, 2);
416 width0
= ALIGN(width0
, 2) * 2;
417 height0
= ALIGN(height0
, 2) * 2;
420 width0
= ALIGN(width0
, 2) * 4;
421 height0
= ALIGN(height0
, 2) * 2;
424 width0
= ALIGN(width0
, 2) * 4;
425 height0
= ALIGN(height0
, 2) * 4;
428 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
431 unreachable("not reached");
434 /* Non-interleaved */
435 depth0
*= num_samples
;
439 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
440 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
441 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
442 * used on Gen8 to make it pick a qpitch value which doesn't include space
443 * for the mipmaps. On Gen9 this is not necessary because it will
444 * automatically pick a packed qpitch value whenever mt->first_level ==
446 * TODO: can we use it elsewhere?
447 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
450 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
452 switch (mt
->msaa_layout
) {
453 case INTEL_MSAA_LAYOUT_NONE
:
454 case INTEL_MSAA_LAYOUT_IMS
:
455 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
457 case INTEL_MSAA_LAYOUT_UMS
:
458 case INTEL_MSAA_LAYOUT_CMS
:
459 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
464 if (target
== GL_TEXTURE_CUBE_MAP
) {
469 mt
->physical_width0
= width0
;
470 mt
->physical_height0
= height0
;
471 mt
->physical_depth0
= depth0
;
473 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
474 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
475 (brw
->must_use_separate_stencil
||
476 (brw
->has_separate_stencil
&&
477 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
478 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
480 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
481 MIPTREE_LAYOUT_TILING_ANY
;
484 mt
->stencil_mt
= intel_miptree_create(brw
,
495 if (!mt
->stencil_mt
) {
496 intel_miptree_release(&mt
);
500 /* Fix up the Z miptree format for how we're splitting out separate
501 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
503 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
506 if (format
== mt
->format
) {
507 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
508 _mesa_get_format_name(mt
->format
));
512 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
516 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
517 * multisampled or have an AUX buffer attached to it.
519 * GEN | MSRT | AUX_CCS_* or AUX_MCS
520 * -------------------------------------------
521 * 9 | HALIGN_16 | HALIGN_16
522 * 8 | HALIGN_ANY | HALIGN_16
526 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
527 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
528 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
529 } else if (brw
->gen
>= 9 && num_samples
> 1) {
530 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
532 /* For now, nothing else has this requirement */
533 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
536 brw_miptree_layout(brw
, mt
, layout_flags
);
538 if (mt
->disable_aux_buffers
)
539 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
546 * Choose an appropriate uncompressed format for a requested
547 * compressed format, if unsupported.
550 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
552 /* No need to lower ETC formats on these platforms,
553 * they are supported natively.
555 if (brw
->gen
>= 8 || brw
->is_baytrail
)
559 case MESA_FORMAT_ETC1_RGB8
:
560 return MESA_FORMAT_R8G8B8X8_UNORM
;
561 case MESA_FORMAT_ETC2_RGB8
:
562 return MESA_FORMAT_R8G8B8X8_UNORM
;
563 case MESA_FORMAT_ETC2_SRGB8
:
564 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
565 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
566 return MESA_FORMAT_B8G8R8A8_SRGB
;
567 case MESA_FORMAT_ETC2_RGBA8_EAC
:
568 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
569 return MESA_FORMAT_R8G8B8A8_UNORM
;
570 case MESA_FORMAT_ETC2_R11_EAC
:
571 return MESA_FORMAT_R_UNORM16
;
572 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
573 return MESA_FORMAT_R_SNORM16
;
574 case MESA_FORMAT_ETC2_RG11_EAC
:
575 return MESA_FORMAT_R16G16_UNORM
;
576 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
577 return MESA_FORMAT_R16G16_SNORM
;
579 /* Non ETC1 / ETC2 format */
584 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
586 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
587 unsigned long *pitch
)
589 uint32_t tile_width
, tile_height
;
590 unsigned long stride
, size
, aligned_y
;
592 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
593 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
594 &tile_width
, &tile_height
);
596 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
597 stride
= mt
->total_width
* mt
->cpp
;
598 stride
= ALIGN(stride
, tile_width
);
599 size
= stride
* aligned_y
;
601 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
602 assert(size
% 4096 == 0);
605 assert(size
% (64 * 1024) == 0);
606 *alignment
= 64 * 1024;
612 static struct intel_mipmap_tree
*
613 miptree_create(struct brw_context
*brw
,
622 uint32_t layout_flags
)
624 struct intel_mipmap_tree
*mt
;
625 mesa_format tex_format
= format
;
626 mesa_format etc_format
= MESA_FORMAT_NONE
;
627 uint32_t alloc_flags
= 0;
629 format
= intel_lower_compressed_format(brw
, format
);
631 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
633 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
634 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
635 mt
= intel_miptree_create_layout(brw
, target
, format
,
636 first_level
, last_level
, width0
,
637 height0
, depth0
, num_samples
,
640 * pitch == 0 || height == 0 indicates the null texture
642 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
643 intel_miptree_release(&mt
);
647 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
648 mt
->tiling
= I915_TILING_Y
;
650 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
651 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
654 mt
->etc_format
= etc_format
;
656 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
657 unsigned alignment
= 0;
659 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
661 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
664 if (format
== MESA_FORMAT_S_UINT8
) {
665 /* Align to size of W tile, 64x64. */
666 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
667 ALIGN(mt
->total_width
, 64),
668 ALIGN(mt
->total_height
, 64),
669 mt
->cpp
, &mt
->tiling
, &pitch
,
672 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
673 mt
->total_width
, mt
->total_height
,
674 mt
->cpp
, &mt
->tiling
, &pitch
,
684 struct intel_mipmap_tree
*
685 intel_miptree_create(struct brw_context
*brw
,
694 uint32_t layout_flags
)
696 struct intel_mipmap_tree
*mt
= miptree_create(
698 first_level
, last_level
,
699 width0
, height0
, depth0
, num_samples
,
702 /* If the BO is too large to fit in the aperture, we need to use the
703 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
704 * handle Y-tiling, so we need to fall back to X.
706 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
707 mt
->tiling
== I915_TILING_Y
) {
708 unsigned long pitch
= mt
->pitch
;
709 const uint32_t alloc_flags
=
710 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
711 BO_ALLOC_FOR_RENDER
: 0;
712 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
713 mt
->total_width
, mt
->total_height
);
715 mt
->tiling
= I915_TILING_X
;
716 drm_intel_bo_unreference(mt
->bo
);
717 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
718 mt
->total_width
, mt
->total_height
, mt
->cpp
,
719 &mt
->tiling
, &pitch
, alloc_flags
);
726 intel_miptree_release(&mt
);
731 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
732 assert(mt
->num_samples
> 1);
733 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
734 intel_miptree_release(&mt
);
739 /* If this miptree is capable of supporting fast color clears, set
740 * fast_clear_state appropriately to ensure that fast clears will occur.
741 * Allocation of the MCS miptree will be deferred until the first fast
742 * clear actually occurs.
744 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
745 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
746 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
747 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
753 struct intel_mipmap_tree
*
754 intel_miptree_create_for_bo(struct brw_context
*brw
,
762 uint32_t layout_flags
)
764 struct intel_mipmap_tree
*mt
;
765 uint32_t tiling
, swizzle
;
768 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
770 /* Nothing will be able to use this miptree with the BO if the offset isn't
773 if (tiling
!= I915_TILING_NONE
)
774 assert(offset
% 4096 == 0);
776 /* miptrees can't handle negative pitch. If you need flipping of images,
777 * that's outside of the scope of the mt.
781 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
783 /* The BO already has a tiling format and we shouldn't confuse the lower
784 * layers by making it try to find a tiling format again.
786 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
787 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
789 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
790 mt
= intel_miptree_create_layout(brw
, target
, format
,
792 width
, height
, depth
, 0,
797 drm_intel_bo_reference(bo
);
807 * For a singlesample renderbuffer, this simply wraps the given BO with a
810 * For a multisample renderbuffer, this wraps the window system's
811 * (singlesample) BO with a singlesample miptree attached to the
812 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
813 * that will contain the actual rendering (which is lazily resolved to
814 * irb->singlesample_mt).
817 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
818 struct intel_renderbuffer
*irb
,
820 uint32_t width
, uint32_t height
,
823 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
824 struct intel_mipmap_tree
*multisample_mt
= NULL
;
825 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
826 mesa_format format
= rb
->Format
;
827 int num_samples
= rb
->NumSamples
;
829 /* Only the front and back buffers, which are color buffers, are allocated
830 * through the image loader.
832 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
833 _mesa_get_format_base_format(format
) == GL_RGBA
);
835 singlesample_mt
= intel_miptree_create_for_bo(intel
,
844 if (!singlesample_mt
)
847 /* If this miptree is capable of supporting fast color clears, set
848 * mcs_state appropriately to ensure that fast clears will occur.
849 * Allocation of the MCS miptree will be deferred until the first fast
850 * clear actually occurs.
852 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
853 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
854 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
857 if (num_samples
== 0) {
858 intel_miptree_release(&irb
->mt
);
859 irb
->mt
= singlesample_mt
;
861 assert(!irb
->singlesample_mt
);
863 intel_miptree_release(&irb
->singlesample_mt
);
864 irb
->singlesample_mt
= singlesample_mt
;
867 irb
->mt
->logical_width0
!= width
||
868 irb
->mt
->logical_height0
!= height
) {
869 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
877 irb
->need_downsample
= false;
878 intel_miptree_release(&irb
->mt
);
879 irb
->mt
= multisample_mt
;
885 intel_miptree_release(&irb
->singlesample_mt
);
886 intel_miptree_release(&irb
->mt
);
890 struct intel_mipmap_tree
*
891 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
895 uint32_t num_samples
)
897 struct intel_mipmap_tree
*mt
;
900 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
901 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
902 MIPTREE_LAYOUT_TILING_ANY
;
905 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
906 width
, height
, depth
, num_samples
,
911 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
912 ok
= intel_miptree_alloc_hiz(brw
, mt
);
920 intel_miptree_release(&mt
);
925 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
926 struct intel_mipmap_tree
*src
)
931 intel_miptree_release(dst
);
935 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
943 intel_miptree_release(struct intel_mipmap_tree
**mt
)
948 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
949 if (--(*mt
)->refcount
<= 0) {
952 DBG("%s deleting %p\n", __func__
, *mt
);
954 drm_intel_bo_unreference((*mt
)->bo
);
955 intel_miptree_release(&(*mt
)->stencil_mt
);
956 if ((*mt
)->hiz_buf
) {
957 if ((*mt
)->hiz_buf
->mt
)
958 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
960 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
961 free((*mt
)->hiz_buf
);
963 intel_miptree_release(&(*mt
)->mcs_mt
);
964 intel_resolve_map_clear(&(*mt
)->hiz_map
);
966 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
967 free((*mt
)->level
[i
].slice
);
977 intel_get_image_dims(struct gl_texture_image
*image
,
978 int *width
, int *height
, int *depth
)
980 switch (image
->TexObject
->Target
) {
981 case GL_TEXTURE_1D_ARRAY
:
982 /* For a 1D Array texture the OpenGL API will treat the image height as
983 * the number of array slices. For Intel hardware, we treat the 1D array
984 * as a 2D Array with a height of 1. So, here we want to swap image
987 *width
= image
->Width
;
989 *depth
= image
->Height
;
992 *width
= image
->Width
;
993 *height
= image
->Height
;
994 *depth
= image
->Depth
;
1000 * Can the image be pulled into a unified mipmap tree? This mirrors
1001 * the completeness test in a lot of ways.
1003 * Not sure whether I want to pass gl_texture_image here.
1006 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1007 struct gl_texture_image
*image
)
1009 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1010 GLuint level
= intelImage
->base
.Base
.Level
;
1011 int width
, height
, depth
;
1013 /* glTexImage* choose the texture object based on the target passed in, and
1014 * objects can't change targets over their lifetimes, so this should be
1017 assert(image
->TexObject
->Target
== mt
->target
);
1019 mesa_format mt_format
= mt
->format
;
1020 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1021 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1022 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1023 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1024 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1025 mt_format
= mt
->etc_format
;
1027 if (image
->TexFormat
!= mt_format
)
1030 intel_get_image_dims(image
, &width
, &height
, &depth
);
1032 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1035 int level_depth
= mt
->level
[level
].depth
;
1036 if (mt
->num_samples
> 1) {
1037 switch (mt
->msaa_layout
) {
1038 case INTEL_MSAA_LAYOUT_NONE
:
1039 case INTEL_MSAA_LAYOUT_IMS
:
1041 case INTEL_MSAA_LAYOUT_UMS
:
1042 case INTEL_MSAA_LAYOUT_CMS
:
1043 level_depth
/= mt
->num_samples
;
1048 /* Test image dimensions against the base level image adjusted for
1049 * minification. This will also catch images not present in the
1050 * tree, changed targets, etc.
1052 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1053 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1054 depth
!= level_depth
) {
1058 if (image
->NumSamples
!= mt
->num_samples
)
1066 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1068 GLuint x
, GLuint y
, GLuint d
)
1070 mt
->level
[level
].depth
= d
;
1071 mt
->level
[level
].level_x
= x
;
1072 mt
->level
[level
].level_y
= y
;
1074 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1077 assert(mt
->level
[level
].slice
== NULL
);
1079 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1080 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1081 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1086 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1087 GLuint level
, GLuint img
,
1090 if (img
== 0 && level
== 0)
1091 assert(x
== 0 && y
== 0);
1093 assert(img
< mt
->level
[level
].depth
);
1095 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1096 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1098 DBG("%s level %d img %d pos %d,%d\n",
1099 __func__
, level
, img
,
1100 mt
->level
[level
].slice
[img
].x_offset
,
1101 mt
->level
[level
].slice
[img
].y_offset
);
1105 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1106 GLuint level
, GLuint slice
,
1107 GLuint
*x
, GLuint
*y
)
1109 assert(slice
< mt
->level
[level
].depth
);
1111 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1112 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1117 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1118 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1119 * and tile_h is set to 1.
1122 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1123 uint32_t *tile_w
, uint32_t *tile_h
)
1125 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1135 case I915_TILING_NONE
:
1140 unreachable("not reached");
1143 uint32_t aspect_ratio
= 1;
1144 assert(_mesa_is_pow_two(cpp
));
1159 unreachable("not reached");
1162 if (cpp
== 2 || cpp
== 8)
1165 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1168 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1174 * This function computes masks that may be used to select the bits of the X
1175 * and Y coordinates that indicate the offset within a tile. If the BO is
1176 * untiled, the masks are set to 0.
1179 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1180 bool map_stencil_as_y_tiled
,
1181 uint32_t *mask_x
, uint32_t *mask_y
)
1183 uint32_t tile_w_bytes
, tile_h
;
1184 if (map_stencil_as_y_tiled
)
1185 tiling
= I915_TILING_Y
;
1187 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1189 *mask_x
= tile_w_bytes
/ cpp
- 1;
1190 *mask_y
= tile_h
- 1;
1194 * Compute the offset (in bytes) from the start of the BO to the given x
1195 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1196 * multiples of the tile size.
1199 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1200 uint32_t x
, uint32_t y
,
1201 bool map_stencil_as_y_tiled
)
1204 uint32_t pitch
= mt
->pitch
;
1205 uint32_t tiling
= mt
->tiling
;
1207 if (map_stencil_as_y_tiled
) {
1208 tiling
= I915_TILING_Y
;
1210 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1211 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1212 * the resulting surface is twice the pitch of the original miptree,
1213 * since each row in the Y-tiled view corresponds to two rows in the
1214 * actual W-tiled surface. So we need to correct the pitch before
1215 * computing the offsets.
1222 unreachable("not reached");
1223 case I915_TILING_NONE
:
1224 return y
* pitch
+ x
* cpp
;
1226 assert((x
% (512 / cpp
)) == 0);
1227 assert((y
% 8) == 0);
1228 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1230 assert((x
% (128 / cpp
)) == 0);
1231 assert((y
% 32) == 0);
1232 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1237 * Rendering with tiled buffers requires that the base address of the buffer
1238 * be aligned to a page boundary. For renderbuffers, and sometimes with
1239 * textures, we may want the surface to point at a texture image level that
1240 * isn't at a page boundary.
1242 * This function returns an appropriately-aligned base offset
1243 * according to the tiling restrictions, plus any required x/y offset
1247 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1248 GLuint level
, GLuint slice
,
1253 uint32_t mask_x
, mask_y
;
1255 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1256 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1258 *tile_x
= x
& mask_x
;
1259 *tile_y
= y
& mask_y
;
1261 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1265 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1266 struct intel_mipmap_tree
*dst_mt
,
1267 struct intel_mipmap_tree
*src_mt
,
1274 ptrdiff_t src_stride
, dst_stride
;
1275 int cpp
= dst_mt
->cpp
;
1277 intel_miptree_map(brw
, src_mt
,
1281 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1284 intel_miptree_map(brw
, dst_mt
,
1288 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1292 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1293 _mesa_get_format_name(src_mt
->format
),
1294 src_mt
, src
, src_stride
,
1295 _mesa_get_format_name(dst_mt
->format
),
1296 dst_mt
, dst
, dst_stride
,
1299 int row_size
= cpp
* width
;
1300 if (src_stride
== row_size
&&
1301 dst_stride
== row_size
) {
1302 memcpy(dst
, src
, row_size
* height
);
1304 for (int i
= 0; i
< height
; i
++) {
1305 memcpy(dst
, src
, row_size
);
1311 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1312 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1314 /* Don't forget to copy the stencil data over, too. We could have skipped
1315 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1316 * shuffling the two data sources in/out of temporary storage instead of
1317 * the direct mapping we get this way.
1319 if (dst_mt
->stencil_mt
) {
1320 assert(src_mt
->stencil_mt
);
1321 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1322 level
, slice
, width
, height
);
1327 intel_miptree_copy_slice(struct brw_context
*brw
,
1328 struct intel_mipmap_tree
*dst_mt
,
1329 struct intel_mipmap_tree
*src_mt
,
1335 mesa_format format
= src_mt
->format
;
1336 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1337 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1345 assert(depth
< src_mt
->level
[level
].depth
);
1346 assert(src_mt
->format
== dst_mt
->format
);
1348 if (dst_mt
->compressed
) {
1350 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1351 height
= ALIGN_NPOT(height
, j
) / j
;
1352 width
= ALIGN_NPOT(width
, i
) / i
;
1355 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1356 * below won't apply since we can't do the depth's Y tiling or the
1357 * stencil's W tiling in the blitter.
1359 if (src_mt
->stencil_mt
) {
1360 intel_miptree_copy_slice_sw(brw
,
1367 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1368 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1369 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1371 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1372 _mesa_get_format_name(src_mt
->format
),
1373 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1374 _mesa_get_format_name(dst_mt
->format
),
1375 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1378 if (!intel_miptree_blit(brw
,
1379 src_mt
, level
, slice
, 0, 0, false,
1380 dst_mt
, level
, slice
, 0, 0, false,
1381 width
, height
, GL_COPY
)) {
1382 perf_debug("miptree validate blit for %s failed\n",
1383 _mesa_get_format_name(format
));
1385 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1391 * Copies the image's current data to the given miptree, and associates that
1392 * miptree with the image.
1394 * If \c invalidate is true, then the actual image data does not need to be
1395 * copied, but the image still needs to be associated to the new miptree (this
1396 * is set to true if we're about to clear the image).
1399 intel_miptree_copy_teximage(struct brw_context
*brw
,
1400 struct intel_texture_image
*intelImage
,
1401 struct intel_mipmap_tree
*dst_mt
,
1404 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1405 struct intel_texture_object
*intel_obj
=
1406 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1407 int level
= intelImage
->base
.Base
.Level
;
1408 int face
= intelImage
->base
.Base
.Face
;
1411 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1412 depth
= intelImage
->base
.Base
.Height
;
1414 depth
= intelImage
->base
.Base
.Depth
;
1417 for (int slice
= 0; slice
< depth
; slice
++) {
1418 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1422 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1423 intel_obj
->needs_validate
= true;
1427 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1428 struct intel_mipmap_tree
*mt
,
1431 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1432 assert(mt
->mcs_mt
== NULL
);
1433 assert(!mt
->disable_aux_buffers
);
1435 /* Choose the correct format for the MCS buffer. All that really matters
1436 * is that we allocate the right buffer size, since we'll always be
1437 * accessing this miptree using MCS-specific hardware mechanisms, which
1438 * infer the correct format based on num_samples.
1441 switch (num_samples
) {
1444 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1447 format
= MESA_FORMAT_R_UNORM8
;
1450 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1451 * for each sample, plus 8 padding bits).
1453 format
= MESA_FORMAT_R_UINT32
;
1456 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1459 format
= MESA_FORMAT_RG_UINT32
;
1462 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1465 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1467 * "The MCS surface must be stored as Tile Y."
1469 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1470 MIPTREE_LAYOUT_TILING_Y
;
1471 mt
->mcs_mt
= miptree_create(brw
,
1477 mt
->logical_height0
,
1479 0 /* num_samples */,
1482 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1484 * When MCS buffer is enabled and bound to MSRT, it is required that it
1485 * is cleared prior to any rendering.
1487 * Since we don't use the MCS buffer for any purpose other than rendering,
1488 * it makes sense to just clear it immediately upon allocation.
1490 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1492 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1493 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1494 intel_miptree_unmap_raw(mt
->mcs_mt
);
1495 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1502 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*mt
)
1505 assert(mt
->mcs_mt
== NULL
);
1506 assert(!mt
->disable_aux_buffers
);
1508 /* The format of the MCS buffer is opaque to the driver; all that matters
1509 * is that we get its size and pitch right. We'll pretend that the format
1510 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1511 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1512 * the block width and then a further factor of 4. Since an MCS tile
1513 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1514 * we'll need to scale the height down by the block height and then a
1515 * further factor of 8.
1517 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1518 unsigned block_width_px
;
1519 unsigned block_height
;
1520 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1521 unsigned width_divisor
= block_width_px
* 4;
1522 unsigned height_divisor
= block_height
* 8;
1524 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1526 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1527 * in the main surface. In Skylake, it's two bits. The extra bit
1528 * doubles the MCS height, not width, because in Skylake the MCS is always
1532 height_divisor
/= 2;
1534 unsigned mcs_width
=
1535 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1536 unsigned mcs_height
=
1537 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1538 assert(mt
->logical_depth0
== 1);
1539 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1540 MIPTREE_LAYOUT_TILING_Y
;
1541 if (brw
->gen
>= 8) {
1542 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1544 mt
->mcs_mt
= miptree_create(brw
,
1552 0 /* num_samples */,
1560 * Helper for intel_miptree_alloc_hiz() that sets
1561 * \c mt->level[level].has_hiz. Return true if and only if
1562 * \c has_hiz was set.
1565 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1566 struct intel_mipmap_tree
*mt
,
1569 assert(mt
->hiz_buf
);
1571 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1572 uint32_t width
= minify(mt
->physical_width0
, level
);
1573 uint32_t height
= minify(mt
->physical_height0
, level
);
1575 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1576 * and the height is 4 aligned. This allows our HiZ support
1577 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1578 * we can grow the width & height to allow the HiZ op to
1579 * force the proper size alignments.
1581 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1582 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1587 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1588 mt
->level
[level
].has_hiz
= true;
1594 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1595 * buffer dimensions and allocates a bo for the hiz buffer.
1597 static struct intel_miptree_aux_buffer
*
1598 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1599 struct intel_mipmap_tree
*mt
)
1601 unsigned z_width
= mt
->logical_width0
;
1602 unsigned z_height
= mt
->logical_height0
;
1603 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1604 unsigned hz_width
, hz_height
;
1605 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1610 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1611 * adjustments required for Z_Height and Z_Width based on multisampling.
1613 switch (mt
->num_samples
) {
1627 unreachable("unsupported sample count");
1630 const unsigned vertical_align
= 8; /* 'j' in the docs */
1631 const unsigned H0
= z_height
;
1632 const unsigned h0
= ALIGN(H0
, vertical_align
);
1633 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1634 const unsigned Z0
= z_depth
;
1636 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1637 hz_width
= ALIGN(z_width
, 16);
1639 if (mt
->target
== GL_TEXTURE_3D
) {
1643 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1644 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1645 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1646 hz_height
+= h_i
* Z_i
;
1647 H_i
= minify(H_i
, 1);
1648 Z_i
= minify(Z_i
, 1);
1651 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1653 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1655 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1656 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1657 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1658 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1659 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1661 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1662 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1666 unsigned long pitch
;
1667 uint32_t tiling
= I915_TILING_Y
;
1668 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1669 hz_width
, hz_height
, 1,
1671 BO_ALLOC_FOR_RENDER
);
1675 } else if (tiling
!= I915_TILING_Y
) {
1676 drm_intel_bo_unreference(buf
->bo
);
1688 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1689 * buffer dimensions and allocates a bo for the hiz buffer.
1691 static struct intel_miptree_aux_buffer
*
1692 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1693 struct intel_mipmap_tree
*mt
)
1695 unsigned z_width
= mt
->logical_width0
;
1696 unsigned z_height
= mt
->logical_height0
;
1697 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1698 unsigned hz_width
, hz_height
;
1699 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1704 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1705 * adjustments required for Z_Height and Z_Width based on multisampling.
1708 switch (mt
->num_samples
) {
1722 unreachable("unsupported sample count");
1726 const unsigned vertical_align
= 8; /* 'j' in the docs */
1727 const unsigned H0
= z_height
;
1728 const unsigned h0
= ALIGN(H0
, vertical_align
);
1729 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1730 const unsigned Z0
= z_depth
;
1732 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1733 hz_width
= ALIGN(z_width
, 16);
1737 unsigned sum_h_i
= 0;
1738 unsigned hz_height_3d_sum
= 0;
1739 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1740 unsigned i
= level
- mt
->first_level
;
1741 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1742 /* sum(i=2 to m; h_i) */
1746 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1747 hz_height_3d_sum
+= h_i
* Z_i
;
1748 H_i
= minify(H_i
, 1);
1749 Z_i
= minify(Z_i
, 1);
1751 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1752 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1754 if (mt
->target
== GL_TEXTURE_3D
) {
1755 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1756 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1758 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1759 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1760 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1761 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1762 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1764 * We can can just take our hz_height calculation from above, and
1765 * multiply by 6 for the cube map and cube map array types.
1771 unsigned long pitch
;
1772 uint32_t tiling
= I915_TILING_Y
;
1773 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1774 hz_width
, hz_height
, 1,
1776 BO_ALLOC_FOR_RENDER
);
1780 } else if (tiling
!= I915_TILING_Y
) {
1781 drm_intel_bo_unreference(buf
->bo
);
1792 static struct intel_miptree_aux_buffer
*
1793 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1794 struct intel_mipmap_tree
*mt
)
1796 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1797 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1800 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1805 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1806 buf
->mt
= intel_miptree_create(brw
,
1812 mt
->logical_height0
,
1821 buf
->bo
= buf
->mt
->bo
;
1822 buf
->pitch
= buf
->mt
->pitch
;
1823 buf
->qpitch
= buf
->mt
->qpitch
;
1829 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1830 struct intel_mipmap_tree
*mt
)
1835 if (mt
->hiz_buf
!= NULL
)
1838 if (mt
->disable_aux_buffers
)
1841 switch (mt
->format
) {
1842 case MESA_FORMAT_Z_FLOAT32
:
1843 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1844 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1845 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1846 case MESA_FORMAT_Z_UNORM16
:
1854 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1855 struct intel_mipmap_tree
*mt
)
1857 assert(mt
->hiz_buf
== NULL
);
1858 assert(!mt
->disable_aux_buffers
);
1860 if (brw
->gen
== 7) {
1861 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1862 } else if (brw
->gen
>= 8) {
1863 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1865 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1871 /* Mark that all slices need a HiZ resolve. */
1872 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1873 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1876 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1877 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1878 exec_node_init(&m
->link
);
1881 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1883 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1891 * Does the miptree slice have hiz enabled?
1894 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1896 intel_miptree_check_level_layer(mt
, level
, 0);
1897 return mt
->level
[level
].has_hiz
;
1901 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1905 if (!intel_miptree_level_has_hiz(mt
, level
))
1908 intel_resolve_map_set(&mt
->hiz_map
,
1909 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1914 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1918 if (!intel_miptree_level_has_hiz(mt
, level
))
1921 intel_resolve_map_set(&mt
->hiz_map
,
1922 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1926 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1930 uint32_t end_layer
= mt
->level
[level
].depth
;
1932 for (layer
= 0; layer
< end_layer
; layer
++) {
1933 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1938 intel_miptree_slice_resolve(struct brw_context
*brw
,
1939 struct intel_mipmap_tree
*mt
,
1942 enum gen6_hiz_op need
)
1944 intel_miptree_check_level_layer(mt
, level
, layer
);
1946 struct intel_resolve_map
*item
=
1947 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1949 if (!item
|| item
->need
!= need
)
1952 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1953 intel_resolve_map_remove(item
);
1958 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1959 struct intel_mipmap_tree
*mt
,
1963 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1964 GEN6_HIZ_OP_HIZ_RESOLVE
);
1968 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1969 struct intel_mipmap_tree
*mt
,
1973 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1974 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1978 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1979 struct intel_mipmap_tree
*mt
,
1980 enum gen6_hiz_op need
)
1982 bool did_resolve
= false;
1984 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1985 if (map
->need
!= need
)
1988 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1989 intel_resolve_map_remove(map
);
1997 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1998 struct intel_mipmap_tree
*mt
)
2000 return intel_miptree_all_slices_resolve(brw
, mt
,
2001 GEN6_HIZ_OP_HIZ_RESOLVE
);
2005 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2006 struct intel_mipmap_tree
*mt
)
2008 return intel_miptree_all_slices_resolve(brw
, mt
,
2009 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2014 intel_miptree_resolve_color(struct brw_context
*brw
,
2015 struct intel_mipmap_tree
*mt
)
2017 switch (mt
->fast_clear_state
) {
2018 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2019 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2020 /* No resolve needed */
2022 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2023 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2024 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2025 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
2026 brw_meta_resolve_color(brw
, mt
);
2033 * Make it possible to share the BO backing the given miptree with another
2034 * process or another miptree.
2036 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2037 * then discard the MCS buffer, if present. We also set the fast_clear_state
2038 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2039 * allocated in the future.
2042 intel_miptree_make_shareable(struct brw_context
*brw
,
2043 struct intel_mipmap_tree
*mt
)
2045 /* MCS buffers are also used for multisample buffers, but we can't resolve
2046 * away a multisample MCS buffer because it's an integral part of how the
2047 * pixel data is stored. Fortunately this code path should never be
2048 * reached for multisample buffers.
2050 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2053 intel_miptree_resolve_color(brw
, mt
);
2054 intel_miptree_release(&mt
->mcs_mt
);
2055 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2061 * \brief Get pointer offset into stencil buffer.
2063 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2064 * must decode the tile's layout in software.
2067 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2069 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2071 * Even though the returned offset is always positive, the return type is
2073 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2074 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2077 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2079 uint32_t tile_size
= 4096;
2080 uint32_t tile_width
= 64;
2081 uint32_t tile_height
= 64;
2082 uint32_t row_size
= 64 * stride
;
2084 uint32_t tile_x
= x
/ tile_width
;
2085 uint32_t tile_y
= y
/ tile_height
;
2087 /* The byte's address relative to the tile's base addres. */
2088 uint32_t byte_x
= x
% tile_width
;
2089 uint32_t byte_y
= y
% tile_height
;
2091 uintptr_t u
= tile_y
* row_size
2092 + tile_x
* tile_size
2093 + 512 * (byte_x
/ 8)
2095 + 32 * ((byte_y
/ 4) % 2)
2096 + 16 * ((byte_x
/ 4) % 2)
2097 + 8 * ((byte_y
/ 2) % 2)
2098 + 4 * ((byte_x
/ 2) % 2)
2103 /* adjust for bit6 swizzling */
2104 if (((byte_x
/ 8) % 2) == 1) {
2105 if (((byte_y
/ 8) % 2) == 0) {
2117 intel_miptree_updownsample(struct brw_context
*brw
,
2118 struct intel_mipmap_tree
*src
,
2119 struct intel_mipmap_tree
*dst
)
2122 brw_blorp_blit_miptrees(brw
,
2123 src
, 0 /* level */, 0 /* layer */, src
->format
,
2124 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2126 src
->logical_width0
, src
->logical_height0
,
2128 dst
->logical_width0
, dst
->logical_height0
,
2129 GL_NEAREST
, false, false /*mirror x, y*/);
2130 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2131 brw_meta_stencil_updownsample(brw
, src
, dst
);
2133 brw_meta_updownsample(brw
, src
, dst
);
2136 if (src
->stencil_mt
) {
2137 if (brw
->gen
>= 8) {
2138 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2142 brw_blorp_blit_miptrees(brw
,
2143 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2144 src
->stencil_mt
->format
,
2145 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2146 dst
->stencil_mt
->format
,
2148 src
->logical_width0
, src
->logical_height0
,
2150 dst
->logical_width0
, dst
->logical_height0
,
2151 GL_NEAREST
, false, false /*mirror x, y*/);
2156 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2158 /* CPU accesses to color buffers don't understand fast color clears, so
2159 * resolve any pending fast color clears before we map.
2161 intel_miptree_resolve_color(brw
, mt
);
2163 drm_intel_bo
*bo
= mt
->bo
;
2165 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2166 intel_batchbuffer_flush(brw
);
2168 if (mt
->tiling
!= I915_TILING_NONE
)
2169 brw_bo_map_gtt(brw
, bo
, "miptree");
2171 brw_bo_map(brw
, bo
, true, "miptree");
2177 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2179 drm_intel_bo_unmap(mt
->bo
);
2183 intel_miptree_map_gtt(struct brw_context
*brw
,
2184 struct intel_mipmap_tree
*mt
,
2185 struct intel_miptree_map
*map
,
2186 unsigned int level
, unsigned int slice
)
2188 unsigned int bw
, bh
;
2190 unsigned int image_x
, image_y
;
2191 intptr_t x
= map
->x
;
2192 intptr_t y
= map
->y
;
2194 /* For compressed formats, the stride is the number of bytes per
2195 * row of blocks. intel_miptree_get_image_offset() already does
2198 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2199 assert(y
% bh
== 0);
2200 assert(x
% bw
== 0);
2204 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2209 /* Note that in the case of cube maps, the caller must have passed the
2210 * slice number referencing the face.
2212 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2216 map
->stride
= mt
->pitch
;
2217 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2220 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2221 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2222 map
->x
, map
->y
, map
->w
, map
->h
,
2223 mt
, _mesa_get_format_name(mt
->format
),
2224 x
, y
, map
->ptr
, map
->stride
);
2228 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2230 intel_miptree_unmap_raw(mt
);
2234 intel_miptree_map_blit(struct brw_context
*brw
,
2235 struct intel_mipmap_tree
*mt
,
2236 struct intel_miptree_map
*map
,
2237 unsigned int level
, unsigned int slice
)
2239 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2240 /* first_level */ 0,
2244 MIPTREE_LAYOUT_TILING_NONE
);
2246 if (!map
->linear_mt
) {
2247 fprintf(stderr
, "Failed to allocate blit temporary\n");
2250 map
->stride
= map
->linear_mt
->pitch
;
2252 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2253 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2254 * invalidate is set, since we'll be writing the whole rectangle from our
2255 * temporary buffer back out.
2257 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2258 if (!intel_miptree_blit(brw
,
2260 map
->x
, map
->y
, false,
2261 map
->linear_mt
, 0, 0,
2263 map
->w
, map
->h
, GL_COPY
)) {
2264 fprintf(stderr
, "Failed to blit\n");
2269 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2271 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2272 map
->x
, map
->y
, map
->w
, map
->h
,
2273 mt
, _mesa_get_format_name(mt
->format
),
2274 level
, slice
, map
->ptr
, map
->stride
);
2279 intel_miptree_release(&map
->linear_mt
);
2285 intel_miptree_unmap_blit(struct brw_context
*brw
,
2286 struct intel_mipmap_tree
*mt
,
2287 struct intel_miptree_map
*map
,
2291 struct gl_context
*ctx
= &brw
->ctx
;
2293 intel_miptree_unmap_raw(map
->linear_mt
);
2295 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2296 bool ok
= intel_miptree_blit(brw
,
2297 map
->linear_mt
, 0, 0,
2300 map
->x
, map
->y
, false,
2301 map
->w
, map
->h
, GL_COPY
);
2302 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2305 intel_miptree_release(&map
->linear_mt
);
2309 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2311 #if defined(USE_SSE41)
2313 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2314 struct intel_mipmap_tree
*mt
,
2315 struct intel_miptree_map
*map
,
2316 unsigned int level
, unsigned int slice
)
2318 assert(map
->mode
& GL_MAP_READ_BIT
);
2319 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2321 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2322 map
->x
, map
->y
, map
->w
, map
->h
,
2323 mt
, _mesa_get_format_name(mt
->format
),
2324 level
, slice
, map
->ptr
, map
->stride
);
2326 /* Map the original image */
2329 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2333 void *src
= intel_miptree_map_raw(brw
, mt
);
2336 src
+= image_y
* mt
->pitch
;
2337 src
+= image_x
* mt
->cpp
;
2339 /* Due to the pixel offsets for the particular image being mapped, our
2340 * src pointer may not be 16-byte aligned. However, if the pitch is
2341 * divisible by 16, then the amount by which it's misaligned will remain
2342 * consistent from row to row.
2344 assert((mt
->pitch
% 16) == 0);
2345 const int misalignment
= ((uintptr_t) src
) & 15;
2347 /* Create an untiled temporary buffer for the mapping. */
2348 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2350 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2352 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2353 /* Offset the destination so it has the same misalignment as src. */
2354 map
->ptr
= map
->buffer
+ misalignment
;
2356 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2358 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2359 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2360 void *src_ptr
= src
+ y
* mt
->pitch
;
2362 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2365 intel_miptree_unmap_raw(mt
);
2369 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2370 struct intel_mipmap_tree
*mt
,
2371 struct intel_miptree_map
*map
,
2375 _mesa_align_free(map
->buffer
);
2382 intel_miptree_map_s8(struct brw_context
*brw
,
2383 struct intel_mipmap_tree
*mt
,
2384 struct intel_miptree_map
*map
,
2385 unsigned int level
, unsigned int slice
)
2387 map
->stride
= map
->w
;
2388 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2392 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2393 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2394 * invalidate is set, since we'll be writing the whole rectangle from our
2395 * temporary buffer back out.
2397 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2398 uint8_t *untiled_s8_map
= map
->ptr
;
2399 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2400 unsigned int image_x
, image_y
;
2402 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2404 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2405 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2406 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2407 x
+ image_x
+ map
->x
,
2408 y
+ image_y
+ map
->y
,
2409 brw
->has_swizzling
);
2410 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2414 intel_miptree_unmap_raw(mt
);
2416 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2417 map
->x
, map
->y
, map
->w
, map
->h
,
2418 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2420 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2421 map
->x
, map
->y
, map
->w
, map
->h
,
2422 mt
, map
->ptr
, map
->stride
);
2427 intel_miptree_unmap_s8(struct brw_context
*brw
,
2428 struct intel_mipmap_tree
*mt
,
2429 struct intel_miptree_map
*map
,
2433 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2434 unsigned int image_x
, image_y
;
2435 uint8_t *untiled_s8_map
= map
->ptr
;
2436 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2438 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2440 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2441 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2442 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2445 brw
->has_swizzling
);
2446 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2450 intel_miptree_unmap_raw(mt
);
2457 intel_miptree_map_etc(struct brw_context
*brw
,
2458 struct intel_mipmap_tree
*mt
,
2459 struct intel_miptree_map
*map
,
2463 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2464 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2465 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2468 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2469 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2471 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2472 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2473 map
->w
, map
->h
, 1));
2474 map
->ptr
= map
->buffer
;
2478 intel_miptree_unmap_etc(struct brw_context
*brw
,
2479 struct intel_mipmap_tree
*mt
,
2480 struct intel_miptree_map
*map
,
2486 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2491 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2492 + image_y
* mt
->pitch
2493 + image_x
* mt
->cpp
;
2495 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2496 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2497 map
->ptr
, map
->stride
,
2500 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2501 map
->ptr
, map
->stride
,
2502 map
->w
, map
->h
, mt
->etc_format
);
2504 intel_miptree_unmap_raw(mt
);
2509 * Mapping function for packed depth/stencil miptrees backed by real separate
2510 * miptrees for depth and stencil.
2512 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2513 * separate from the depth buffer. Yet at the GL API level, we have to expose
2514 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2515 * be able to map that memory for texture storage and glReadPixels-type
2516 * operations. We give Mesa core that access by mallocing a temporary and
2517 * copying the data between the actual backing store and the temporary.
2520 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2521 struct intel_mipmap_tree
*mt
,
2522 struct intel_miptree_map
*map
,
2523 unsigned int level
, unsigned int slice
)
2525 struct intel_mipmap_tree
*z_mt
= mt
;
2526 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2527 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2528 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2530 map
->stride
= map
->w
* packed_bpp
;
2531 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2535 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2536 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2537 * invalidate is set, since we'll be writing the whole rectangle from our
2538 * temporary buffer back out.
2540 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2541 uint32_t *packed_map
= map
->ptr
;
2542 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2543 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2544 unsigned int s_image_x
, s_image_y
;
2545 unsigned int z_image_x
, z_image_y
;
2547 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2548 &s_image_x
, &s_image_y
);
2549 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2550 &z_image_x
, &z_image_y
);
2552 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2553 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2554 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2555 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2558 brw
->has_swizzling
);
2559 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2561 (map_x
+ z_image_x
));
2562 uint8_t s
= s_map
[s_offset
];
2563 uint32_t z
= z_map
[z_offset
];
2565 if (map_z32f_x24s8
) {
2566 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2567 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2569 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2574 intel_miptree_unmap_raw(s_mt
);
2575 intel_miptree_unmap_raw(z_mt
);
2577 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2579 map
->x
, map
->y
, map
->w
, map
->h
,
2580 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2581 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2582 map
->ptr
, map
->stride
);
2584 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2585 map
->x
, map
->y
, map
->w
, map
->h
,
2586 mt
, map
->ptr
, map
->stride
);
2591 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2592 struct intel_mipmap_tree
*mt
,
2593 struct intel_miptree_map
*map
,
2597 struct intel_mipmap_tree
*z_mt
= mt
;
2598 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2599 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2601 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2602 uint32_t *packed_map
= map
->ptr
;
2603 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2604 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2605 unsigned int s_image_x
, s_image_y
;
2606 unsigned int z_image_x
, z_image_y
;
2608 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2609 &s_image_x
, &s_image_y
);
2610 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2611 &z_image_x
, &z_image_y
);
2613 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2614 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2615 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2616 x
+ s_image_x
+ map
->x
,
2617 y
+ s_image_y
+ map
->y
,
2618 brw
->has_swizzling
);
2619 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2621 (x
+ z_image_x
+ map
->x
));
2623 if (map_z32f_x24s8
) {
2624 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2625 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2627 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2628 s_map
[s_offset
] = packed
>> 24;
2629 z_map
[z_offset
] = packed
;
2634 intel_miptree_unmap_raw(s_mt
);
2635 intel_miptree_unmap_raw(z_mt
);
2637 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2639 map
->x
, map
->y
, map
->w
, map
->h
,
2640 z_mt
, _mesa_get_format_name(z_mt
->format
),
2641 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2642 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2643 map
->ptr
, map
->stride
);
2650 * Create and attach a map to the miptree at (level, slice). Return the
2653 static struct intel_miptree_map
*
2654 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2663 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2668 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2669 mt
->level
[level
].slice
[slice
].map
= map
;
2681 * Release the map at (level, slice).
2684 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2688 struct intel_miptree_map
**map
;
2690 map
= &mt
->level
[level
].slice
[slice
].map
;
2696 can_blit_slice(struct intel_mipmap_tree
*mt
,
2697 unsigned int level
, unsigned int slice
)
2701 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2702 if (image_x
>= 32768 || image_y
>= 32768)
2705 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2706 if (mt
->pitch
>= 32768)
2713 use_intel_mipree_map_blit(struct brw_context
*brw
,
2714 struct intel_mipmap_tree
*mt
,
2720 /* It's probably not worth swapping to the blit ring because of
2721 * all the overhead involved. But, we must use blitter for the
2722 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2724 (!(mode
& GL_MAP_WRITE_BIT
) ||
2725 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2727 (mt
->tiling
== I915_TILING_X
||
2728 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2729 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2730 /* Fast copy blit on skl+ supports all tiling formats. */
2732 can_blit_slice(mt
, level
, slice
))
2735 if (mt
->tiling
!= I915_TILING_NONE
&&
2736 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2737 assert(can_blit_slice(mt
, level
, slice
));
2745 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2746 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2747 * arithmetic overflow.
2749 * If you call this function and use \a out_stride, then you're doing pointer
2750 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2751 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2752 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2753 * which usually have type uint32_t or GLuint.
2756 intel_miptree_map(struct brw_context
*brw
,
2757 struct intel_mipmap_tree
*mt
,
2766 ptrdiff_t *out_stride
)
2768 struct intel_miptree_map
*map
;
2770 assert(mt
->num_samples
<= 1);
2772 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2779 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2780 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2781 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2784 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2785 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2786 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2787 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2788 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2789 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2790 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2791 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2792 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2793 #if defined(USE_SSE41)
2794 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2795 !mt
->compressed
&& cpu_has_sse4_1
&&
2796 (mt
->pitch
% 16 == 0)) {
2797 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2800 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2801 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2802 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2805 *out_ptr
= map
->ptr
;
2806 *out_stride
= map
->stride
;
2808 if (map
->ptr
== NULL
)
2809 intel_miptree_release_map(mt
, level
, slice
);
2813 intel_miptree_unmap(struct brw_context
*brw
,
2814 struct intel_mipmap_tree
*mt
,
2818 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2820 assert(mt
->num_samples
<= 1);
2825 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2826 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2828 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2829 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2830 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2831 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2832 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2833 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2834 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2835 } else if (map
->linear_mt
) {
2836 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2837 #if defined(USE_SSE41)
2838 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2839 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2842 intel_miptree_unmap_gtt(mt
);
2845 intel_miptree_release_map(mt
, level
, slice
);