2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_mcs(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
,
63 * Determine which MSAA layout should be used by the MSAA surface being
64 * created, based on the chip generation and the surface type.
66 static enum intel_msaa_layout
67 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
68 uint32_t layout_flags
)
70 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
72 return INTEL_MSAA_LAYOUT_IMS
;
74 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
75 switch (_mesa_get_format_base_format(format
)) {
76 case GL_DEPTH_COMPONENT
:
77 case GL_STENCIL_INDEX
:
78 case GL_DEPTH_STENCIL
:
79 return INTEL_MSAA_LAYOUT_IMS
;
81 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
83 * This field must be set to 0 for all SINT MSRTs when all RT channels
86 * In practice this means that we have to disable MCS for all signed
87 * integer MSAA buffers. The alternative, to disable MCS only when one
88 * of the render target channels is disabled, is impractical because it
89 * would require converting between CMS and UMS MSAA layouts on the fly,
92 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
93 return INTEL_MSAA_LAYOUT_UMS
;
94 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
95 /* We can't use the CMS layout because it uses an aux buffer, the MCS
96 * buffer. So fallback to UMS, which is identical to CMS without the
98 return INTEL_MSAA_LAYOUT_UMS
;
100 return INTEL_MSAA_LAYOUT_CMS
;
106 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 /* This function applies only to non-multisampled render targets. */
153 if (mt
->num_samples
> 1)
156 /* MCS is only supported for color buffers */
157 switch (_mesa_get_format_base_format(mt
->format
)) {
158 case GL_DEPTH_COMPONENT
:
159 case GL_DEPTH_STENCIL
:
160 case GL_STENCIL_INDEX
:
164 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
167 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
168 const bool arrayed
= mt
->physical_depth0
!= 1;
171 /* Multisample surfaces with the CMS layout are not layered surfaces,
172 * yet still have physical_depth0 > 1. Assert that we don't
173 * accidentally reject a multisampled surface here. We should have
174 * rejected it earlier by explicitly checking the sample count.
176 assert(mt
->num_samples
<= 1);
179 /* Handle the hardware restrictions...
181 * All GENs have the following restriction: "MCS buffer for non-MSRT is
182 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
184 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
185 * Non-MultiSampler Render Target Restrictions) Support is for
186 * non-mip-mapped and non-array surface types only.
188 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
189 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
190 * surfaces are supported with MCS buffer layout with these alignments in
191 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
193 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
194 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
195 * surfaces are supported with MCS buffer layout with these alignments in
196 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
198 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
201 /* There's no point in using an MCS buffer if the surface isn't in a
204 if (!brw
->mesa_format_supports_render
[mt
->format
])
208 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
209 const enum isl_format isl_format
=
210 brw_isl_format_for_mesa_format(linear_format
);
211 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
217 intel_miptree_supports_hiz(struct brw_context
*brw
,
218 struct intel_mipmap_tree
*mt
)
223 switch (mt
->format
) {
224 case MESA_FORMAT_Z_FLOAT32
:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
227 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
228 case MESA_FORMAT_Z_UNORM16
:
236 /* On Gen9 support for color buffer compression was extended to single
237 * sampled surfaces. This is a helper considering both auxiliary buffer
238 * type and number of samples telling if the given miptree represents
239 * the new single sampled case - also called lossless compression.
242 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
243 const struct intel_mipmap_tree
*mt
)
245 /* Only available from Gen9 onwards. */
249 /* Compression always requires auxiliary buffer. */
253 /* Single sample compression is represented re-using msaa compression
254 * layout type: "Compressed Multisampled Surfaces".
256 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
259 /* And finally distinguish between msaa and single sample case. */
260 return mt
->num_samples
<= 1;
264 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
265 const struct intel_mipmap_tree
*mt
)
267 /* For now compression is only enabled for integer formats even though
268 * there exist supported floating point formats also. This is a heuristic
269 * decision based on current public benchmarks. In none of the cases these
270 * formats provided any improvement but a few cases were seen to regress.
271 * Hence these are left to to be enabled in the future when they are known
274 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
277 if (!intel_miptree_supports_ccs(brw
, mt
))
280 /* Fast clear can be also used to clear srgb surfaces by using equivalent
281 * linear format. This trick, however, can't be extended to be used with
282 * lossless compression and therefore a check is needed to see if the format
285 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
289 * Determine depth format corresponding to a depth+stencil format,
290 * for separate stencil.
293 intel_depth_format_for_depthstencil_format(mesa_format format
) {
295 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
296 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
297 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
298 return MESA_FORMAT_Z_FLOAT32
;
305 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
306 unsigned depth0
, struct intel_mipmap_level
*table
)
308 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
310 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
312 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
313 if (!table
[level
].slice
)
320 for (unsigned level
= first_level
; level
<= last_level
; level
++)
321 free(table
[level
].slice
);
327 * @param for_bo Indicates that the caller is
328 * intel_miptree_create_for_bo(). If true, then do not create
331 static struct intel_mipmap_tree
*
332 intel_miptree_create_layout(struct brw_context
*brw
,
341 uint32_t layout_flags
)
343 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
347 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
348 _mesa_enum_to_string(target
),
349 _mesa_get_format_name(format
),
350 first_level
, last_level
, depth0
, mt
);
352 if (target
== GL_TEXTURE_1D_ARRAY
)
353 assert(height0
== 1);
357 mt
->first_level
= first_level
;
358 mt
->last_level
= last_level
;
359 mt
->logical_width0
= width0
;
360 mt
->logical_height0
= height0
;
361 mt
->logical_depth0
= depth0
;
362 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
363 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
364 mt
->supports_fast_clear
= false;
365 mt
->aux_state
= NULL
;
366 mt
->cpp
= _mesa_get_format_bytes(format
);
367 mt
->num_samples
= num_samples
;
368 mt
->compressed
= _mesa_is_format_compressed(format
);
369 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
372 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
373 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
375 int depth_multiply
= 1;
376 if (num_samples
> 1) {
377 /* Adjust width/height/depth for MSAA */
378 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
379 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
380 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
381 * "If the surface is multisampled and it is a depth or stencil
382 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
383 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
386 * +----------------------------------------------------------------+
387 * | Num Multisamples | W_l = | H_l = |
388 * +----------------------------------------------------------------+
389 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
390 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
391 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
392 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
393 * +----------------------------------------------------------------+
396 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
397 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
398 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
400 * Another more complicated explanation for these adjustments comes
401 * from the Sandybridge PRM, volume 4, part 1, page 31:
403 * "Any of the other messages (sample*, LOD, load4) used with a
404 * (4x) multisampled surface will in-effect sample a surface with
405 * double the height and width as that indicated in the surface
406 * state. Each pixel position on the original-sized surface is
407 * replaced with a 2x2 of samples with the following arrangement:
412 * Thus, when sampling from a multisampled texture, it behaves as
413 * though the layout in memory for (x,y,sample) is:
415 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
416 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
418 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
419 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
421 * However, the actual layout of multisampled data in memory is:
423 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
424 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
426 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
427 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
429 * This pattern repeats for each 2x2 pixel block.
431 * As a result, when calculating the size of our 4-sample buffer for
432 * an odd width or height, we have to align before scaling up because
433 * sample 3 is in that bottom right 2x2 block.
435 switch (num_samples
) {
437 assert(brw
->gen
>= 8);
438 width0
= ALIGN(width0
, 2) * 2;
439 height0
= ALIGN(height0
, 2);
442 width0
= ALIGN(width0
, 2) * 2;
443 height0
= ALIGN(height0
, 2) * 2;
446 width0
= ALIGN(width0
, 2) * 4;
447 height0
= ALIGN(height0
, 2) * 2;
450 width0
= ALIGN(width0
, 2) * 4;
451 height0
= ALIGN(height0
, 2) * 4;
454 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
457 unreachable("not reached");
460 /* Non-interleaved */
461 depth_multiply
= num_samples
;
462 depth0
*= depth_multiply
;
466 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
472 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
473 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
474 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
475 * used on Gen8 to make it pick a qpitch value which doesn't include space
476 * for the mipmaps. On Gen9 this is not necessary because it will
477 * automatically pick a packed qpitch value whenever mt->first_level ==
479 * TODO: can we use it elsewhere?
480 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
483 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
485 switch (mt
->msaa_layout
) {
486 case INTEL_MSAA_LAYOUT_NONE
:
487 case INTEL_MSAA_LAYOUT_IMS
:
488 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
490 case INTEL_MSAA_LAYOUT_UMS
:
491 case INTEL_MSAA_LAYOUT_CMS
:
492 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
497 if (target
== GL_TEXTURE_CUBE_MAP
)
498 assert(depth0
== 6 * depth_multiply
);
500 mt
->physical_width0
= width0
;
501 mt
->physical_height0
= height0
;
502 mt
->physical_depth0
= depth0
;
504 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
505 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
506 (brw
->must_use_separate_stencil
||
507 (brw
->has_separate_stencil
&& intel_miptree_supports_hiz(brw
, mt
)))) {
508 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
510 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
513 mt
->stencil_mt
= intel_miptree_create(brw
,
524 if (!mt
->stencil_mt
) {
525 intel_miptree_release(&mt
);
528 mt
->stencil_mt
->r8stencil_needs_update
= true;
530 /* Fix up the Z miptree format for how we're splitting out separate
531 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
533 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
536 if (format
== mt
->format
) {
537 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
538 _mesa_get_format_name(mt
->format
));
542 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
543 mt
->array_layout
= GEN6_HIZ_STENCIL
;
546 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
547 * multisampled or have an AUX buffer attached to it.
549 * GEN | MSRT | AUX_CCS_* or AUX_MCS
550 * -------------------------------------------
551 * 9 | HALIGN_16 | HALIGN_16
552 * 8 | HALIGN_ANY | HALIGN_16
556 if (intel_miptree_supports_ccs(brw
, mt
)) {
557 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
558 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
559 } else if (brw
->gen
>= 9 && num_samples
> 1) {
560 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
562 const UNUSED
bool is_lossless_compressed_aux
=
563 brw
->gen
>= 9 && num_samples
== 1 &&
564 mt
->format
== MESA_FORMAT_R_UINT32
;
566 /* For now, nothing else has this requirement */
567 assert(is_lossless_compressed_aux
||
568 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
571 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
572 intel_miptree_release(&mt
);
581 * Choose the aux usage for this miptree. This function must be called fairly
582 * late in the miptree create process after we have a tiling.
585 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
586 struct intel_mipmap_tree
*mt
)
588 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
590 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
591 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
592 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
593 intel_miptree_supports_ccs(brw
, mt
)) {
594 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
595 brw
->gen
>= 9 && !mt
->is_scanout
&&
596 intel_miptree_supports_ccs_e(brw
, mt
)) {
597 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
599 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
601 } else if (intel_miptree_supports_hiz(brw
, mt
)) {
602 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
605 /* We can do fast-clear on all auxiliary surface types that are
606 * allocated through the normal texture creation paths.
608 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
609 mt
->supports_fast_clear
= true;
614 * Choose an appropriate uncompressed format for a requested
615 * compressed format, if unsupported.
618 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
620 /* No need to lower ETC formats on these platforms,
621 * they are supported natively.
623 if (brw
->gen
>= 8 || brw
->is_baytrail
)
627 case MESA_FORMAT_ETC1_RGB8
:
628 return MESA_FORMAT_R8G8B8X8_UNORM
;
629 case MESA_FORMAT_ETC2_RGB8
:
630 return MESA_FORMAT_R8G8B8X8_UNORM
;
631 case MESA_FORMAT_ETC2_SRGB8
:
632 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
633 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
634 return MESA_FORMAT_B8G8R8A8_SRGB
;
635 case MESA_FORMAT_ETC2_RGBA8_EAC
:
636 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
637 return MESA_FORMAT_R8G8B8A8_UNORM
;
638 case MESA_FORMAT_ETC2_R11_EAC
:
639 return MESA_FORMAT_R_UNORM16
;
640 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
641 return MESA_FORMAT_R_SNORM16
;
642 case MESA_FORMAT_ETC2_RG11_EAC
:
643 return MESA_FORMAT_R16G16_UNORM
;
644 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
645 return MESA_FORMAT_R16G16_SNORM
;
647 /* Non ETC1 / ETC2 format */
652 /** \brief Assert that the level and layer are valid for the miptree. */
654 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
662 assert(level
>= mt
->first_level
);
663 assert(level
<= mt
->last_level
);
665 if (mt
->surf
.size
> 0)
666 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
667 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
668 mt
->surf
.phys_level0_sa
.array_len
));
670 assert(layer
< mt
->level
[level
].depth
);
673 static enum isl_aux_state
**
674 create_aux_state_map(struct intel_mipmap_tree
*mt
,
675 enum isl_aux_state initial
)
677 const uint32_t levels
= mt
->last_level
+ 1;
679 uint32_t total_slices
= 0;
680 for (uint32_t level
= 0; level
< levels
; level
++)
681 total_slices
+= mt
->level
[level
].depth
;
683 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
685 /* We're going to allocate a single chunk of data for both the per-level
686 * reference array and the arrays of aux_state. This makes cleanup
687 * significantly easier.
689 const size_t total_size
= per_level_array_size
+
690 total_slices
* sizeof(enum isl_aux_state
);
691 void *data
= malloc(total_size
);
695 enum isl_aux_state
**per_level_arr
= data
;
696 enum isl_aux_state
*s
= data
+ per_level_array_size
;
697 for (uint32_t level
= 0; level
< levels
; level
++) {
698 per_level_arr
[level
] = s
;
699 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
702 assert((void *)s
== data
+ total_size
);
704 return per_level_arr
;
708 free_aux_state_map(enum isl_aux_state
**state
)
713 static struct intel_mipmap_tree
*
714 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
715 unsigned first_level
, unsigned last_level
,
716 unsigned width0
, unsigned height0
, unsigned depth0
,
717 unsigned num_samples
, enum isl_tiling isl_tiling
,
718 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
721 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
725 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
731 if (target
== GL_TEXTURE_CUBE_MAP
||
732 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
733 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
735 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
737 _mesa_enum_to_string(target
),
738 _mesa_get_format_name(format
),
739 num_samples
, width0
, height0
, depth0
,
740 first_level
, last_level
, mt
);
742 struct isl_surf_init_info init_info
= {
743 .dim
= get_isl_surf_dim(target
),
744 .format
= translate_tex_format(brw
, format
, false),
747 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
748 .levels
= last_level
- first_level
+ 1,
749 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
750 .samples
= MAX2(num_samples
, 1),
751 .usage
= isl_usage_flags
,
752 .tiling_flags
= 1u << isl_tiling
755 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
758 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
761 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
763 isl_tiling_to_bufmgr_tiling(isl_tiling
),
764 mt
->surf
.row_pitch
, alloc_flags
);
771 mt
->first_level
= first_level
;
772 mt
->last_level
= last_level
;
776 mt
->aux_state
= NULL
;
781 intel_miptree_release(&mt
);
785 static struct intel_mipmap_tree
*
786 miptree_create(struct brw_context
*brw
,
795 uint32_t layout_flags
)
797 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
798 return make_surface(brw
, target
, format
, first_level
, last_level
,
799 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
800 ISL_SURF_USAGE_STENCIL_BIT
|
801 ISL_SURF_USAGE_TEXTURE_BIT
,
802 BO_ALLOC_FOR_RENDER
, NULL
);
804 struct intel_mipmap_tree
*mt
;
805 mesa_format tex_format
= format
;
806 mesa_format etc_format
= MESA_FORMAT_NONE
;
807 uint32_t alloc_flags
= 0;
809 format
= intel_lower_compressed_format(brw
, format
);
811 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
813 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
814 mt
= intel_miptree_create_layout(brw
, target
, format
,
815 first_level
, last_level
, width0
,
816 height0
, depth0
, num_samples
,
821 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
822 mt
->tiling
= I915_TILING_Y
;
824 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
825 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
827 mt
->etc_format
= etc_format
;
829 if (format
== MESA_FORMAT_S_UINT8
) {
830 /* Align to size of W tile, 64x64. */
831 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
832 ALIGN(mt
->total_width
, 64),
833 ALIGN(mt
->total_height
, 64),
834 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
837 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
838 mt
->total_width
, mt
->total_height
,
839 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
843 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
844 mt
->bo
->cache_coherent
= false;
846 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
847 intel_miptree_choose_aux_usage(brw
, mt
);
852 struct intel_mipmap_tree
*
853 intel_miptree_create(struct brw_context
*brw
,
862 uint32_t layout_flags
)
864 struct intel_mipmap_tree
*mt
= miptree_create(
866 first_level
, last_level
,
867 width0
, height0
, depth0
, num_samples
,
870 /* If the BO is too large to fit in the aperture, we need to use the
871 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
872 * handle Y-tiling, so we need to fall back to X.
874 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
875 mt
->tiling
== I915_TILING_Y
) {
876 const uint32_t alloc_flags
=
877 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
878 BO_ALLOC_FOR_RENDER
: 0;
879 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
880 mt
->total_width
, mt
->total_height
);
882 mt
->tiling
= I915_TILING_X
;
883 brw_bo_unreference(mt
->bo
);
884 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
885 mt
->total_width
, mt
->total_height
, mt
->cpp
,
886 mt
->tiling
, &mt
->pitch
, alloc_flags
);
892 intel_miptree_release(&mt
);
897 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
898 assert(mt
->num_samples
> 1);
899 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
900 intel_miptree_release(&mt
);
905 /* Since CCS_E can compress more than just clear color, we create the CCS
906 * for it up-front. For CCS_D which only compresses clears, we create the
907 * CCS on-demand when a clear occurs that wants one.
909 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
910 if (!intel_miptree_alloc_ccs(brw
, mt
)) {
911 intel_miptree_release(&mt
);
919 struct intel_mipmap_tree
*
920 intel_miptree_create_for_bo(struct brw_context
*brw
,
928 uint32_t layout_flags
)
930 struct intel_mipmap_tree
*mt
;
931 uint32_t tiling
, swizzle
;
932 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
934 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
935 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
936 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
937 ISL_SURF_USAGE_STENCIL_BIT
|
938 ISL_SURF_USAGE_TEXTURE_BIT
,
939 BO_ALLOC_FOR_RENDER
, bo
);
943 assert(bo
->size
>= mt
->surf
.size
);
945 brw_bo_reference(bo
);
949 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
951 /* Nothing will be able to use this miptree with the BO if the offset isn't
954 if (tiling
!= I915_TILING_NONE
)
955 assert(offset
% 4096 == 0);
957 /* miptrees can't handle negative pitch. If you need flipping of images,
958 * that's outside of the scope of the mt.
962 /* The BO already has a tiling format and we shouldn't confuse the lower
963 * layers by making it try to find a tiling format again.
965 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
966 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
968 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
969 mt
= intel_miptree_create_layout(brw
, target
, format
,
971 width
, height
, depth
, 0,
976 brw_bo_reference(bo
);
982 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
)) {
983 intel_miptree_choose_aux_usage(brw
, mt
);
985 /* Since CCS_E can compress more than just clear color, we create the
986 * CCS for it up-front. For CCS_D which only compresses clears, we
987 * create the CCS on-demand when a clear occurs that wants one.
989 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
990 if (!intel_miptree_alloc_ccs(brw
, mt
)) {
991 intel_miptree_release(&mt
);
1000 static struct intel_mipmap_tree
*
1001 miptree_create_for_planar_image(struct brw_context
*brw
,
1002 __DRIimage
*image
, GLenum target
)
1004 struct intel_image_format
*f
= image
->planar_format
;
1005 struct intel_mipmap_tree
*planar_mt
;
1007 for (int i
= 0; i
< f
->nplanes
; i
++) {
1008 const int index
= f
->planes
[i
].buffer_index
;
1009 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1010 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1011 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1012 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1014 /* Disable creation of the texture's aux buffers because the driver
1015 * exposes no EGL API to manage them. That is, there is no API for
1016 * resolving the aux buffer's content to the main buffer nor for
1017 * invalidating the aux buffer's content.
1019 struct intel_mipmap_tree
*mt
=
1020 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1021 image
->offsets
[index
],
1023 image
->strides
[index
],
1024 MIPTREE_LAYOUT_DISABLE_AUX
);
1028 mt
->target
= target
;
1029 mt
->total_width
= width
;
1030 mt
->total_height
= height
;
1035 planar_mt
->plane
[i
- 1] = mt
;
1041 struct intel_mipmap_tree
*
1042 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1043 __DRIimage
*image
, GLenum target
)
1045 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0)
1046 return miptree_create_for_planar_image(brw
, image
, target
);
1048 mesa_format format
= image
->format
;
1050 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1051 /* The texture storage paths in core Mesa detect if the driver does not
1052 * support the user-requested format, and then searches for a
1053 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1054 * do the fallbacks here for important formats.
1056 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1057 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1058 * the Chrome OS compositor consumes as dma_buf EGLImages.
1060 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1063 if (!brw
->ctx
.TextureFormatSupported
[format
])
1066 /* Disable creation of the texture's aux buffers because the driver exposes
1067 * no EGL API to manage them. That is, there is no API for resolving the aux
1068 * buffer's content to the main buffer nor for invalidating the aux buffer's
1071 struct intel_mipmap_tree
*mt
=
1072 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1073 image
->offset
, image
->width
, image
->height
, 1,
1075 MIPTREE_LAYOUT_DISABLE_AUX
);
1079 mt
->target
= target
;
1080 mt
->total_width
= image
->width
;
1081 mt
->total_height
= image
->height
;
1082 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1083 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1085 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1086 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1087 * trouble resolving back to destination image due to alignment issues.
1089 if (!brw
->has_surface_tile_offset
) {
1090 uint32_t draw_x
, draw_y
;
1091 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1093 if (draw_x
!= 0 || draw_y
!= 0) {
1094 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1095 intel_miptree_release(&mt
);
1104 * For a singlesample renderbuffer, this simply wraps the given BO with a
1107 * For a multisample renderbuffer, this wraps the window system's
1108 * (singlesample) BO with a singlesample miptree attached to the
1109 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1110 * that will contain the actual rendering (which is lazily resolved to
1111 * irb->singlesample_mt).
1114 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1115 struct intel_renderbuffer
*irb
,
1117 uint32_t width
, uint32_t height
,
1120 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
1121 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1122 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1123 mesa_format format
= rb
->Format
;
1124 int num_samples
= rb
->NumSamples
;
1126 /* Only the front and back buffers, which are color buffers, are allocated
1127 * through the image loader.
1129 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1130 _mesa_get_format_base_format(format
) == GL_RGBA
);
1132 singlesample_mt
= intel_miptree_create_for_bo(intel
,
1140 MIPTREE_LAYOUT_FOR_SCANOUT
);
1141 if (!singlesample_mt
)
1144 if (num_samples
== 0) {
1145 intel_miptree_release(&irb
->mt
);
1146 irb
->mt
= singlesample_mt
;
1148 assert(!irb
->singlesample_mt
);
1150 intel_miptree_release(&irb
->singlesample_mt
);
1151 irb
->singlesample_mt
= singlesample_mt
;
1154 irb
->mt
->logical_width0
!= width
||
1155 irb
->mt
->logical_height0
!= height
) {
1156 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1161 if (!multisample_mt
)
1164 irb
->need_downsample
= false;
1165 intel_miptree_release(&irb
->mt
);
1166 irb
->mt
= multisample_mt
;
1172 intel_miptree_release(&irb
->singlesample_mt
);
1173 intel_miptree_release(&irb
->mt
);
1177 struct intel_mipmap_tree
*
1178 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1182 uint32_t num_samples
)
1184 struct intel_mipmap_tree
*mt
;
1187 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1188 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1189 MIPTREE_LAYOUT_TILING_ANY
|
1190 MIPTREE_LAYOUT_FOR_SCANOUT
;
1192 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1193 width
, height
, depth
, num_samples
,
1198 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1199 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1207 intel_miptree_release(&mt
);
1212 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1213 struct intel_mipmap_tree
*src
)
1218 intel_miptree_release(dst
);
1222 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1229 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1231 if (aux_buf
== NULL
)
1234 brw_bo_unreference(aux_buf
->bo
);
1240 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1245 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1246 if (--(*mt
)->refcount
<= 0) {
1249 DBG("%s deleting %p\n", __func__
, *mt
);
1251 brw_bo_unreference((*mt
)->bo
);
1252 intel_miptree_release(&(*mt
)->stencil_mt
);
1253 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1254 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1255 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1256 free_aux_state_map((*mt
)->aux_state
);
1258 intel_miptree_release(&(*mt
)->plane
[0]);
1259 intel_miptree_release(&(*mt
)->plane
[1]);
1261 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1262 free((*mt
)->level
[i
].slice
);
1272 intel_get_image_dims(struct gl_texture_image
*image
,
1273 int *width
, int *height
, int *depth
)
1275 switch (image
->TexObject
->Target
) {
1276 case GL_TEXTURE_1D_ARRAY
:
1277 /* For a 1D Array texture the OpenGL API will treat the image height as
1278 * the number of array slices. For Intel hardware, we treat the 1D array
1279 * as a 2D Array with a height of 1. So, here we want to swap image
1282 assert(image
->Depth
== 1);
1283 *width
= image
->Width
;
1285 *depth
= image
->Height
;
1287 case GL_TEXTURE_CUBE_MAP
:
1288 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1289 * though we really have 6 slices.
1291 assert(image
->Depth
== 1);
1292 *width
= image
->Width
;
1293 *height
= image
->Height
;
1297 *width
= image
->Width
;
1298 *height
= image
->Height
;
1299 *depth
= image
->Depth
;
1305 * Can the image be pulled into a unified mipmap tree? This mirrors
1306 * the completeness test in a lot of ways.
1308 * Not sure whether I want to pass gl_texture_image here.
1311 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1312 struct gl_texture_image
*image
)
1314 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1315 GLuint level
= intelImage
->base
.Base
.Level
;
1316 int width
, height
, depth
;
1318 /* glTexImage* choose the texture object based on the target passed in, and
1319 * objects can't change targets over their lifetimes, so this should be
1322 assert(image
->TexObject
->Target
== mt
->target
);
1324 mesa_format mt_format
= mt
->format
;
1325 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1326 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1327 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1328 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1329 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1330 mt_format
= mt
->etc_format
;
1332 if (image
->TexFormat
!= mt_format
)
1335 intel_get_image_dims(image
, &width
, &height
, &depth
);
1337 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1340 if (mt
->surf
.size
> 0) {
1341 if (level
>= mt
->surf
.levels
)
1344 const unsigned level_depth
=
1345 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1346 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1347 mt
->surf
.logical_level0_px
.array_len
;
1349 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1350 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1351 depth
== level_depth
&&
1352 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1355 int level_depth
= mt
->level
[level
].depth
;
1356 if (mt
->num_samples
> 1) {
1357 switch (mt
->msaa_layout
) {
1358 case INTEL_MSAA_LAYOUT_NONE
:
1359 case INTEL_MSAA_LAYOUT_IMS
:
1361 case INTEL_MSAA_LAYOUT_UMS
:
1362 case INTEL_MSAA_LAYOUT_CMS
:
1363 level_depth
/= mt
->num_samples
;
1368 /* Test image dimensions against the base level image adjusted for
1369 * minification. This will also catch images not present in the
1370 * tree, changed targets, etc.
1372 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1373 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1374 depth
!= level_depth
) {
1378 if (image
->NumSamples
!= mt
->num_samples
)
1386 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1388 GLuint x
, GLuint y
, GLuint d
)
1390 mt
->level
[level
].depth
= d
;
1391 mt
->level
[level
].level_x
= x
;
1392 mt
->level
[level
].level_y
= y
;
1394 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1397 assert(mt
->level
[level
].slice
);
1399 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1400 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1405 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1406 GLuint level
, GLuint img
,
1409 if (img
== 0 && level
== 0)
1410 assert(x
== 0 && y
== 0);
1412 assert(img
< mt
->level
[level
].depth
);
1414 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1415 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1417 DBG("%s level %d img %d pos %d,%d\n",
1418 __func__
, level
, img
,
1419 mt
->level
[level
].slice
[img
].x_offset
,
1420 mt
->level
[level
].slice
[img
].y_offset
);
1424 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1425 GLuint level
, GLuint slice
,
1426 GLuint
*x
, GLuint
*y
)
1428 if (mt
->surf
.size
> 0) {
1429 uint32_t x_offset_sa
, y_offset_sa
;
1431 /* Given level is relative to level zero while the miptree may be
1432 * represent just a subset of all levels starting from 'first_level'.
1434 assert(level
>= mt
->first_level
);
1435 level
-= mt
->first_level
;
1437 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1438 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1439 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1440 &x_offset_sa
, &y_offset_sa
);
1447 assert(slice
< mt
->level
[level
].depth
);
1449 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1450 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1455 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1456 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1457 * and tile_h is set to 1.
1460 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1461 uint32_t *tile_w
, uint32_t *tile_h
)
1472 case I915_TILING_NONE
:
1477 unreachable("not reached");
1483 * This function computes masks that may be used to select the bits of the X
1484 * and Y coordinates that indicate the offset within a tile. If the BO is
1485 * untiled, the masks are set to 0.
1488 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1489 uint32_t *mask_x
, uint32_t *mask_y
)
1491 uint32_t tile_w_bytes
, tile_h
;
1493 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1495 *mask_x
= tile_w_bytes
/ cpp
- 1;
1496 *mask_y
= tile_h
- 1;
1500 * Compute the offset (in bytes) from the start of the BO to the given x
1501 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1502 * multiples of the tile size.
1505 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1506 uint32_t x
, uint32_t y
)
1509 uint32_t pitch
= mt
->pitch
;
1510 uint32_t tiling
= mt
->tiling
;
1514 unreachable("not reached");
1515 case I915_TILING_NONE
:
1516 return y
* pitch
+ x
* cpp
;
1518 assert((x
% (512 / cpp
)) == 0);
1519 assert((y
% 8) == 0);
1520 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1522 assert((x
% (128 / cpp
)) == 0);
1523 assert((y
% 32) == 0);
1524 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1529 * Rendering with tiled buffers requires that the base address of the buffer
1530 * be aligned to a page boundary. For renderbuffers, and sometimes with
1531 * textures, we may want the surface to point at a texture image level that
1532 * isn't at a page boundary.
1534 * This function returns an appropriately-aligned base offset
1535 * according to the tiling restrictions, plus any required x/y offset
1539 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1540 GLuint level
, GLuint slice
,
1545 uint32_t mask_x
, mask_y
;
1547 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1548 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1550 *tile_x
= x
& mask_x
;
1551 *tile_y
= y
& mask_y
;
1553 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1557 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1558 struct intel_mipmap_tree
*src_mt
,
1559 unsigned src_level
, unsigned src_layer
,
1560 struct intel_mipmap_tree
*dst_mt
,
1561 unsigned dst_level
, unsigned dst_layer
,
1562 unsigned width
, unsigned height
)
1565 ptrdiff_t src_stride
, dst_stride
;
1566 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1567 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1569 intel_miptree_map(brw
, src_mt
,
1570 src_level
, src_layer
,
1573 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1576 intel_miptree_map(brw
, dst_mt
,
1577 dst_level
, dst_layer
,
1580 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1584 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1585 _mesa_get_format_name(src_mt
->format
),
1586 src_mt
, src
, src_stride
,
1587 _mesa_get_format_name(dst_mt
->format
),
1588 dst_mt
, dst
, dst_stride
,
1591 int row_size
= cpp
* width
;
1592 if (src_stride
== row_size
&&
1593 dst_stride
== row_size
) {
1594 memcpy(dst
, src
, row_size
* height
);
1596 for (int i
= 0; i
< height
; i
++) {
1597 memcpy(dst
, src
, row_size
);
1603 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1604 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1606 /* Don't forget to copy the stencil data over, too. We could have skipped
1607 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1608 * shuffling the two data sources in/out of temporary storage instead of
1609 * the direct mapping we get this way.
1611 if (dst_mt
->stencil_mt
) {
1612 assert(src_mt
->stencil_mt
);
1613 intel_miptree_copy_slice_sw(brw
,
1614 src_mt
->stencil_mt
, src_level
, src_layer
,
1615 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1621 intel_miptree_copy_slice(struct brw_context
*brw
,
1622 struct intel_mipmap_tree
*src_mt
,
1623 unsigned src_level
, unsigned src_layer
,
1624 struct intel_mipmap_tree
*dst_mt
,
1625 unsigned dst_level
, unsigned dst_layer
)
1628 mesa_format format
= src_mt
->format
;
1629 uint32_t width
, height
;
1631 if (src_mt
->surf
.size
> 0) {
1632 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1633 src_level
- src_mt
->first_level
);
1634 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1635 src_level
- src_mt
->first_level
);
1637 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1638 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1639 src_level
- src_mt
->first_level
));
1641 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1643 width
= minify(src_mt
->physical_width0
,
1644 src_level
- src_mt
->first_level
);
1645 height
= minify(src_mt
->physical_height0
,
1646 src_level
- src_mt
->first_level
);
1647 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1650 assert(src_mt
->format
== dst_mt
->format
);
1652 if (dst_mt
->compressed
) {
1654 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1655 height
= ALIGN_NPOT(height
, j
) / j
;
1656 width
= ALIGN_NPOT(width
, i
) / i
;
1659 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1660 * below won't apply since we can't do the depth's Y tiling or the
1661 * stencil's W tiling in the blitter.
1663 if (src_mt
->stencil_mt
) {
1664 intel_miptree_copy_slice_sw(brw
,
1665 src_mt
, src_level
, src_layer
,
1666 dst_mt
, dst_level
, dst_layer
,
1671 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1672 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1674 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1677 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1678 _mesa_get_format_name(src_mt
->format
),
1679 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1680 _mesa_get_format_name(dst_mt
->format
),
1681 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1684 if (!intel_miptree_blit(brw
,
1685 src_mt
, src_level
, src_layer
, 0, 0, false,
1686 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1687 width
, height
, GL_COPY
)) {
1688 perf_debug("miptree validate blit for %s failed\n",
1689 _mesa_get_format_name(format
));
1691 intel_miptree_copy_slice_sw(brw
,
1692 src_mt
, src_level
, src_layer
,
1693 dst_mt
, dst_level
, dst_layer
,
1699 * Copies the image's current data to the given miptree, and associates that
1700 * miptree with the image.
1702 * If \c invalidate is true, then the actual image data does not need to be
1703 * copied, but the image still needs to be associated to the new miptree (this
1704 * is set to true if we're about to clear the image).
1707 intel_miptree_copy_teximage(struct brw_context
*brw
,
1708 struct intel_texture_image
*intelImage
,
1709 struct intel_mipmap_tree
*dst_mt
,
1712 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1713 struct intel_texture_object
*intel_obj
=
1714 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1715 int level
= intelImage
->base
.Base
.Level
;
1716 const unsigned face
= intelImage
->base
.Base
.Face
;
1717 unsigned start_layer
, end_layer
;
1719 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1721 assert(intelImage
->base
.Base
.Height
);
1723 end_layer
= intelImage
->base
.Base
.Height
- 1;
1724 } else if (face
> 0) {
1728 assert(intelImage
->base
.Base
.Depth
);
1730 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1734 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1735 intel_miptree_copy_slice(brw
,
1741 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1742 intel_obj
->needs_validate
= true;
1746 intel_miptree_init_mcs(struct brw_context
*brw
,
1747 struct intel_mipmap_tree
*mt
,
1750 assert(mt
->mcs_buf
!= NULL
);
1752 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1754 * When MCS buffer is enabled and bound to MSRT, it is required that it
1755 * is cleared prior to any rendering.
1757 * Since we don't use the MCS buffer for any purpose other than rendering,
1758 * it makes sense to just clear it immediately upon allocation.
1760 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1762 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1763 if (unlikely(map
== NULL
)) {
1764 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1765 brw_bo_unreference(mt
->mcs_buf
->bo
);
1770 memset(data
, init_value
, mt
->mcs_buf
->size
);
1771 brw_bo_unmap(mt
->mcs_buf
->bo
);
1774 static struct intel_miptree_aux_buffer
*
1775 intel_alloc_aux_buffer(struct brw_context
*brw
,
1777 const struct isl_surf
*aux_surf
,
1778 uint32_t alloc_flags
,
1779 struct intel_mipmap_tree
*mt
)
1781 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1785 buf
->size
= aux_surf
->size
;
1786 buf
->pitch
= aux_surf
->row_pitch
;
1787 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1789 /* ISL has stricter set of alignment rules then the drm allocator.
1790 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1791 * trying to recalculate based on different format block sizes.
1793 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1794 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1800 buf
->surf
= *aux_surf
;
1806 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1807 struct intel_mipmap_tree
*mt
,
1810 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1811 assert(mt
->mcs_buf
== NULL
);
1812 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1814 /* Multisampled miptrees are only supported for single level. */
1815 assert(mt
->first_level
== 0);
1816 enum isl_aux_state
**aux_state
=
1817 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1821 struct isl_surf temp_main_surf
;
1822 struct isl_surf temp_mcs_surf
;
1824 /* Create first an ISL presentation for the main color surface and let ISL
1825 * calculate equivalent MCS surface against it.
1827 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1828 MAYBE_UNUSED
bool ok
=
1829 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1832 /* Buffer needs to be initialised requiring the buffer to be immediately
1833 * mapped to cpu space for writing. Therefore do not use the gpu access
1834 * flag which can cause an unnecessary delay if the backing pages happened
1835 * to be just used by the GPU.
1837 const uint32_t alloc_flags
= 0;
1838 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1839 &temp_mcs_surf
, alloc_flags
, mt
);
1845 mt
->aux_state
= aux_state
;
1847 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1853 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1854 struct intel_mipmap_tree
*mt
)
1856 assert(mt
->mcs_buf
== NULL
);
1857 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1858 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1860 struct isl_surf temp_main_surf
;
1861 struct isl_surf temp_ccs_surf
;
1863 /* Create first an ISL presentation for the main color surface and let ISL
1864 * calculate equivalent CCS surface against it.
1866 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1867 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1870 assert(temp_ccs_surf
.size
&&
1871 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1873 enum isl_aux_state
**aux_state
=
1874 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1878 /* In case of compression mcs buffer needs to be initialised requiring the
1879 * buffer to be immediately mapped to cpu space for writing. Therefore do
1880 * not use the gpu access flag which can cause an unnecessary delay if the
1881 * backing pages happened to be just used by the GPU.
1883 const uint32_t alloc_flags
=
1884 mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
? 0 : BO_ALLOC_FOR_RENDER
;
1885 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1886 &temp_ccs_surf
, alloc_flags
, mt
);
1892 mt
->aux_state
= aux_state
;
1894 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1895 * used for lossless compression which requires similar initialisation
1896 * as multi-sample compression.
1898 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1899 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1900 * resolve. Initialize it accordingly in case the first renderer is
1901 * cpu (or other none compression aware party).
1903 * This is also explicitly stated in the spec (MCS Buffer for Render
1905 * "If Software wants to enable Color Compression without Fast clear,
1906 * Software needs to initialize MCS with zeros."
1908 intel_miptree_init_mcs(brw
, mt
, 0);
1909 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1916 * Helper for intel_miptree_alloc_hiz() that sets
1917 * \c mt->level[level].has_hiz. Return true if and only if
1918 * \c has_hiz was set.
1921 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1922 struct intel_mipmap_tree
*mt
,
1925 assert(mt
->hiz_buf
);
1927 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1928 uint32_t width
= minify(mt
->physical_width0
, level
);
1929 uint32_t height
= minify(mt
->physical_height0
, level
);
1931 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1932 * and the height is 4 aligned. This allows our HiZ support
1933 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1934 * we can grow the width & height to allow the HiZ op to
1935 * force the proper size alignments.
1937 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1938 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1943 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1944 mt
->level
[level
].has_hiz
= true;
1949 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1950 struct intel_mipmap_tree
*mt
)
1952 assert(mt
->hiz_buf
== NULL
);
1953 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1955 enum isl_aux_state
**aux_state
=
1956 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1960 struct isl_surf temp_main_surf
;
1961 struct isl_surf temp_hiz_surf
;
1963 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1964 MAYBE_UNUSED
bool ok
=
1965 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1968 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1969 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1970 &temp_hiz_surf
, alloc_flags
, mt
);
1977 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1978 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1980 mt
->aux_state
= aux_state
;
1986 * Can the miptree sample using the hiz buffer?
1989 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1990 struct intel_mipmap_tree
*mt
)
1992 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1993 * so keep things conservative for now and never enable it unless we're SKL+.
2003 /* It seems the hardware won't fallback to the depth buffer if some of the
2004 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2005 * of the texture to be HiZ enabled.
2007 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2008 if (!intel_miptree_level_has_hiz(mt
, level
))
2012 /* If compressed multisampling is enabled, then we use it for the auxiliary
2015 * From the BDW PRM (Volume 2d: Command Reference: Structures
2016 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2018 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2019 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2021 * There is no such blurb for 1D textures, but there is sufficient evidence
2022 * that this is broken on SKL+.
2024 return (mt
->num_samples
<= 1 &&
2025 mt
->target
!= GL_TEXTURE_3D
&&
2026 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2030 * Does the miptree slice have hiz enabled?
2033 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2035 intel_miptree_check_level_layer(mt
, level
, 0);
2036 return mt
->level
[level
].has_hiz
;
2040 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2041 unsigned start_level
, unsigned num_levels
,
2042 unsigned start_layer
, unsigned num_layers
)
2044 assert(_mesa_is_format_color_format(mt
->format
));
2049 /* Clamp the level range to fit the miptree */
2050 assert(start_level
+ num_levels
>= start_level
);
2051 const uint32_t last_level
=
2052 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2053 start_level
= MAX2(mt
->first_level
, start_level
);
2054 num_levels
= last_level
- start_level
+ 1;
2056 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2057 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2058 for (unsigned a
= 0; a
< level_layers
; a
++) {
2059 enum isl_aux_state aux_state
=
2060 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2061 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2062 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2071 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2072 const struct intel_mipmap_tree
*mt
,
2073 unsigned level
, unsigned layer
)
2079 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2080 assert(brw
->gen
>= 8 ||
2081 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2083 /* Compression of arrayed msaa surfaces is supported. */
2084 if (mt
->num_samples
> 1)
2087 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2088 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2094 static enum blorp_fast_clear_op
2095 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2096 bool ccs_supported
, bool fast_clear_supported
)
2098 assert(ccs_supported
== fast_clear_supported
);
2100 switch (aux_state
) {
2101 case ISL_AUX_STATE_CLEAR
:
2102 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2104 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2106 return BLORP_FAST_CLEAR_OP_NONE
;
2108 case ISL_AUX_STATE_PASS_THROUGH
:
2109 return BLORP_FAST_CLEAR_OP_NONE
;
2111 case ISL_AUX_STATE_RESOLVED
:
2112 case ISL_AUX_STATE_AUX_INVALID
:
2113 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2117 unreachable("Invalid aux state for CCS_D");
2120 static enum blorp_fast_clear_op
2121 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2122 bool ccs_supported
, bool fast_clear_supported
)
2124 switch (aux_state
) {
2125 case ISL_AUX_STATE_CLEAR
:
2126 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2128 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2129 else if (!fast_clear_supported
)
2130 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2132 return BLORP_FAST_CLEAR_OP_NONE
;
2134 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2136 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2138 return BLORP_FAST_CLEAR_OP_NONE
;
2140 case ISL_AUX_STATE_PASS_THROUGH
:
2141 return BLORP_FAST_CLEAR_OP_NONE
;
2143 case ISL_AUX_STATE_RESOLVED
:
2144 case ISL_AUX_STATE_AUX_INVALID
:
2148 unreachable("Invalid aux state for CCS_E");
2152 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2153 struct intel_mipmap_tree
*mt
,
2154 uint32_t level
, uint32_t layer
,
2156 bool fast_clear_supported
)
2158 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2160 enum blorp_fast_clear_op resolve_op
;
2161 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2162 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2163 fast_clear_supported
);
2165 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2166 fast_clear_supported
);
2169 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2170 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2171 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2173 switch (resolve_op
) {
2174 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2175 /* The CCS full resolve operation destroys the CCS and sets it to the
2176 * pass-through state. (You can also think of this as being both a
2177 * resolve and an ambiguate in one operation.)
2179 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2180 ISL_AUX_STATE_PASS_THROUGH
);
2183 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2184 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2185 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2189 unreachable("Invalid resolve op");
2195 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2196 struct intel_mipmap_tree
*mt
,
2197 uint32_t level
, uint32_t layer
,
2198 bool written_with_ccs
)
2200 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2202 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2203 switch (aux_state
) {
2204 case ISL_AUX_STATE_CLEAR
:
2205 assert(written_with_ccs
);
2206 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2207 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2210 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2211 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2212 assert(written_with_ccs
);
2213 break; /* Nothing to do */
2215 case ISL_AUX_STATE_PASS_THROUGH
:
2216 if (written_with_ccs
) {
2217 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2218 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2224 case ISL_AUX_STATE_RESOLVED
:
2225 case ISL_AUX_STATE_AUX_INVALID
:
2226 unreachable("Invalid aux state for CCS_E");
2229 /* CCS_D is a bit simpler */
2230 switch (aux_state
) {
2231 case ISL_AUX_STATE_CLEAR
:
2232 assert(written_with_ccs
);
2233 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2234 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2237 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2238 assert(written_with_ccs
);
2239 break; /* Nothing to do */
2241 case ISL_AUX_STATE_PASS_THROUGH
:
2245 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2246 case ISL_AUX_STATE_RESOLVED
:
2247 case ISL_AUX_STATE_AUX_INVALID
:
2248 unreachable("Invalid aux state for CCS_D");
2254 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2255 struct intel_mipmap_tree
*mt
,
2256 uint32_t level
, uint32_t layer
,
2257 bool written_with_aux
)
2259 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2260 case ISL_AUX_STATE_CLEAR
:
2261 assert(written_with_aux
);
2262 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2263 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2266 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2267 assert(written_with_aux
);
2268 break; /* Nothing to do */
2270 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2271 case ISL_AUX_STATE_RESOLVED
:
2272 case ISL_AUX_STATE_PASS_THROUGH
:
2273 case ISL_AUX_STATE_AUX_INVALID
:
2274 unreachable("Invalid aux state for MCS");
2279 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2280 struct intel_mipmap_tree
*mt
,
2281 uint32_t level
, uint32_t layer
,
2282 bool hiz_supported
, bool fast_clear_supported
)
2284 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2285 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2286 case ISL_AUX_STATE_CLEAR
:
2287 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2288 if (!hiz_supported
|| !fast_clear_supported
)
2289 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2292 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2294 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2297 case ISL_AUX_STATE_PASS_THROUGH
:
2298 case ISL_AUX_STATE_RESOLVED
:
2301 case ISL_AUX_STATE_AUX_INVALID
:
2303 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2307 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2308 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2311 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2312 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2313 ISL_AUX_STATE_RESOLVED
);
2316 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2317 /* The HiZ resolve operation is actually an ambiguate */
2318 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2319 ISL_AUX_STATE_PASS_THROUGH
);
2323 unreachable("Invalid HiZ op");
2329 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2330 struct intel_mipmap_tree
*mt
,
2331 uint32_t level
, uint32_t layer
,
2332 bool written_with_hiz
)
2334 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2335 case ISL_AUX_STATE_CLEAR
:
2336 assert(written_with_hiz
);
2337 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2338 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2341 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2342 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2343 assert(written_with_hiz
);
2344 break; /* Nothing to do */
2346 case ISL_AUX_STATE_RESOLVED
:
2347 if (written_with_hiz
) {
2348 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2349 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2351 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2352 ISL_AUX_STATE_AUX_INVALID
);
2356 case ISL_AUX_STATE_PASS_THROUGH
:
2357 if (written_with_hiz
) {
2358 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2359 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2363 case ISL_AUX_STATE_AUX_INVALID
:
2364 assert(!written_with_hiz
);
2369 static inline uint32_t
2370 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2371 uint32_t start_level
, uint32_t num_levels
)
2373 assert(start_level
>= mt
->first_level
);
2374 assert(start_level
<= mt
->last_level
);
2376 if (num_levels
== INTEL_REMAINING_LAYERS
)
2377 num_levels
= mt
->last_level
- start_level
+ 1;
2378 /* Check for overflow */
2379 assert(start_level
+ num_levels
>= start_level
);
2380 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2385 static inline uint32_t
2386 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2387 uint32_t start_layer
, uint32_t num_layers
)
2389 assert(level
<= mt
->last_level
);
2390 uint32_t total_num_layers
;
2392 if (mt
->surf
.size
> 0)
2393 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2394 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2395 mt
->surf
.phys_level0_sa
.array_len
;
2397 total_num_layers
= mt
->level
[level
].depth
;
2399 assert(start_layer
< total_num_layers
);
2400 if (num_layers
== INTEL_REMAINING_LAYERS
)
2401 num_layers
= total_num_layers
- start_layer
;
2402 /* Check for overflow */
2403 assert(start_layer
+ num_layers
>= start_layer
);
2404 assert(start_layer
+ num_layers
<= total_num_layers
);
2410 intel_miptree_prepare_access(struct brw_context
*brw
,
2411 struct intel_mipmap_tree
*mt
,
2412 uint32_t start_level
, uint32_t num_levels
,
2413 uint32_t start_layer
, uint32_t num_layers
,
2414 bool aux_supported
, bool fast_clear_supported
)
2416 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2418 if (_mesa_is_format_color_format(mt
->format
)) {
2422 if (mt
->num_samples
> 1) {
2423 /* Nothing to do for MSAA */
2424 assert(aux_supported
&& fast_clear_supported
);
2426 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2427 const uint32_t level
= start_level
+ l
;
2428 const uint32_t level_layers
=
2429 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2430 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2431 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2432 start_layer
+ a
, aux_supported
,
2433 fast_clear_supported
);
2437 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2438 /* Nothing to do for stencil */
2443 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2444 const uint32_t level
= start_level
+ l
;
2445 if (!intel_miptree_level_has_hiz(mt
, level
))
2448 const uint32_t level_layers
=
2449 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2450 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2451 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2453 fast_clear_supported
);
2460 intel_miptree_finish_write(struct brw_context
*brw
,
2461 struct intel_mipmap_tree
*mt
, uint32_t level
,
2462 uint32_t start_layer
, uint32_t num_layers
,
2463 bool written_with_aux
)
2465 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2467 if (_mesa_is_format_color_format(mt
->format
)) {
2471 if (mt
->num_samples
> 1) {
2472 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2473 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2477 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2478 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2482 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2483 /* Nothing to do for stencil */
2485 if (!intel_miptree_level_has_hiz(mt
, level
))
2488 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2489 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2496 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2497 uint32_t level
, uint32_t layer
)
2499 intel_miptree_check_level_layer(mt
, level
, layer
);
2501 if (_mesa_is_format_color_format(mt
->format
)) {
2502 assert(mt
->mcs_buf
!= NULL
);
2503 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2504 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2505 unreachable("Cannot get aux state for stencil");
2507 assert(intel_miptree_level_has_hiz(mt
, level
));
2510 return mt
->aux_state
[level
][layer
];
2514 intel_miptree_set_aux_state(struct brw_context
*brw
,
2515 struct intel_mipmap_tree
*mt
, uint32_t level
,
2516 uint32_t start_layer
, uint32_t num_layers
,
2517 enum isl_aux_state aux_state
)
2519 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2521 if (_mesa_is_format_color_format(mt
->format
)) {
2522 assert(mt
->mcs_buf
!= NULL
);
2523 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2524 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2525 unreachable("Cannot get aux state for stencil");
2527 assert(intel_miptree_level_has_hiz(mt
, level
));
2530 for (unsigned a
= 0; a
< num_layers
; a
++)
2531 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2534 /* On Gen9 color buffers may be compressed by the hardware (lossless
2535 * compression). There are, however, format restrictions and care needs to be
2536 * taken that the sampler engine is capable for re-interpreting a buffer with
2537 * format different the buffer was originally written with.
2539 * For example, SRGB formats are not compressible and the sampler engine isn't
2540 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2541 * color buffer needs to be resolved so that the sampling surface can be
2542 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2546 can_texture_with_ccs(struct brw_context
*brw
,
2547 struct intel_mipmap_tree
*mt
,
2548 mesa_format view_format
)
2550 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2553 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2554 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2556 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2557 isl_mt_format
, isl_view_format
)) {
2558 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2559 _mesa_get_format_name(view_format
),
2560 _mesa_get_format_name(mt
->format
));
2568 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2569 struct intel_mipmap_tree
*mt
,
2570 mesa_format view_format
,
2571 uint32_t start_level
, uint32_t num_levels
,
2572 uint32_t start_layer
, uint32_t num_layers
,
2573 bool *aux_supported_out
)
2575 bool aux_supported
, clear_supported
;
2576 if (_mesa_is_format_color_format(mt
->format
)) {
2577 if (mt
->num_samples
> 1) {
2578 aux_supported
= clear_supported
= true;
2580 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2582 /* Clear color is specified as ints or floats and the conversion is
2583 * done by the sampler. If we have a texture view, we would have to
2584 * perform the clear color conversion manually. Just disable clear
2587 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2589 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2590 aux_supported
= clear_supported
= false;
2592 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2595 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2596 start_layer
, num_layers
,
2597 aux_supported
, clear_supported
);
2598 if (aux_supported_out
)
2599 *aux_supported_out
= aux_supported
;
2603 intel_miptree_prepare_texture(struct brw_context
*brw
,
2604 struct intel_mipmap_tree
*mt
,
2605 mesa_format view_format
,
2606 bool *aux_supported_out
)
2608 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2609 0, INTEL_REMAINING_LEVELS
,
2610 0, INTEL_REMAINING_LAYERS
,
2615 intel_miptree_prepare_image(struct brw_context
*brw
,
2616 struct intel_mipmap_tree
*mt
)
2618 /* The data port doesn't understand any compression */
2619 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2620 0, INTEL_REMAINING_LAYERS
, false, false);
2624 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2625 struct intel_mipmap_tree
*mt
, uint32_t level
,
2626 uint32_t start_layer
, uint32_t num_layers
)
2628 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2629 start_layer
, num_layers
, NULL
);
2633 intel_miptree_prepare_render(struct brw_context
*brw
,
2634 struct intel_mipmap_tree
*mt
, uint32_t level
,
2635 uint32_t start_layer
, uint32_t layer_count
,
2638 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2639 * the single-sampled color renderbuffers because the CCS buffer isn't
2640 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2641 * enabled because otherwise the surface state will be programmed with
2642 * the linear equivalent format anyway.
2644 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2645 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2647 /* Lossless compression is not supported for SRGB formats, it
2648 * should be impossible to get here with such surfaces.
2650 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2651 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2657 intel_miptree_finish_render(struct brw_context
*brw
,
2658 struct intel_mipmap_tree
*mt
, uint32_t level
,
2659 uint32_t start_layer
, uint32_t layer_count
)
2661 assert(_mesa_is_format_color_format(mt
->format
));
2662 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2663 mt
->mcs_buf
!= NULL
);
2667 intel_miptree_prepare_depth(struct brw_context
*brw
,
2668 struct intel_mipmap_tree
*mt
, uint32_t level
,
2669 uint32_t start_layer
, uint32_t layer_count
)
2671 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2672 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2676 intel_miptree_finish_depth(struct brw_context
*brw
,
2677 struct intel_mipmap_tree
*mt
, uint32_t level
,
2678 uint32_t start_layer
, uint32_t layer_count
,
2681 if (depth_written
) {
2682 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2683 mt
->hiz_buf
!= NULL
);
2688 * Make it possible to share the BO backing the given miptree with another
2689 * process or another miptree.
2691 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2692 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2693 * ensure that no MCS buffer gets allocated in the future.
2695 * HiZ is similarly unsafe with shared buffers.
2698 intel_miptree_make_shareable(struct brw_context
*brw
,
2699 struct intel_mipmap_tree
*mt
)
2701 /* MCS buffers are also used for multisample buffers, but we can't resolve
2702 * away a multisample MCS buffer because it's an integral part of how the
2703 * pixel data is stored. Fortunately this code path should never be
2704 * reached for multisample buffers.
2706 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2708 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2709 0, INTEL_REMAINING_LAYERS
, false, false);
2712 brw_bo_unreference(mt
->mcs_buf
->bo
);
2716 /* Any pending MCS/CCS operations are no longer needed. Trying to
2717 * execute any will likely crash due to the missing aux buffer. So let's
2718 * delete all pending ops.
2720 free(mt
->aux_state
);
2721 mt
->aux_state
= NULL
;
2725 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2728 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2729 mt
->level
[l
].has_hiz
= false;
2732 /* Any pending HiZ operations are no longer needed. Trying to execute
2733 * any will likely crash due to the missing aux buffer. So let's delete
2736 free(mt
->aux_state
);
2737 mt
->aux_state
= NULL
;
2740 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2745 * \brief Get pointer offset into stencil buffer.
2747 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2748 * must decode the tile's layout in software.
2751 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2753 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2755 * Even though the returned offset is always positive, the return type is
2757 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2758 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2761 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2763 uint32_t tile_size
= 4096;
2764 uint32_t tile_width
= 64;
2765 uint32_t tile_height
= 64;
2766 uint32_t row_size
= 64 * stride
;
2768 uint32_t tile_x
= x
/ tile_width
;
2769 uint32_t tile_y
= y
/ tile_height
;
2771 /* The byte's address relative to the tile's base addres. */
2772 uint32_t byte_x
= x
% tile_width
;
2773 uint32_t byte_y
= y
% tile_height
;
2775 uintptr_t u
= tile_y
* row_size
2776 + tile_x
* tile_size
2777 + 512 * (byte_x
/ 8)
2779 + 32 * ((byte_y
/ 4) % 2)
2780 + 16 * ((byte_x
/ 4) % 2)
2781 + 8 * ((byte_y
/ 2) % 2)
2782 + 4 * ((byte_x
/ 2) % 2)
2787 /* adjust for bit6 swizzling */
2788 if (((byte_x
/ 8) % 2) == 1) {
2789 if (((byte_y
/ 8) % 2) == 0) {
2801 intel_miptree_updownsample(struct brw_context
*brw
,
2802 struct intel_mipmap_tree
*src
,
2803 struct intel_mipmap_tree
*dst
)
2805 unsigned src_w
, src_h
, dst_w
, dst_h
;
2807 if (src
->surf
.size
> 0) {
2808 src_w
= src
->surf
.logical_level0_px
.width
;
2809 src_h
= src
->surf
.logical_level0_px
.height
;
2811 src_w
= src
->logical_width0
;
2812 src_h
= src
->logical_height0
;
2815 if (dst
->surf
.size
> 0) {
2816 dst_w
= dst
->surf
.logical_level0_px
.width
;
2817 dst_h
= dst
->surf
.logical_level0_px
.height
;
2819 dst_w
= dst
->logical_width0
;
2820 dst_h
= dst
->logical_height0
;
2823 brw_blorp_blit_miptrees(brw
,
2824 src
, 0 /* level */, 0 /* layer */,
2825 src
->format
, SWIZZLE_XYZW
,
2826 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2829 GL_NEAREST
, false, false /*mirror x, y*/,
2832 if (src
->stencil_mt
) {
2833 if (src
->stencil_mt
->surf
.size
> 0) {
2834 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2835 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2837 src_w
= src
->stencil_mt
->logical_width0
;
2838 src_h
= src
->stencil_mt
->logical_height0
;
2841 if (dst
->stencil_mt
->surf
.size
> 0) {
2842 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2843 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2845 dst_w
= dst
->stencil_mt
->logical_width0
;
2846 dst_h
= dst
->stencil_mt
->logical_height0
;
2849 brw_blorp_blit_miptrees(brw
,
2850 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2851 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2852 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2853 dst
->stencil_mt
->format
,
2856 GL_NEAREST
, false, false /*mirror x, y*/,
2857 false, false /* decode/encode srgb */);
2862 intel_update_r8stencil(struct brw_context
*brw
,
2863 struct intel_mipmap_tree
*mt
)
2865 assert(brw
->gen
>= 7);
2866 struct intel_mipmap_tree
*src
=
2867 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2868 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2871 if (!mt
->r8stencil_mt
) {
2872 const uint32_t r8stencil_flags
=
2873 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2874 MIPTREE_LAYOUT_DISABLE_AUX
;
2875 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2876 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2878 MESA_FORMAT_R_UINT8
,
2881 src
->logical_width0
,
2882 src
->logical_height0
,
2883 src
->logical_depth0
,
2886 assert(mt
->r8stencil_mt
);
2889 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2891 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2892 const unsigned depth
= src
->level
[level
].depth
;
2894 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2895 brw_blorp_copy_miptrees(brw
,
2899 minify(src
->logical_width0
, level
),
2900 minify(src
->logical_height0
, level
));
2904 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2905 src
->r8stencil_needs_update
= false;
2909 intel_miptree_map_raw(struct brw_context
*brw
,
2910 struct intel_mipmap_tree
*mt
,
2913 struct brw_bo
*bo
= mt
->bo
;
2915 if (brw_batch_references(&brw
->batch
, bo
))
2916 intel_batchbuffer_flush(brw
);
2918 return brw_bo_map(brw
, bo
, mode
);
2922 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2924 brw_bo_unmap(mt
->bo
);
2928 intel_miptree_map_gtt(struct brw_context
*brw
,
2929 struct intel_mipmap_tree
*mt
,
2930 struct intel_miptree_map
*map
,
2931 unsigned int level
, unsigned int slice
)
2933 unsigned int bw
, bh
;
2935 unsigned int image_x
, image_y
;
2936 intptr_t x
= map
->x
;
2937 intptr_t y
= map
->y
;
2939 /* For compressed formats, the stride is the number of bytes per
2940 * row of blocks. intel_miptree_get_image_offset() already does
2943 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2944 assert(y
% bh
== 0);
2945 assert(x
% bw
== 0);
2949 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2954 /* Note that in the case of cube maps, the caller must have passed the
2955 * slice number referencing the face.
2957 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2961 map
->stride
= mt
->pitch
;
2962 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2965 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2966 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2967 map
->x
, map
->y
, map
->w
, map
->h
,
2968 mt
, _mesa_get_format_name(mt
->format
),
2969 x
, y
, map
->ptr
, map
->stride
);
2973 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2975 intel_miptree_unmap_raw(mt
);
2979 intel_miptree_map_blit(struct brw_context
*brw
,
2980 struct intel_mipmap_tree
*mt
,
2981 struct intel_miptree_map
*map
,
2982 unsigned int level
, unsigned int slice
)
2984 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2985 /* first_level */ 0,
2989 MIPTREE_LAYOUT_TILING_NONE
);
2991 if (!map
->linear_mt
) {
2992 fprintf(stderr
, "Failed to allocate blit temporary\n");
2995 map
->stride
= map
->linear_mt
->pitch
;
2997 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2998 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2999 * invalidate is set, since we'll be writing the whole rectangle from our
3000 * temporary buffer back out.
3002 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3003 if (!intel_miptree_copy(brw
,
3004 mt
, level
, slice
, map
->x
, map
->y
,
3005 map
->linear_mt
, 0, 0, 0, 0,
3007 fprintf(stderr
, "Failed to blit\n");
3012 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3014 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3015 map
->x
, map
->y
, map
->w
, map
->h
,
3016 mt
, _mesa_get_format_name(mt
->format
),
3017 level
, slice
, map
->ptr
, map
->stride
);
3022 intel_miptree_release(&map
->linear_mt
);
3028 intel_miptree_unmap_blit(struct brw_context
*brw
,
3029 struct intel_mipmap_tree
*mt
,
3030 struct intel_miptree_map
*map
,
3034 struct gl_context
*ctx
= &brw
->ctx
;
3036 intel_miptree_unmap_raw(map
->linear_mt
);
3038 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3039 bool ok
= intel_miptree_copy(brw
,
3040 map
->linear_mt
, 0, 0, 0, 0,
3041 mt
, level
, slice
, map
->x
, map
->y
,
3043 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3046 intel_miptree_release(&map
->linear_mt
);
3050 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3052 #if defined(USE_SSE41)
3054 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3055 struct intel_mipmap_tree
*mt
,
3056 struct intel_miptree_map
*map
,
3057 unsigned int level
, unsigned int slice
)
3059 assert(map
->mode
& GL_MAP_READ_BIT
);
3060 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3062 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3063 map
->x
, map
->y
, map
->w
, map
->h
,
3064 mt
, _mesa_get_format_name(mt
->format
),
3065 level
, slice
, map
->ptr
, map
->stride
);
3067 /* Map the original image */
3070 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3074 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3080 src
+= image_y
* mt
->pitch
;
3081 src
+= image_x
* mt
->cpp
;
3083 /* Due to the pixel offsets for the particular image being mapped, our
3084 * src pointer may not be 16-byte aligned. However, if the pitch is
3085 * divisible by 16, then the amount by which it's misaligned will remain
3086 * consistent from row to row.
3088 assert((mt
->pitch
% 16) == 0);
3089 const int misalignment
= ((uintptr_t) src
) & 15;
3091 /* Create an untiled temporary buffer for the mapping. */
3092 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3094 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3096 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3097 /* Offset the destination so it has the same misalignment as src. */
3098 map
->ptr
= map
->buffer
+ misalignment
;
3100 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3102 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3103 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3104 void *src_ptr
= src
+ y
* mt
->pitch
;
3106 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3109 intel_miptree_unmap_raw(mt
);
3113 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3114 struct intel_mipmap_tree
*mt
,
3115 struct intel_miptree_map
*map
,
3119 _mesa_align_free(map
->buffer
);
3126 intel_miptree_map_s8(struct brw_context
*brw
,
3127 struct intel_mipmap_tree
*mt
,
3128 struct intel_miptree_map
*map
,
3129 unsigned int level
, unsigned int slice
)
3131 map
->stride
= map
->w
;
3132 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3136 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3137 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3138 * invalidate is set, since we'll be writing the whole rectangle from our
3139 * temporary buffer back out.
3141 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3142 /* ISL uses a stencil pitch value that is expected by hardware whereas
3143 * traditional miptree uses half of that. Below the value gets supplied
3144 * to intel_offset_S8() which expects the legacy interpretation.
3146 const unsigned pitch
= mt
->surf
.size
> 0 ?
3147 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3148 uint8_t *untiled_s8_map
= map
->ptr
;
3149 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3150 unsigned int image_x
, image_y
;
3152 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3154 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3155 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3156 ptrdiff_t offset
= intel_offset_S8(pitch
,
3157 x
+ image_x
+ map
->x
,
3158 y
+ image_y
+ map
->y
,
3159 brw
->has_swizzling
);
3160 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3164 intel_miptree_unmap_raw(mt
);
3166 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3167 map
->x
, map
->y
, map
->w
, map
->h
,
3168 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3170 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3171 map
->x
, map
->y
, map
->w
, map
->h
,
3172 mt
, map
->ptr
, map
->stride
);
3177 intel_miptree_unmap_s8(struct brw_context
*brw
,
3178 struct intel_mipmap_tree
*mt
,
3179 struct intel_miptree_map
*map
,
3183 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3184 /* ISL uses a stencil pitch value that is expected by hardware whereas
3185 * traditional miptree uses half of that. Below the value gets supplied
3186 * to intel_offset_S8() which expects the legacy interpretation.
3188 const unsigned pitch
= mt
->surf
.size
> 0 ?
3189 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3190 unsigned int image_x
, image_y
;
3191 uint8_t *untiled_s8_map
= map
->ptr
;
3192 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3194 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3196 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3197 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3198 ptrdiff_t offset
= intel_offset_S8(pitch
,
3199 image_x
+ x
+ map
->x
,
3200 image_y
+ y
+ map
->y
,
3201 brw
->has_swizzling
);
3202 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3206 intel_miptree_unmap_raw(mt
);
3213 intel_miptree_map_etc(struct brw_context
*brw
,
3214 struct intel_mipmap_tree
*mt
,
3215 struct intel_miptree_map
*map
,
3219 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3220 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3221 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3224 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3225 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3227 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3228 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3229 map
->w
, map
->h
, 1));
3230 map
->ptr
= map
->buffer
;
3234 intel_miptree_unmap_etc(struct brw_context
*brw
,
3235 struct intel_mipmap_tree
*mt
,
3236 struct intel_miptree_map
*map
,
3242 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3247 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3248 + image_y
* mt
->pitch
3249 + image_x
* mt
->cpp
;
3251 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3252 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3253 map
->ptr
, map
->stride
,
3256 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3257 map
->ptr
, map
->stride
,
3258 map
->w
, map
->h
, mt
->etc_format
);
3260 intel_miptree_unmap_raw(mt
);
3265 * Mapping function for packed depth/stencil miptrees backed by real separate
3266 * miptrees for depth and stencil.
3268 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3269 * separate from the depth buffer. Yet at the GL API level, we have to expose
3270 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3271 * be able to map that memory for texture storage and glReadPixels-type
3272 * operations. We give Mesa core that access by mallocing a temporary and
3273 * copying the data between the actual backing store and the temporary.
3276 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3277 struct intel_mipmap_tree
*mt
,
3278 struct intel_miptree_map
*map
,
3279 unsigned int level
, unsigned int slice
)
3281 struct intel_mipmap_tree
*z_mt
= mt
;
3282 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3283 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3284 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3286 map
->stride
= map
->w
* packed_bpp
;
3287 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3291 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3292 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3293 * invalidate is set, since we'll be writing the whole rectangle from our
3294 * temporary buffer back out.
3296 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3297 /* ISL uses a stencil pitch value that is expected by hardware whereas
3298 * traditional miptree uses half of that. Below the value gets supplied
3299 * to intel_offset_S8() which expects the legacy interpretation.
3301 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3302 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3303 uint32_t *packed_map
= map
->ptr
;
3304 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3305 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3306 unsigned int s_image_x
, s_image_y
;
3307 unsigned int z_image_x
, z_image_y
;
3309 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3310 &s_image_x
, &s_image_y
);
3311 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3312 &z_image_x
, &z_image_y
);
3314 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3315 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3316 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3317 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3320 brw
->has_swizzling
);
3321 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3323 (map_x
+ z_image_x
));
3324 uint8_t s
= s_map
[s_offset
];
3325 uint32_t z
= z_map
[z_offset
];
3327 if (map_z32f_x24s8
) {
3328 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3329 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3331 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3336 intel_miptree_unmap_raw(s_mt
);
3337 intel_miptree_unmap_raw(z_mt
);
3339 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3341 map
->x
, map
->y
, map
->w
, map
->h
,
3342 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3343 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3344 map
->ptr
, map
->stride
);
3346 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3347 map
->x
, map
->y
, map
->w
, map
->h
,
3348 mt
, map
->ptr
, map
->stride
);
3353 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3354 struct intel_mipmap_tree
*mt
,
3355 struct intel_miptree_map
*map
,
3359 struct intel_mipmap_tree
*z_mt
= mt
;
3360 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3361 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3363 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3364 /* ISL uses a stencil pitch value that is expected by hardware whereas
3365 * traditional miptree uses half of that. Below the value gets supplied
3366 * to intel_offset_S8() which expects the legacy interpretation.
3368 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3369 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3370 uint32_t *packed_map
= map
->ptr
;
3371 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3372 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3373 unsigned int s_image_x
, s_image_y
;
3374 unsigned int z_image_x
, z_image_y
;
3376 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3377 &s_image_x
, &s_image_y
);
3378 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3379 &z_image_x
, &z_image_y
);
3381 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3382 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3383 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3384 x
+ s_image_x
+ map
->x
,
3385 y
+ s_image_y
+ map
->y
,
3386 brw
->has_swizzling
);
3387 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3389 (x
+ z_image_x
+ map
->x
));
3391 if (map_z32f_x24s8
) {
3392 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3393 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3395 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3396 s_map
[s_offset
] = packed
>> 24;
3397 z_map
[z_offset
] = packed
;
3402 intel_miptree_unmap_raw(s_mt
);
3403 intel_miptree_unmap_raw(z_mt
);
3405 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3407 map
->x
, map
->y
, map
->w
, map
->h
,
3408 z_mt
, _mesa_get_format_name(z_mt
->format
),
3409 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3410 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3411 map
->ptr
, map
->stride
);
3418 * Create and attach a map to the miptree at (level, slice). Return the
3421 static struct intel_miptree_map
*
3422 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3431 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3436 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3437 mt
->level
[level
].slice
[slice
].map
= map
;
3449 * Release the map at (level, slice).
3452 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3456 struct intel_miptree_map
**map
;
3458 map
= &mt
->level
[level
].slice
[slice
].map
;
3464 can_blit_slice(struct intel_mipmap_tree
*mt
,
3465 unsigned int level
, unsigned int slice
)
3467 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3468 if (mt
->pitch
>= 32768)
3475 use_intel_mipree_map_blit(struct brw_context
*brw
,
3476 struct intel_mipmap_tree
*mt
,
3482 /* It's probably not worth swapping to the blit ring because of
3483 * all the overhead involved.
3485 !(mode
& GL_MAP_WRITE_BIT
) &&
3487 (mt
->tiling
== I915_TILING_X
||
3488 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3489 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3490 /* Fast copy blit on skl+ supports all tiling formats. */
3492 can_blit_slice(mt
, level
, slice
))
3495 if (mt
->tiling
!= I915_TILING_NONE
&&
3496 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3497 assert(can_blit_slice(mt
, level
, slice
));
3505 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3506 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3507 * arithmetic overflow.
3509 * If you call this function and use \a out_stride, then you're doing pointer
3510 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3511 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3512 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3513 * which usually have type uint32_t or GLuint.
3516 intel_miptree_map(struct brw_context
*brw
,
3517 struct intel_mipmap_tree
*mt
,
3526 ptrdiff_t *out_stride
)
3528 struct intel_miptree_map
*map
;
3530 assert(mt
->num_samples
<= 1);
3532 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3539 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3540 map
->mode
& GL_MAP_WRITE_BIT
);
3542 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3543 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3544 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3545 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3546 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3547 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3548 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3549 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3550 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3551 #if defined(USE_SSE41)
3552 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3553 !mt
->compressed
&& cpu_has_sse4_1
&&
3554 (mt
->pitch
% 16 == 0)) {
3555 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3558 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3561 *out_ptr
= map
->ptr
;
3562 *out_stride
= map
->stride
;
3564 if (map
->ptr
== NULL
)
3565 intel_miptree_release_map(mt
, level
, slice
);
3569 intel_miptree_unmap(struct brw_context
*brw
,
3570 struct intel_mipmap_tree
*mt
,
3574 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3576 assert(mt
->num_samples
<= 1);
3581 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3582 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3584 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3585 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3586 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3587 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3588 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3589 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3590 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3591 } else if (map
->linear_mt
) {
3592 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3593 #if defined(USE_SSE41)
3594 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3595 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3598 intel_miptree_unmap_gtt(mt
);
3601 intel_miptree_release_map(mt
, level
, slice
);
3605 get_isl_surf_dim(GLenum target
)
3609 case GL_TEXTURE_1D_ARRAY
:
3610 return ISL_SURF_DIM_1D
;
3613 case GL_TEXTURE_2D_ARRAY
:
3614 case GL_TEXTURE_RECTANGLE
:
3615 case GL_TEXTURE_CUBE_MAP
:
3616 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3617 case GL_TEXTURE_2D_MULTISAMPLE
:
3618 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3619 case GL_TEXTURE_EXTERNAL_OES
:
3620 return ISL_SURF_DIM_2D
;
3623 return ISL_SURF_DIM_3D
;
3626 unreachable("Invalid texture target");
3630 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3631 GLenum target
, enum miptree_array_layout array_layout
)
3633 if (array_layout
== GEN6_HIZ_STENCIL
)
3634 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3638 case GL_TEXTURE_1D_ARRAY
:
3639 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3640 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3643 case GL_TEXTURE_2D_ARRAY
:
3644 case GL_TEXTURE_RECTANGLE
:
3645 case GL_TEXTURE_2D_MULTISAMPLE
:
3646 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3647 case GL_TEXTURE_EXTERNAL_OES
:
3648 return ISL_DIM_LAYOUT_GEN4_2D
;
3650 case GL_TEXTURE_CUBE_MAP
:
3651 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3652 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3653 ISL_DIM_LAYOUT_GEN4_2D
);
3656 return (devinfo
->gen
>= 9 ?
3657 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3660 unreachable("Invalid texture target");
3664 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3666 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3667 return ISL_TILING_W
;
3669 switch (mt
->tiling
) {
3670 case I915_TILING_NONE
:
3671 return ISL_TILING_LINEAR
;
3673 return ISL_TILING_X
;
3675 return ISL_TILING_Y0
;
3677 unreachable("Invalid tiling mode");
3683 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3684 const struct intel_mipmap_tree
*mt
,
3685 struct isl_surf
*surf
)
3687 surf
->dim
= get_isl_surf_dim(mt
->target
);
3688 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3689 mt
->tiling
, mt
->target
,
3692 if (mt
->num_samples
> 1) {
3693 switch (mt
->msaa_layout
) {
3694 case INTEL_MSAA_LAYOUT_IMS
:
3695 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3697 case INTEL_MSAA_LAYOUT_UMS
:
3698 case INTEL_MSAA_LAYOUT_CMS
:
3699 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3702 unreachable("Invalid MSAA layout");
3705 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3708 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3710 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3711 /* The ISL definition of row_pitch matches the surface state pitch field
3712 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3713 * the factor of 2 for W-tiling in row_pitch.
3715 surf
->row_pitch
= 2 * mt
->pitch
;
3717 surf
->row_pitch
= mt
->pitch
;
3720 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3722 if (brw
->gen
>= 9) {
3723 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3724 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3725 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3727 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3728 * alignment in terms of surface elements like we want.
3730 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3733 /* On earlier gens it's stored in pixels. */
3735 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3736 surf
->image_alignment_el
=
3737 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3740 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3741 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3742 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3743 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3744 surf
->logical_level0_px
.array_len
= 1;
3746 surf
->logical_level0_px
.depth
= 1;
3747 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3750 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3751 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3752 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3753 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3754 surf
->phys_level0_sa
.array_len
= 1;
3756 surf
->phys_level0_sa
.depth
= 1;
3757 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3760 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3761 surf
->samples
= MAX2(mt
->num_samples
, 1);
3763 surf
->size
= 0; /* TODO */
3764 surf
->alignment
= 0; /* TODO */
3766 switch (surf
->dim_layout
) {
3767 case ISL_DIM_LAYOUT_GEN4_2D
:
3768 case ISL_DIM_LAYOUT_GEN4_3D
:
3769 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3770 if (brw
->gen
>= 9) {
3771 surf
->array_pitch_el_rows
= mt
->qpitch
;
3774 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3775 assert(mt
->qpitch
% bh
== 0);
3776 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3779 case ISL_DIM_LAYOUT_GEN9_1D
:
3780 surf
->array_pitch_el_rows
= 1;
3784 switch (mt
->array_layout
) {
3785 case ALL_LOD_IN_EACH_SLICE
:
3786 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3788 case ALL_SLICES_AT_EACH_LOD
:
3789 case GEN6_HIZ_STENCIL
:
3790 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3793 unreachable("Invalid array layout");
3796 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3797 switch (base_format
) {
3798 case GL_DEPTH_COMPONENT
:
3799 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3801 case GL_STENCIL_INDEX
:
3802 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3804 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3806 case GL_DEPTH_STENCIL
:
3807 /* In this case we only texture from the depth part */
3808 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3809 ISL_SURF_USAGE_TEXTURE_BIT
;
3812 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3813 if (brw
->mesa_format_supports_render
[mt
->format
])
3814 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3818 if (_mesa_is_cube_map_texture(mt
->target
))
3819 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3823 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3824 const struct intel_mipmap_tree
*mt
)
3827 return ISL_AUX_USAGE_HIZ
;
3830 return ISL_AUX_USAGE_NONE
;
3832 return mt
->aux_usage
;