1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_resolve_map.h"
35 #include "intel_tex.h"
36 #include "intel_blit.h"
37 #include "intel_fbo.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
73 * This field must be set to 0 for all SINT MSRTs when all RT channels
76 * In practice this means that we have to disable MCS for all signed
77 * integer MSAA buffers. The alternative, to disable MCS only when one
78 * of the render target channels is disabled, is impractical because it
79 * would require converting between CMS and UMS MSAA layouts on the fly,
82 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
83 return INTEL_MSAA_LAYOUT_UMS
;
85 return INTEL_MSAA_LAYOUT_CMS
;
92 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
93 * scaled-down bitfield representation of the color buffer which is capable of
94 * recording when blocks of the color buffer are equal to the clear value.
95 * This function returns the block size that will be used by the MCS buffer
96 * corresponding to a certain color miptree.
98 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
99 * beneath the "Fast Color Clear" bullet (p327):
101 * The following table describes the RT alignment
115 * This alignment has the following uses:
117 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
118 * buffer contains 128 blocks horizontally and 256 blocks vertically.
120 * - For figuring out alignment restrictions for a fast clear operation. Fast
121 * clear operations must always clear aligned multiples of 16 blocks
122 * horizontally and 32 blocks vertically.
124 * - For scaling down the coordinates sent through the render pipeline during
125 * a fast clear. X coordinates must be scaled down by 8 times the block
126 * width, and Y coordinates by 16 times the block height.
128 * - For scaling down the coordinates sent through the render pipeline during
129 * a "Render Target Resolve" operation. X coordinates must be scaled down
130 * by half the block width, and Y coordinates by half the block height.
133 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*mt
,
135 unsigned *width_px
, unsigned *height
)
137 switch (mt
->tiling
) {
139 unreachable("Non-MSRT MCS requires X or Y tiling");
140 /* In release builds, fall through */
142 *width_px
= 32 / mt
->cpp
;
146 *width_px
= 64 / mt
->cpp
;
153 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
156 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
157 * beneath the "Fast Color Clear" bullet (p326):
159 * - Support is limited to tiled render targets.
160 * - Support is for non-mip-mapped and non-array surface types only.
162 * And then later, on p327:
164 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
168 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
169 struct intel_mipmap_tree
*mt
)
171 /* MCS support does not exist prior to Gen7 */
172 if (brw
->gen
< 7 || brw
->gen
>= 8)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->tiling
!= I915_TILING_X
&&
184 mt
->tiling
!= I915_TILING_Y
)
186 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
188 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
190 if (mt
->physical_depth0
!= 1)
193 /* There's no point in using an MCS buffer if the surface isn't in a
196 if (!brw
->format_supported_as_render_target
[mt
->format
])
204 * Determine depth format corresponding to a depth+stencil format,
205 * for separate stencil.
208 intel_depth_format_for_depthstencil_format(mesa_format format
) {
210 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
211 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
212 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
213 return MESA_FORMAT_Z_FLOAT32
;
221 * @param for_bo Indicates that the caller is
222 * intel_miptree_create_for_bo(). If true, then do not create
225 struct intel_mipmap_tree
*
226 intel_miptree_create_layout(struct brw_context
*brw
,
237 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
241 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
242 _mesa_lookup_enum_by_nr(target
),
243 _mesa_get_format_name(format
),
244 first_level
, last_level
, depth0
, mt
);
248 mt
->first_level
= first_level
;
249 mt
->last_level
= last_level
;
250 mt
->logical_width0
= width0
;
251 mt
->logical_height0
= height0
;
252 mt
->logical_depth0
= depth0
;
253 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
254 exec_list_make_empty(&mt
->hiz_map
);
256 /* The cpp is bytes per (1, blockheight)-sized block for compressed
257 * textures. This is why you'll see divides by blockheight all over
260 _mesa_get_format_block_size(format
, &bw
, &bh
);
261 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
262 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
264 mt
->num_samples
= num_samples
;
265 mt
->compressed
= _mesa_is_format_compressed(format
);
266 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
269 if (num_samples
> 1) {
270 /* Adjust width/height/depth for MSAA */
271 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
272 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
273 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
275 * "Any of the other messages (sample*, LOD, load4) used with a
276 * (4x) multisampled surface will in-effect sample a surface with
277 * double the height and width as that indicated in the surface
278 * state. Each pixel position on the original-sized surface is
279 * replaced with a 2x2 of samples with the following arrangement:
284 * Thus, when sampling from a multisampled texture, it behaves as
285 * though the layout in memory for (x,y,sample) is:
287 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
288 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
290 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
291 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
293 * However, the actual layout of multisampled data in memory is:
295 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
296 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
298 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
299 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
301 * This pattern repeats for each 2x2 pixel block.
303 * As a result, when calculating the size of our 4-sample buffer for
304 * an odd width or height, we have to align before scaling up because
305 * sample 3 is in that bottom right 2x2 block.
307 switch (num_samples
) {
309 assert(brw
->gen
>= 8);
310 width0
= ALIGN(width0
, 2) * 2;
311 height0
= ALIGN(height0
, 2);
314 width0
= ALIGN(width0
, 2) * 2;
315 height0
= ALIGN(height0
, 2) * 2;
318 width0
= ALIGN(width0
, 2) * 4;
319 height0
= ALIGN(height0
, 2) * 2;
322 /* num_samples should already have been quantized to 0, 1, 2, 4, or
325 unreachable("not reached");
328 /* Non-interleaved */
329 depth0
*= num_samples
;
333 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
336 switch (mt
->msaa_layout
) {
337 case INTEL_MSAA_LAYOUT_NONE
:
338 case INTEL_MSAA_LAYOUT_IMS
:
339 mt
->array_spacing_lod0
= false;
341 case INTEL_MSAA_LAYOUT_UMS
:
342 case INTEL_MSAA_LAYOUT_CMS
:
343 mt
->array_spacing_lod0
= true;
347 if (target
== GL_TEXTURE_CUBE_MAP
) {
352 mt
->physical_width0
= width0
;
353 mt
->physical_height0
= height0
;
354 mt
->physical_depth0
= depth0
;
357 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
358 (brw
->must_use_separate_stencil
||
359 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
360 mt
->stencil_mt
= intel_miptree_create(brw
,
370 INTEL_MIPTREE_TILING_ANY
);
371 if (!mt
->stencil_mt
) {
372 intel_miptree_release(&mt
);
376 /* Fix up the Z miptree format for how we're splitting out separate
377 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
379 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
382 if (format
== mt
->format
) {
383 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
384 _mesa_get_format_name(mt
->format
));
388 brw_miptree_layout(brw
, mt
);
394 * \brief Helper function for intel_miptree_create().
397 intel_miptree_choose_tiling(struct brw_context
*brw
,
400 uint32_t num_samples
,
401 enum intel_miptree_tiling_mode requested
,
402 struct intel_mipmap_tree
*mt
)
404 if (format
== MESA_FORMAT_S_UINT8
) {
405 /* The stencil buffer is W tiled. However, we request from the kernel a
406 * non-tiled buffer because the GTT is incapable of W fencing.
408 return I915_TILING_NONE
;
411 /* Some usages may want only one type of tiling, like depth miptrees (Y
412 * tiled), or temporary BOs for uploading data once (linear).
415 case INTEL_MIPTREE_TILING_ANY
:
417 case INTEL_MIPTREE_TILING_Y
:
418 return I915_TILING_Y
;
419 case INTEL_MIPTREE_TILING_NONE
:
420 return I915_TILING_NONE
;
423 if (num_samples
> 1) {
424 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
427 * [DevSNB+]: For multi-sample render targets, this field must be
428 * 1. MSRTs can only be tiled.
430 * Our usual reason for preferring X tiling (fast blits using the
431 * blitting engine) doesn't apply to MSAA, since we'll generally be
432 * downsampling or upsampling when blitting between the MSAA buffer
433 * and another buffer, and the blitting engine doesn't support that.
434 * So use Y tiling, since it makes better use of the cache.
436 return I915_TILING_Y
;
439 GLenum base_format
= _mesa_get_format_base_format(format
);
440 if (base_format
== GL_DEPTH_COMPONENT
||
441 base_format
== GL_DEPTH_STENCIL_EXT
)
442 return I915_TILING_Y
;
444 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
446 /* If the width is much smaller than a tile, don't bother tiling. */
447 if (minimum_pitch
< 64)
448 return I915_TILING_NONE
;
450 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
451 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
452 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
453 mt
->total_width
, mt
->total_height
);
454 return I915_TILING_NONE
;
457 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
459 return I915_TILING_X
;
461 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
462 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
464 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
465 * all the way back to 965, but is explicitly permitted on Gen7.
467 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
468 return I915_TILING_X
;
470 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
471 * messages), on p64, under the heading "Surface Vertical Alignment":
473 * This field must be set to VALIGN_4 for all tiled Y Render Target
476 * So if the surface is renderable and uses a vertical alignment of 2,
477 * force it to be X tiled. This is somewhat conservative (it's possible
478 * that the client won't ever render to this surface), but it's difficult
479 * to know that ahead of time. And besides, since we use a vertical
480 * alignment of 4 as often as we can, this shouldn't happen very often.
482 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
483 brw
->format_supported_as_render_target
[format
]) {
484 return I915_TILING_X
;
487 return I915_TILING_Y
| I915_TILING_X
;
492 * Choose an appropriate uncompressed format for a requested
493 * compressed format, if unsupported.
496 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
498 /* No need to lower ETC formats on these platforms,
499 * they are supported natively.
501 if (brw
->gen
>= 8 || brw
->is_baytrail
)
505 case MESA_FORMAT_ETC1_RGB8
:
506 return MESA_FORMAT_R8G8B8X8_UNORM
;
507 case MESA_FORMAT_ETC2_RGB8
:
508 return MESA_FORMAT_R8G8B8X8_UNORM
;
509 case MESA_FORMAT_ETC2_SRGB8
:
510 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
511 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
512 return MESA_FORMAT_B8G8R8A8_SRGB
;
513 case MESA_FORMAT_ETC2_RGBA8_EAC
:
514 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
515 return MESA_FORMAT_R8G8B8A8_UNORM
;
516 case MESA_FORMAT_ETC2_R11_EAC
:
517 return MESA_FORMAT_R_UNORM16
;
518 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
519 return MESA_FORMAT_R_SNORM16
;
520 case MESA_FORMAT_ETC2_RG11_EAC
:
521 return MESA_FORMAT_R16G16_UNORM
;
522 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
523 return MESA_FORMAT_R16G16_SNORM
;
525 /* Non ETC1 / ETC2 format */
531 struct intel_mipmap_tree
*
532 intel_miptree_create(struct brw_context
*brw
,
540 bool expect_accelerated_upload
,
542 enum intel_miptree_tiling_mode requested_tiling
)
544 struct intel_mipmap_tree
*mt
;
545 mesa_format tex_format
= format
;
546 mesa_format etc_format
= MESA_FORMAT_NONE
;
547 GLuint total_width
, total_height
;
549 format
= intel_lower_compressed_format(brw
, format
);
551 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
553 mt
= intel_miptree_create_layout(brw
, target
, format
,
554 first_level
, last_level
, width0
,
558 * pitch == 0 || height == 0 indicates the null texture
560 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
561 intel_miptree_release(&mt
);
565 total_width
= mt
->total_width
;
566 total_height
= mt
->total_height
;
568 if (format
== MESA_FORMAT_S_UINT8
) {
569 /* Align to size of W tile, 64x64. */
570 total_width
= ALIGN(total_width
, 64);
571 total_height
= ALIGN(total_height
, 64);
574 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
575 num_samples
, requested_tiling
,
579 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
581 mt
->tiling
= I915_TILING_Y
;
587 mt
->etc_format
= etc_format
;
588 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
589 total_width
, total_height
, mt
->cpp
,
591 (expect_accelerated_upload
?
592 BO_ALLOC_FOR_RENDER
: 0));
595 /* If the BO is too large to fit in the aperture, we need to use the
596 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
597 * so we need to fall back to X.
599 if (y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
600 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
601 mt
->total_width
, mt
->total_height
);
603 mt
->tiling
= I915_TILING_X
;
604 drm_intel_bo_unreference(mt
->bo
);
605 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
606 total_width
, total_height
, mt
->cpp
,
608 (expect_accelerated_upload
?
609 BO_ALLOC_FOR_RENDER
: 0));
616 intel_miptree_release(&mt
);
621 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
622 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
623 intel_miptree_release(&mt
);
628 /* If this miptree is capable of supporting fast color clears, set
629 * fast_clear_state appropriately to ensure that fast clears will occur.
630 * Allocation of the MCS miptree will be deferred until the first fast
631 * clear actually occurs.
633 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
634 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
639 struct intel_mipmap_tree
*
640 intel_miptree_create_for_bo(struct brw_context
*brw
,
648 struct intel_mipmap_tree
*mt
;
649 uint32_t tiling
, swizzle
;
651 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
653 /* Nothing will be able to use this miptree with the BO if the offset isn't
656 if (tiling
!= I915_TILING_NONE
)
657 assert(offset
% 4096 == 0);
659 /* miptrees can't handle negative pitch. If you need flipping of images,
660 * that's outside of the scope of the mt.
664 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
667 true, 0 /* num_samples */);
673 drm_intel_bo_reference(bo
);
683 * For a singlesample renderbuffer, this simply wraps the given BO with a
686 * For a multisample renderbuffer, this wraps the window system's
687 * (singlesample) BO with a singlesample miptree attached to the
688 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
689 * that will contain the actual rendering (which is lazily resolved to
690 * irb->singlesample_mt).
693 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
694 struct intel_renderbuffer
*irb
,
696 uint32_t width
, uint32_t height
,
699 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
700 struct intel_mipmap_tree
*multisample_mt
= NULL
;
701 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
702 mesa_format format
= rb
->Format
;
703 int num_samples
= rb
->NumSamples
;
705 /* Only the front and back buffers, which are color buffers, are allocated
706 * through the image loader.
708 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
709 _mesa_get_format_base_format(format
) == GL_RGBA
);
711 singlesample_mt
= intel_miptree_create_for_bo(intel
,
718 if (!singlesample_mt
)
721 /* If this miptree is capable of supporting fast color clears, set
722 * mcs_state appropriately to ensure that fast clears will occur.
723 * Allocation of the MCS miptree will be deferred until the first fast
724 * clear actually occurs.
726 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
727 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
729 if (num_samples
== 0) {
730 intel_miptree_release(&irb
->mt
);
731 irb
->mt
= singlesample_mt
;
733 assert(!irb
->singlesample_mt
);
735 intel_miptree_release(&irb
->singlesample_mt
);
736 irb
->singlesample_mt
= singlesample_mt
;
739 irb
->mt
->logical_width0
!= width
||
740 irb
->mt
->logical_height0
!= height
) {
741 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
749 irb
->need_downsample
= false;
750 intel_miptree_release(&irb
->mt
);
751 irb
->mt
= multisample_mt
;
757 intel_miptree_release(&irb
->singlesample_mt
);
758 intel_miptree_release(&irb
->mt
);
762 struct intel_mipmap_tree
*
763 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
767 uint32_t num_samples
)
769 struct intel_mipmap_tree
*mt
;
772 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
774 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
775 width
, height
, depth
, true, num_samples
,
776 INTEL_MIPTREE_TILING_ANY
);
780 if (brw_is_hiz_depth_format(brw
, format
)) {
781 ok
= intel_miptree_alloc_hiz(brw
, mt
);
789 intel_miptree_release(&mt
);
794 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
795 struct intel_mipmap_tree
*src
)
800 intel_miptree_release(dst
);
804 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
812 intel_miptree_release(struct intel_mipmap_tree
**mt
)
817 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
818 if (--(*mt
)->refcount
<= 0) {
821 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
823 drm_intel_bo_unreference((*mt
)->bo
);
824 intel_miptree_release(&(*mt
)->stencil_mt
);
825 intel_miptree_release(&(*mt
)->hiz_mt
);
826 intel_miptree_release(&(*mt
)->mcs_mt
);
827 intel_resolve_map_clear(&(*mt
)->hiz_map
);
829 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
830 free((*mt
)->level
[i
].slice
);
839 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
840 int *width
, int *height
, int *depth
)
842 switch (image
->TexObject
->Target
) {
843 case GL_TEXTURE_1D_ARRAY
:
844 *width
= image
->Width
;
846 *depth
= image
->Height
;
849 *width
= image
->Width
;
850 *height
= image
->Height
;
851 *depth
= image
->Depth
;
857 * Can the image be pulled into a unified mipmap tree? This mirrors
858 * the completeness test in a lot of ways.
860 * Not sure whether I want to pass gl_texture_image here.
863 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
864 struct gl_texture_image
*image
)
866 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
867 GLuint level
= intelImage
->base
.Base
.Level
;
868 int width
, height
, depth
;
870 /* glTexImage* choose the texture object based on the target passed in, and
871 * objects can't change targets over their lifetimes, so this should be
874 assert(image
->TexObject
->Target
== mt
->target
);
876 mesa_format mt_format
= mt
->format
;
877 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
878 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
879 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
880 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
881 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
882 mt_format
= mt
->etc_format
;
884 if (image
->TexFormat
!= mt_format
)
887 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
889 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
892 int level_depth
= mt
->level
[level
].depth
;
893 if (mt
->num_samples
> 1) {
894 switch (mt
->msaa_layout
) {
895 case INTEL_MSAA_LAYOUT_NONE
:
896 case INTEL_MSAA_LAYOUT_IMS
:
898 case INTEL_MSAA_LAYOUT_UMS
:
899 case INTEL_MSAA_LAYOUT_CMS
:
900 level_depth
/= mt
->num_samples
;
905 /* Test image dimensions against the base level image adjusted for
906 * minification. This will also catch images not present in the
907 * tree, changed targets, etc.
909 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
910 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
911 depth
!= level_depth
) {
915 if (image
->NumSamples
!= mt
->num_samples
)
923 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
925 GLuint x
, GLuint y
, GLuint d
)
927 mt
->level
[level
].depth
= d
;
928 mt
->level
[level
].level_x
= x
;
929 mt
->level
[level
].level_y
= y
;
931 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
934 assert(mt
->level
[level
].slice
== NULL
);
936 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
937 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
938 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
943 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
944 GLuint level
, GLuint img
,
947 if (img
== 0 && level
== 0)
948 assert(x
== 0 && y
== 0);
950 assert(img
< mt
->level
[level
].depth
);
952 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
953 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
955 DBG("%s level %d img %d pos %d,%d\n",
956 __FUNCTION__
, level
, img
,
957 mt
->level
[level
].slice
[img
].x_offset
,
958 mt
->level
[level
].slice
[img
].y_offset
);
962 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
963 GLuint level
, GLuint slice
,
964 GLuint
*x
, GLuint
*y
)
966 assert(slice
< mt
->level
[level
].depth
);
968 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
969 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
973 * This function computes masks that may be used to select the bits of the X
974 * and Y coordinates that indicate the offset within a tile. If the BO is
975 * untiled, the masks are set to 0.
978 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
979 uint32_t *mask_x
, uint32_t *mask_y
,
980 bool map_stencil_as_y_tiled
)
983 uint32_t tiling
= mt
->tiling
;
985 if (map_stencil_as_y_tiled
)
986 tiling
= I915_TILING_Y
;
990 unreachable("not reached");
991 case I915_TILING_NONE
:
992 *mask_x
= *mask_y
= 0;
995 *mask_x
= 512 / cpp
- 1;
999 *mask_x
= 128 / cpp
- 1;
1006 * Compute the offset (in bytes) from the start of the BO to the given x
1007 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1008 * multiples of the tile size.
1011 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1012 uint32_t x
, uint32_t y
,
1013 bool map_stencil_as_y_tiled
)
1016 uint32_t pitch
= mt
->pitch
;
1017 uint32_t tiling
= mt
->tiling
;
1019 if (map_stencil_as_y_tiled
) {
1020 tiling
= I915_TILING_Y
;
1022 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1023 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1024 * the resulting surface is twice the pitch of the original miptree,
1025 * since each row in the Y-tiled view corresponds to two rows in the
1026 * actual W-tiled surface. So we need to correct the pitch before
1027 * computing the offsets.
1034 unreachable("not reached");
1035 case I915_TILING_NONE
:
1036 return y
* pitch
+ x
* cpp
;
1038 assert((x
% (512 / cpp
)) == 0);
1039 assert((y
% 8) == 0);
1040 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1042 assert((x
% (128 / cpp
)) == 0);
1043 assert((y
% 32) == 0);
1044 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1049 * Rendering with tiled buffers requires that the base address of the buffer
1050 * be aligned to a page boundary. For renderbuffers, and sometimes with
1051 * textures, we may want the surface to point at a texture image level that
1052 * isn't at a page boundary.
1054 * This function returns an appropriately-aligned base offset
1055 * according to the tiling restrictions, plus any required x/y offset
1059 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1060 GLuint level
, GLuint slice
,
1065 uint32_t mask_x
, mask_y
;
1067 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1068 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1070 *tile_x
= x
& mask_x
;
1071 *tile_y
= y
& mask_y
;
1073 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1077 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1078 struct intel_mipmap_tree
*dst_mt
,
1079 struct intel_mipmap_tree
*src_mt
,
1086 int src_stride
, dst_stride
;
1087 int cpp
= dst_mt
->cpp
;
1089 intel_miptree_map(brw
, src_mt
,
1093 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1096 intel_miptree_map(brw
, dst_mt
,
1100 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1104 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1105 _mesa_get_format_name(src_mt
->format
),
1106 src_mt
, src
, src_stride
,
1107 _mesa_get_format_name(dst_mt
->format
),
1108 dst_mt
, dst
, dst_stride
,
1111 int row_size
= cpp
* width
;
1112 if (src_stride
== row_size
&&
1113 dst_stride
== row_size
) {
1114 memcpy(dst
, src
, row_size
* height
);
1116 for (int i
= 0; i
< height
; i
++) {
1117 memcpy(dst
, src
, row_size
);
1123 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1124 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1126 /* Don't forget to copy the stencil data over, too. We could have skipped
1127 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1128 * shuffling the two data sources in/out of temporary storage instead of
1129 * the direct mapping we get this way.
1131 if (dst_mt
->stencil_mt
) {
1132 assert(src_mt
->stencil_mt
);
1133 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1134 level
, slice
, width
, height
);
1139 intel_miptree_copy_slice(struct brw_context
*brw
,
1140 struct intel_mipmap_tree
*dst_mt
,
1141 struct intel_mipmap_tree
*src_mt
,
1147 mesa_format format
= src_mt
->format
;
1148 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1149 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1157 assert(depth
< src_mt
->level
[level
].depth
);
1158 assert(src_mt
->format
== dst_mt
->format
);
1160 if (dst_mt
->compressed
) {
1161 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1162 width
= ALIGN(width
, dst_mt
->align_w
);
1165 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1166 * below won't apply since we can't do the depth's Y tiling or the
1167 * stencil's W tiling in the blitter.
1169 if (src_mt
->stencil_mt
) {
1170 intel_miptree_copy_slice_sw(brw
,
1177 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1178 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1179 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1181 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1182 _mesa_get_format_name(src_mt
->format
),
1183 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1184 _mesa_get_format_name(dst_mt
->format
),
1185 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1188 if (!intel_miptree_blit(brw
,
1189 src_mt
, level
, slice
, 0, 0, false,
1190 dst_mt
, level
, slice
, 0, 0, false,
1191 width
, height
, GL_COPY
)) {
1192 perf_debug("miptree validate blit for %s failed\n",
1193 _mesa_get_format_name(format
));
1195 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1201 * Copies the image's current data to the given miptree, and associates that
1202 * miptree with the image.
1204 * If \c invalidate is true, then the actual image data does not need to be
1205 * copied, but the image still needs to be associated to the new miptree (this
1206 * is set to true if we're about to clear the image).
1209 intel_miptree_copy_teximage(struct brw_context
*brw
,
1210 struct intel_texture_image
*intelImage
,
1211 struct intel_mipmap_tree
*dst_mt
,
1214 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1215 struct intel_texture_object
*intel_obj
=
1216 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1217 int level
= intelImage
->base
.Base
.Level
;
1218 int face
= intelImage
->base
.Base
.Face
;
1219 GLuint depth
= intelImage
->base
.Base
.Depth
;
1222 for (int slice
= 0; slice
< depth
; slice
++) {
1223 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1227 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1228 intel_obj
->needs_validate
= true;
1232 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1233 struct intel_mipmap_tree
*mt
,
1236 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1237 assert(mt
->mcs_mt
== NULL
);
1239 /* Choose the correct format for the MCS buffer. All that really matters
1240 * is that we allocate the right buffer size, since we'll always be
1241 * accessing this miptree using MCS-specific hardware mechanisms, which
1242 * infer the correct format based on num_samples.
1245 switch (num_samples
) {
1248 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1251 format
= MESA_FORMAT_R_UNORM8
;
1254 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1255 * for each sample, plus 8 padding bits).
1257 format
= MESA_FORMAT_R_UINT32
;
1260 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1263 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1265 * "The MCS surface must be stored as Tile Y."
1267 mt
->mcs_mt
= intel_miptree_create(brw
,
1273 mt
->logical_height0
,
1276 0 /* num_samples */,
1277 INTEL_MIPTREE_TILING_Y
);
1279 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1281 * When MCS buffer is enabled and bound to MSRT, it is required that it
1282 * is cleared prior to any rendering.
1284 * Since we don't use the MCS buffer for any purpose other than rendering,
1285 * it makes sense to just clear it immediately upon allocation.
1287 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1289 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1290 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1291 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1292 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1299 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1300 struct intel_mipmap_tree
*mt
)
1302 assert(mt
->mcs_mt
== NULL
);
1304 /* The format of the MCS buffer is opaque to the driver; all that matters
1305 * is that we get its size and pitch right. We'll pretend that the format
1306 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1307 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1308 * the block width and then a further factor of 4. Since an MCS tile
1309 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1310 * we'll need to scale the height down by the block height and then a
1311 * further factor of 8.
1313 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1314 unsigned block_width_px
;
1315 unsigned block_height
;
1316 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1317 unsigned width_divisor
= block_width_px
* 4;
1318 unsigned height_divisor
= block_height
* 8;
1319 unsigned mcs_width
=
1320 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1321 unsigned mcs_height
=
1322 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1323 assert(mt
->logical_depth0
== 1);
1324 mt
->mcs_mt
= intel_miptree_create(brw
,
1333 0 /* num_samples */,
1334 INTEL_MIPTREE_TILING_Y
);
1341 * Helper for intel_miptree_alloc_hiz() that sets
1342 * \c mt->level[level].has_hiz. Return true if and only if
1343 * \c has_hiz was set.
1346 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1347 struct intel_mipmap_tree
*mt
,
1352 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1353 uint32_t width
= minify(mt
->physical_width0
, level
);
1354 uint32_t height
= minify(mt
->physical_height0
, level
);
1356 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1357 * and the height is 4 aligned. This allows our HiZ support
1358 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1359 * we can grow the width & height to allow the HiZ op to
1360 * force the proper size alignments.
1362 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1363 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1368 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1369 mt
->level
[level
].has_hiz
= true;
1376 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1377 struct intel_mipmap_tree
*mt
)
1379 assert(mt
->hiz_mt
== NULL
);
1380 mt
->hiz_mt
= intel_miptree_create(brw
,
1386 mt
->logical_height0
,
1390 INTEL_MIPTREE_TILING_ANY
);
1395 /* Mark that all slices need a HiZ resolve. */
1396 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1397 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1400 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1401 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1402 exec_node_init(&m
->link
);
1405 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1407 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1415 * Does the miptree slice have hiz enabled?
1418 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1420 intel_miptree_check_level_layer(mt
, level
, 0);
1421 return mt
->level
[level
].has_hiz
;
1425 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1429 if (!intel_miptree_level_has_hiz(mt
, level
))
1432 intel_resolve_map_set(&mt
->hiz_map
,
1433 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1438 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1442 if (!intel_miptree_level_has_hiz(mt
, level
))
1445 intel_resolve_map_set(&mt
->hiz_map
,
1446 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1450 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1454 uint32_t end_layer
= mt
->level
[level
].depth
;
1456 for (layer
= 0; layer
< end_layer
; layer
++) {
1457 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1462 intel_miptree_slice_resolve(struct brw_context
*brw
,
1463 struct intel_mipmap_tree
*mt
,
1466 enum gen6_hiz_op need
)
1468 intel_miptree_check_level_layer(mt
, level
, layer
);
1470 struct intel_resolve_map
*item
=
1471 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1473 if (!item
|| item
->need
!= need
)
1476 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1477 intel_resolve_map_remove(item
);
1482 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1483 struct intel_mipmap_tree
*mt
,
1487 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1488 GEN6_HIZ_OP_HIZ_RESOLVE
);
1492 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1493 struct intel_mipmap_tree
*mt
,
1497 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1498 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1502 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*mt
,
1504 enum gen6_hiz_op need
)
1506 bool did_resolve
= false;
1508 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1509 if (map
->need
!= need
)
1512 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1513 intel_resolve_map_remove(map
);
1521 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1522 struct intel_mipmap_tree
*mt
)
1524 return intel_miptree_all_slices_resolve(brw
, mt
,
1525 GEN6_HIZ_OP_HIZ_RESOLVE
);
1529 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1530 struct intel_mipmap_tree
*mt
)
1532 return intel_miptree_all_slices_resolve(brw
, mt
,
1533 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1538 intel_miptree_resolve_color(struct brw_context
*brw
,
1539 struct intel_mipmap_tree
*mt
)
1541 switch (mt
->fast_clear_state
) {
1542 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1543 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1544 /* No resolve needed */
1546 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1547 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1548 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1549 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1550 brw_blorp_resolve_color(brw
, mt
);
1557 * Make it possible to share the BO backing the given miptree with another
1558 * process or another miptree.
1560 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1561 * then discard the MCS buffer, if present. We also set the fast_clear_state
1562 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1563 * allocated in the future.
1566 intel_miptree_make_shareable(struct brw_context
*brw
,
1567 struct intel_mipmap_tree
*mt
)
1569 /* MCS buffers are also used for multisample buffers, but we can't resolve
1570 * away a multisample MCS buffer because it's an integral part of how the
1571 * pixel data is stored. Fortunately this code path should never be
1572 * reached for multisample buffers.
1574 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1577 intel_miptree_resolve_color(brw
, mt
);
1578 intel_miptree_release(&mt
->mcs_mt
);
1579 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1585 * \brief Get pointer offset into stencil buffer.
1587 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1588 * must decode the tile's layout in software.
1591 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1593 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1595 * Even though the returned offset is always positive, the return type is
1597 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1598 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1601 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1603 uint32_t tile_size
= 4096;
1604 uint32_t tile_width
= 64;
1605 uint32_t tile_height
= 64;
1606 uint32_t row_size
= 64 * stride
;
1608 uint32_t tile_x
= x
/ tile_width
;
1609 uint32_t tile_y
= y
/ tile_height
;
1611 /* The byte's address relative to the tile's base addres. */
1612 uint32_t byte_x
= x
% tile_width
;
1613 uint32_t byte_y
= y
% tile_height
;
1615 uintptr_t u
= tile_y
* row_size
1616 + tile_x
* tile_size
1617 + 512 * (byte_x
/ 8)
1619 + 32 * ((byte_y
/ 4) % 2)
1620 + 16 * ((byte_x
/ 4) % 2)
1621 + 8 * ((byte_y
/ 2) % 2)
1622 + 4 * ((byte_x
/ 2) % 2)
1627 /* adjust for bit6 swizzling */
1628 if (((byte_x
/ 8) % 2) == 1) {
1629 if (((byte_y
/ 8) % 2) == 0) {
1641 intel_miptree_updownsample(struct brw_context
*brw
,
1642 struct intel_mipmap_tree
*src
,
1643 struct intel_mipmap_tree
*dst
)
1646 brw_blorp_blit_miptrees(brw
,
1647 src
, 0 /* level */, 0 /* layer */,
1648 dst
, 0 /* level */, 0 /* layer */,
1650 src
->logical_width0
, src
->logical_height0
,
1652 dst
->logical_width0
, dst
->logical_height0
,
1653 GL_NEAREST
, false, false /*mirror x, y*/);
1654 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1655 brw_meta_stencil_updownsample(brw
, src
, dst
);
1657 brw_meta_updownsample(brw
, src
, dst
);
1660 if (src
->stencil_mt
) {
1661 if (brw
->gen
>= 8) {
1662 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1666 brw_blorp_blit_miptrees(brw
,
1667 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1668 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1670 src
->logical_width0
, src
->logical_height0
,
1672 dst
->logical_width0
, dst
->logical_height0
,
1673 GL_NEAREST
, false, false /*mirror x, y*/);
1678 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1680 /* CPU accesses to color buffers don't understand fast color clears, so
1681 * resolve any pending fast color clears before we map.
1683 intel_miptree_resolve_color(brw
, mt
);
1685 drm_intel_bo
*bo
= mt
->bo
;
1687 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1688 intel_batchbuffer_flush(brw
);
1690 if (mt
->tiling
!= I915_TILING_NONE
)
1691 brw_bo_map_gtt(brw
, bo
, "miptree");
1693 brw_bo_map(brw
, bo
, true, "miptree");
1699 intel_miptree_unmap_raw(struct brw_context
*brw
,
1700 struct intel_mipmap_tree
*mt
)
1702 drm_intel_bo_unmap(mt
->bo
);
1706 intel_miptree_map_gtt(struct brw_context
*brw
,
1707 struct intel_mipmap_tree
*mt
,
1708 struct intel_miptree_map
*map
,
1709 unsigned int level
, unsigned int slice
)
1711 unsigned int bw
, bh
;
1713 unsigned int image_x
, image_y
;
1717 /* For compressed formats, the stride is the number of bytes per
1718 * row of blocks. intel_miptree_get_image_offset() already does
1721 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1722 assert(y
% bh
== 0);
1725 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1730 /* Note that in the case of cube maps, the caller must have passed the
1731 * slice number referencing the face.
1733 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1737 map
->stride
= mt
->pitch
;
1738 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1741 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1742 map
->x
, map
->y
, map
->w
, map
->h
,
1743 mt
, _mesa_get_format_name(mt
->format
),
1744 x
, y
, map
->ptr
, map
->stride
);
1748 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1749 struct intel_mipmap_tree
*mt
,
1750 struct intel_miptree_map
*map
,
1754 intel_miptree_unmap_raw(brw
, mt
);
1758 intel_miptree_map_blit(struct brw_context
*brw
,
1759 struct intel_mipmap_tree
*mt
,
1760 struct intel_miptree_map
*map
,
1761 unsigned int level
, unsigned int slice
)
1763 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1767 INTEL_MIPTREE_TILING_NONE
);
1769 fprintf(stderr
, "Failed to allocate blit temporary\n");
1772 map
->stride
= map
->mt
->pitch
;
1774 if (!intel_miptree_blit(brw
,
1776 map
->x
, map
->y
, false,
1779 map
->w
, map
->h
, GL_COPY
)) {
1780 fprintf(stderr
, "Failed to blit\n");
1784 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1786 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1787 map
->x
, map
->y
, map
->w
, map
->h
,
1788 mt
, _mesa_get_format_name(mt
->format
),
1789 level
, slice
, map
->ptr
, map
->stride
);
1794 intel_miptree_release(&map
->mt
);
1800 intel_miptree_unmap_blit(struct brw_context
*brw
,
1801 struct intel_mipmap_tree
*mt
,
1802 struct intel_miptree_map
*map
,
1806 struct gl_context
*ctx
= &brw
->ctx
;
1808 intel_miptree_unmap_raw(brw
, map
->mt
);
1810 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1811 bool ok
= intel_miptree_blit(brw
,
1815 map
->x
, map
->y
, false,
1816 map
->w
, map
->h
, GL_COPY
);
1817 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1820 intel_miptree_release(&map
->mt
);
1824 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1827 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1828 struct intel_mipmap_tree
*mt
,
1829 struct intel_miptree_map
*map
,
1830 unsigned int level
, unsigned int slice
)
1832 assert(map
->mode
& GL_MAP_READ_BIT
);
1833 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1835 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1836 map
->x
, map
->y
, map
->w
, map
->h
,
1837 mt
, _mesa_get_format_name(mt
->format
),
1838 level
, slice
, map
->ptr
, map
->stride
);
1840 /* Map the original image */
1843 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1847 void *src
= intel_miptree_map_raw(brw
, mt
);
1850 src
+= image_y
* mt
->pitch
;
1851 src
+= image_x
* mt
->cpp
;
1853 /* Due to the pixel offsets for the particular image being mapped, our
1854 * src pointer may not be 16-byte aligned. However, if the pitch is
1855 * divisible by 16, then the amount by which it's misaligned will remain
1856 * consistent from row to row.
1858 assert((mt
->pitch
% 16) == 0);
1859 const int misalignment
= ((uintptr_t) src
) & 15;
1861 /* Create an untiled temporary buffer for the mapping. */
1862 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1864 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1866 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
1867 /* Offset the destination so it has the same misalignment as src. */
1868 map
->ptr
= map
->buffer
+ misalignment
;
1870 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1872 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1873 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1874 void *src_ptr
= src
+ y
* mt
->pitch
;
1876 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1879 intel_miptree_unmap_raw(brw
, mt
);
1883 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1884 struct intel_mipmap_tree
*mt
,
1885 struct intel_miptree_map
*map
,
1889 _mesa_align_free(map
->buffer
);
1895 intel_miptree_map_s8(struct brw_context
*brw
,
1896 struct intel_mipmap_tree
*mt
,
1897 struct intel_miptree_map
*map
,
1898 unsigned int level
, unsigned int slice
)
1900 map
->stride
= map
->w
;
1901 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1905 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1906 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1907 * invalidate is set, since we'll be writing the whole rectangle from our
1908 * temporary buffer back out.
1910 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1911 uint8_t *untiled_s8_map
= map
->ptr
;
1912 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1913 unsigned int image_x
, image_y
;
1915 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1917 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1918 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1919 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1920 x
+ image_x
+ map
->x
,
1921 y
+ image_y
+ map
->y
,
1922 brw
->has_swizzling
);
1923 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1927 intel_miptree_unmap_raw(brw
, mt
);
1929 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1930 map
->x
, map
->y
, map
->w
, map
->h
,
1931 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1933 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1934 map
->x
, map
->y
, map
->w
, map
->h
,
1935 mt
, map
->ptr
, map
->stride
);
1940 intel_miptree_unmap_s8(struct brw_context
*brw
,
1941 struct intel_mipmap_tree
*mt
,
1942 struct intel_miptree_map
*map
,
1946 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1947 unsigned int image_x
, image_y
;
1948 uint8_t *untiled_s8_map
= map
->ptr
;
1949 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1951 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1953 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1954 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1955 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1958 brw
->has_swizzling
);
1959 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1963 intel_miptree_unmap_raw(brw
, mt
);
1970 intel_miptree_map_etc(struct brw_context
*brw
,
1971 struct intel_mipmap_tree
*mt
,
1972 struct intel_miptree_map
*map
,
1976 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1977 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1978 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1981 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1982 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1984 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1985 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1986 map
->w
, map
->h
, 1));
1987 map
->ptr
= map
->buffer
;
1991 intel_miptree_unmap_etc(struct brw_context
*brw
,
1992 struct intel_mipmap_tree
*mt
,
1993 struct intel_miptree_map
*map
,
1999 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2004 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2005 + image_y
* mt
->pitch
2006 + image_x
* mt
->cpp
;
2008 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2009 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2010 map
->ptr
, map
->stride
,
2013 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2014 map
->ptr
, map
->stride
,
2015 map
->w
, map
->h
, mt
->etc_format
);
2017 intel_miptree_unmap_raw(brw
, mt
);
2022 * Mapping function for packed depth/stencil miptrees backed by real separate
2023 * miptrees for depth and stencil.
2025 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2026 * separate from the depth buffer. Yet at the GL API level, we have to expose
2027 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2028 * be able to map that memory for texture storage and glReadPixels-type
2029 * operations. We give Mesa core that access by mallocing a temporary and
2030 * copying the data between the actual backing store and the temporary.
2033 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2034 struct intel_mipmap_tree
*mt
,
2035 struct intel_miptree_map
*map
,
2036 unsigned int level
, unsigned int slice
)
2038 struct intel_mipmap_tree
*z_mt
= mt
;
2039 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2040 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2041 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2043 map
->stride
= map
->w
* packed_bpp
;
2044 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2048 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2049 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2050 * invalidate is set, since we'll be writing the whole rectangle from our
2051 * temporary buffer back out.
2053 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2054 uint32_t *packed_map
= map
->ptr
;
2055 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2056 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2057 unsigned int s_image_x
, s_image_y
;
2058 unsigned int z_image_x
, z_image_y
;
2060 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2061 &s_image_x
, &s_image_y
);
2062 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2063 &z_image_x
, &z_image_y
);
2065 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2066 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2067 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2068 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2071 brw
->has_swizzling
);
2072 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2074 (map_x
+ z_image_x
));
2075 uint8_t s
= s_map
[s_offset
];
2076 uint32_t z
= z_map
[z_offset
];
2078 if (map_z32f_x24s8
) {
2079 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2080 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2082 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2087 intel_miptree_unmap_raw(brw
, s_mt
);
2088 intel_miptree_unmap_raw(brw
, z_mt
);
2090 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2092 map
->x
, map
->y
, map
->w
, map
->h
,
2093 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2094 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2095 map
->ptr
, map
->stride
);
2097 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2098 map
->x
, map
->y
, map
->w
, map
->h
,
2099 mt
, map
->ptr
, map
->stride
);
2104 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2105 struct intel_mipmap_tree
*mt
,
2106 struct intel_miptree_map
*map
,
2110 struct intel_mipmap_tree
*z_mt
= mt
;
2111 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2112 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2114 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2115 uint32_t *packed_map
= map
->ptr
;
2116 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2117 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2118 unsigned int s_image_x
, s_image_y
;
2119 unsigned int z_image_x
, z_image_y
;
2121 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2122 &s_image_x
, &s_image_y
);
2123 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2124 &z_image_x
, &z_image_y
);
2126 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2127 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2128 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2129 x
+ s_image_x
+ map
->x
,
2130 y
+ s_image_y
+ map
->y
,
2131 brw
->has_swizzling
);
2132 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2134 (x
+ z_image_x
+ map
->x
));
2136 if (map_z32f_x24s8
) {
2137 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2138 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2140 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2141 s_map
[s_offset
] = packed
>> 24;
2142 z_map
[z_offset
] = packed
;
2147 intel_miptree_unmap_raw(brw
, s_mt
);
2148 intel_miptree_unmap_raw(brw
, z_mt
);
2150 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2152 map
->x
, map
->y
, map
->w
, map
->h
,
2153 z_mt
, _mesa_get_format_name(z_mt
->format
),
2154 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2155 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2156 map
->ptr
, map
->stride
);
2163 * Create and attach a map to the miptree at (level, slice). Return the
2166 static struct intel_miptree_map
*
2167 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2176 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2181 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2182 mt
->level
[level
].slice
[slice
].map
= map
;
2194 * Release the map at (level, slice).
2197 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2201 struct intel_miptree_map
**map
;
2203 map
= &mt
->level
[level
].slice
[slice
].map
;
2209 can_blit_slice(struct intel_mipmap_tree
*mt
,
2210 unsigned int level
, unsigned int slice
)
2214 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2215 if (image_x
>= 32768 || image_y
>= 32768)
2218 if (mt
->pitch
>= 32768)
2225 intel_miptree_map(struct brw_context
*brw
,
2226 struct intel_mipmap_tree
*mt
,
2237 struct intel_miptree_map
*map
;
2239 assert(mt
->num_samples
<= 1);
2241 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2248 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2249 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2250 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2253 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2254 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2255 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2256 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2257 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2258 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2259 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2261 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2262 else if (brw
->has_llc
&&
2263 !(mode
& GL_MAP_WRITE_BIT
) &&
2265 (mt
->tiling
== I915_TILING_X
||
2266 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2267 can_blit_slice(mt
, level
, slice
)) {
2268 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2269 } else if (mt
->tiling
!= I915_TILING_NONE
&&
2270 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2271 assert(can_blit_slice(mt
, level
, slice
));
2272 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2273 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2274 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2276 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2279 *out_ptr
= map
->ptr
;
2280 *out_stride
= map
->stride
;
2282 if (map
->ptr
== NULL
)
2283 intel_miptree_release_map(mt
, level
, slice
);
2287 intel_miptree_unmap(struct brw_context
*brw
,
2288 struct intel_mipmap_tree
*mt
,
2292 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2294 assert(mt
->num_samples
<= 1);
2299 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2300 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2302 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2303 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2304 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2305 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2306 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2307 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2308 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2309 } else if (map
->mt
) {
2310 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2311 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2312 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2314 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2317 intel_miptree_release_map(mt
, level
, slice
);