2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
230 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
231 const bool arrayed
= mt
->physical_depth0
!= 1;
234 /* Multisample surfaces with the CMS layout are not layered surfaces,
235 * yet still have physical_depth0 > 1. Assert that we don't
236 * accidentally reject a multisampled surface here. We should have
237 * rejected it earlier by explicitly checking the sample count.
239 assert(mt
->num_samples
<= 1);
242 /* Handle the hardware restrictions...
244 * All GENs have the following restriction: "MCS buffer for non-MSRT is
245 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
247 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
248 * Non-MultiSampler Render Target Restrictions) Support is for
249 * non-mip-mapped and non-array surface types only.
251 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
252 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
253 * surfaces are supported with MCS buffer layout with these alignments in
254 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
256 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
257 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
258 * surfaces are supported with MCS buffer layout with these alignments in
259 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
261 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
264 /* Not implemented yet. */
266 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
267 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
271 /* Not implemented yet. */
273 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
274 mt
->logical_width0
, mt
->logical_height0
,
275 mt
->physical_depth0
);
279 /* There's no point in using an MCS buffer if the surface isn't in a
282 if (!brw
->format_supported_as_render_target
[mt
->format
])
286 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
287 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
288 return isl_format_supports_lossless_compression(&brw
->screen
->devinfo
,
294 /* On Gen9 support for color buffer compression was extended to single
295 * sampled surfaces. This is a helper considering both auxiliary buffer
296 * type and number of samples telling if the given miptree represents
297 * the new single sampled case - also called lossless compression.
300 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
301 const struct intel_mipmap_tree
*mt
)
303 /* Only available from Gen9 onwards. */
307 /* Compression always requires auxiliary buffer. */
311 /* Single sample compression is represented re-using msaa compression
312 * layout type: "Compressed Multisampled Surfaces".
314 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
317 /* And finally distinguish between msaa and single sample case. */
318 return mt
->num_samples
<= 1;
322 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
323 const struct intel_mipmap_tree
*mt
)
325 /* For now compression is only enabled for integer formats even though
326 * there exist supported floating point formats also. This is a heuristic
327 * decision based on current public benchmarks. In none of the cases these
328 * formats provided any improvement but a few cases were seen to regress.
329 * Hence these are left to to be enabled in the future when they are known
332 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
335 /* Fast clear mechanism and lossless compression go hand in hand. */
336 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
339 /* Fast clear can be also used to clear srgb surfaces by using equivalent
340 * linear format. This trick, however, can't be extended to be used with
341 * lossless compression and therefore a check is needed to see if the format
344 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
348 * Determine depth format corresponding to a depth+stencil format,
349 * for separate stencil.
352 intel_depth_format_for_depthstencil_format(mesa_format format
) {
354 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
355 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
356 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
357 return MESA_FORMAT_Z_FLOAT32
;
365 * @param for_bo Indicates that the caller is
366 * intel_miptree_create_for_bo(). If true, then do not create
369 static struct intel_mipmap_tree
*
370 intel_miptree_create_layout(struct brw_context
*brw
,
379 uint32_t layout_flags
)
381 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
385 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
386 _mesa_enum_to_string(target
),
387 _mesa_get_format_name(format
),
388 first_level
, last_level
, depth0
, mt
);
390 if (target
== GL_TEXTURE_1D_ARRAY
)
391 assert(height0
== 1);
395 mt
->first_level
= first_level
;
396 mt
->last_level
= last_level
;
397 mt
->logical_width0
= width0
;
398 mt
->logical_height0
= height0
;
399 mt
->logical_depth0
= depth0
;
400 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
401 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
402 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
403 exec_list_make_empty(&mt
->hiz_map
);
404 mt
->cpp
= _mesa_get_format_bytes(format
);
405 mt
->num_samples
= num_samples
;
406 mt
->compressed
= _mesa_is_format_compressed(format
);
407 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
410 int depth_multiply
= 1;
411 if (num_samples
> 1) {
412 /* Adjust width/height/depth for MSAA */
413 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
414 mt
->disable_aux_buffers
);
415 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
416 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
417 * "If the surface is multisampled and it is a depth or stencil
418 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
419 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
422 * +----------------------------------------------------------------+
423 * | Num Multisamples | W_l = | H_l = |
424 * +----------------------------------------------------------------+
425 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
426 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
427 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
428 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
429 * +----------------------------------------------------------------+
432 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
433 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
434 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
436 * Another more complicated explanation for these adjustments comes
437 * from the Sandybridge PRM, volume 4, part 1, page 31:
439 * "Any of the other messages (sample*, LOD, load4) used with a
440 * (4x) multisampled surface will in-effect sample a surface with
441 * double the height and width as that indicated in the surface
442 * state. Each pixel position on the original-sized surface is
443 * replaced with a 2x2 of samples with the following arrangement:
448 * Thus, when sampling from a multisampled texture, it behaves as
449 * though the layout in memory for (x,y,sample) is:
451 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
452 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
454 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
455 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
457 * However, the actual layout of multisampled data in memory is:
459 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
460 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
462 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
463 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
465 * This pattern repeats for each 2x2 pixel block.
467 * As a result, when calculating the size of our 4-sample buffer for
468 * an odd width or height, we have to align before scaling up because
469 * sample 3 is in that bottom right 2x2 block.
471 switch (num_samples
) {
473 assert(brw
->gen
>= 8);
474 width0
= ALIGN(width0
, 2) * 2;
475 height0
= ALIGN(height0
, 2);
478 width0
= ALIGN(width0
, 2) * 2;
479 height0
= ALIGN(height0
, 2) * 2;
482 width0
= ALIGN(width0
, 2) * 4;
483 height0
= ALIGN(height0
, 2) * 2;
486 width0
= ALIGN(width0
, 2) * 4;
487 height0
= ALIGN(height0
, 2) * 4;
490 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
493 unreachable("not reached");
496 /* Non-interleaved */
497 depth_multiply
= num_samples
;
498 depth0
*= depth_multiply
;
502 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
503 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
504 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
505 * used on Gen8 to make it pick a qpitch value which doesn't include space
506 * for the mipmaps. On Gen9 this is not necessary because it will
507 * automatically pick a packed qpitch value whenever mt->first_level ==
509 * TODO: can we use it elsewhere?
510 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
513 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
515 switch (mt
->msaa_layout
) {
516 case INTEL_MSAA_LAYOUT_NONE
:
517 case INTEL_MSAA_LAYOUT_IMS
:
518 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
520 case INTEL_MSAA_LAYOUT_UMS
:
521 case INTEL_MSAA_LAYOUT_CMS
:
522 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
527 if (target
== GL_TEXTURE_CUBE_MAP
)
528 assert(depth0
== 6 * depth_multiply
);
530 mt
->physical_width0
= width0
;
531 mt
->physical_height0
= height0
;
532 mt
->physical_depth0
= depth0
;
534 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
535 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
536 (brw
->must_use_separate_stencil
||
537 (brw
->has_separate_stencil
&&
538 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
539 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
541 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
542 MIPTREE_LAYOUT_TILING_ANY
;
545 mt
->stencil_mt
= intel_miptree_create(brw
,
556 if (!mt
->stencil_mt
) {
557 intel_miptree_release(&mt
);
560 mt
->stencil_mt
->r8stencil_needs_update
= true;
562 /* Fix up the Z miptree format for how we're splitting out separate
563 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
565 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
568 if (format
== mt
->format
) {
569 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
570 _mesa_get_format_name(mt
->format
));
574 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
575 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
578 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
579 * multisampled or have an AUX buffer attached to it.
581 * GEN | MSRT | AUX_CCS_* or AUX_MCS
582 * -------------------------------------------
583 * 9 | HALIGN_16 | HALIGN_16
584 * 8 | HALIGN_ANY | HALIGN_16
588 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
589 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
590 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
591 } else if (brw
->gen
>= 9 && num_samples
> 1) {
592 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
594 const UNUSED
bool is_lossless_compressed_aux
=
595 brw
->gen
>= 9 && num_samples
== 1 &&
596 mt
->format
== MESA_FORMAT_R_UINT32
;
598 /* For now, nothing else has this requirement */
599 assert(is_lossless_compressed_aux
||
600 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
603 brw_miptree_layout(brw
, mt
, layout_flags
);
605 if (mt
->disable_aux_buffers
)
606 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
613 * Choose an appropriate uncompressed format for a requested
614 * compressed format, if unsupported.
617 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
619 /* No need to lower ETC formats on these platforms,
620 * they are supported natively.
622 if (brw
->gen
>= 8 || brw
->is_baytrail
)
626 case MESA_FORMAT_ETC1_RGB8
:
627 return MESA_FORMAT_R8G8B8X8_UNORM
;
628 case MESA_FORMAT_ETC2_RGB8
:
629 return MESA_FORMAT_R8G8B8X8_UNORM
;
630 case MESA_FORMAT_ETC2_SRGB8
:
631 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
632 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
633 return MESA_FORMAT_B8G8R8A8_SRGB
;
634 case MESA_FORMAT_ETC2_RGBA8_EAC
:
635 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
636 return MESA_FORMAT_R8G8B8A8_UNORM
;
637 case MESA_FORMAT_ETC2_R11_EAC
:
638 return MESA_FORMAT_R_UNORM16
;
639 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
640 return MESA_FORMAT_R_SNORM16
;
641 case MESA_FORMAT_ETC2_RG11_EAC
:
642 return MESA_FORMAT_R16G16_UNORM
;
643 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
644 return MESA_FORMAT_R16G16_SNORM
;
646 /* Non ETC1 / ETC2 format */
651 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
653 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
654 unsigned long *pitch
)
656 uint32_t tile_width
, tile_height
;
657 unsigned long stride
, size
, aligned_y
;
659 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
660 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
661 &tile_width
, &tile_height
);
663 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
664 stride
= mt
->total_width
* mt
->cpp
;
665 stride
= ALIGN(stride
, tile_width
);
666 size
= stride
* aligned_y
;
668 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
669 assert(size
% 4096 == 0);
672 assert(size
% (64 * 1024) == 0);
673 *alignment
= 64 * 1024;
679 static struct intel_mipmap_tree
*
680 miptree_create(struct brw_context
*brw
,
689 uint32_t layout_flags
)
691 struct intel_mipmap_tree
*mt
;
692 mesa_format tex_format
= format
;
693 mesa_format etc_format
= MESA_FORMAT_NONE
;
694 uint32_t alloc_flags
= 0;
696 format
= intel_lower_compressed_format(brw
, format
);
698 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
700 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
701 mt
= intel_miptree_create_layout(brw
, target
, format
,
702 first_level
, last_level
, width0
,
703 height0
, depth0
, num_samples
,
706 * pitch == 0 || height == 0 indicates the null texture
708 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
709 intel_miptree_release(&mt
);
713 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
714 mt
->tiling
= I915_TILING_Y
;
716 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
717 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
720 mt
->etc_format
= etc_format
;
722 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
723 unsigned alignment
= 0;
725 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
727 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
730 if (format
== MESA_FORMAT_S_UINT8
) {
731 /* Align to size of W tile, 64x64. */
732 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
733 ALIGN(mt
->total_width
, 64),
734 ALIGN(mt
->total_height
, 64),
735 mt
->cpp
, &mt
->tiling
, &pitch
,
738 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
739 mt
->total_width
, mt
->total_height
,
740 mt
->cpp
, &mt
->tiling
, &pitch
,
750 struct intel_mipmap_tree
*
751 intel_miptree_create(struct brw_context
*brw
,
760 uint32_t layout_flags
)
762 struct intel_mipmap_tree
*mt
= miptree_create(
764 first_level
, last_level
,
765 width0
, height0
, depth0
, num_samples
,
768 /* If the BO is too large to fit in the aperture, we need to use the
769 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
770 * handle Y-tiling, so we need to fall back to X.
772 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
773 mt
->tiling
== I915_TILING_Y
) {
774 unsigned long pitch
= mt
->pitch
;
775 const uint32_t alloc_flags
=
776 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
777 BO_ALLOC_FOR_RENDER
: 0;
778 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
779 mt
->total_width
, mt
->total_height
);
781 mt
->tiling
= I915_TILING_X
;
782 drm_intel_bo_unreference(mt
->bo
);
783 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
784 mt
->total_width
, mt
->total_height
, mt
->cpp
,
785 &mt
->tiling
, &pitch
, alloc_flags
);
792 intel_miptree_release(&mt
);
797 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
798 assert(mt
->num_samples
> 1);
799 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
800 intel_miptree_release(&mt
);
805 /* If this miptree is capable of supporting fast color clears, set
806 * fast_clear_state appropriately to ensure that fast clears will occur.
807 * Allocation of the MCS miptree will be deferred until the first fast
808 * clear actually occurs or when compressed single sampled buffer is
809 * written by the GPU for the first time.
811 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
812 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
813 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
814 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
816 /* On Gen9+ clients are not currently capable of consuming compressed
817 * single-sampled buffers. Disabling compression allows us to skip
820 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
821 const bool is_lossless_compressed
=
822 unlikely(!lossless_compression_disabled
) &&
823 brw
->gen
>= 9 && !mt
->is_scanout
&&
824 intel_miptree_supports_lossless_compressed(brw
, mt
);
826 if (is_lossless_compressed
) {
827 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
834 struct intel_mipmap_tree
*
835 intel_miptree_create_for_bo(struct brw_context
*brw
,
843 uint32_t layout_flags
)
845 struct intel_mipmap_tree
*mt
;
846 uint32_t tiling
, swizzle
;
849 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
851 /* Nothing will be able to use this miptree with the BO if the offset isn't
854 if (tiling
!= I915_TILING_NONE
)
855 assert(offset
% 4096 == 0);
857 /* miptrees can't handle negative pitch. If you need flipping of images,
858 * that's outside of the scope of the mt.
862 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
864 /* The BO already has a tiling format and we shouldn't confuse the lower
865 * layers by making it try to find a tiling format again.
867 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
868 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
870 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
871 mt
= intel_miptree_create_layout(brw
, target
, format
,
873 width
, height
, depth
, 0,
878 drm_intel_bo_reference(bo
);
888 * For a singlesample renderbuffer, this simply wraps the given BO with a
891 * For a multisample renderbuffer, this wraps the window system's
892 * (singlesample) BO with a singlesample miptree attached to the
893 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
894 * that will contain the actual rendering (which is lazily resolved to
895 * irb->singlesample_mt).
898 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
899 struct intel_renderbuffer
*irb
,
901 uint32_t width
, uint32_t height
,
904 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
905 struct intel_mipmap_tree
*multisample_mt
= NULL
;
906 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
907 mesa_format format
= rb
->Format
;
908 int num_samples
= rb
->NumSamples
;
910 /* Only the front and back buffers, which are color buffers, are allocated
911 * through the image loader.
913 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
914 _mesa_get_format_base_format(format
) == GL_RGBA
);
916 singlesample_mt
= intel_miptree_create_for_bo(intel
,
924 MIPTREE_LAYOUT_FOR_SCANOUT
);
925 if (!singlesample_mt
)
928 /* If this miptree is capable of supporting fast color clears, set
929 * mcs_state appropriately to ensure that fast clears will occur.
930 * Allocation of the MCS miptree will be deferred until the first fast
931 * clear actually occurs.
933 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
934 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
935 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
938 if (num_samples
== 0) {
939 intel_miptree_release(&irb
->mt
);
940 irb
->mt
= singlesample_mt
;
942 assert(!irb
->singlesample_mt
);
944 intel_miptree_release(&irb
->singlesample_mt
);
945 irb
->singlesample_mt
= singlesample_mt
;
948 irb
->mt
->logical_width0
!= width
||
949 irb
->mt
->logical_height0
!= height
) {
950 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
958 irb
->need_downsample
= false;
959 intel_miptree_release(&irb
->mt
);
960 irb
->mt
= multisample_mt
;
966 intel_miptree_release(&irb
->singlesample_mt
);
967 intel_miptree_release(&irb
->mt
);
971 struct intel_mipmap_tree
*
972 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
976 uint32_t num_samples
)
978 struct intel_mipmap_tree
*mt
;
981 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
982 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
983 MIPTREE_LAYOUT_TILING_ANY
|
984 MIPTREE_LAYOUT_FOR_SCANOUT
;
986 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
987 width
, height
, depth
, num_samples
,
992 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
993 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1001 intel_miptree_release(&mt
);
1006 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1007 struct intel_mipmap_tree
*src
)
1012 intel_miptree_release(dst
);
1016 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1024 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1029 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1030 if (--(*mt
)->refcount
<= 0) {
1033 DBG("%s deleting %p\n", __func__
, *mt
);
1035 drm_intel_bo_unreference((*mt
)->bo
);
1036 intel_miptree_release(&(*mt
)->stencil_mt
);
1037 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1038 if ((*mt
)->hiz_buf
) {
1039 if ((*mt
)->hiz_buf
->mt
)
1040 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1042 drm_intel_bo_unreference((*mt
)->hiz_buf
->aux_base
.bo
);
1043 free((*mt
)->hiz_buf
);
1045 if ((*mt
)->mcs_buf
) {
1046 drm_intel_bo_unreference((*mt
)->mcs_buf
->bo
);
1047 free((*mt
)->mcs_buf
);
1049 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1051 intel_miptree_release(&(*mt
)->plane
[0]);
1052 intel_miptree_release(&(*mt
)->plane
[1]);
1054 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1055 free((*mt
)->level
[i
].slice
);
1065 intel_get_image_dims(struct gl_texture_image
*image
,
1066 int *width
, int *height
, int *depth
)
1068 switch (image
->TexObject
->Target
) {
1069 case GL_TEXTURE_1D_ARRAY
:
1070 /* For a 1D Array texture the OpenGL API will treat the image height as
1071 * the number of array slices. For Intel hardware, we treat the 1D array
1072 * as a 2D Array with a height of 1. So, here we want to swap image
1075 assert(image
->Depth
== 1);
1076 *width
= image
->Width
;
1078 *depth
= image
->Height
;
1080 case GL_TEXTURE_CUBE_MAP
:
1081 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1082 * though we really have 6 slices.
1084 assert(image
->Depth
== 1);
1085 *width
= image
->Width
;
1086 *height
= image
->Height
;
1090 *width
= image
->Width
;
1091 *height
= image
->Height
;
1092 *depth
= image
->Depth
;
1098 * Can the image be pulled into a unified mipmap tree? This mirrors
1099 * the completeness test in a lot of ways.
1101 * Not sure whether I want to pass gl_texture_image here.
1104 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1105 struct gl_texture_image
*image
)
1107 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1108 GLuint level
= intelImage
->base
.Base
.Level
;
1109 int width
, height
, depth
;
1111 /* glTexImage* choose the texture object based on the target passed in, and
1112 * objects can't change targets over their lifetimes, so this should be
1115 assert(image
->TexObject
->Target
== mt
->target
);
1117 mesa_format mt_format
= mt
->format
;
1118 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1119 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1120 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1121 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1122 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1123 mt_format
= mt
->etc_format
;
1125 if (image
->TexFormat
!= mt_format
)
1128 intel_get_image_dims(image
, &width
, &height
, &depth
);
1130 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1133 int level_depth
= mt
->level
[level
].depth
;
1134 if (mt
->num_samples
> 1) {
1135 switch (mt
->msaa_layout
) {
1136 case INTEL_MSAA_LAYOUT_NONE
:
1137 case INTEL_MSAA_LAYOUT_IMS
:
1139 case INTEL_MSAA_LAYOUT_UMS
:
1140 case INTEL_MSAA_LAYOUT_CMS
:
1141 level_depth
/= mt
->num_samples
;
1146 /* Test image dimensions against the base level image adjusted for
1147 * minification. This will also catch images not present in the
1148 * tree, changed targets, etc.
1150 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1151 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1152 depth
!= level_depth
) {
1156 if (image
->NumSamples
!= mt
->num_samples
)
1164 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1166 GLuint x
, GLuint y
, GLuint d
)
1168 mt
->level
[level
].depth
= d
;
1169 mt
->level
[level
].level_x
= x
;
1170 mt
->level
[level
].level_y
= y
;
1172 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1175 assert(mt
->level
[level
].slice
== NULL
);
1177 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1178 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1179 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1184 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1185 GLuint level
, GLuint img
,
1188 if (img
== 0 && level
== 0)
1189 assert(x
== 0 && y
== 0);
1191 assert(img
< mt
->level
[level
].depth
);
1193 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1194 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1196 DBG("%s level %d img %d pos %d,%d\n",
1197 __func__
, level
, img
,
1198 mt
->level
[level
].slice
[img
].x_offset
,
1199 mt
->level
[level
].slice
[img
].y_offset
);
1203 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1204 GLuint level
, GLuint slice
,
1205 GLuint
*x
, GLuint
*y
)
1207 assert(slice
< mt
->level
[level
].depth
);
1209 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1210 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1215 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1216 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1217 * and tile_h is set to 1.
1220 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1221 uint32_t *tile_w
, uint32_t *tile_h
)
1223 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1233 case I915_TILING_NONE
:
1238 unreachable("not reached");
1241 uint32_t aspect_ratio
= 1;
1242 assert(_mesa_is_pow_two(cpp
));
1257 unreachable("not reached");
1260 if (cpp
== 2 || cpp
== 8)
1263 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1266 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1272 * This function computes masks that may be used to select the bits of the X
1273 * and Y coordinates that indicate the offset within a tile. If the BO is
1274 * untiled, the masks are set to 0.
1277 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1278 uint32_t *mask_x
, uint32_t *mask_y
)
1280 uint32_t tile_w_bytes
, tile_h
;
1282 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1284 *mask_x
= tile_w_bytes
/ cpp
- 1;
1285 *mask_y
= tile_h
- 1;
1289 * Compute the offset (in bytes) from the start of the BO to the given x
1290 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1291 * multiples of the tile size.
1294 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1295 uint32_t x
, uint32_t y
)
1298 uint32_t pitch
= mt
->pitch
;
1299 uint32_t tiling
= mt
->tiling
;
1303 unreachable("not reached");
1304 case I915_TILING_NONE
:
1305 return y
* pitch
+ x
* cpp
;
1307 assert((x
% (512 / cpp
)) == 0);
1308 assert((y
% 8) == 0);
1309 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1311 assert((x
% (128 / cpp
)) == 0);
1312 assert((y
% 32) == 0);
1313 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1318 * Rendering with tiled buffers requires that the base address of the buffer
1319 * be aligned to a page boundary. For renderbuffers, and sometimes with
1320 * textures, we may want the surface to point at a texture image level that
1321 * isn't at a page boundary.
1323 * This function returns an appropriately-aligned base offset
1324 * according to the tiling restrictions, plus any required x/y offset
1328 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1329 GLuint level
, GLuint slice
,
1334 uint32_t mask_x
, mask_y
;
1336 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, &mask_x
, &mask_y
);
1337 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1339 *tile_x
= x
& mask_x
;
1340 *tile_y
= y
& mask_y
;
1342 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1346 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1347 struct intel_mipmap_tree
*dst_mt
,
1348 struct intel_mipmap_tree
*src_mt
,
1355 ptrdiff_t src_stride
, dst_stride
;
1356 int cpp
= dst_mt
->cpp
;
1358 intel_miptree_map(brw
, src_mt
,
1362 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1365 intel_miptree_map(brw
, dst_mt
,
1369 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1373 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1374 _mesa_get_format_name(src_mt
->format
),
1375 src_mt
, src
, src_stride
,
1376 _mesa_get_format_name(dst_mt
->format
),
1377 dst_mt
, dst
, dst_stride
,
1380 int row_size
= cpp
* width
;
1381 if (src_stride
== row_size
&&
1382 dst_stride
== row_size
) {
1383 memcpy(dst
, src
, row_size
* height
);
1385 for (int i
= 0; i
< height
; i
++) {
1386 memcpy(dst
, src
, row_size
);
1392 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1393 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1395 /* Don't forget to copy the stencil data over, too. We could have skipped
1396 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1397 * shuffling the two data sources in/out of temporary storage instead of
1398 * the direct mapping we get this way.
1400 if (dst_mt
->stencil_mt
) {
1401 assert(src_mt
->stencil_mt
);
1402 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1403 level
, slice
, width
, height
);
1408 intel_miptree_copy_slice(struct brw_context
*brw
,
1409 struct intel_mipmap_tree
*dst_mt
,
1410 struct intel_mipmap_tree
*src_mt
,
1416 mesa_format format
= src_mt
->format
;
1417 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1418 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1426 assert(depth
< src_mt
->level
[level
].depth
);
1427 assert(src_mt
->format
== dst_mt
->format
);
1429 if (dst_mt
->compressed
) {
1431 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1432 height
= ALIGN_NPOT(height
, j
) / j
;
1433 width
= ALIGN_NPOT(width
, i
) / i
;
1436 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1437 * below won't apply since we can't do the depth's Y tiling or the
1438 * stencil's W tiling in the blitter.
1440 if (src_mt
->stencil_mt
) {
1441 intel_miptree_copy_slice_sw(brw
,
1448 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1449 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1450 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1452 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1453 _mesa_get_format_name(src_mt
->format
),
1454 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1455 _mesa_get_format_name(dst_mt
->format
),
1456 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1459 if (!intel_miptree_blit(brw
,
1460 src_mt
, level
, slice
, 0, 0, false,
1461 dst_mt
, level
, slice
, 0, 0, false,
1462 width
, height
, GL_COPY
)) {
1463 perf_debug("miptree validate blit for %s failed\n",
1464 _mesa_get_format_name(format
));
1466 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1472 * Copies the image's current data to the given miptree, and associates that
1473 * miptree with the image.
1475 * If \c invalidate is true, then the actual image data does not need to be
1476 * copied, but the image still needs to be associated to the new miptree (this
1477 * is set to true if we're about to clear the image).
1480 intel_miptree_copy_teximage(struct brw_context
*brw
,
1481 struct intel_texture_image
*intelImage
,
1482 struct intel_mipmap_tree
*dst_mt
,
1485 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1486 struct intel_texture_object
*intel_obj
=
1487 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1488 int level
= intelImage
->base
.Base
.Level
;
1489 int face
= intelImage
->base
.Base
.Face
;
1492 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1493 depth
= intelImage
->base
.Base
.Height
;
1495 depth
= intelImage
->base
.Base
.Depth
;
1498 for (int slice
= 0; slice
< depth
; slice
++) {
1499 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1503 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1504 intel_obj
->needs_validate
= true;
1508 intel_miptree_init_mcs(struct brw_context
*brw
,
1509 struct intel_mipmap_tree
*mt
,
1512 assert(mt
->mcs_buf
!= NULL
);
1514 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1516 * When MCS buffer is enabled and bound to MSRT, it is required that it
1517 * is cleared prior to any rendering.
1519 * Since we don't use the MCS buffer for any purpose other than rendering,
1520 * it makes sense to just clear it immediately upon allocation.
1522 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1524 const int ret
= brw_bo_map_gtt(brw
, mt
->mcs_buf
->bo
, "miptree");
1525 if (unlikely(ret
)) {
1526 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1527 drm_intel_bo_unreference(mt
->mcs_buf
->bo
);
1531 void *data
= mt
->mcs_buf
->bo
->virtual;
1532 memset(data
, init_value
, mt
->mcs_buf
->size
);
1533 drm_intel_bo_unmap(mt
->mcs_buf
->bo
);
1536 static struct intel_miptree_aux_buffer
*
1537 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1538 struct intel_mipmap_tree
*mt
,
1541 unsigned mcs_height
,
1542 uint32_t layout_flags
)
1544 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1545 struct intel_mipmap_tree
*temp_mt
;
1550 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1552 * "The MCS surface must be stored as Tile Y."
1554 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1555 temp_mt
= miptree_create(brw
,
1563 0 /* num_samples */,
1570 buf
->bo
= temp_mt
->bo
;
1571 buf
->offset
= temp_mt
->offset
;
1572 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1573 buf
->pitch
= temp_mt
->pitch
;
1574 buf
->qpitch
= temp_mt
->qpitch
;
1576 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1577 * structure should go away. We use miptree create simply as a means to make
1578 * sure all the constraints for the buffer are satisfied.
1580 drm_intel_bo_reference(temp_mt
->bo
);
1581 intel_miptree_release(&temp_mt
);
1587 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1588 struct intel_mipmap_tree
*mt
,
1591 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1592 assert(mt
->mcs_buf
== NULL
);
1593 assert(!mt
->disable_aux_buffers
);
1595 /* Choose the correct format for the MCS buffer. All that really matters
1596 * is that we allocate the right buffer size, since we'll always be
1597 * accessing this miptree using MCS-specific hardware mechanisms, which
1598 * infer the correct format based on num_samples.
1601 switch (num_samples
) {
1604 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1607 format
= MESA_FORMAT_R_UNORM8
;
1610 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1611 * for each sample, plus 8 padding bits).
1613 format
= MESA_FORMAT_R_UINT32
;
1616 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1619 format
= MESA_FORMAT_RG_UINT32
;
1622 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1626 intel_mcs_miptree_buf_create(brw
, mt
,
1629 mt
->logical_height0
,
1630 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1634 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1635 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1642 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1643 struct intel_mipmap_tree
*mt
,
1644 bool is_lossless_compressed
)
1646 assert(mt
->mcs_buf
== NULL
);
1647 assert(!mt
->disable_aux_buffers
);
1649 /* The format of the MCS buffer is opaque to the driver; all that matters
1650 * is that we get its size and pitch right. We'll pretend that the format
1651 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1652 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1653 * the block width and then a further factor of 4. Since an MCS tile
1654 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1655 * we'll need to scale the height down by the block height and then a
1656 * further factor of 8.
1658 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1659 unsigned block_width_px
;
1660 unsigned block_height
;
1661 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1662 unsigned width_divisor
= block_width_px
* 4;
1663 unsigned height_divisor
= block_height
* 8;
1665 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1667 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1668 * in the main surface. In Skylake, it's two bits. The extra bit
1669 * doubles the MCS height, not width, because in Skylake the MCS is always
1673 height_divisor
/= 2;
1675 unsigned mcs_width
=
1676 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1677 unsigned mcs_height
=
1678 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1679 assert(mt
->logical_depth0
== 1);
1681 uint32_t layout_flags
=
1682 (brw
->gen
>= 8) ? MIPTREE_LAYOUT_FORCE_HALIGN16
: 0;
1683 /* In case of compression mcs buffer needs to be initialised requiring the
1684 * buffer to be immediately mapped to cpu space for writing. Therefore do
1685 * not use the gpu access flag which can cause an unnecessary delay if the
1686 * backing pages happened to be just used by the GPU.
1688 if (!is_lossless_compressed
)
1689 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1691 mt
->mcs_buf
= intel_mcs_miptree_buf_create(brw
, mt
,
1699 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1700 * used for lossless compression which requires similar initialisation
1701 * as multi-sample compression.
1703 if (is_lossless_compressed
) {
1704 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1705 * resolve. Initialize it accordingly in case the first renderer is
1706 * cpu (or other none compression aware party).
1708 * This is also explicitly stated in the spec (MCS Buffer for Render
1710 * "If Software wants to enable Color Compression without Fast clear,
1711 * Software needs to initialize MCS with zeros."
1713 intel_miptree_init_mcs(brw
, mt
, 0);
1714 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1715 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1722 * Helper for intel_miptree_alloc_hiz() that sets
1723 * \c mt->level[level].has_hiz. Return true if and only if
1724 * \c has_hiz was set.
1727 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1728 struct intel_mipmap_tree
*mt
,
1731 assert(mt
->hiz_buf
);
1733 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1734 uint32_t width
= minify(mt
->physical_width0
, level
);
1735 uint32_t height
= minify(mt
->physical_height0
, level
);
1737 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1738 * and the height is 4 aligned. This allows our HiZ support
1739 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1740 * we can grow the width & height to allow the HiZ op to
1741 * force the proper size alignments.
1743 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1744 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1749 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1750 mt
->level
[level
].has_hiz
= true;
1756 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1757 * buffer dimensions and allocates a bo for the hiz buffer.
1759 static struct intel_miptree_hiz_buffer
*
1760 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1761 struct intel_mipmap_tree
*mt
)
1763 unsigned z_width
= mt
->logical_width0
;
1764 unsigned z_height
= mt
->logical_height0
;
1765 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1766 unsigned hz_width
, hz_height
;
1767 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1772 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1773 * adjustments required for Z_Height and Z_Width based on multisampling.
1775 switch (mt
->num_samples
) {
1789 unreachable("unsupported sample count");
1792 const unsigned vertical_align
= 8; /* 'j' in the docs */
1793 const unsigned H0
= z_height
;
1794 const unsigned h0
= ALIGN(H0
, vertical_align
);
1795 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1796 const unsigned Z0
= z_depth
;
1798 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1799 hz_width
= ALIGN(z_width
, 16);
1801 if (mt
->target
== GL_TEXTURE_3D
) {
1805 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1806 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1807 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1808 hz_height
+= h_i
* Z_i
;
1809 H_i
= minify(H_i
, 1);
1810 Z_i
= minify(Z_i
, 1);
1813 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1815 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1817 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1818 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1819 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1822 unsigned long pitch
;
1823 uint32_t tiling
= I915_TILING_Y
;
1824 buf
->aux_base
.bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1825 hz_width
, hz_height
, 1,
1827 BO_ALLOC_FOR_RENDER
);
1828 if (!buf
->aux_base
.bo
) {
1831 } else if (tiling
!= I915_TILING_Y
) {
1832 drm_intel_bo_unreference(buf
->aux_base
.bo
);
1837 buf
->aux_base
.size
= hz_width
* hz_height
;
1838 buf
->aux_base
.pitch
= pitch
;
1845 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1846 * buffer dimensions and allocates a bo for the hiz buffer.
1848 static struct intel_miptree_hiz_buffer
*
1849 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1850 struct intel_mipmap_tree
*mt
)
1852 unsigned z_width
= mt
->logical_width0
;
1853 unsigned z_height
= mt
->logical_height0
;
1854 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1855 unsigned hz_width
, hz_height
;
1856 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1861 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1862 * adjustments required for Z_Height and Z_Width based on multisampling.
1865 switch (mt
->num_samples
) {
1879 unreachable("unsupported sample count");
1883 const unsigned vertical_align
= 8; /* 'j' in the docs */
1884 const unsigned H0
= z_height
;
1885 const unsigned h0
= ALIGN(H0
, vertical_align
);
1886 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1887 const unsigned Z0
= z_depth
;
1889 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1890 hz_width
= ALIGN(z_width
, 16);
1894 unsigned sum_h_i
= 0;
1895 unsigned hz_height_3d_sum
= 0;
1896 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1897 unsigned i
= level
- mt
->first_level
;
1898 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1899 /* sum(i=2 to m; h_i) */
1903 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1904 hz_height_3d_sum
+= h_i
* Z_i
;
1905 H_i
= minify(H_i
, 1);
1906 Z_i
= minify(Z_i
, 1);
1908 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1909 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1911 if (mt
->target
== GL_TEXTURE_3D
) {
1912 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1913 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1915 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1916 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1919 unsigned long pitch
;
1920 uint32_t tiling
= I915_TILING_Y
;
1921 buf
->aux_base
.bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1922 hz_width
, hz_height
, 1,
1924 BO_ALLOC_FOR_RENDER
);
1925 if (!buf
->aux_base
.bo
) {
1928 } else if (tiling
!= I915_TILING_Y
) {
1929 drm_intel_bo_unreference(buf
->aux_base
.bo
);
1934 buf
->aux_base
.size
= hz_width
* hz_height
;
1935 buf
->aux_base
.pitch
= pitch
;
1941 static struct intel_miptree_hiz_buffer
*
1942 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1943 struct intel_mipmap_tree
*mt
)
1945 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1946 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1949 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1954 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1955 buf
->mt
= intel_miptree_create(brw
,
1961 mt
->logical_height0
,
1970 buf
->aux_base
.bo
= buf
->mt
->bo
;
1971 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1972 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1973 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
;
1979 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1980 struct intel_mipmap_tree
*mt
)
1985 if (mt
->hiz_buf
!= NULL
)
1988 if (mt
->disable_aux_buffers
)
1991 switch (mt
->format
) {
1992 case MESA_FORMAT_Z_FLOAT32
:
1993 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1994 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1995 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1996 case MESA_FORMAT_Z_UNORM16
:
2004 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2005 struct intel_mipmap_tree
*mt
)
2007 assert(mt
->hiz_buf
== NULL
);
2008 assert(!mt
->disable_aux_buffers
);
2010 if (brw
->gen
== 7) {
2011 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
2012 } else if (brw
->gen
>= 8) {
2013 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
2015 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
2021 /* Mark that all slices need a HiZ resolve. */
2022 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2023 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
2026 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
2027 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
2028 exec_node_init(&m
->link
);
2031 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2033 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
2041 * Can the miptree sample using the hiz buffer?
2044 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2045 struct intel_mipmap_tree
*mt
)
2047 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2048 * so keep things conservative for now and never enable it unless we're SKL+.
2058 /* It seems the hardware won't fallback to the depth buffer if some of the
2059 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2060 * of the texture to be HiZ enabled.
2062 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2063 if (!intel_miptree_level_has_hiz(mt
, level
))
2067 /* If compressed multisampling is enabled, then we use it for the auxiliary
2070 * From the BDW PRM (Volume 2d: Command Reference: Structures
2071 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2073 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2074 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2076 * There is no such blurb for 1D textures, but there is sufficient evidence
2077 * that this is broken on SKL+.
2079 return (mt
->num_samples
<= 1 &&
2080 mt
->target
!= GL_TEXTURE_3D
&&
2081 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2085 * Does the miptree slice have hiz enabled?
2088 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2090 intel_miptree_check_level_layer(mt
, level
, 0);
2091 return mt
->level
[level
].has_hiz
;
2095 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2099 if (!intel_miptree_level_has_hiz(mt
, level
))
2102 intel_resolve_map_set(&mt
->hiz_map
,
2103 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2108 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2112 if (!intel_miptree_level_has_hiz(mt
, level
))
2115 intel_resolve_map_set(&mt
->hiz_map
,
2116 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2120 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2124 uint32_t end_layer
= mt
->level
[level
].depth
;
2126 for (layer
= 0; layer
< end_layer
; layer
++) {
2127 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2132 intel_miptree_slice_resolve(struct brw_context
*brw
,
2133 struct intel_mipmap_tree
*mt
,
2136 enum blorp_hiz_op need
)
2138 intel_miptree_check_level_layer(mt
, level
, layer
);
2140 struct intel_resolve_map
*item
=
2141 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2143 if (!item
|| item
->need
!= need
)
2146 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2147 intel_resolve_map_remove(item
);
2152 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2153 struct intel_mipmap_tree
*mt
,
2157 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2158 BLORP_HIZ_OP_HIZ_RESOLVE
);
2162 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2163 struct intel_mipmap_tree
*mt
,
2167 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2168 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2172 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2173 struct intel_mipmap_tree
*mt
,
2174 enum blorp_hiz_op need
)
2176 bool did_resolve
= false;
2178 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2179 if (map
->need
!= need
)
2182 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2183 intel_resolve_map_remove(map
);
2191 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2192 struct intel_mipmap_tree
*mt
)
2194 return intel_miptree_all_slices_resolve(brw
, mt
,
2195 BLORP_HIZ_OP_HIZ_RESOLVE
);
2199 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2200 struct intel_mipmap_tree
*mt
)
2202 return intel_miptree_all_slices_resolve(brw
, mt
,
2203 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2207 intel_miptree_check_color_resolve(const struct intel_mipmap_tree
*mt
,
2208 unsigned level
, unsigned layer
)
2213 /* Fast color clear is not supported for mipmapped surfaces. */
2214 assert(level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0);
2216 /* Compression of arrayed msaa surfaces is supported. */
2217 if (mt
->num_samples
> 1)
2220 /* Fast color clear is not supported for non-msaa arrays. */
2221 assert(layer
== 0 && mt
->logical_depth0
== 1);
2228 intel_miptree_resolve_color(struct brw_context
*brw
,
2229 struct intel_mipmap_tree
*mt
, unsigned level
,
2230 unsigned start_layer
, unsigned num_layers
,
2233 intel_miptree_check_color_resolve(mt
, level
, start_layer
);
2235 /* From gen9 onwards there is new compression scheme for single sampled
2236 * surfaces called "lossless compressed". These don't need to be always
2239 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2240 intel_miptree_is_lossless_compressed(brw
, mt
))
2243 switch (mt
->fast_clear_state
) {
2244 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2245 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2246 /* No resolve needed */
2248 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2249 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2250 /* For now arrayed fast clear is not supported. */
2251 assert(num_layers
== 1);
2253 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2254 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2255 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2256 brw_blorp_resolve_color(brw
, mt
, level
, start_layer
);
2262 unreachable("Invalid fast clear state");
2267 intel_miptree_all_slices_resolve_color(struct brw_context
*brw
,
2268 struct intel_mipmap_tree
*mt
,
2271 intel_miptree_resolve_color(brw
, mt
, 0, 0, 1, flags
);
2275 * Make it possible to share the BO backing the given miptree with another
2276 * process or another miptree.
2278 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2279 * then discard the MCS buffer, if present. We also set the fast_clear_state
2280 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2281 * allocated in the future.
2284 intel_miptree_make_shareable(struct brw_context
*brw
,
2285 struct intel_mipmap_tree
*mt
)
2287 /* MCS buffers are also used for multisample buffers, but we can't resolve
2288 * away a multisample MCS buffer because it's an integral part of how the
2289 * pixel data is stored. Fortunately this code path should never be
2290 * reached for multisample buffers.
2292 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2295 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2296 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2302 * \brief Get pointer offset into stencil buffer.
2304 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2305 * must decode the tile's layout in software.
2308 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2310 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2312 * Even though the returned offset is always positive, the return type is
2314 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2315 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2318 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2320 uint32_t tile_size
= 4096;
2321 uint32_t tile_width
= 64;
2322 uint32_t tile_height
= 64;
2323 uint32_t row_size
= 64 * stride
;
2325 uint32_t tile_x
= x
/ tile_width
;
2326 uint32_t tile_y
= y
/ tile_height
;
2328 /* The byte's address relative to the tile's base addres. */
2329 uint32_t byte_x
= x
% tile_width
;
2330 uint32_t byte_y
= y
% tile_height
;
2332 uintptr_t u
= tile_y
* row_size
2333 + tile_x
* tile_size
2334 + 512 * (byte_x
/ 8)
2336 + 32 * ((byte_y
/ 4) % 2)
2337 + 16 * ((byte_x
/ 4) % 2)
2338 + 8 * ((byte_y
/ 2) % 2)
2339 + 4 * ((byte_x
/ 2) % 2)
2344 /* adjust for bit6 swizzling */
2345 if (((byte_x
/ 8) % 2) == 1) {
2346 if (((byte_y
/ 8) % 2) == 0) {
2358 intel_miptree_updownsample(struct brw_context
*brw
,
2359 struct intel_mipmap_tree
*src
,
2360 struct intel_mipmap_tree
*dst
)
2362 brw_blorp_blit_miptrees(brw
,
2363 src
, 0 /* level */, 0 /* layer */,
2364 src
->format
, SWIZZLE_XYZW
,
2365 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2367 src
->logical_width0
, src
->logical_height0
,
2369 dst
->logical_width0
, dst
->logical_height0
,
2370 GL_NEAREST
, false, false /*mirror x, y*/,
2373 if (src
->stencil_mt
) {
2374 brw_blorp_blit_miptrees(brw
,
2375 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2376 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2377 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2378 dst
->stencil_mt
->format
,
2380 src
->logical_width0
, src
->logical_height0
,
2382 dst
->logical_width0
, dst
->logical_height0
,
2383 GL_NEAREST
, false, false /*mirror x, y*/,
2384 false, false /* decode/encode srgb */);
2389 intel_update_r8stencil(struct brw_context
*brw
,
2390 struct intel_mipmap_tree
*mt
)
2392 assert(brw
->gen
>= 7);
2393 struct intel_mipmap_tree
*src
=
2394 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2395 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2398 if (!mt
->r8stencil_mt
) {
2399 const uint32_t r8stencil_flags
=
2400 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2401 MIPTREE_LAYOUT_DISABLE_AUX
;
2402 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2403 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2405 MESA_FORMAT_R_UINT8
,
2408 src
->logical_width0
,
2409 src
->logical_height0
,
2410 src
->logical_depth0
,
2413 assert(mt
->r8stencil_mt
);
2416 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2418 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2419 const unsigned depth
= src
->level
[level
].depth
;
2420 const int layers_per_blit
=
2421 (dst
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
2422 dst
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
2423 dst
->num_samples
: 1;
2425 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2426 brw_blorp_blit_miptrees(brw
,
2428 src
->format
, SWIZZLE_X
,
2429 dst
, level
, layers_per_blit
* layer
,
2430 MESA_FORMAT_R_UNORM8
,
2432 minify(src
->logical_width0
, level
),
2433 minify(src
->logical_height0
, level
),
2435 minify(dst
->logical_width0
, level
),
2436 minify(dst
->logical_height0
, level
),
2437 GL_NEAREST
, false, false /*mirror x, y*/,
2438 false, false /* decode/encode srgb */);
2442 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2443 src
->r8stencil_needs_update
= false;
2447 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2449 /* CPU accesses to color buffers don't understand fast color clears, so
2450 * resolve any pending fast color clears before we map.
2452 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2454 drm_intel_bo
*bo
= mt
->bo
;
2456 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2457 intel_batchbuffer_flush(brw
);
2459 if (mt
->tiling
!= I915_TILING_NONE
)
2460 brw_bo_map_gtt(brw
, bo
, "miptree");
2462 brw_bo_map(brw
, bo
, true, "miptree");
2468 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2470 drm_intel_bo_unmap(mt
->bo
);
2474 intel_miptree_map_gtt(struct brw_context
*brw
,
2475 struct intel_mipmap_tree
*mt
,
2476 struct intel_miptree_map
*map
,
2477 unsigned int level
, unsigned int slice
)
2479 unsigned int bw
, bh
;
2481 unsigned int image_x
, image_y
;
2482 intptr_t x
= map
->x
;
2483 intptr_t y
= map
->y
;
2485 /* For compressed formats, the stride is the number of bytes per
2486 * row of blocks. intel_miptree_get_image_offset() already does
2489 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2490 assert(y
% bh
== 0);
2491 assert(x
% bw
== 0);
2495 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2500 /* Note that in the case of cube maps, the caller must have passed the
2501 * slice number referencing the face.
2503 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2507 map
->stride
= mt
->pitch
;
2508 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2511 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2512 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2513 map
->x
, map
->y
, map
->w
, map
->h
,
2514 mt
, _mesa_get_format_name(mt
->format
),
2515 x
, y
, map
->ptr
, map
->stride
);
2519 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2521 intel_miptree_unmap_raw(mt
);
2525 intel_miptree_map_blit(struct brw_context
*brw
,
2526 struct intel_mipmap_tree
*mt
,
2527 struct intel_miptree_map
*map
,
2528 unsigned int level
, unsigned int slice
)
2530 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2531 /* first_level */ 0,
2535 MIPTREE_LAYOUT_TILING_NONE
);
2537 if (!map
->linear_mt
) {
2538 fprintf(stderr
, "Failed to allocate blit temporary\n");
2541 map
->stride
= map
->linear_mt
->pitch
;
2543 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2544 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2545 * invalidate is set, since we'll be writing the whole rectangle from our
2546 * temporary buffer back out.
2548 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2549 if (!intel_miptree_blit(brw
,
2551 map
->x
, map
->y
, false,
2552 map
->linear_mt
, 0, 0,
2554 map
->w
, map
->h
, GL_COPY
)) {
2555 fprintf(stderr
, "Failed to blit\n");
2560 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2562 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2563 map
->x
, map
->y
, map
->w
, map
->h
,
2564 mt
, _mesa_get_format_name(mt
->format
),
2565 level
, slice
, map
->ptr
, map
->stride
);
2570 intel_miptree_release(&map
->linear_mt
);
2576 intel_miptree_unmap_blit(struct brw_context
*brw
,
2577 struct intel_mipmap_tree
*mt
,
2578 struct intel_miptree_map
*map
,
2582 struct gl_context
*ctx
= &brw
->ctx
;
2584 intel_miptree_unmap_raw(map
->linear_mt
);
2586 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2587 bool ok
= intel_miptree_blit(brw
,
2588 map
->linear_mt
, 0, 0,
2591 map
->x
, map
->y
, false,
2592 map
->w
, map
->h
, GL_COPY
);
2593 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2596 intel_miptree_release(&map
->linear_mt
);
2600 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2602 #if defined(USE_SSE41)
2604 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2605 struct intel_mipmap_tree
*mt
,
2606 struct intel_miptree_map
*map
,
2607 unsigned int level
, unsigned int slice
)
2609 assert(map
->mode
& GL_MAP_READ_BIT
);
2610 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2612 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2613 map
->x
, map
->y
, map
->w
, map
->h
,
2614 mt
, _mesa_get_format_name(mt
->format
),
2615 level
, slice
, map
->ptr
, map
->stride
);
2617 /* Map the original image */
2620 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2624 void *src
= intel_miptree_map_raw(brw
, mt
);
2630 src
+= image_y
* mt
->pitch
;
2631 src
+= image_x
* mt
->cpp
;
2633 /* Due to the pixel offsets for the particular image being mapped, our
2634 * src pointer may not be 16-byte aligned. However, if the pitch is
2635 * divisible by 16, then the amount by which it's misaligned will remain
2636 * consistent from row to row.
2638 assert((mt
->pitch
% 16) == 0);
2639 const int misalignment
= ((uintptr_t) src
) & 15;
2641 /* Create an untiled temporary buffer for the mapping. */
2642 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2644 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2646 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2647 /* Offset the destination so it has the same misalignment as src. */
2648 map
->ptr
= map
->buffer
+ misalignment
;
2650 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2652 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2653 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2654 void *src_ptr
= src
+ y
* mt
->pitch
;
2656 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2659 intel_miptree_unmap_raw(mt
);
2663 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2664 struct intel_mipmap_tree
*mt
,
2665 struct intel_miptree_map
*map
,
2669 _mesa_align_free(map
->buffer
);
2676 intel_miptree_map_s8(struct brw_context
*brw
,
2677 struct intel_mipmap_tree
*mt
,
2678 struct intel_miptree_map
*map
,
2679 unsigned int level
, unsigned int slice
)
2681 map
->stride
= map
->w
;
2682 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2686 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2687 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2688 * invalidate is set, since we'll be writing the whole rectangle from our
2689 * temporary buffer back out.
2691 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2692 uint8_t *untiled_s8_map
= map
->ptr
;
2693 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2694 unsigned int image_x
, image_y
;
2696 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2698 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2699 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2700 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2701 x
+ image_x
+ map
->x
,
2702 y
+ image_y
+ map
->y
,
2703 brw
->has_swizzling
);
2704 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2708 intel_miptree_unmap_raw(mt
);
2710 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2711 map
->x
, map
->y
, map
->w
, map
->h
,
2712 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2714 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2715 map
->x
, map
->y
, map
->w
, map
->h
,
2716 mt
, map
->ptr
, map
->stride
);
2721 intel_miptree_unmap_s8(struct brw_context
*brw
,
2722 struct intel_mipmap_tree
*mt
,
2723 struct intel_miptree_map
*map
,
2727 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2728 unsigned int image_x
, image_y
;
2729 uint8_t *untiled_s8_map
= map
->ptr
;
2730 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2732 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2734 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2735 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2736 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2737 image_x
+ x
+ map
->x
,
2738 image_y
+ y
+ map
->y
,
2739 brw
->has_swizzling
);
2740 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2744 intel_miptree_unmap_raw(mt
);
2751 intel_miptree_map_etc(struct brw_context
*brw
,
2752 struct intel_mipmap_tree
*mt
,
2753 struct intel_miptree_map
*map
,
2757 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2758 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2759 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2762 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2763 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2765 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2766 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2767 map
->w
, map
->h
, 1));
2768 map
->ptr
= map
->buffer
;
2772 intel_miptree_unmap_etc(struct brw_context
*brw
,
2773 struct intel_mipmap_tree
*mt
,
2774 struct intel_miptree_map
*map
,
2780 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2785 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2786 + image_y
* mt
->pitch
2787 + image_x
* mt
->cpp
;
2789 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2790 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2791 map
->ptr
, map
->stride
,
2794 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2795 map
->ptr
, map
->stride
,
2796 map
->w
, map
->h
, mt
->etc_format
);
2798 intel_miptree_unmap_raw(mt
);
2803 * Mapping function for packed depth/stencil miptrees backed by real separate
2804 * miptrees for depth and stencil.
2806 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2807 * separate from the depth buffer. Yet at the GL API level, we have to expose
2808 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2809 * be able to map that memory for texture storage and glReadPixels-type
2810 * operations. We give Mesa core that access by mallocing a temporary and
2811 * copying the data between the actual backing store and the temporary.
2814 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2815 struct intel_mipmap_tree
*mt
,
2816 struct intel_miptree_map
*map
,
2817 unsigned int level
, unsigned int slice
)
2819 struct intel_mipmap_tree
*z_mt
= mt
;
2820 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2821 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2822 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2824 map
->stride
= map
->w
* packed_bpp
;
2825 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2829 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2830 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2831 * invalidate is set, since we'll be writing the whole rectangle from our
2832 * temporary buffer back out.
2834 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2835 uint32_t *packed_map
= map
->ptr
;
2836 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2837 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2838 unsigned int s_image_x
, s_image_y
;
2839 unsigned int z_image_x
, z_image_y
;
2841 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2842 &s_image_x
, &s_image_y
);
2843 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2844 &z_image_x
, &z_image_y
);
2846 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2847 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2848 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2849 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2852 brw
->has_swizzling
);
2853 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2855 (map_x
+ z_image_x
));
2856 uint8_t s
= s_map
[s_offset
];
2857 uint32_t z
= z_map
[z_offset
];
2859 if (map_z32f_x24s8
) {
2860 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2861 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2863 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2868 intel_miptree_unmap_raw(s_mt
);
2869 intel_miptree_unmap_raw(z_mt
);
2871 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2873 map
->x
, map
->y
, map
->w
, map
->h
,
2874 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2875 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2876 map
->ptr
, map
->stride
);
2878 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2879 map
->x
, map
->y
, map
->w
, map
->h
,
2880 mt
, map
->ptr
, map
->stride
);
2885 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2886 struct intel_mipmap_tree
*mt
,
2887 struct intel_miptree_map
*map
,
2891 struct intel_mipmap_tree
*z_mt
= mt
;
2892 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2893 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2895 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2896 uint32_t *packed_map
= map
->ptr
;
2897 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2898 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2899 unsigned int s_image_x
, s_image_y
;
2900 unsigned int z_image_x
, z_image_y
;
2902 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2903 &s_image_x
, &s_image_y
);
2904 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2905 &z_image_x
, &z_image_y
);
2907 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2908 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2909 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2910 x
+ s_image_x
+ map
->x
,
2911 y
+ s_image_y
+ map
->y
,
2912 brw
->has_swizzling
);
2913 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2915 (x
+ z_image_x
+ map
->x
));
2917 if (map_z32f_x24s8
) {
2918 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2919 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2921 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2922 s_map
[s_offset
] = packed
>> 24;
2923 z_map
[z_offset
] = packed
;
2928 intel_miptree_unmap_raw(s_mt
);
2929 intel_miptree_unmap_raw(z_mt
);
2931 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2933 map
->x
, map
->y
, map
->w
, map
->h
,
2934 z_mt
, _mesa_get_format_name(z_mt
->format
),
2935 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2936 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2937 map
->ptr
, map
->stride
);
2944 * Create and attach a map to the miptree at (level, slice). Return the
2947 static struct intel_miptree_map
*
2948 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2957 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2962 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2963 mt
->level
[level
].slice
[slice
].map
= map
;
2975 * Release the map at (level, slice).
2978 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2982 struct intel_miptree_map
**map
;
2984 map
= &mt
->level
[level
].slice
[slice
].map
;
2990 can_blit_slice(struct intel_mipmap_tree
*mt
,
2991 unsigned int level
, unsigned int slice
)
2993 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2994 if (mt
->pitch
>= 32768)
3001 use_intel_mipree_map_blit(struct brw_context
*brw
,
3002 struct intel_mipmap_tree
*mt
,
3008 /* It's probably not worth swapping to the blit ring because of
3009 * all the overhead involved. But, we must use blitter for the
3010 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
3012 (!(mode
& GL_MAP_WRITE_BIT
) ||
3013 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
3015 (mt
->tiling
== I915_TILING_X
||
3016 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3017 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3018 /* Fast copy blit on skl+ supports all tiling formats. */
3020 can_blit_slice(mt
, level
, slice
))
3023 if (mt
->tiling
!= I915_TILING_NONE
&&
3024 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3025 assert(can_blit_slice(mt
, level
, slice
));
3033 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3034 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3035 * arithmetic overflow.
3037 * If you call this function and use \a out_stride, then you're doing pointer
3038 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3039 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3040 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3041 * which usually have type uint32_t or GLuint.
3044 intel_miptree_map(struct brw_context
*brw
,
3045 struct intel_mipmap_tree
*mt
,
3054 ptrdiff_t *out_stride
)
3056 struct intel_miptree_map
*map
;
3058 assert(mt
->num_samples
<= 1);
3060 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3067 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
3068 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3069 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
3072 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3073 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3074 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3075 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3076 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3077 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3078 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3079 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3080 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3081 #if defined(USE_SSE41)
3082 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3083 !mt
->compressed
&& cpu_has_sse4_1
&&
3084 (mt
->pitch
% 16 == 0)) {
3085 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3088 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
3089 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
3090 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3093 *out_ptr
= map
->ptr
;
3094 *out_stride
= map
->stride
;
3096 if (map
->ptr
== NULL
)
3097 intel_miptree_release_map(mt
, level
, slice
);
3101 intel_miptree_unmap(struct brw_context
*brw
,
3102 struct intel_mipmap_tree
*mt
,
3106 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3108 assert(mt
->num_samples
<= 1);
3113 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3114 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3116 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3117 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3118 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3119 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3120 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3121 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3122 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3123 } else if (map
->linear_mt
) {
3124 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3125 #if defined(USE_SSE41)
3126 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3127 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3130 intel_miptree_unmap_gtt(mt
);
3133 intel_miptree_release_map(mt
, level
, slice
);
3137 get_isl_surf_dim(GLenum target
)
3141 case GL_TEXTURE_1D_ARRAY
:
3142 return ISL_SURF_DIM_1D
;
3145 case GL_TEXTURE_2D_ARRAY
:
3146 case GL_TEXTURE_RECTANGLE
:
3147 case GL_TEXTURE_CUBE_MAP
:
3148 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3149 case GL_TEXTURE_2D_MULTISAMPLE
:
3150 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3151 case GL_TEXTURE_EXTERNAL_OES
:
3152 return ISL_SURF_DIM_2D
;
3155 return ISL_SURF_DIM_3D
;
3158 unreachable("Invalid texture target");
3162 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3167 case GL_TEXTURE_1D_ARRAY
:
3168 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3169 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3172 case GL_TEXTURE_2D_ARRAY
:
3173 case GL_TEXTURE_RECTANGLE
:
3174 case GL_TEXTURE_2D_MULTISAMPLE
:
3175 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3176 case GL_TEXTURE_EXTERNAL_OES
:
3177 return ISL_DIM_LAYOUT_GEN4_2D
;
3179 case GL_TEXTURE_CUBE_MAP
:
3180 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3181 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3182 ISL_DIM_LAYOUT_GEN4_2D
);
3185 return (devinfo
->gen
>= 9 ?
3186 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3189 unreachable("Invalid texture target");
3193 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3195 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3196 return ISL_TILING_W
;
3198 switch (mt
->tiling
) {
3199 case I915_TILING_NONE
:
3200 return ISL_TILING_LINEAR
;
3202 return ISL_TILING_X
;
3204 switch (mt
->tr_mode
) {
3205 case INTEL_MIPTREE_TRMODE_NONE
:
3206 return ISL_TILING_Y0
;
3207 case INTEL_MIPTREE_TRMODE_YF
:
3208 return ISL_TILING_Yf
;
3209 case INTEL_MIPTREE_TRMODE_YS
:
3210 return ISL_TILING_Ys
;
3212 unreachable("Invalid tiled resource mode");
3215 unreachable("Invalid tiling mode");
3221 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3222 const struct intel_mipmap_tree
*mt
,
3223 struct isl_surf
*surf
)
3225 surf
->dim
= get_isl_surf_dim(mt
->target
);
3226 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3227 mt
->tiling
, mt
->target
);
3229 if (mt
->num_samples
> 1) {
3230 switch (mt
->msaa_layout
) {
3231 case INTEL_MSAA_LAYOUT_IMS
:
3232 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3234 case INTEL_MSAA_LAYOUT_UMS
:
3235 case INTEL_MSAA_LAYOUT_CMS
:
3236 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3239 unreachable("Invalid MSAA layout");
3242 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3245 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3247 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3248 /* The ISL definition of row_pitch matches the surface state pitch field
3249 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3250 * the factor of 2 for W-tiling in row_pitch.
3252 surf
->row_pitch
= 2 * mt
->pitch
;
3254 surf
->row_pitch
= mt
->pitch
;
3257 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3259 if (brw
->gen
>= 9) {
3260 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3261 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3262 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3264 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3265 * alignment in terms of surface elements like we want.
3267 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3270 /* On earlier gens it's stored in pixels. */
3272 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3273 surf
->image_alignment_el
=
3274 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3277 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3278 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3279 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3280 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3281 surf
->logical_level0_px
.array_len
= 1;
3283 surf
->logical_level0_px
.depth
= 1;
3284 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3287 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3288 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3289 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3290 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3291 surf
->phys_level0_sa
.array_len
= 1;
3293 surf
->phys_level0_sa
.depth
= 1;
3294 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3297 surf
->levels
= mt
->last_level
+ 1;
3298 surf
->samples
= MAX2(mt
->num_samples
, 1);
3300 surf
->size
= 0; /* TODO */
3301 surf
->alignment
= 0; /* TODO */
3303 switch (surf
->dim_layout
) {
3304 case ISL_DIM_LAYOUT_GEN4_2D
:
3305 case ISL_DIM_LAYOUT_GEN4_3D
:
3306 if (brw
->gen
>= 9) {
3307 surf
->array_pitch_el_rows
= mt
->qpitch
;
3310 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3311 assert(mt
->qpitch
% bh
== 0);
3312 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3315 case ISL_DIM_LAYOUT_GEN9_1D
:
3316 surf
->array_pitch_el_rows
= 1;
3320 switch (mt
->array_layout
) {
3321 case ALL_LOD_IN_EACH_SLICE
:
3322 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3324 case ALL_SLICES_AT_EACH_LOD
:
3325 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3328 unreachable("Invalid array layout");
3331 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3332 switch (base_format
) {
3333 case GL_DEPTH_COMPONENT
:
3334 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3336 case GL_STENCIL_INDEX
:
3337 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3339 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3341 case GL_DEPTH_STENCIL
:
3342 /* In this case we only texture from the depth part */
3343 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3344 ISL_SURF_USAGE_TEXTURE_BIT
;
3347 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3348 if (brw
->format_supported_as_render_target
[mt
->format
])
3349 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3353 if (_mesa_is_cube_map_texture(mt
->target
))
3354 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3357 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3358 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3359 * PASS IT INTO isl_surf_fill_state.
3362 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3363 const struct intel_mipmap_tree
*mt
,
3364 struct isl_surf
*surf
,
3365 enum isl_aux_usage
*usage
)
3367 uint32_t aux_pitch
, aux_qpitch
;
3369 aux_pitch
= mt
->mcs_buf
->pitch
;
3370 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3372 if (mt
->num_samples
> 1) {
3373 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3374 *usage
= ISL_AUX_USAGE_MCS
;
3375 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3376 assert(brw
->gen
>= 9);
3377 *usage
= ISL_AUX_USAGE_CCS_E
;
3378 } else if (mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_NO_MCS
) {
3379 *usage
= ISL_AUX_USAGE_CCS_D
;
3381 unreachable("Invalid MCS miptree");
3383 } else if (mt
->hiz_buf
) {
3384 if (mt
->hiz_buf
->mt
) {
3385 aux_pitch
= mt
->hiz_buf
->mt
->pitch
;
3386 aux_qpitch
= mt
->hiz_buf
->mt
->qpitch
;
3388 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3389 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3392 *usage
= ISL_AUX_USAGE_HIZ
;
3394 *usage
= ISL_AUX_USAGE_NONE
;
3398 /* Start with a copy of the original surface. */
3399 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3401 /* Figure out the format and tiling of the auxiliary surface */
3403 case ISL_AUX_USAGE_NONE
:
3404 unreachable("Invalid auxiliary usage");
3406 case ISL_AUX_USAGE_HIZ
:
3407 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3410 case ISL_AUX_USAGE_MCS
:
3413 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3414 * HALIGN 16 must be used."
3417 assert(mt
->halign
== 16);
3419 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3422 case ISL_AUX_USAGE_CCS_D
:
3423 case ISL_AUX_USAGE_CCS_E
:
3425 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3427 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3429 * From the hardware spec for GEN9:
3431 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3432 * HALIGN 16 must be used."
3434 assert(mt
->num_samples
<= 1);
3436 assert(mt
->halign
== 16);
3438 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3442 /* We want the pitch of the actual aux buffer. */
3443 surf
->row_pitch
= aux_pitch
;
3445 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3446 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3447 * in elements of the primary color surface so we have to divide by the
3448 * compression block height.
3450 surf
->array_pitch_el_rows
=
3451 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3454 union isl_color_value
3455 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3456 const struct intel_mipmap_tree
*mt
)
3458 union isl_color_value clear_color
;
3460 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3461 clear_color
.i32
[0] = mt
->depth_clear_value
;
3462 clear_color
.i32
[1] = 0;
3463 clear_color
.i32
[2] = 0;
3464 clear_color
.i32
[3] = 0;
3465 } else if (brw
->gen
>= 9) {
3466 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3467 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3468 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3469 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3470 } else if (_mesa_is_format_integer(mt
->format
)) {
3471 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3472 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3473 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3474 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3476 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3477 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3478 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3479 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;