2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
77 switch (_mesa_get_format_base_format(mt
->format
)) {
78 case GL_DEPTH_COMPONENT
:
79 case GL_STENCIL_INDEX
:
80 case GL_DEPTH_STENCIL
:
83 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
85 * This field must be set to 0 for all SINT MSRTs when all RT channels
88 * In practice this means that we have to disable MCS for all signed
89 * integer MSAA buffers. The alternative, to disable MCS only when one
90 * of the render target channels is disabled, is impractical because it
91 * would require converting between CMS and UMS MSAA layouts on the fly,
94 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
103 intel_tiling_supports_ccs(const struct brw_context
*brw
,
104 enum isl_tiling tiling
)
106 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
115 if (devinfo
->gen
>= 9)
116 return tiling
== ISL_TILING_Y0
;
117 else if (devinfo
->gen
>= 7)
118 return tiling
!= ISL_TILING_LINEAR
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
150 /* MCS support does not exist prior to Gen7 */
151 if (devinfo
->gen
< 7)
154 /* This function applies only to non-multisampled render targets. */
155 if (mt
->surf
.samples
> 1)
158 /* MCS is only supported for color buffers */
159 switch (_mesa_get_format_base_format(mt
->format
)) {
160 case GL_DEPTH_COMPONENT
:
161 case GL_DEPTH_STENCIL
:
162 case GL_STENCIL_INDEX
:
166 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
169 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
170 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
171 mt
->surf
.logical_level0_px
.depth
> 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->surf
.samples
== 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->mesa_format_supports_render
[mt
->format
])
214 intel_tiling_supports_hiz(const struct brw_context
*brw
,
215 enum isl_tiling tiling
)
217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
219 if (devinfo
->gen
< 6)
222 return tiling
== ISL_TILING_Y0
;
226 intel_miptree_supports_hiz(const struct brw_context
*brw
,
227 const struct intel_mipmap_tree
*mt
)
232 switch (mt
->format
) {
233 case MESA_FORMAT_Z_FLOAT32
:
234 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
235 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 case MESA_FORMAT_Z_UNORM16
:
245 * Return true if the format that will be used to access the miptree is
246 * CCS_E-compatible with the miptree's linear/non-sRGB format.
248 * Why use the linear format? Well, although the miptree may be specified with
249 * an sRGB format, the usage of that color space/format can be toggled. Since
250 * our HW tends to support more linear formats than sRGB ones, we use this
251 * format variant for check for CCS_E compatibility.
254 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
255 const struct intel_mipmap_tree
*mt
,
256 enum isl_format access_format
)
258 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
260 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
261 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
262 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
266 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
267 const struct intel_mipmap_tree
*mt
)
269 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
271 if (devinfo
->gen
< 9)
274 /* For now compression is only enabled for integer formats even though
275 * there exist supported floating point formats also. This is a heuristic
276 * decision based on current public benchmarks. In none of the cases these
277 * formats provided any improvement but a few cases were seen to regress.
278 * Hence these are left to to be enabled in the future when they are known
281 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
284 if (!intel_miptree_supports_ccs(brw
, mt
))
287 /* Many window system buffers are sRGB even if they are never rendered as
288 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
289 * surface is used as sRGB, we fall back to CCS_D.
291 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
292 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
293 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
297 * Determine depth format corresponding to a depth+stencil format,
298 * for separate stencil.
301 intel_depth_format_for_depthstencil_format(mesa_format format
) {
303 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
304 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
305 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
306 return MESA_FORMAT_Z_FLOAT32
;
313 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
314 unsigned depth0
, struct intel_mipmap_level
*table
)
316 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
318 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
320 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
321 if (!table
[level
].slice
)
328 for (unsigned level
= first_level
; level
<= last_level
; level
++)
329 free(table
[level
].slice
);
335 needs_separate_stencil(const struct brw_context
*brw
,
336 struct intel_mipmap_tree
*mt
,
339 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
341 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
344 if (devinfo
->must_use_separate_stencil
)
347 return brw
->has_separate_stencil
&&
348 intel_miptree_supports_hiz(brw
, mt
);
352 * Choose the aux usage for this miptree. This function must be called fairly
353 * late in the miptree create process after we have a tiling.
356 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
357 struct intel_mipmap_tree
*mt
)
359 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
361 if (intel_miptree_supports_mcs(brw
, mt
)) {
362 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
363 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
364 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
365 intel_miptree_supports_ccs(brw
, mt
)) {
366 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
367 intel_miptree_supports_ccs_e(brw
, mt
)) {
368 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
370 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
372 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
373 intel_miptree_supports_hiz(brw
, mt
)) {
374 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
377 /* We can do fast-clear on all auxiliary surface types that are
378 * allocated through the normal texture creation paths.
380 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
381 mt
->supports_fast_clear
= true;
386 * Choose an appropriate uncompressed format for a requested
387 * compressed format, if unsupported.
390 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
392 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
394 /* No need to lower ETC formats on these platforms,
395 * they are supported natively.
397 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
401 case MESA_FORMAT_ETC1_RGB8
:
402 return MESA_FORMAT_R8G8B8X8_UNORM
;
403 case MESA_FORMAT_ETC2_RGB8
:
404 return MESA_FORMAT_R8G8B8X8_UNORM
;
405 case MESA_FORMAT_ETC2_SRGB8
:
406 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
407 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
408 return MESA_FORMAT_B8G8R8A8_SRGB
;
409 case MESA_FORMAT_ETC2_RGBA8_EAC
:
410 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
411 return MESA_FORMAT_R8G8B8A8_UNORM
;
412 case MESA_FORMAT_ETC2_R11_EAC
:
413 return MESA_FORMAT_R_UNORM16
;
414 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
415 return MESA_FORMAT_R_SNORM16
;
416 case MESA_FORMAT_ETC2_RG11_EAC
:
417 return MESA_FORMAT_R16G16_UNORM
;
418 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
419 return MESA_FORMAT_R16G16_SNORM
;
421 /* Non ETC1 / ETC2 format */
427 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
429 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
430 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
432 return mt
->surf
.logical_level0_px
.array_len
;
435 UNUSED
static unsigned
436 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
438 /* In case of physical dimensions one needs to consider also the layout.
439 * See isl_calc_phys_level0_extent_sa().
441 if (surf
->dim
!= ISL_SURF_DIM_3D
)
442 return surf
->phys_level0_sa
.array_len
;
444 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
445 return minify(surf
->phys_level0_sa
.array_len
, level
);
447 return minify(surf
->phys_level0_sa
.depth
, level
);
450 /** \brief Assert that the level and layer are valid for the miptree. */
452 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
460 assert(level
>= mt
->first_level
);
461 assert(level
<= mt
->last_level
);
462 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
465 static enum isl_aux_state
**
466 create_aux_state_map(struct intel_mipmap_tree
*mt
,
467 enum isl_aux_state initial
)
469 const uint32_t levels
= mt
->last_level
+ 1;
471 uint32_t total_slices
= 0;
472 for (uint32_t level
= 0; level
< levels
; level
++)
473 total_slices
+= brw_get_num_logical_layers(mt
, level
);
475 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
477 /* We're going to allocate a single chunk of data for both the per-level
478 * reference array and the arrays of aux_state. This makes cleanup
479 * significantly easier.
481 const size_t total_size
= per_level_array_size
+
482 total_slices
* sizeof(enum isl_aux_state
);
483 void *data
= malloc(total_size
);
487 enum isl_aux_state
**per_level_arr
= data
;
488 enum isl_aux_state
*s
= data
+ per_level_array_size
;
489 for (uint32_t level
= 0; level
< levels
; level
++) {
490 per_level_arr
[level
] = s
;
491 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
492 for (uint32_t a
= 0; a
< level_layers
; a
++)
495 assert((void *)s
== data
+ total_size
);
497 return per_level_arr
;
501 free_aux_state_map(enum isl_aux_state
**state
)
507 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
508 enum isl_tiling tiling
, unsigned samples
)
513 if (tiling
== ISL_TILING_LINEAR
)
516 /* If the width is much smaller than a tile, don't bother tiling. */
520 if (ALIGN(row_pitch
, 512) >= 32768) {
521 perf_debug("row pitch %u too large to blit, falling back to untiled",
530 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
531 enum isl_tiling tiling
)
533 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
535 /* If the BO is too large to fit in the aperture, we need to use the
536 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
537 * handle Y-tiling, so we need to fall back to X.
539 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
540 tiling
== ISL_TILING_Y0
)
546 static struct intel_mipmap_tree
*
547 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
548 unsigned first_level
, unsigned last_level
,
549 unsigned width0
, unsigned height0
, unsigned depth0
,
550 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
551 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
552 unsigned row_pitch
, struct brw_bo
*bo
)
554 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
558 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
566 if (target
== GL_TEXTURE_CUBE_MAP
||
567 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
568 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
570 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
572 _mesa_enum_to_string(target
),
573 _mesa_get_format_name(format
),
574 num_samples
, width0
, height0
, depth0
,
575 first_level
, last_level
, mt
);
577 struct isl_surf_init_info init_info
= {
578 .dim
= get_isl_surf_dim(target
),
579 .format
= translate_tex_format(brw
, format
, false),
582 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
583 .levels
= last_level
- first_level
+ 1,
584 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
585 .samples
= num_samples
,
586 .row_pitch
= row_pitch
,
587 .usage
= isl_usage_flags
,
588 .tiling_flags
= tiling_flags
,
591 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
594 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
595 * on gen7 platforms we also need to create Y-tiled copies of stencil for
596 * texturing since the hardware can't sample from W-tiled surfaces. For
597 * everything else, check for corner cases needing special treatment.
599 bool is_depth_stencil
=
600 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
601 if (!is_depth_stencil
) {
602 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
603 mt
->surf
.tiling
, mt
->surf
.samples
)) {
604 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
605 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
607 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
608 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
609 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
614 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
615 * the size may not be multiple of row_pitch.
616 * See isl_apply_surface_padding().
618 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
619 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
622 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
624 isl_tiling_to_i915_tiling(
626 mt
->surf
.row_pitch
, alloc_flags
);
633 mt
->first_level
= first_level
;
634 mt
->last_level
= last_level
;
637 mt
->aux_state
= NULL
;
638 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
639 mt
->compressed
= _mesa_is_format_compressed(format
);
640 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
645 intel_miptree_release(&mt
);
650 make_separate_stencil_surface(struct brw_context
*brw
,
651 struct intel_mipmap_tree
*mt
)
653 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
654 0, mt
->surf
.levels
- 1,
655 mt
->surf
.logical_level0_px
.width
,
656 mt
->surf
.logical_level0_px
.height
,
657 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
658 mt
->surf
.logical_level0_px
.depth
:
659 mt
->surf
.logical_level0_px
.array_len
,
660 mt
->surf
.samples
, ISL_TILING_W_BIT
,
661 ISL_SURF_USAGE_STENCIL_BIT
|
662 ISL_SURF_USAGE_TEXTURE_BIT
,
663 BO_ALLOC_BUSY
, 0, NULL
);
668 mt
->stencil_mt
->r8stencil_needs_update
= true;
673 static struct intel_mipmap_tree
*
674 miptree_create(struct brw_context
*brw
,
683 enum intel_miptree_create_flags flags
)
685 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
687 if (format
== MESA_FORMAT_S_UINT8
)
688 return make_surface(brw
, target
, format
, first_level
, last_level
,
689 width0
, height0
, depth0
, num_samples
,
691 ISL_SURF_USAGE_STENCIL_BIT
|
692 ISL_SURF_USAGE_TEXTURE_BIT
,
697 const GLenum base_format
= _mesa_get_format_base_format(format
);
698 if ((base_format
== GL_DEPTH_COMPONENT
||
699 base_format
== GL_DEPTH_STENCIL
) &&
700 !(flags
& MIPTREE_CREATE_LINEAR
)) {
701 /* Fix up the Z miptree format for how we're splitting out separate
702 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
704 const mesa_format depth_only_format
=
705 intel_depth_format_for_depthstencil_format(format
);
706 struct intel_mipmap_tree
*mt
= make_surface(
707 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
708 first_level
, last_level
,
709 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
710 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
711 BO_ALLOC_BUSY
, 0, NULL
);
713 if (needs_separate_stencil(brw
, mt
, format
) &&
714 !make_separate_stencil_surface(brw
, mt
)) {
715 intel_miptree_release(&mt
);
719 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
720 intel_miptree_choose_aux_usage(brw
, mt
);
725 mesa_format tex_format
= format
;
726 mesa_format etc_format
= MESA_FORMAT_NONE
;
727 uint32_t alloc_flags
= 0;
729 format
= intel_lower_compressed_format(brw
, format
);
731 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
733 if (flags
& MIPTREE_CREATE_BUSY
)
734 alloc_flags
|= BO_ALLOC_BUSY
;
736 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
737 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
739 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
740 if (devinfo
->gen
< 6)
741 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
743 struct intel_mipmap_tree
*mt
= make_surface(
745 first_level
, last_level
,
746 width0
, height0
, depth0
,
747 num_samples
, tiling_flags
,
748 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
749 ISL_SURF_USAGE_TEXTURE_BIT
,
750 alloc_flags
, 0, NULL
);
754 mt
->etc_format
= etc_format
;
756 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
757 intel_miptree_choose_aux_usage(brw
, mt
);
762 struct intel_mipmap_tree
*
763 intel_miptree_create(struct brw_context
*brw
,
772 enum intel_miptree_create_flags flags
)
774 assert(num_samples
> 0);
776 struct intel_mipmap_tree
*mt
= miptree_create(
778 first_level
, last_level
,
779 width0
, height0
, depth0
, num_samples
,
786 if (!intel_miptree_alloc_aux(brw
, mt
)) {
787 intel_miptree_release(&mt
);
794 struct intel_mipmap_tree
*
795 intel_miptree_create_for_bo(struct brw_context
*brw
,
803 enum intel_miptree_create_flags flags
)
805 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
806 struct intel_mipmap_tree
*mt
;
807 uint32_t tiling
, swizzle
;
808 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
809 const GLenum base_format
= _mesa_get_format_base_format(format
);
811 if ((base_format
== GL_DEPTH_COMPONENT
||
812 base_format
== GL_DEPTH_STENCIL
)) {
813 const mesa_format depth_only_format
=
814 intel_depth_format_for_depthstencil_format(format
);
815 mt
= make_surface(brw
, target
,
816 devinfo
->gen
>= 6 ? depth_only_format
: format
,
817 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
818 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
819 BO_ALLOC_BUSY
, pitch
, bo
);
823 brw_bo_reference(bo
);
825 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
826 intel_miptree_choose_aux_usage(brw
, mt
);
829 } else if (format
== MESA_FORMAT_S_UINT8
) {
830 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
831 0, 0, width
, height
, depth
, 1,
833 ISL_SURF_USAGE_STENCIL_BIT
|
834 ISL_SURF_USAGE_TEXTURE_BIT
,
835 BO_ALLOC_BUSY
, pitch
, bo
);
839 assert(bo
->size
>= mt
->surf
.size
);
841 brw_bo_reference(bo
);
845 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
847 /* Nothing will be able to use this miptree with the BO if the offset isn't
850 if (tiling
!= I915_TILING_NONE
)
851 assert(offset
% 4096 == 0);
853 /* miptrees can't handle negative pitch. If you need flipping of images,
854 * that's outside of the scope of the mt.
858 /* The BO already has a tiling format and we shouldn't confuse the lower
859 * layers by making it try to find a tiling format again.
861 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
863 mt
= make_surface(brw
, target
, format
,
864 0, 0, width
, height
, depth
, 1,
865 1lu << isl_tiling_from_i915_tiling(tiling
),
866 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
867 ISL_SURF_USAGE_TEXTURE_BIT
,
872 brw_bo_reference(bo
);
876 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
877 intel_miptree_choose_aux_usage(brw
, mt
);
879 if (!intel_miptree_alloc_aux(brw
, mt
)) {
880 intel_miptree_release(&mt
);
888 static struct intel_mipmap_tree
*
889 miptree_create_for_planar_image(struct brw_context
*brw
,
890 __DRIimage
*image
, GLenum target
)
892 const struct intel_image_format
*f
= image
->planar_format
;
893 struct intel_mipmap_tree
*planar_mt
= NULL
;
895 for (int i
= 0; i
< f
->nplanes
; i
++) {
896 const int index
= f
->planes
[i
].buffer_index
;
897 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
898 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
899 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
900 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
902 /* Disable creation of the texture's aux buffers because the driver
903 * exposes no EGL API to manage them. That is, there is no API for
904 * resolving the aux buffer's content to the main buffer nor for
905 * invalidating the aux buffer's content.
907 struct intel_mipmap_tree
*mt
=
908 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
909 image
->offsets
[index
],
911 image
->strides
[index
],
912 MIPTREE_CREATE_NO_AUX
);
921 planar_mt
->plane
[i
- 1] = mt
;
924 planar_mt
->drm_modifier
= image
->modifier
;
930 create_ccs_buf_for_image(struct brw_context
*brw
,
932 struct intel_mipmap_tree
*mt
,
933 enum isl_aux_state initial_state
)
935 struct isl_surf temp_ccs_surf
;
937 /* CCS is only supported for very simple miptrees */
938 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
939 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
940 assert(mt
->surf
.samples
== 1);
941 assert(mt
->surf
.levels
== 1);
942 assert(mt
->surf
.logical_level0_px
.depth
== 1);
943 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
944 assert(mt
->first_level
== 0);
945 assert(mt
->last_level
== 0);
947 /* We shouldn't already have a CCS */
948 assert(!mt
->mcs_buf
);
950 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
954 assert(image
->aux_offset
< image
->bo
->size
);
955 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
957 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
958 if (mt
->mcs_buf
== NULL
)
961 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
962 if (!mt
->aux_state
) {
968 mt
->mcs_buf
->bo
= image
->bo
;
969 brw_bo_reference(image
->bo
);
971 mt
->mcs_buf
->offset
= image
->aux_offset
;
972 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
973 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
974 mt
->mcs_buf
->qpitch
= 0;
975 mt
->mcs_buf
->surf
= temp_ccs_surf
;
980 struct intel_mipmap_tree
*
981 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
982 __DRIimage
*image
, GLenum target
,
984 bool is_winsys_image
)
986 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
987 return miptree_create_for_planar_image(brw
, image
, target
);
989 if (image
->planar_format
)
990 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
992 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
993 /* The texture storage paths in core Mesa detect if the driver does not
994 * support the user-requested format, and then searches for a
995 * fallback format. The DRIimage code bypasses core Mesa, though. So we
996 * do the fallbacks here for important formats.
998 * We must support DRM_FOURCC_XBGR8888 textures because the Android
999 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1000 * the Chrome OS compositor consumes as dma_buf EGLImages.
1002 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1005 if (!brw
->ctx
.TextureFormatSupported
[format
])
1008 const struct isl_drm_modifier_info
*mod_info
=
1009 isl_drm_modifier_get_info(image
->modifier
);
1011 enum intel_miptree_create_flags mt_create_flags
= 0;
1013 /* If this image comes in from a window system, we have different
1014 * requirements than if it comes in via an EGL import operation. Window
1015 * system images can use any form of auxiliary compression we wish because
1016 * they get "flushed" before being handed off to the window system and we
1017 * have the opportunity to do resolves. Non window-system images, on the
1018 * other hand, have no resolve point so we can't have aux without a
1021 if (!is_winsys_image
)
1022 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1024 /* If we have a modifier which specifies aux, don't create one yet */
1025 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1026 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1028 /* Disable creation of the texture's aux buffers because the driver exposes
1029 * no EGL API to manage them. That is, there is no API for resolving the aux
1030 * buffer's content to the main buffer nor for invalidating the aux buffer's
1033 struct intel_mipmap_tree
*mt
=
1034 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1035 image
->offset
, image
->width
, image
->height
, 1,
1036 image
->pitch
, mt_create_flags
);
1040 mt
->target
= target
;
1041 mt
->level
[0].level_x
= image
->tile_x
;
1042 mt
->level
[0].level_y
= image
->tile_y
;
1043 mt
->drm_modifier
= image
->modifier
;
1045 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1046 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1047 * trouble resolving back to destination image due to alignment issues.
1049 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1050 if (!devinfo
->has_surface_tile_offset
) {
1051 uint32_t draw_x
, draw_y
;
1052 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1054 if (draw_x
!= 0 || draw_y
!= 0) {
1055 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1056 intel_miptree_release(&mt
);
1061 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1062 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1064 mt
->aux_usage
= mod_info
->aux_usage
;
1065 /* If we are a window system buffer, then we can support fast-clears
1066 * even if the modifier doesn't support them by doing a partial resolve
1067 * as part of the flush operation.
1069 mt
->supports_fast_clear
=
1070 is_winsys_image
|| mod_info
->supports_clear_color
;
1072 /* We don't know the actual state of the surface when we get it but we
1073 * can make a pretty good guess based on the modifier. What we do know
1074 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1075 * a worst case of compression.
1077 enum isl_aux_state initial_state
=
1078 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1080 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1081 intel_miptree_release(&mt
);
1086 /* Don't assume coherency for imported EGLimages. We don't know what
1087 * external clients are going to do with it. They may scan it out.
1089 image
->bo
->cache_coherent
= false;
1095 * For a singlesample renderbuffer, this simply wraps the given BO with a
1098 * For a multisample renderbuffer, this wraps the window system's
1099 * (singlesample) BO with a singlesample miptree attached to the
1100 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1101 * that will contain the actual rendering (which is lazily resolved to
1102 * irb->singlesample_mt).
1105 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1106 struct intel_renderbuffer
*irb
,
1107 struct intel_mipmap_tree
*singlesample_mt
,
1108 uint32_t width
, uint32_t height
,
1111 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1112 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1113 mesa_format format
= rb
->Format
;
1114 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1116 /* Only the front and back buffers, which are color buffers, are allocated
1117 * through the image loader.
1119 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1120 _mesa_get_format_base_format(format
) == GL_RGBA
);
1122 assert(singlesample_mt
);
1124 if (num_samples
== 1) {
1125 intel_miptree_release(&irb
->mt
);
1126 irb
->mt
= singlesample_mt
;
1128 assert(!irb
->singlesample_mt
);
1130 intel_miptree_release(&irb
->singlesample_mt
);
1131 irb
->singlesample_mt
= singlesample_mt
;
1134 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1135 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1136 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1141 if (!multisample_mt
)
1144 irb
->need_downsample
= false;
1145 intel_miptree_release(&irb
->mt
);
1146 irb
->mt
= multisample_mt
;
1152 intel_miptree_release(&irb
->mt
);
1156 struct intel_mipmap_tree
*
1157 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1161 uint32_t num_samples
)
1163 struct intel_mipmap_tree
*mt
;
1165 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1167 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1168 width
, height
, depth
, num_samples
,
1169 MIPTREE_CREATE_BUSY
);
1176 intel_miptree_release(&mt
);
1181 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1182 struct intel_mipmap_tree
*src
)
1187 intel_miptree_release(dst
);
1191 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1198 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1200 if (aux_buf
== NULL
)
1203 brw_bo_unreference(aux_buf
->bo
);
1209 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1214 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1215 if (--(*mt
)->refcount
<= 0) {
1218 DBG("%s deleting %p\n", __func__
, *mt
);
1220 brw_bo_unreference((*mt
)->bo
);
1221 intel_miptree_release(&(*mt
)->stencil_mt
);
1222 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1223 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1224 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1225 free_aux_state_map((*mt
)->aux_state
);
1227 intel_miptree_release(&(*mt
)->plane
[0]);
1228 intel_miptree_release(&(*mt
)->plane
[1]);
1230 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1231 free((*mt
)->level
[i
].slice
);
1241 intel_get_image_dims(struct gl_texture_image
*image
,
1242 int *width
, int *height
, int *depth
)
1244 switch (image
->TexObject
->Target
) {
1245 case GL_TEXTURE_1D_ARRAY
:
1246 /* For a 1D Array texture the OpenGL API will treat the image height as
1247 * the number of array slices. For Intel hardware, we treat the 1D array
1248 * as a 2D Array with a height of 1. So, here we want to swap image
1251 assert(image
->Depth
== 1);
1252 *width
= image
->Width
;
1254 *depth
= image
->Height
;
1256 case GL_TEXTURE_CUBE_MAP
:
1257 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1258 * though we really have 6 slices.
1260 assert(image
->Depth
== 1);
1261 *width
= image
->Width
;
1262 *height
= image
->Height
;
1266 *width
= image
->Width
;
1267 *height
= image
->Height
;
1268 *depth
= image
->Depth
;
1274 * Can the image be pulled into a unified mipmap tree? This mirrors
1275 * the completeness test in a lot of ways.
1277 * Not sure whether I want to pass gl_texture_image here.
1280 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1281 struct gl_texture_image
*image
)
1283 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1284 GLuint level
= intelImage
->base
.Base
.Level
;
1285 int width
, height
, depth
;
1287 /* glTexImage* choose the texture object based on the target passed in, and
1288 * objects can't change targets over their lifetimes, so this should be
1291 assert(image
->TexObject
->Target
== mt
->target
);
1293 mesa_format mt_format
= mt
->format
;
1294 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1295 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1296 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1297 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1298 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1299 mt_format
= mt
->etc_format
;
1301 if (image
->TexFormat
!= mt_format
)
1304 intel_get_image_dims(image
, &width
, &height
, &depth
);
1306 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1309 if (level
>= mt
->surf
.levels
)
1312 const unsigned level_depth
=
1313 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1314 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1315 mt
->surf
.logical_level0_px
.array_len
;
1317 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1318 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1319 depth
== level_depth
&&
1320 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1324 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1325 GLuint level
, GLuint slice
,
1326 GLuint
*x
, GLuint
*y
)
1328 if (level
== 0 && slice
== 0) {
1329 *x
= mt
->level
[0].level_x
;
1330 *y
= mt
->level
[0].level_y
;
1334 uint32_t x_offset_sa
, y_offset_sa
;
1336 /* Miptree itself can have an offset only if it represents a single
1337 * slice in an imported buffer object.
1338 * See intel_miptree_create_for_dri_image().
1340 assert(mt
->level
[0].level_x
== 0);
1341 assert(mt
->level
[0].level_y
== 0);
1343 /* Given level is relative to level zero while the miptree may be
1344 * represent just a subset of all levels starting from 'first_level'.
1346 assert(level
>= mt
->first_level
);
1347 level
-= mt
->first_level
;
1349 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1350 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1351 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1352 &x_offset_sa
, &y_offset_sa
);
1360 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1361 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1362 * and tile_h is set to 1.
1365 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1366 uint32_t *tile_w
, uint32_t *tile_h
)
1377 case ISL_TILING_LINEAR
:
1382 unreachable("not reached");
1388 * This function computes masks that may be used to select the bits of the X
1389 * and Y coordinates that indicate the offset within a tile. If the BO is
1390 * untiled, the masks are set to 0.
1393 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1394 uint32_t *mask_x
, uint32_t *mask_y
)
1396 uint32_t tile_w_bytes
, tile_h
;
1398 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1400 *mask_x
= tile_w_bytes
/ cpp
- 1;
1401 *mask_y
= tile_h
- 1;
1405 * Compute the offset (in bytes) from the start of the BO to the given x
1406 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1407 * multiples of the tile size.
1410 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1411 uint32_t x
, uint32_t y
)
1414 uint32_t pitch
= mt
->surf
.row_pitch
;
1416 switch (mt
->surf
.tiling
) {
1418 unreachable("not reached");
1419 case ISL_TILING_LINEAR
:
1420 return y
* pitch
+ x
* cpp
;
1422 assert((x
% (512 / cpp
)) == 0);
1423 assert((y
% 8) == 0);
1424 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1426 assert((x
% (128 / cpp
)) == 0);
1427 assert((y
% 32) == 0);
1428 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1433 * Rendering with tiled buffers requires that the base address of the buffer
1434 * be aligned to a page boundary. For renderbuffers, and sometimes with
1435 * textures, we may want the surface to point at a texture image level that
1436 * isn't at a page boundary.
1438 * This function returns an appropriately-aligned base offset
1439 * according to the tiling restrictions, plus any required x/y offset
1443 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1444 GLuint level
, GLuint slice
,
1449 uint32_t mask_x
, mask_y
;
1451 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1452 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1454 *tile_x
= x
& mask_x
;
1455 *tile_y
= y
& mask_y
;
1457 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1461 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1462 struct intel_mipmap_tree
*src_mt
,
1463 unsigned src_level
, unsigned src_layer
,
1464 struct intel_mipmap_tree
*dst_mt
,
1465 unsigned dst_level
, unsigned dst_layer
,
1466 unsigned width
, unsigned height
)
1469 ptrdiff_t src_stride
, dst_stride
;
1470 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1472 intel_miptree_map(brw
, src_mt
,
1473 src_level
, src_layer
,
1476 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1479 intel_miptree_map(brw
, dst_mt
,
1480 dst_level
, dst_layer
,
1483 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1487 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1488 _mesa_get_format_name(src_mt
->format
),
1489 src_mt
, src
, src_stride
,
1490 _mesa_get_format_name(dst_mt
->format
),
1491 dst_mt
, dst
, dst_stride
,
1494 int row_size
= cpp
* width
;
1495 if (src_stride
== row_size
&&
1496 dst_stride
== row_size
) {
1497 memcpy(dst
, src
, row_size
* height
);
1499 for (int i
= 0; i
< height
; i
++) {
1500 memcpy(dst
, src
, row_size
);
1506 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1507 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1509 /* Don't forget to copy the stencil data over, too. We could have skipped
1510 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1511 * shuffling the two data sources in/out of temporary storage instead of
1512 * the direct mapping we get this way.
1514 if (dst_mt
->stencil_mt
) {
1515 assert(src_mt
->stencil_mt
);
1516 intel_miptree_copy_slice_sw(brw
,
1517 src_mt
->stencil_mt
, src_level
, src_layer
,
1518 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1524 intel_miptree_copy_slice(struct brw_context
*brw
,
1525 struct intel_mipmap_tree
*src_mt
,
1526 unsigned src_level
, unsigned src_layer
,
1527 struct intel_mipmap_tree
*dst_mt
,
1528 unsigned dst_level
, unsigned dst_layer
)
1531 mesa_format format
= src_mt
->format
;
1532 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1533 src_level
- src_mt
->first_level
);
1534 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1535 src_level
- src_mt
->first_level
);
1537 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1538 src_level
- src_mt
->first_level
));
1540 assert(src_mt
->format
== dst_mt
->format
);
1542 if (dst_mt
->compressed
) {
1544 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1545 height
= ALIGN_NPOT(height
, j
) / j
;
1546 width
= ALIGN_NPOT(width
, i
) / i
;
1549 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1550 * below won't apply since we can't do the depth's Y tiling or the
1551 * stencil's W tiling in the blitter.
1553 if (src_mt
->stencil_mt
) {
1554 intel_miptree_copy_slice_sw(brw
,
1555 src_mt
, src_level
, src_layer
,
1556 dst_mt
, dst_level
, dst_layer
,
1561 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1562 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1564 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1567 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1568 _mesa_get_format_name(src_mt
->format
),
1569 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1570 _mesa_get_format_name(dst_mt
->format
),
1571 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1574 if (!intel_miptree_blit(brw
,
1575 src_mt
, src_level
, src_layer
, 0, 0, false,
1576 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1577 width
, height
, GL_COPY
)) {
1578 perf_debug("miptree validate blit for %s failed\n",
1579 _mesa_get_format_name(format
));
1581 intel_miptree_copy_slice_sw(brw
,
1582 src_mt
, src_level
, src_layer
,
1583 dst_mt
, dst_level
, dst_layer
,
1589 * Copies the image's current data to the given miptree, and associates that
1590 * miptree with the image.
1593 intel_miptree_copy_teximage(struct brw_context
*brw
,
1594 struct intel_texture_image
*intelImage
,
1595 struct intel_mipmap_tree
*dst_mt
)
1597 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1598 struct intel_texture_object
*intel_obj
=
1599 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1600 int level
= intelImage
->base
.Base
.Level
;
1601 const unsigned face
= intelImage
->base
.Base
.Face
;
1602 unsigned start_layer
, end_layer
;
1604 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1606 assert(intelImage
->base
.Base
.Height
);
1608 end_layer
= intelImage
->base
.Base
.Height
- 1;
1609 } else if (face
> 0) {
1613 assert(intelImage
->base
.Base
.Depth
);
1615 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1618 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1619 intel_miptree_copy_slice(brw
,
1624 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1625 intel_obj
->needs_validate
= true;
1629 intel_miptree_init_mcs(struct brw_context
*brw
,
1630 struct intel_mipmap_tree
*mt
,
1633 assert(mt
->mcs_buf
!= NULL
);
1635 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1637 * When MCS buffer is enabled and bound to MSRT, it is required that it
1638 * is cleared prior to any rendering.
1640 * Since we don't use the MCS buffer for any purpose other than rendering,
1641 * it makes sense to just clear it immediately upon allocation.
1643 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1645 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1646 if (unlikely(map
== NULL
)) {
1647 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1648 brw_bo_unreference(mt
->mcs_buf
->bo
);
1653 memset(data
, init_value
, mt
->mcs_buf
->size
);
1654 brw_bo_unmap(mt
->mcs_buf
->bo
);
1657 static struct intel_miptree_aux_buffer
*
1658 intel_alloc_aux_buffer(struct brw_context
*brw
,
1660 const struct isl_surf
*aux_surf
,
1661 uint32_t alloc_flags
,
1662 struct intel_mipmap_tree
*mt
)
1664 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1668 buf
->size
= aux_surf
->size
;
1669 buf
->pitch
= aux_surf
->row_pitch
;
1670 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1672 /* ISL has stricter set of alignment rules then the drm allocator.
1673 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1674 * trying to recalculate based on different format block sizes.
1676 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1677 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1683 buf
->surf
= *aux_surf
;
1689 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1690 struct intel_mipmap_tree
*mt
,
1693 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1694 assert(mt
->mcs_buf
== NULL
);
1695 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1697 /* Multisampled miptrees are only supported for single level. */
1698 assert(mt
->first_level
== 0);
1699 enum isl_aux_state
**aux_state
=
1700 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1704 struct isl_surf temp_mcs_surf
;
1706 MAYBE_UNUSED
bool ok
=
1707 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1710 /* Buffer needs to be initialised requiring the buffer to be immediately
1711 * mapped to cpu space for writing. Therefore do not use the gpu access
1712 * flag which can cause an unnecessary delay if the backing pages happened
1713 * to be just used by the GPU.
1715 const uint32_t alloc_flags
= 0;
1716 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1717 &temp_mcs_surf
, alloc_flags
, mt
);
1723 mt
->aux_state
= aux_state
;
1725 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1731 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1732 struct intel_mipmap_tree
*mt
)
1734 assert(mt
->mcs_buf
== NULL
);
1735 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1736 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1738 struct isl_surf temp_ccs_surf
;
1740 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1743 assert(temp_ccs_surf
.size
&&
1744 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1746 enum isl_aux_state
**aux_state
=
1747 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1751 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1752 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1754 * "If Software wants to enable Color Compression without Fast clear,
1755 * Software needs to initialize MCS with zeros."
1757 * A CCS value of 0 indicates that the corresponding block is in the
1758 * pass-through state which is what we want.
1760 * For CCS_D, on the other hand, we don't care as we're about to perform a
1761 * fast-clear operation. In that case, being hot in caches more useful.
1763 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1764 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1765 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1766 &temp_ccs_surf
, alloc_flags
, mt
);
1772 mt
->aux_state
= aux_state
;
1778 * Helper for intel_miptree_alloc_hiz() that sets
1779 * \c mt->level[level].has_hiz. Return true if and only if
1780 * \c has_hiz was set.
1783 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1784 struct intel_mipmap_tree
*mt
,
1787 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1789 assert(mt
->hiz_buf
);
1790 assert(mt
->surf
.size
> 0);
1792 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1793 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1794 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1796 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1797 * and the height is 4 aligned. This allows our HiZ support
1798 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1799 * we can grow the width & height to allow the HiZ op to
1800 * force the proper size alignments.
1802 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1803 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1808 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1809 mt
->level
[level
].has_hiz
= true;
1814 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1815 struct intel_mipmap_tree
*mt
)
1817 assert(mt
->hiz_buf
== NULL
);
1818 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1820 enum isl_aux_state
**aux_state
=
1821 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1825 struct isl_surf temp_hiz_surf
;
1827 MAYBE_UNUSED
bool ok
=
1828 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1831 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1832 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1833 &temp_hiz_surf
, alloc_flags
, mt
);
1840 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1841 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1843 mt
->aux_state
= aux_state
;
1850 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1852 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1853 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1854 * compress clear color so we wait until an actual fast-clear to allocate it.
1857 intel_miptree_alloc_aux(struct brw_context
*brw
,
1858 struct intel_mipmap_tree
*mt
)
1860 switch (mt
->aux_usage
) {
1861 case ISL_AUX_USAGE_NONE
:
1864 case ISL_AUX_USAGE_HIZ
:
1865 assert(!_mesa_is_format_color_format(mt
->format
));
1866 if (!intel_miptree_alloc_hiz(brw
, mt
))
1870 case ISL_AUX_USAGE_MCS
:
1871 assert(_mesa_is_format_color_format(mt
->format
));
1872 assert(mt
->surf
.samples
> 1);
1873 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1877 case ISL_AUX_USAGE_CCS_D
:
1878 /* Since CCS_D can only compress clear color so we wait until an actual
1879 * fast-clear to allocate it.
1883 case ISL_AUX_USAGE_CCS_E
:
1884 assert(_mesa_is_format_color_format(mt
->format
));
1885 assert(mt
->surf
.samples
== 1);
1886 if (!intel_miptree_alloc_ccs(brw
, mt
))
1891 unreachable("Invalid aux usage");
1896 * Can the miptree sample using the hiz buffer?
1899 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1900 struct intel_mipmap_tree
*mt
)
1902 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1904 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1905 * so keep things conservative for now and never enable it unless we're SKL+.
1907 if (devinfo
->gen
< 9) {
1915 /* It seems the hardware won't fallback to the depth buffer if some of the
1916 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1917 * of the texture to be HiZ enabled.
1919 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1920 if (!intel_miptree_level_has_hiz(mt
, level
))
1924 /* If compressed multisampling is enabled, then we use it for the auxiliary
1927 * From the BDW PRM (Volume 2d: Command Reference: Structures
1928 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1930 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1931 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1933 * There is no such blurb for 1D textures, but there is sufficient evidence
1934 * that this is broken on SKL+.
1936 return (mt
->surf
.samples
== 1 &&
1937 mt
->target
!= GL_TEXTURE_3D
&&
1938 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1942 * Does the miptree slice have hiz enabled?
1945 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1947 intel_miptree_check_level_layer(mt
, level
, 0);
1948 return mt
->level
[level
].has_hiz
;
1951 static inline uint32_t
1952 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1953 uint32_t start_level
, uint32_t num_levels
)
1955 assert(start_level
>= mt
->first_level
);
1956 assert(start_level
<= mt
->last_level
);
1958 if (num_levels
== INTEL_REMAINING_LAYERS
)
1959 num_levels
= mt
->last_level
- start_level
+ 1;
1960 /* Check for overflow */
1961 assert(start_level
+ num_levels
>= start_level
);
1962 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1967 static inline uint32_t
1968 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1969 uint32_t start_layer
, uint32_t num_layers
)
1971 assert(level
<= mt
->last_level
);
1973 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1974 assert(start_layer
< total_num_layers
);
1975 if (num_layers
== INTEL_REMAINING_LAYERS
)
1976 num_layers
= total_num_layers
- start_layer
;
1977 /* Check for overflow */
1978 assert(start_layer
+ num_layers
>= start_layer
);
1979 assert(start_layer
+ num_layers
<= total_num_layers
);
1985 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1986 unsigned start_level
, unsigned num_levels
,
1987 unsigned start_layer
, unsigned num_layers
)
1989 assert(_mesa_is_format_color_format(mt
->format
));
1994 /* Clamp the level range to fit the miptree */
1995 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1997 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1998 const uint32_t level
= start_level
+ l
;
1999 const uint32_t level_layers
=
2000 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2001 for (unsigned a
= 0; a
< level_layers
; a
++) {
2002 enum isl_aux_state aux_state
=
2003 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2004 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2005 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2014 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2015 const struct intel_mipmap_tree
*mt
,
2016 unsigned level
, unsigned layer
)
2021 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2022 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2023 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2025 /* Compression of arrayed msaa surfaces is supported. */
2026 if (mt
->surf
.samples
> 1)
2029 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2030 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2032 mt
->surf
.logical_level0_px
.depth
== 1 &&
2033 mt
->surf
.logical_level0_px
.array_len
== 1));
2039 static enum blorp_fast_clear_op
2040 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2041 enum isl_aux_usage aux_usage
,
2042 bool fast_clear_supported
)
2044 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2046 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2048 assert(ccs_supported
== fast_clear_supported
);
2050 switch (aux_state
) {
2051 case ISL_AUX_STATE_CLEAR
:
2052 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2054 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2056 return BLORP_FAST_CLEAR_OP_NONE
;
2058 case ISL_AUX_STATE_PASS_THROUGH
:
2059 return BLORP_FAST_CLEAR_OP_NONE
;
2061 case ISL_AUX_STATE_RESOLVED
:
2062 case ISL_AUX_STATE_AUX_INVALID
:
2063 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2064 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2068 unreachable("Invalid aux state for CCS_D");
2071 static enum blorp_fast_clear_op
2072 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2073 enum isl_aux_usage aux_usage
,
2074 bool fast_clear_supported
)
2076 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2077 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2078 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2079 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2081 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2082 assert(fast_clear_supported
);
2084 switch (aux_state
) {
2085 case ISL_AUX_STATE_CLEAR
:
2086 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2087 if (fast_clear_supported
)
2088 return BLORP_FAST_CLEAR_OP_NONE
;
2089 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2090 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2092 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2094 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2095 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2096 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2097 else if (!fast_clear_supported
)
2098 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2100 return BLORP_FAST_CLEAR_OP_NONE
;
2102 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2103 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2104 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2106 return BLORP_FAST_CLEAR_OP_NONE
;
2108 case ISL_AUX_STATE_PASS_THROUGH
:
2109 return BLORP_FAST_CLEAR_OP_NONE
;
2111 case ISL_AUX_STATE_RESOLVED
:
2112 case ISL_AUX_STATE_AUX_INVALID
:
2116 unreachable("Invalid aux state for CCS_E");
2120 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2121 struct intel_mipmap_tree
*mt
,
2122 uint32_t level
, uint32_t layer
,
2123 enum isl_aux_usage aux_usage
,
2124 bool fast_clear_supported
)
2126 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2128 enum blorp_fast_clear_op resolve_op
;
2129 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2130 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2131 fast_clear_supported
);
2133 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2134 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2135 fast_clear_supported
);
2138 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2139 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2140 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2142 switch (resolve_op
) {
2143 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2144 /* The CCS full resolve operation destroys the CCS and sets it to the
2145 * pass-through state. (You can also think of this as being both a
2146 * resolve and an ambiguate in one operation.)
2148 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2149 ISL_AUX_STATE_PASS_THROUGH
);
2152 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2153 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2154 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2158 unreachable("Invalid resolve op");
2164 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2165 struct intel_mipmap_tree
*mt
,
2166 uint32_t level
, uint32_t layer
,
2167 enum isl_aux_usage aux_usage
)
2169 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2170 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2171 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2173 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2175 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2176 switch (aux_state
) {
2177 case ISL_AUX_STATE_CLEAR
:
2178 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2179 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2180 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2182 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2183 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2184 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2185 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2186 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2187 ISL_AUX_STATE_PARTIAL_CLEAR
);
2191 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2192 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2193 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2194 break; /* Nothing to do */
2196 case ISL_AUX_STATE_PASS_THROUGH
:
2197 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2198 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2199 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2205 case ISL_AUX_STATE_RESOLVED
:
2206 case ISL_AUX_STATE_AUX_INVALID
:
2207 unreachable("Invalid aux state for CCS_E");
2210 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2211 /* CCS_D is a bit simpler */
2212 switch (aux_state
) {
2213 case ISL_AUX_STATE_CLEAR
:
2214 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2215 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2216 ISL_AUX_STATE_PARTIAL_CLEAR
);
2219 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2220 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2221 break; /* Nothing to do */
2223 case ISL_AUX_STATE_PASS_THROUGH
:
2227 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2228 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2229 case ISL_AUX_STATE_RESOLVED
:
2230 case ISL_AUX_STATE_AUX_INVALID
:
2231 unreachable("Invalid aux state for CCS_D");
2237 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2238 struct intel_mipmap_tree
*mt
,
2240 enum isl_aux_usage aux_usage
,
2241 bool fast_clear_supported
)
2243 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2245 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2246 case ISL_AUX_STATE_CLEAR
:
2247 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2248 if (!fast_clear_supported
) {
2249 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2250 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2251 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2255 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2256 break; /* Nothing to do */
2258 case ISL_AUX_STATE_RESOLVED
:
2259 case ISL_AUX_STATE_PASS_THROUGH
:
2260 case ISL_AUX_STATE_AUX_INVALID
:
2261 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2262 unreachable("Invalid aux state for MCS");
2267 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2268 struct intel_mipmap_tree
*mt
,
2270 enum isl_aux_usage aux_usage
)
2272 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2274 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2275 case ISL_AUX_STATE_CLEAR
:
2276 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2277 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2280 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2281 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2282 break; /* Nothing to do */
2284 case ISL_AUX_STATE_RESOLVED
:
2285 case ISL_AUX_STATE_PASS_THROUGH
:
2286 case ISL_AUX_STATE_AUX_INVALID
:
2287 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2288 unreachable("Invalid aux state for MCS");
2293 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2294 struct intel_mipmap_tree
*mt
,
2295 uint32_t level
, uint32_t layer
,
2296 enum isl_aux_usage aux_usage
,
2297 bool fast_clear_supported
)
2299 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2301 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2302 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2303 case ISL_AUX_STATE_CLEAR
:
2304 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2305 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2306 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2309 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2310 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2311 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2314 case ISL_AUX_STATE_PASS_THROUGH
:
2315 case ISL_AUX_STATE_RESOLVED
:
2318 case ISL_AUX_STATE_AUX_INVALID
:
2319 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2320 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2323 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2324 unreachable("Invalid HiZ state");
2327 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2328 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2331 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2332 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2333 ISL_AUX_STATE_RESOLVED
);
2336 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2337 /* The HiZ resolve operation is actually an ambiguate */
2338 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2339 ISL_AUX_STATE_PASS_THROUGH
);
2343 unreachable("Invalid HiZ op");
2349 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2350 struct intel_mipmap_tree
*mt
,
2351 uint32_t level
, uint32_t layer
,
2352 enum isl_aux_usage aux_usage
)
2354 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2356 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2357 case ISL_AUX_STATE_CLEAR
:
2358 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2359 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2360 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2363 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2364 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2365 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2366 break; /* Nothing to do */
2368 case ISL_AUX_STATE_RESOLVED
:
2369 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2370 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2371 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2373 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2374 ISL_AUX_STATE_AUX_INVALID
);
2378 case ISL_AUX_STATE_PASS_THROUGH
:
2379 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2380 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2381 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2385 case ISL_AUX_STATE_AUX_INVALID
:
2386 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2389 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2390 unreachable("Invalid HiZ state");
2395 intel_miptree_prepare_access(struct brw_context
*brw
,
2396 struct intel_mipmap_tree
*mt
,
2397 uint32_t start_level
, uint32_t num_levels
,
2398 uint32_t start_layer
, uint32_t num_layers
,
2399 enum isl_aux_usage aux_usage
,
2400 bool fast_clear_supported
)
2402 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2404 switch (mt
->aux_usage
) {
2405 case ISL_AUX_USAGE_NONE
:
2409 case ISL_AUX_USAGE_MCS
:
2410 assert(mt
->mcs_buf
);
2411 assert(start_level
== 0 && num_levels
== 1);
2412 const uint32_t level_layers
=
2413 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2414 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2415 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2416 aux_usage
, fast_clear_supported
);
2420 case ISL_AUX_USAGE_CCS_D
:
2421 case ISL_AUX_USAGE_CCS_E
:
2425 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2426 const uint32_t level
= start_level
+ l
;
2427 const uint32_t level_layers
=
2428 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2429 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2430 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2432 aux_usage
, fast_clear_supported
);
2437 case ISL_AUX_USAGE_HIZ
:
2438 assert(mt
->hiz_buf
);
2439 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2440 const uint32_t level
= start_level
+ l
;
2441 if (!intel_miptree_level_has_hiz(mt
, level
))
2444 const uint32_t level_layers
=
2445 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2446 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2447 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2448 aux_usage
, fast_clear_supported
);
2454 unreachable("Invalid aux usage");
2459 intel_miptree_finish_write(struct brw_context
*brw
,
2460 struct intel_mipmap_tree
*mt
, uint32_t level
,
2461 uint32_t start_layer
, uint32_t num_layers
,
2462 enum isl_aux_usage aux_usage
)
2464 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2466 switch (mt
->aux_usage
) {
2467 case ISL_AUX_USAGE_NONE
:
2471 case ISL_AUX_USAGE_MCS
:
2472 assert(mt
->mcs_buf
);
2473 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2474 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2479 case ISL_AUX_USAGE_CCS_D
:
2480 case ISL_AUX_USAGE_CCS_E
:
2484 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2485 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2490 case ISL_AUX_USAGE_HIZ
:
2491 if (!intel_miptree_level_has_hiz(mt
, level
))
2494 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2495 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2501 unreachable("Invavlid aux usage");
2506 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2507 uint32_t level
, uint32_t layer
)
2509 intel_miptree_check_level_layer(mt
, level
, layer
);
2511 if (_mesa_is_format_color_format(mt
->format
)) {
2512 assert(mt
->mcs_buf
!= NULL
);
2513 assert(mt
->surf
.samples
== 1 ||
2514 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2515 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2516 unreachable("Cannot get aux state for stencil");
2518 assert(intel_miptree_level_has_hiz(mt
, level
));
2521 return mt
->aux_state
[level
][layer
];
2525 intel_miptree_set_aux_state(struct brw_context
*brw
,
2526 struct intel_mipmap_tree
*mt
, uint32_t level
,
2527 uint32_t start_layer
, uint32_t num_layers
,
2528 enum isl_aux_state aux_state
)
2530 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2532 if (_mesa_is_format_color_format(mt
->format
)) {
2533 assert(mt
->mcs_buf
!= NULL
);
2534 assert(mt
->surf
.samples
== 1 ||
2535 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2536 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2537 unreachable("Cannot get aux state for stencil");
2539 assert(intel_miptree_level_has_hiz(mt
, level
));
2542 for (unsigned a
= 0; a
< num_layers
; a
++) {
2543 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2544 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2545 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2550 /* On Gen9 color buffers may be compressed by the hardware (lossless
2551 * compression). There are, however, format restrictions and care needs to be
2552 * taken that the sampler engine is capable for re-interpreting a buffer with
2553 * format different the buffer was originally written with.
2555 * For example, SRGB formats are not compressible and the sampler engine isn't
2556 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2557 * color buffer needs to be resolved so that the sampling surface can be
2558 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2562 can_texture_with_ccs(struct brw_context
*brw
,
2563 struct intel_mipmap_tree
*mt
,
2564 enum isl_format view_format
)
2566 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2569 /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
2570 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2571 mt
->surf
.format
, view_format
)) {
2572 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2573 isl_format_get_layout(view_format
)->name
,
2574 _mesa_get_format_name(mt
->format
));
2582 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2583 struct intel_mipmap_tree
*mt
,
2584 enum isl_format view_format
)
2586 switch (mt
->aux_usage
) {
2587 case ISL_AUX_USAGE_HIZ
:
2588 if (intel_miptree_sample_with_hiz(brw
, mt
))
2589 return ISL_AUX_USAGE_HIZ
;
2592 case ISL_AUX_USAGE_MCS
:
2593 return ISL_AUX_USAGE_MCS
;
2595 case ISL_AUX_USAGE_CCS_D
:
2596 case ISL_AUX_USAGE_CCS_E
:
2598 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2599 return ISL_AUX_USAGE_NONE
;
2602 /* If we don't have any unresolved color, report an aux usage of
2603 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2604 * aux surface and we can save some bandwidth.
2606 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2607 0, INTEL_REMAINING_LAYERS
))
2608 return ISL_AUX_USAGE_NONE
;
2610 if (can_texture_with_ccs(brw
, mt
, view_format
))
2611 return ISL_AUX_USAGE_CCS_E
;
2618 return ISL_AUX_USAGE_NONE
;
2622 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2624 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2625 * values so sRGB curve application was a no-op for all fast-clearable
2628 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2629 * values, the hardware interprets the floats, not as what would be
2630 * returned from the sampler (or written by the shader), but as being
2631 * between format conversion and sRGB curve application. This means that
2632 * we can switch between sRGB and UNORM without having to whack the clear
2635 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2639 intel_miptree_prepare_texture(struct brw_context
*brw
,
2640 struct intel_mipmap_tree
*mt
,
2641 enum isl_format view_format
,
2642 uint32_t start_level
, uint32_t num_levels
,
2643 uint32_t start_layer
, uint32_t num_layers
,
2646 enum isl_aux_usage aux_usage
= disable_aux
? ISL_AUX_USAGE_NONE
:
2647 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2648 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2650 /* Clear color is specified as ints or floats and the conversion is done by
2651 * the sampler. If we have a texture view, we would have to perform the
2652 * clear color conversion manually. Just disable clear color.
2654 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2655 clear_supported
= false;
2657 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2658 start_layer
, num_layers
,
2659 aux_usage
, clear_supported
);
2663 intel_miptree_prepare_image(struct brw_context
*brw
,
2664 struct intel_mipmap_tree
*mt
)
2666 /* The data port doesn't understand any compression */
2667 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2668 0, INTEL_REMAINING_LAYERS
,
2669 ISL_AUX_USAGE_NONE
, false);
2673 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2674 struct intel_mipmap_tree
*mt
,
2675 enum isl_format render_format
,
2678 switch (mt
->aux_usage
) {
2679 case ISL_AUX_USAGE_MCS
:
2680 assert(mt
->mcs_buf
);
2681 return ISL_AUX_USAGE_MCS
;
2683 case ISL_AUX_USAGE_CCS_D
:
2684 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2686 case ISL_AUX_USAGE_CCS_E
: {
2687 /* If the format supports CCS_E and is compatible with the miptree,
2688 * then we can use it.
2690 if (format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2692 return ISL_AUX_USAGE_CCS_E
;
2694 /* Otherwise, we have to fall back to CCS_D */
2696 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2697 * formats. However, there are issues with blending where it doesn't
2698 * properly apply the sRGB curve to the clear color when blending.
2700 if (blend_enabled
&& isl_format_is_srgb(render_format
) &&
2701 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2702 return ISL_AUX_USAGE_NONE
;
2704 return ISL_AUX_USAGE_CCS_D
;
2708 return ISL_AUX_USAGE_NONE
;
2713 intel_miptree_prepare_render(struct brw_context
*brw
,
2714 struct intel_mipmap_tree
*mt
, uint32_t level
,
2715 uint32_t start_layer
, uint32_t layer_count
,
2716 enum isl_format render_format
,
2719 enum isl_aux_usage aux_usage
=
2720 intel_miptree_render_aux_usage(brw
, mt
, render_format
, blend_enabled
);
2721 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2722 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2726 intel_miptree_finish_render(struct brw_context
*brw
,
2727 struct intel_mipmap_tree
*mt
, uint32_t level
,
2728 uint32_t start_layer
, uint32_t layer_count
,
2729 enum isl_format render_format
,
2732 assert(_mesa_is_format_color_format(mt
->format
));
2734 enum isl_aux_usage aux_usage
=
2735 intel_miptree_render_aux_usage(brw
, mt
, render_format
, blend_enabled
);
2736 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2741 intel_miptree_prepare_depth(struct brw_context
*brw
,
2742 struct intel_mipmap_tree
*mt
, uint32_t level
,
2743 uint32_t start_layer
, uint32_t layer_count
)
2745 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2746 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2750 intel_miptree_finish_depth(struct brw_context
*brw
,
2751 struct intel_mipmap_tree
*mt
, uint32_t level
,
2752 uint32_t start_layer
, uint32_t layer_count
,
2755 if (depth_written
) {
2756 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2757 mt
->hiz_buf
!= NULL
);
2762 intel_miptree_prepare_external(struct brw_context
*brw
,
2763 struct intel_mipmap_tree
*mt
)
2765 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2766 bool supports_fast_clear
= false;
2768 const struct isl_drm_modifier_info
*mod_info
=
2769 isl_drm_modifier_get_info(mt
->drm_modifier
);
2771 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2772 /* CCS_E is the only supported aux for external images and it's only
2773 * supported on very simple images.
2775 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2776 assert(_mesa_is_format_color_format(mt
->format
));
2777 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2778 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2779 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2780 assert(mt
->surf
.samples
== 1);
2781 assert(mt
->mcs_buf
!= NULL
);
2783 aux_usage
= mod_info
->aux_usage
;
2784 supports_fast_clear
= mod_info
->supports_clear_color
;
2787 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2788 0, INTEL_REMAINING_LAYERS
,
2789 aux_usage
, supports_fast_clear
);
2793 * Make it possible to share the BO backing the given miptree with another
2794 * process or another miptree.
2796 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2797 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2798 * ensure that no MCS buffer gets allocated in the future.
2800 * HiZ is similarly unsafe with shared buffers.
2803 intel_miptree_make_shareable(struct brw_context
*brw
,
2804 struct intel_mipmap_tree
*mt
)
2806 /* MCS buffers are also used for multisample buffers, but we can't resolve
2807 * away a multisample MCS buffer because it's an integral part of how the
2808 * pixel data is stored. Fortunately this code path should never be
2809 * reached for multisample buffers.
2811 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2812 mt
->surf
.samples
== 1);
2814 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2815 0, INTEL_REMAINING_LAYERS
,
2816 ISL_AUX_USAGE_NONE
, false);
2819 brw_bo_unreference(mt
->mcs_buf
->bo
);
2823 /* Any pending MCS/CCS operations are no longer needed. Trying to
2824 * execute any will likely crash due to the missing aux buffer. So let's
2825 * delete all pending ops.
2827 free(mt
->aux_state
);
2828 mt
->aux_state
= NULL
;
2829 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2833 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2836 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2837 mt
->level
[l
].has_hiz
= false;
2840 /* Any pending HiZ operations are no longer needed. Trying to execute
2841 * any will likely crash due to the missing aux buffer. So let's delete
2844 free(mt
->aux_state
);
2845 mt
->aux_state
= NULL
;
2846 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2849 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2850 mt
->supports_fast_clear
= false;
2855 * \brief Get pointer offset into stencil buffer.
2857 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2858 * must decode the tile's layout in software.
2861 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2863 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2865 * Even though the returned offset is always positive, the return type is
2867 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2868 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2871 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2873 uint32_t tile_size
= 4096;
2874 uint32_t tile_width
= 64;
2875 uint32_t tile_height
= 64;
2876 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2878 uint32_t tile_x
= x
/ tile_width
;
2879 uint32_t tile_y
= y
/ tile_height
;
2881 /* The byte's address relative to the tile's base addres. */
2882 uint32_t byte_x
= x
% tile_width
;
2883 uint32_t byte_y
= y
% tile_height
;
2885 uintptr_t u
= tile_y
* row_size
2886 + tile_x
* tile_size
2887 + 512 * (byte_x
/ 8)
2889 + 32 * ((byte_y
/ 4) % 2)
2890 + 16 * ((byte_x
/ 4) % 2)
2891 + 8 * ((byte_y
/ 2) % 2)
2892 + 4 * ((byte_x
/ 2) % 2)
2897 /* adjust for bit6 swizzling */
2898 if (((byte_x
/ 8) % 2) == 1) {
2899 if (((byte_y
/ 8) % 2) == 0) {
2911 intel_miptree_updownsample(struct brw_context
*brw
,
2912 struct intel_mipmap_tree
*src
,
2913 struct intel_mipmap_tree
*dst
)
2915 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2916 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2917 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2918 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2920 brw_blorp_blit_miptrees(brw
,
2921 src
, 0 /* level */, 0 /* layer */,
2922 src
->format
, SWIZZLE_XYZW
,
2923 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2926 GL_NEAREST
, false, false /*mirror x, y*/,
2929 if (src
->stencil_mt
) {
2930 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2931 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2932 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2933 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2935 brw_blorp_blit_miptrees(brw
,
2936 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2937 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2938 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2939 dst
->stencil_mt
->format
,
2942 GL_NEAREST
, false, false /*mirror x, y*/,
2943 false, false /* decode/encode srgb */);
2948 intel_update_r8stencil(struct brw_context
*brw
,
2949 struct intel_mipmap_tree
*mt
)
2951 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2953 assert(devinfo
->gen
>= 7);
2954 struct intel_mipmap_tree
*src
=
2955 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2956 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2959 assert(src
->surf
.size
> 0);
2961 if (!mt
->r8stencil_mt
) {
2962 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2963 mt
->r8stencil_mt
= make_surface(
2966 MESA_FORMAT_R_UINT8
,
2967 src
->first_level
, src
->last_level
,
2968 src
->surf
.logical_level0_px
.width
,
2969 src
->surf
.logical_level0_px
.height
,
2970 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2971 src
->surf
.logical_level0_px
.depth
:
2972 src
->surf
.logical_level0_px
.array_len
,
2975 ISL_SURF_USAGE_TEXTURE_BIT
,
2976 BO_ALLOC_BUSY
, 0, NULL
);
2977 assert(mt
->r8stencil_mt
);
2980 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2982 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2983 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2984 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2985 src
->surf
.phys_level0_sa
.array_len
;
2987 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2988 brw_blorp_copy_miptrees(brw
,
2992 minify(src
->surf
.logical_level0_px
.width
,
2994 minify(src
->surf
.logical_level0_px
.height
,
2999 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3000 src
->r8stencil_needs_update
= false;
3004 intel_miptree_map_raw(struct brw_context
*brw
,
3005 struct intel_mipmap_tree
*mt
,
3008 struct brw_bo
*bo
= mt
->bo
;
3010 if (brw_batch_references(&brw
->batch
, bo
))
3011 intel_batchbuffer_flush(brw
);
3013 return brw_bo_map(brw
, bo
, mode
);
3017 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3019 brw_bo_unmap(mt
->bo
);
3023 intel_miptree_map_gtt(struct brw_context
*brw
,
3024 struct intel_mipmap_tree
*mt
,
3025 struct intel_miptree_map
*map
,
3026 unsigned int level
, unsigned int slice
)
3028 unsigned int bw
, bh
;
3030 unsigned int image_x
, image_y
;
3031 intptr_t x
= map
->x
;
3032 intptr_t y
= map
->y
;
3034 /* For compressed formats, the stride is the number of bytes per
3035 * row of blocks. intel_miptree_get_image_offset() already does
3038 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3039 assert(y
% bh
== 0);
3040 assert(x
% bw
== 0);
3044 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3051 /* Note that in the case of cube maps, the caller must have passed the
3052 * slice number referencing the face.
3054 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3058 map
->stride
= mt
->surf
.row_pitch
;
3059 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3062 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3063 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3064 map
->x
, map
->y
, map
->w
, map
->h
,
3065 mt
, _mesa_get_format_name(mt
->format
),
3066 x
, y
, map
->ptr
, map
->stride
);
3070 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3072 intel_miptree_unmap_raw(mt
);
3076 intel_miptree_map_blit(struct brw_context
*brw
,
3077 struct intel_mipmap_tree
*mt
,
3078 struct intel_miptree_map
*map
,
3079 unsigned int level
, unsigned int slice
)
3081 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3082 /* first_level */ 0,
3086 MIPTREE_CREATE_LINEAR
);
3088 if (!map
->linear_mt
) {
3089 fprintf(stderr
, "Failed to allocate blit temporary\n");
3092 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3094 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3095 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3096 * invalidate is set, since we'll be writing the whole rectangle from our
3097 * temporary buffer back out.
3099 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3100 if (!intel_miptree_copy(brw
,
3101 mt
, level
, slice
, map
->x
, map
->y
,
3102 map
->linear_mt
, 0, 0, 0, 0,
3104 fprintf(stderr
, "Failed to blit\n");
3109 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3111 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3112 map
->x
, map
->y
, map
->w
, map
->h
,
3113 mt
, _mesa_get_format_name(mt
->format
),
3114 level
, slice
, map
->ptr
, map
->stride
);
3119 intel_miptree_release(&map
->linear_mt
);
3125 intel_miptree_unmap_blit(struct brw_context
*brw
,
3126 struct intel_mipmap_tree
*mt
,
3127 struct intel_miptree_map
*map
,
3131 struct gl_context
*ctx
= &brw
->ctx
;
3133 intel_miptree_unmap_raw(map
->linear_mt
);
3135 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3136 bool ok
= intel_miptree_copy(brw
,
3137 map
->linear_mt
, 0, 0, 0, 0,
3138 mt
, level
, slice
, map
->x
, map
->y
,
3140 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3143 intel_miptree_release(&map
->linear_mt
);
3147 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3149 #if defined(USE_SSE41)
3151 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3152 struct intel_mipmap_tree
*mt
,
3153 struct intel_miptree_map
*map
,
3154 unsigned int level
, unsigned int slice
)
3156 assert(map
->mode
& GL_MAP_READ_BIT
);
3157 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3159 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3160 map
->x
, map
->y
, map
->w
, map
->h
,
3161 mt
, _mesa_get_format_name(mt
->format
),
3162 level
, slice
, map
->ptr
, map
->stride
);
3164 /* Map the original image */
3167 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3171 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3177 src
+= image_y
* mt
->surf
.row_pitch
;
3178 src
+= image_x
* mt
->cpp
;
3180 /* Due to the pixel offsets for the particular image being mapped, our
3181 * src pointer may not be 16-byte aligned. However, if the pitch is
3182 * divisible by 16, then the amount by which it's misaligned will remain
3183 * consistent from row to row.
3185 assert((mt
->surf
.row_pitch
% 16) == 0);
3186 const int misalignment
= ((uintptr_t) src
) & 15;
3188 /* Create an untiled temporary buffer for the mapping. */
3189 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3191 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3193 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3194 /* Offset the destination so it has the same misalignment as src. */
3195 map
->ptr
= map
->buffer
+ misalignment
;
3197 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3199 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3200 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3201 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3203 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3206 intel_miptree_unmap_raw(mt
);
3210 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3211 struct intel_mipmap_tree
*mt
,
3212 struct intel_miptree_map
*map
,
3216 _mesa_align_free(map
->buffer
);
3223 intel_miptree_map_s8(struct brw_context
*brw
,
3224 struct intel_mipmap_tree
*mt
,
3225 struct intel_miptree_map
*map
,
3226 unsigned int level
, unsigned int slice
)
3228 map
->stride
= map
->w
;
3229 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3233 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3234 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3235 * invalidate is set, since we'll be writing the whole rectangle from our
3236 * temporary buffer back out.
3238 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3239 uint8_t *untiled_s8_map
= map
->ptr
;
3240 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3241 unsigned int image_x
, image_y
;
3243 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3245 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3246 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3247 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3248 x
+ image_x
+ map
->x
,
3249 y
+ image_y
+ map
->y
,
3250 brw
->has_swizzling
);
3251 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3255 intel_miptree_unmap_raw(mt
);
3257 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3258 map
->x
, map
->y
, map
->w
, map
->h
,
3259 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3261 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3262 map
->x
, map
->y
, map
->w
, map
->h
,
3263 mt
, map
->ptr
, map
->stride
);
3268 intel_miptree_unmap_s8(struct brw_context
*brw
,
3269 struct intel_mipmap_tree
*mt
,
3270 struct intel_miptree_map
*map
,
3274 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3275 unsigned int image_x
, image_y
;
3276 uint8_t *untiled_s8_map
= map
->ptr
;
3277 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3279 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3281 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3282 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3283 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3284 image_x
+ x
+ map
->x
,
3285 image_y
+ y
+ map
->y
,
3286 brw
->has_swizzling
);
3287 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3291 intel_miptree_unmap_raw(mt
);
3298 intel_miptree_map_etc(struct brw_context
*brw
,
3299 struct intel_mipmap_tree
*mt
,
3300 struct intel_miptree_map
*map
,
3304 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3305 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3306 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3309 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3310 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3312 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3313 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3314 map
->w
, map
->h
, 1));
3315 map
->ptr
= map
->buffer
;
3319 intel_miptree_unmap_etc(struct brw_context
*brw
,
3320 struct intel_mipmap_tree
*mt
,
3321 struct intel_miptree_map
*map
,
3327 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3332 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3333 + image_y
* mt
->surf
.row_pitch
3334 + image_x
* mt
->cpp
;
3336 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3337 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3338 map
->ptr
, map
->stride
,
3341 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3342 map
->ptr
, map
->stride
,
3343 map
->w
, map
->h
, mt
->etc_format
);
3345 intel_miptree_unmap_raw(mt
);
3350 * Mapping function for packed depth/stencil miptrees backed by real separate
3351 * miptrees for depth and stencil.
3353 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3354 * separate from the depth buffer. Yet at the GL API level, we have to expose
3355 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3356 * be able to map that memory for texture storage and glReadPixels-type
3357 * operations. We give Mesa core that access by mallocing a temporary and
3358 * copying the data between the actual backing store and the temporary.
3361 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3362 struct intel_mipmap_tree
*mt
,
3363 struct intel_miptree_map
*map
,
3364 unsigned int level
, unsigned int slice
)
3366 struct intel_mipmap_tree
*z_mt
= mt
;
3367 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3368 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3369 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3371 map
->stride
= map
->w
* packed_bpp
;
3372 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3376 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3377 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3378 * invalidate is set, since we'll be writing the whole rectangle from our
3379 * temporary buffer back out.
3381 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3382 uint32_t *packed_map
= map
->ptr
;
3383 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3384 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3385 unsigned int s_image_x
, s_image_y
;
3386 unsigned int z_image_x
, z_image_y
;
3388 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3389 &s_image_x
, &s_image_y
);
3390 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3391 &z_image_x
, &z_image_y
);
3393 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3394 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3395 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3396 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3399 brw
->has_swizzling
);
3400 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3401 (z_mt
->surf
.row_pitch
/ 4) +
3402 (map_x
+ z_image_x
));
3403 uint8_t s
= s_map
[s_offset
];
3404 uint32_t z
= z_map
[z_offset
];
3406 if (map_z32f_x24s8
) {
3407 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3408 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3410 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3415 intel_miptree_unmap_raw(s_mt
);
3416 intel_miptree_unmap_raw(z_mt
);
3418 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3420 map
->x
, map
->y
, map
->w
, map
->h
,
3421 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3422 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3423 map
->ptr
, map
->stride
);
3425 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3426 map
->x
, map
->y
, map
->w
, map
->h
,
3427 mt
, map
->ptr
, map
->stride
);
3432 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3433 struct intel_mipmap_tree
*mt
,
3434 struct intel_miptree_map
*map
,
3438 struct intel_mipmap_tree
*z_mt
= mt
;
3439 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3440 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3442 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3443 uint32_t *packed_map
= map
->ptr
;
3444 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3445 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3446 unsigned int s_image_x
, s_image_y
;
3447 unsigned int z_image_x
, z_image_y
;
3449 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3450 &s_image_x
, &s_image_y
);
3451 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3452 &z_image_x
, &z_image_y
);
3454 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3455 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3456 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3457 x
+ s_image_x
+ map
->x
,
3458 y
+ s_image_y
+ map
->y
,
3459 brw
->has_swizzling
);
3460 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3461 (z_mt
->surf
.row_pitch
/ 4) +
3462 (x
+ z_image_x
+ map
->x
));
3464 if (map_z32f_x24s8
) {
3465 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3466 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3468 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3469 s_map
[s_offset
] = packed
>> 24;
3470 z_map
[z_offset
] = packed
;
3475 intel_miptree_unmap_raw(s_mt
);
3476 intel_miptree_unmap_raw(z_mt
);
3478 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3480 map
->x
, map
->y
, map
->w
, map
->h
,
3481 z_mt
, _mesa_get_format_name(z_mt
->format
),
3482 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3483 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3484 map
->ptr
, map
->stride
);
3491 * Create and attach a map to the miptree at (level, slice). Return the
3494 static struct intel_miptree_map
*
3495 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3504 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3509 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3510 mt
->level
[level
].slice
[slice
].map
= map
;
3522 * Release the map at (level, slice).
3525 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3529 struct intel_miptree_map
**map
;
3531 map
= &mt
->level
[level
].slice
[slice
].map
;
3537 can_blit_slice(struct intel_mipmap_tree
*mt
,
3538 unsigned int level
, unsigned int slice
)
3540 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3541 if (mt
->surf
.row_pitch
>= 32768)
3548 use_intel_mipree_map_blit(struct brw_context
*brw
,
3549 struct intel_mipmap_tree
*mt
,
3554 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3556 if (devinfo
->has_llc
&&
3557 /* It's probably not worth swapping to the blit ring because of
3558 * all the overhead involved.
3560 !(mode
& GL_MAP_WRITE_BIT
) &&
3562 (mt
->surf
.tiling
== ISL_TILING_X
||
3563 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3564 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3565 /* Fast copy blit on skl+ supports all tiling formats. */
3566 devinfo
->gen
>= 9) &&
3567 can_blit_slice(mt
, level
, slice
))
3570 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3571 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3572 assert(can_blit_slice(mt
, level
, slice
));
3580 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3581 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3582 * arithmetic overflow.
3584 * If you call this function and use \a out_stride, then you're doing pointer
3585 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3586 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3587 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3588 * which usually have type uint32_t or GLuint.
3591 intel_miptree_map(struct brw_context
*brw
,
3592 struct intel_mipmap_tree
*mt
,
3601 ptrdiff_t *out_stride
)
3603 struct intel_miptree_map
*map
;
3605 assert(mt
->surf
.samples
== 1);
3607 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3614 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3615 map
->mode
& GL_MAP_WRITE_BIT
);
3617 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3618 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3619 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3620 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3621 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3622 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3623 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3624 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3625 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3626 #if defined(USE_SSE41)
3627 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3628 !mt
->compressed
&& cpu_has_sse4_1
&&
3629 (mt
->surf
.row_pitch
% 16 == 0)) {
3630 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3633 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3636 *out_ptr
= map
->ptr
;
3637 *out_stride
= map
->stride
;
3639 if (map
->ptr
== NULL
)
3640 intel_miptree_release_map(mt
, level
, slice
);
3644 intel_miptree_unmap(struct brw_context
*brw
,
3645 struct intel_mipmap_tree
*mt
,
3649 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3651 assert(mt
->surf
.samples
== 1);
3656 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3657 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3659 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3660 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3661 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3662 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3663 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3664 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3665 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3666 } else if (map
->linear_mt
) {
3667 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3668 #if defined(USE_SSE41)
3669 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3670 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3673 intel_miptree_unmap_gtt(mt
);
3676 intel_miptree_release_map(mt
, level
, slice
);
3680 get_isl_surf_dim(GLenum target
)
3684 case GL_TEXTURE_1D_ARRAY
:
3685 return ISL_SURF_DIM_1D
;
3688 case GL_TEXTURE_2D_ARRAY
:
3689 case GL_TEXTURE_RECTANGLE
:
3690 case GL_TEXTURE_CUBE_MAP
:
3691 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3692 case GL_TEXTURE_2D_MULTISAMPLE
:
3693 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3694 case GL_TEXTURE_EXTERNAL_OES
:
3695 return ISL_SURF_DIM_2D
;
3698 return ISL_SURF_DIM_3D
;
3701 unreachable("Invalid texture target");
3705 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3706 enum isl_tiling tiling
, GLenum target
)
3710 case GL_TEXTURE_1D_ARRAY
:
3711 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3712 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3715 case GL_TEXTURE_2D_ARRAY
:
3716 case GL_TEXTURE_RECTANGLE
:
3717 case GL_TEXTURE_2D_MULTISAMPLE
:
3718 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3719 case GL_TEXTURE_EXTERNAL_OES
:
3720 return ISL_DIM_LAYOUT_GEN4_2D
;
3722 case GL_TEXTURE_CUBE_MAP
:
3723 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3724 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3725 ISL_DIM_LAYOUT_GEN4_2D
);
3728 return (devinfo
->gen
>= 9 ?
3729 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3732 unreachable("Invalid texture target");
3736 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3737 const struct intel_mipmap_tree
*mt
)
3740 return ISL_AUX_USAGE_HIZ
;
3743 return ISL_AUX_USAGE_NONE
;
3745 return mt
->aux_usage
;