2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 /* MCS compression only applies to multisampled miptrees */
66 if (mt
->surf
.samples
<= 1)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(mt
->format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
100 intel_tiling_supports_ccs(const struct brw_context
*brw
,
101 enum isl_tiling tiling
)
103 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
104 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
106 * - Support is limited to tiled render targets.
108 * Gen9 changes the restriction to Y-tile only.
111 return tiling
== ISL_TILING_Y0
;
112 else if (brw
->gen
>= 7)
113 return tiling
!= ISL_TILING_LINEAR
;
119 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
120 * can be used. This doesn't (and should not) inspect any of the properties of
123 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
124 * beneath the "Fast Color Clear" bullet (p326):
126 * - Support is for non-mip-mapped and non-array surface types only.
128 * And then later, on p327:
130 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
133 * From the Skylake documentation, it is made clear that X-tiling is no longer
136 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
140 intel_miptree_supports_ccs(struct brw_context
*brw
,
141 const struct intel_mipmap_tree
*mt
)
143 /* MCS support does not exist prior to Gen7 */
147 /* This function applies only to non-multisampled render targets. */
148 if (mt
->surf
.samples
> 1)
151 /* MCS is only supported for color buffers */
152 switch (_mesa_get_format_base_format(mt
->format
)) {
153 case GL_DEPTH_COMPONENT
:
154 case GL_DEPTH_STENCIL
:
155 case GL_STENCIL_INDEX
:
159 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
162 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
163 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
164 mt
->surf
.logical_level0_px
.depth
> 1;
167 /* Multisample surfaces with the CMS layout are not layered surfaces,
168 * yet still have physical_depth0 > 1. Assert that we don't
169 * accidentally reject a multisampled surface here. We should have
170 * rejected it earlier by explicitly checking the sample count.
172 assert(mt
->surf
.samples
== 1);
175 /* Handle the hardware restrictions...
177 * All GENs have the following restriction: "MCS buffer for non-MSRT is
178 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
180 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
181 * Non-MultiSampler Render Target Restrictions) Support is for
182 * non-mip-mapped and non-array surface types only.
184 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
185 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
186 * surfaces are supported with MCS buffer layout with these alignments in
187 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
189 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
190 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
191 * surfaces are supported with MCS buffer layout with these alignments in
192 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
194 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
197 /* There's no point in using an MCS buffer if the surface isn't in a
200 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 intel_tiling_supports_hiz(const struct brw_context
*brw
,
208 enum isl_tiling tiling
)
213 return tiling
== ISL_TILING_Y0
;
217 intel_miptree_supports_hiz(const struct brw_context
*brw
,
218 const struct intel_mipmap_tree
*mt
)
223 switch (mt
->format
) {
224 case MESA_FORMAT_Z_FLOAT32
:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
227 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
228 case MESA_FORMAT_Z_UNORM16
:
236 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
237 const struct intel_mipmap_tree
*mt
)
242 /* For now compression is only enabled for integer formats even though
243 * there exist supported floating point formats also. This is a heuristic
244 * decision based on current public benchmarks. In none of the cases these
245 * formats provided any improvement but a few cases were seen to regress.
246 * Hence these are left to to be enabled in the future when they are known
249 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
252 if (!intel_miptree_supports_ccs(brw
, mt
))
255 /* Many window system buffers are sRGB even if they are never rendered as
256 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
257 * surface is used as sRGB, we fall back to CCS_D.
259 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
260 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
261 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
265 * Determine depth format corresponding to a depth+stencil format,
266 * for separate stencil.
269 intel_depth_format_for_depthstencil_format(mesa_format format
) {
271 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
272 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
273 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
274 return MESA_FORMAT_Z_FLOAT32
;
281 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
282 unsigned depth0
, struct intel_mipmap_level
*table
)
284 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
286 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
288 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
289 if (!table
[level
].slice
)
296 for (unsigned level
= first_level
; level
<= last_level
; level
++)
297 free(table
[level
].slice
);
303 needs_separate_stencil(const struct brw_context
*brw
,
304 struct intel_mipmap_tree
*mt
,
307 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
310 if (brw
->must_use_separate_stencil
)
313 return brw
->has_separate_stencil
&&
314 intel_miptree_supports_hiz(brw
, mt
);
318 * Choose the aux usage for this miptree. This function must be called fairly
319 * late in the miptree create process after we have a tiling.
322 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
323 struct intel_mipmap_tree
*mt
)
325 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
327 if (intel_miptree_supports_mcs(brw
, mt
)) {
328 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
329 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
330 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
331 intel_miptree_supports_ccs(brw
, mt
)) {
332 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
333 intel_miptree_supports_ccs_e(brw
, mt
)) {
334 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
336 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
338 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
339 intel_miptree_supports_hiz(brw
, mt
)) {
340 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
343 /* We can do fast-clear on all auxiliary surface types that are
344 * allocated through the normal texture creation paths.
346 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
347 mt
->supports_fast_clear
= true;
352 * Choose an appropriate uncompressed format for a requested
353 * compressed format, if unsupported.
356 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
358 /* No need to lower ETC formats on these platforms,
359 * they are supported natively.
361 if (brw
->gen
>= 8 || brw
->is_baytrail
)
365 case MESA_FORMAT_ETC1_RGB8
:
366 return MESA_FORMAT_R8G8B8X8_UNORM
;
367 case MESA_FORMAT_ETC2_RGB8
:
368 return MESA_FORMAT_R8G8B8X8_UNORM
;
369 case MESA_FORMAT_ETC2_SRGB8
:
370 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
371 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
372 return MESA_FORMAT_B8G8R8A8_SRGB
;
373 case MESA_FORMAT_ETC2_RGBA8_EAC
:
374 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
375 return MESA_FORMAT_R8G8B8A8_UNORM
;
376 case MESA_FORMAT_ETC2_R11_EAC
:
377 return MESA_FORMAT_R_UNORM16
;
378 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
379 return MESA_FORMAT_R_SNORM16
;
380 case MESA_FORMAT_ETC2_RG11_EAC
:
381 return MESA_FORMAT_R16G16_UNORM
;
382 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
383 return MESA_FORMAT_R16G16_SNORM
;
385 /* Non ETC1 / ETC2 format */
391 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
393 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
394 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
396 return mt
->surf
.logical_level0_px
.array_len
;
400 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
402 /* In case of physical dimensions one needs to consider also the layout.
403 * See isl_calc_phys_level0_extent_sa().
405 if (surf
->dim
!= ISL_SURF_DIM_3D
)
406 return surf
->phys_level0_sa
.array_len
;
408 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
409 return minify(surf
->phys_level0_sa
.array_len
, level
);
411 return minify(surf
->phys_level0_sa
.depth
, level
);
414 /** \brief Assert that the level and layer are valid for the miptree. */
416 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
424 assert(level
>= mt
->first_level
);
425 assert(level
<= mt
->last_level
);
426 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
429 static enum isl_aux_state
**
430 create_aux_state_map(struct intel_mipmap_tree
*mt
,
431 enum isl_aux_state initial
)
433 const uint32_t levels
= mt
->last_level
+ 1;
435 uint32_t total_slices
= 0;
436 for (uint32_t level
= 0; level
< levels
; level
++)
437 total_slices
+= brw_get_num_logical_layers(mt
, level
);
439 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
441 /* We're going to allocate a single chunk of data for both the per-level
442 * reference array and the arrays of aux_state. This makes cleanup
443 * significantly easier.
445 const size_t total_size
= per_level_array_size
+
446 total_slices
* sizeof(enum isl_aux_state
);
447 void *data
= malloc(total_size
);
451 enum isl_aux_state
**per_level_arr
= data
;
452 enum isl_aux_state
*s
= data
+ per_level_array_size
;
453 for (uint32_t level
= 0; level
< levels
; level
++) {
454 per_level_arr
[level
] = s
;
455 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
456 for (uint32_t a
= 0; a
< level_layers
; a
++)
459 assert((void *)s
== data
+ total_size
);
461 return per_level_arr
;
465 free_aux_state_map(enum isl_aux_state
**state
)
471 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
472 enum isl_tiling tiling
, unsigned samples
)
477 if (tiling
== ISL_TILING_LINEAR
)
480 /* If the width is much smaller than a tile, don't bother tiling. */
484 if (ALIGN(row_pitch
, 512) >= 32768) {
485 perf_debug("row pitch %u too large to blit, falling back to untiled",
494 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
495 enum isl_tiling tiling
)
497 /* If the BO is too large to fit in the aperture, we need to use the
498 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
499 * handle Y-tiling, so we need to fall back to X.
501 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
502 tiling
== ISL_TILING_Y0
)
508 static struct intel_mipmap_tree
*
509 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
510 unsigned first_level
, unsigned last_level
,
511 unsigned width0
, unsigned height0
, unsigned depth0
,
512 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
513 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
514 unsigned row_pitch
, struct brw_bo
*bo
)
516 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
520 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
528 if (target
== GL_TEXTURE_CUBE_MAP
||
529 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
530 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
532 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
534 _mesa_enum_to_string(target
),
535 _mesa_get_format_name(format
),
536 num_samples
, width0
, height0
, depth0
,
537 first_level
, last_level
, mt
);
539 struct isl_surf_init_info init_info
= {
540 .dim
= get_isl_surf_dim(target
),
541 .format
= translate_tex_format(brw
, format
, false),
544 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
545 .levels
= last_level
- first_level
+ 1,
546 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
547 .samples
= num_samples
,
548 .row_pitch
= row_pitch
,
549 .usage
= isl_usage_flags
,
550 .tiling_flags
= tiling_flags
,
553 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
556 /* In case caller doesn't specifically request Y-tiling (needed
557 * unconditionally for depth), check for corner cases needing special
560 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
561 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
562 mt
->surf
.tiling
, mt
->surf
.samples
)) {
563 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
564 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
566 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
567 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
568 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
574 * the size may not be multiple of row_pitch.
575 * See isl_apply_surface_padding().
577 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
578 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
581 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
583 isl_tiling_to_i915_tiling(
585 mt
->surf
.row_pitch
, alloc_flags
);
592 mt
->first_level
= first_level
;
593 mt
->last_level
= last_level
;
596 mt
->aux_state
= NULL
;
597 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
598 mt
->compressed
= _mesa_is_format_compressed(format
);
603 intel_miptree_release(&mt
);
608 make_separate_stencil_surface(struct brw_context
*brw
,
609 struct intel_mipmap_tree
*mt
)
611 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
612 0, mt
->surf
.levels
- 1,
613 mt
->surf
.logical_level0_px
.width
,
614 mt
->surf
.logical_level0_px
.height
,
615 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
616 mt
->surf
.logical_level0_px
.depth
:
617 mt
->surf
.logical_level0_px
.array_len
,
618 mt
->surf
.samples
, ISL_TILING_W_BIT
,
619 ISL_SURF_USAGE_STENCIL_BIT
|
620 ISL_SURF_USAGE_TEXTURE_BIT
,
621 BO_ALLOC_FOR_RENDER
, 0, NULL
);
626 mt
->stencil_mt
->r8stencil_needs_update
= true;
631 static struct intel_mipmap_tree
*
632 miptree_create(struct brw_context
*brw
,
641 enum intel_miptree_create_flags flags
)
643 if (format
== MESA_FORMAT_S_UINT8
)
644 return make_surface(brw
, target
, format
, first_level
, last_level
,
645 width0
, height0
, depth0
, num_samples
,
647 ISL_SURF_USAGE_STENCIL_BIT
|
648 ISL_SURF_USAGE_TEXTURE_BIT
,
653 const GLenum base_format
= _mesa_get_format_base_format(format
);
654 if ((base_format
== GL_DEPTH_COMPONENT
||
655 base_format
== GL_DEPTH_STENCIL
) &&
656 !(flags
& MIPTREE_CREATE_LINEAR
)) {
657 /* Fix up the Z miptree format for how we're splitting out separate
658 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
660 const mesa_format depth_only_format
=
661 intel_depth_format_for_depthstencil_format(format
);
662 struct intel_mipmap_tree
*mt
= make_surface(
663 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
664 first_level
, last_level
,
665 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
666 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_FOR_RENDER
, 0, NULL
);
669 if (needs_separate_stencil(brw
, mt
, format
) &&
670 !make_separate_stencil_surface(brw
, mt
)) {
671 intel_miptree_release(&mt
);
675 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
676 intel_miptree_choose_aux_usage(brw
, mt
);
681 mesa_format tex_format
= format
;
682 mesa_format etc_format
= MESA_FORMAT_NONE
;
683 uint32_t alloc_flags
= 0;
685 format
= intel_lower_compressed_format(brw
, format
);
687 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
689 if (flags
& MIPTREE_CREATE_BUSY
)
690 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
692 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
693 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
695 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
697 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
699 struct intel_mipmap_tree
*mt
= make_surface(
701 first_level
, last_level
,
702 width0
, height0
, depth0
,
703 num_samples
, tiling_flags
,
704 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
705 ISL_SURF_USAGE_TEXTURE_BIT
,
706 alloc_flags
, 0, NULL
);
710 mt
->etc_format
= etc_format
;
712 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
713 intel_miptree_choose_aux_usage(brw
, mt
);
718 struct intel_mipmap_tree
*
719 intel_miptree_create(struct brw_context
*brw
,
728 enum intel_miptree_create_flags flags
)
730 assert(num_samples
> 0);
732 struct intel_mipmap_tree
*mt
= miptree_create(
734 first_level
, last_level
,
735 width0
, height0
, depth0
, num_samples
,
742 if (!intel_miptree_alloc_aux(brw
, mt
)) {
743 intel_miptree_release(&mt
);
750 struct intel_mipmap_tree
*
751 intel_miptree_create_for_bo(struct brw_context
*brw
,
759 enum intel_miptree_create_flags flags
)
761 struct intel_mipmap_tree
*mt
;
762 uint32_t tiling
, swizzle
;
763 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
764 const GLenum base_format
= _mesa_get_format_base_format(format
);
766 if ((base_format
== GL_DEPTH_COMPONENT
||
767 base_format
== GL_DEPTH_STENCIL
)) {
768 const mesa_format depth_only_format
=
769 intel_depth_format_for_depthstencil_format(format
);
770 mt
= make_surface(brw
, target
,
771 brw
->gen
>= 6 ? depth_only_format
: format
,
772 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
773 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
774 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
778 brw_bo_reference(bo
);
780 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
781 intel_miptree_choose_aux_usage(brw
, mt
);
784 } else if (format
== MESA_FORMAT_S_UINT8
) {
785 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
786 0, 0, width
, height
, depth
, 1,
788 ISL_SURF_USAGE_STENCIL_BIT
|
789 ISL_SURF_USAGE_TEXTURE_BIT
,
790 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
794 assert(bo
->size
>= mt
->surf
.size
);
796 brw_bo_reference(bo
);
800 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
802 /* Nothing will be able to use this miptree with the BO if the offset isn't
805 if (tiling
!= I915_TILING_NONE
)
806 assert(offset
% 4096 == 0);
808 /* miptrees can't handle negative pitch. If you need flipping of images,
809 * that's outside of the scope of the mt.
813 /* The BO already has a tiling format and we shouldn't confuse the lower
814 * layers by making it try to find a tiling format again.
816 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
818 mt
= make_surface(brw
, target
, format
,
819 0, 0, width
, height
, depth
, 1,
820 1lu << isl_tiling_from_i915_tiling(tiling
),
821 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
822 ISL_SURF_USAGE_TEXTURE_BIT
,
827 brw_bo_reference(bo
);
831 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
832 intel_miptree_choose_aux_usage(brw
, mt
);
834 if (!intel_miptree_alloc_aux(brw
, mt
)) {
835 intel_miptree_release(&mt
);
843 static struct intel_mipmap_tree
*
844 miptree_create_for_planar_image(struct brw_context
*brw
,
845 __DRIimage
*image
, GLenum target
)
847 const struct intel_image_format
*f
= image
->planar_format
;
848 struct intel_mipmap_tree
*planar_mt
= NULL
;
850 for (int i
= 0; i
< f
->nplanes
; i
++) {
851 const int index
= f
->planes
[i
].buffer_index
;
852 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
853 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
854 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
855 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
857 /* Disable creation of the texture's aux buffers because the driver
858 * exposes no EGL API to manage them. That is, there is no API for
859 * resolving the aux buffer's content to the main buffer nor for
860 * invalidating the aux buffer's content.
862 struct intel_mipmap_tree
*mt
=
863 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
864 image
->offsets
[index
],
866 image
->strides
[index
],
867 MIPTREE_CREATE_NO_AUX
);
876 planar_mt
->plane
[i
- 1] = mt
;
883 create_ccs_buf_for_image(struct brw_context
*brw
,
885 struct intel_mipmap_tree
*mt
,
886 enum isl_aux_state initial_state
)
888 struct isl_surf temp_ccs_surf
;
890 /* CCS is only supported for very simple miptrees */
891 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
892 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
893 assert(mt
->surf
.samples
== 1);
894 assert(mt
->surf
.levels
== 1);
895 assert(mt
->surf
.logical_level0_px
.depth
== 1);
896 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
897 assert(mt
->first_level
== 0);
898 assert(mt
->last_level
== 0);
900 /* We shouldn't already have a CCS */
901 assert(!mt
->mcs_buf
);
903 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
907 assert(image
->aux_offset
< image
->bo
->size
);
908 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
910 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
911 if (mt
->mcs_buf
== NULL
)
914 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
915 if (!mt
->aux_state
) {
921 mt
->mcs_buf
->bo
= image
->bo
;
922 brw_bo_reference(image
->bo
);
924 mt
->mcs_buf
->offset
= image
->aux_offset
;
925 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
926 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
927 mt
->mcs_buf
->qpitch
= 0;
928 mt
->mcs_buf
->surf
= temp_ccs_surf
;
933 struct intel_mipmap_tree
*
934 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
935 __DRIimage
*image
, GLenum target
,
936 enum isl_colorspace colorspace
,
937 bool is_winsys_image
)
939 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
940 assert(colorspace
== ISL_COLORSPACE_NONE
||
941 colorspace
== ISL_COLORSPACE_YUV
);
942 return miptree_create_for_planar_image(brw
, image
, target
);
945 if (image
->planar_format
)
946 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
948 mesa_format format
= image
->format
;
949 switch (colorspace
) {
950 case ISL_COLORSPACE_NONE
:
951 /* Keep the image format unmodified */
954 case ISL_COLORSPACE_LINEAR
:
955 format
=_mesa_get_srgb_format_linear(format
);
958 case ISL_COLORSPACE_SRGB
:
959 format
=_mesa_get_linear_format_srgb(format
);
963 unreachable("Inalid colorspace for non-planar image");
966 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
967 /* The texture storage paths in core Mesa detect if the driver does not
968 * support the user-requested format, and then searches for a
969 * fallback format. The DRIimage code bypasses core Mesa, though. So we
970 * do the fallbacks here for important formats.
972 * We must support DRM_FOURCC_XBGR8888 textures because the Android
973 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
974 * the Chrome OS compositor consumes as dma_buf EGLImages.
976 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
979 if (!brw
->ctx
.TextureFormatSupported
[format
])
982 const struct isl_drm_modifier_info
*mod_info
=
983 isl_drm_modifier_get_info(image
->modifier
);
985 enum intel_miptree_create_flags mt_create_flags
= 0;
987 /* If this image comes in from a window system, we have different
988 * requirements than if it comes in via an EGL import operation. Window
989 * system images can use any form of auxiliary compression we wish because
990 * they get "flushed" before being handed off to the window system and we
991 * have the opportunity to do resolves. Non window-system images, on the
992 * other hand, have no resolve point so we can't have aux without a
995 if (!is_winsys_image
)
996 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
998 /* If we have a modifier which specifies aux, don't create one yet */
999 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1000 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1002 /* Disable creation of the texture's aux buffers because the driver exposes
1003 * no EGL API to manage them. That is, there is no API for resolving the aux
1004 * buffer's content to the main buffer nor for invalidating the aux buffer's
1007 struct intel_mipmap_tree
*mt
=
1008 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1009 image
->offset
, image
->width
, image
->height
, 1,
1010 image
->pitch
, mt_create_flags
);
1014 mt
->target
= target
;
1015 mt
->level
[0].level_x
= image
->tile_x
;
1016 mt
->level
[0].level_y
= image
->tile_y
;
1018 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1019 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1020 * trouble resolving back to destination image due to alignment issues.
1022 if (!brw
->has_surface_tile_offset
) {
1023 uint32_t draw_x
, draw_y
;
1024 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1026 if (draw_x
!= 0 || draw_y
!= 0) {
1027 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1028 intel_miptree_release(&mt
);
1033 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1034 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1036 mt
->aux_usage
= mod_info
->aux_usage
;
1037 /* If we are a window system buffer, then we can support fast-clears
1038 * even if the modifier doesn't support them by doing a partial resolve
1039 * as part of the flush operation.
1041 mt
->supports_fast_clear
=
1042 is_winsys_image
|| mod_info
->supports_clear_color
;
1044 /* We don't know the actual state of the surface when we get it but we
1045 * can make a pretty good guess based on the modifier. What we do know
1046 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1047 * a worst case of compression.
1049 enum isl_aux_state initial_state
=
1050 mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1051 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1053 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1054 intel_miptree_release(&mt
);
1059 /* If this is a window-system image, then we can no longer assume it's
1060 * cache-coherent because it may suddenly get scanned out which destroys
1063 if (is_winsys_image
)
1064 image
->bo
->cache_coherent
= false;
1070 * For a singlesample renderbuffer, this simply wraps the given BO with a
1073 * For a multisample renderbuffer, this wraps the window system's
1074 * (singlesample) BO with a singlesample miptree attached to the
1075 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1076 * that will contain the actual rendering (which is lazily resolved to
1077 * irb->singlesample_mt).
1080 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1081 struct intel_renderbuffer
*irb
,
1082 struct intel_mipmap_tree
*singlesample_mt
,
1083 uint32_t width
, uint32_t height
,
1086 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1087 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1088 mesa_format format
= rb
->Format
;
1089 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1091 /* Only the front and back buffers, which are color buffers, are allocated
1092 * through the image loader.
1094 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1095 _mesa_get_format_base_format(format
) == GL_RGBA
);
1097 assert(singlesample_mt
);
1099 if (num_samples
== 1) {
1100 intel_miptree_release(&irb
->mt
);
1101 irb
->mt
= singlesample_mt
;
1103 assert(!irb
->singlesample_mt
);
1105 intel_miptree_release(&irb
->singlesample_mt
);
1106 irb
->singlesample_mt
= singlesample_mt
;
1109 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1110 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1111 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1116 if (!multisample_mt
)
1119 irb
->need_downsample
= false;
1120 intel_miptree_release(&irb
->mt
);
1121 irb
->mt
= multisample_mt
;
1127 intel_miptree_release(&irb
->mt
);
1131 struct intel_mipmap_tree
*
1132 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1136 uint32_t num_samples
)
1138 struct intel_mipmap_tree
*mt
;
1140 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1142 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1143 width
, height
, depth
, num_samples
,
1144 MIPTREE_CREATE_BUSY
);
1151 intel_miptree_release(&mt
);
1156 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1157 struct intel_mipmap_tree
*src
)
1162 intel_miptree_release(dst
);
1166 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1173 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1175 if (aux_buf
== NULL
)
1178 brw_bo_unreference(aux_buf
->bo
);
1184 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1189 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1190 if (--(*mt
)->refcount
<= 0) {
1193 DBG("%s deleting %p\n", __func__
, *mt
);
1195 brw_bo_unreference((*mt
)->bo
);
1196 intel_miptree_release(&(*mt
)->stencil_mt
);
1197 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1198 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1199 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1200 free_aux_state_map((*mt
)->aux_state
);
1202 intel_miptree_release(&(*mt
)->plane
[0]);
1203 intel_miptree_release(&(*mt
)->plane
[1]);
1205 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1206 free((*mt
)->level
[i
].slice
);
1216 intel_get_image_dims(struct gl_texture_image
*image
,
1217 int *width
, int *height
, int *depth
)
1219 switch (image
->TexObject
->Target
) {
1220 case GL_TEXTURE_1D_ARRAY
:
1221 /* For a 1D Array texture the OpenGL API will treat the image height as
1222 * the number of array slices. For Intel hardware, we treat the 1D array
1223 * as a 2D Array with a height of 1. So, here we want to swap image
1226 assert(image
->Depth
== 1);
1227 *width
= image
->Width
;
1229 *depth
= image
->Height
;
1231 case GL_TEXTURE_CUBE_MAP
:
1232 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1233 * though we really have 6 slices.
1235 assert(image
->Depth
== 1);
1236 *width
= image
->Width
;
1237 *height
= image
->Height
;
1241 *width
= image
->Width
;
1242 *height
= image
->Height
;
1243 *depth
= image
->Depth
;
1249 * Can the image be pulled into a unified mipmap tree? This mirrors
1250 * the completeness test in a lot of ways.
1252 * Not sure whether I want to pass gl_texture_image here.
1255 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1256 struct gl_texture_image
*image
)
1258 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1259 GLuint level
= intelImage
->base
.Base
.Level
;
1260 int width
, height
, depth
;
1262 /* glTexImage* choose the texture object based on the target passed in, and
1263 * objects can't change targets over their lifetimes, so this should be
1266 assert(image
->TexObject
->Target
== mt
->target
);
1268 mesa_format mt_format
= mt
->format
;
1269 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1270 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1271 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1272 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1273 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1274 mt_format
= mt
->etc_format
;
1276 if (image
->TexFormat
!= mt_format
)
1279 intel_get_image_dims(image
, &width
, &height
, &depth
);
1281 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1284 if (level
>= mt
->surf
.levels
)
1287 const unsigned level_depth
=
1288 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1289 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1290 mt
->surf
.logical_level0_px
.array_len
;
1292 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1293 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1294 depth
== level_depth
&&
1295 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1299 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1300 GLuint level
, GLuint slice
,
1301 GLuint
*x
, GLuint
*y
)
1303 if (level
== 0 && slice
== 0) {
1304 *x
= mt
->level
[0].level_x
;
1305 *y
= mt
->level
[0].level_y
;
1309 uint32_t x_offset_sa
, y_offset_sa
;
1311 /* Miptree itself can have an offset only if it represents a single
1312 * slice in an imported buffer object.
1313 * See intel_miptree_create_for_dri_image().
1315 assert(mt
->level
[0].level_x
== 0);
1316 assert(mt
->level
[0].level_y
== 0);
1318 /* Given level is relative to level zero while the miptree may be
1319 * represent just a subset of all levels starting from 'first_level'.
1321 assert(level
>= mt
->first_level
);
1322 level
-= mt
->first_level
;
1324 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1325 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1326 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1327 &x_offset_sa
, &y_offset_sa
);
1335 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1336 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1337 * and tile_h is set to 1.
1340 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1341 uint32_t *tile_w
, uint32_t *tile_h
)
1352 case ISL_TILING_LINEAR
:
1357 unreachable("not reached");
1363 * This function computes masks that may be used to select the bits of the X
1364 * and Y coordinates that indicate the offset within a tile. If the BO is
1365 * untiled, the masks are set to 0.
1368 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1369 uint32_t *mask_x
, uint32_t *mask_y
)
1371 uint32_t tile_w_bytes
, tile_h
;
1373 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1375 *mask_x
= tile_w_bytes
/ cpp
- 1;
1376 *mask_y
= tile_h
- 1;
1380 * Compute the offset (in bytes) from the start of the BO to the given x
1381 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1382 * multiples of the tile size.
1385 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1386 uint32_t x
, uint32_t y
)
1389 uint32_t pitch
= mt
->surf
.row_pitch
;
1391 switch (mt
->surf
.tiling
) {
1393 unreachable("not reached");
1394 case ISL_TILING_LINEAR
:
1395 return y
* pitch
+ x
* cpp
;
1397 assert((x
% (512 / cpp
)) == 0);
1398 assert((y
% 8) == 0);
1399 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1401 assert((x
% (128 / cpp
)) == 0);
1402 assert((y
% 32) == 0);
1403 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1408 * Rendering with tiled buffers requires that the base address of the buffer
1409 * be aligned to a page boundary. For renderbuffers, and sometimes with
1410 * textures, we may want the surface to point at a texture image level that
1411 * isn't at a page boundary.
1413 * This function returns an appropriately-aligned base offset
1414 * according to the tiling restrictions, plus any required x/y offset
1418 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1419 GLuint level
, GLuint slice
,
1424 uint32_t mask_x
, mask_y
;
1426 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1427 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1429 *tile_x
= x
& mask_x
;
1430 *tile_y
= y
& mask_y
;
1432 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1436 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1437 struct intel_mipmap_tree
*src_mt
,
1438 unsigned src_level
, unsigned src_layer
,
1439 struct intel_mipmap_tree
*dst_mt
,
1440 unsigned dst_level
, unsigned dst_layer
,
1441 unsigned width
, unsigned height
)
1444 ptrdiff_t src_stride
, dst_stride
;
1445 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1447 intel_miptree_map(brw
, src_mt
,
1448 src_level
, src_layer
,
1451 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1454 intel_miptree_map(brw
, dst_mt
,
1455 dst_level
, dst_layer
,
1458 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1462 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1463 _mesa_get_format_name(src_mt
->format
),
1464 src_mt
, src
, src_stride
,
1465 _mesa_get_format_name(dst_mt
->format
),
1466 dst_mt
, dst
, dst_stride
,
1469 int row_size
= cpp
* width
;
1470 if (src_stride
== row_size
&&
1471 dst_stride
== row_size
) {
1472 memcpy(dst
, src
, row_size
* height
);
1474 for (int i
= 0; i
< height
; i
++) {
1475 memcpy(dst
, src
, row_size
);
1481 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1482 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1484 /* Don't forget to copy the stencil data over, too. We could have skipped
1485 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1486 * shuffling the two data sources in/out of temporary storage instead of
1487 * the direct mapping we get this way.
1489 if (dst_mt
->stencil_mt
) {
1490 assert(src_mt
->stencil_mt
);
1491 intel_miptree_copy_slice_sw(brw
,
1492 src_mt
->stencil_mt
, src_level
, src_layer
,
1493 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1499 intel_miptree_copy_slice(struct brw_context
*brw
,
1500 struct intel_mipmap_tree
*src_mt
,
1501 unsigned src_level
, unsigned src_layer
,
1502 struct intel_mipmap_tree
*dst_mt
,
1503 unsigned dst_level
, unsigned dst_layer
)
1506 mesa_format format
= src_mt
->format
;
1507 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1508 src_level
- src_mt
->first_level
);
1509 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1510 src_level
- src_mt
->first_level
);
1512 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1513 src_level
- src_mt
->first_level
));
1515 assert(src_mt
->format
== dst_mt
->format
);
1517 if (dst_mt
->compressed
) {
1519 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1520 height
= ALIGN_NPOT(height
, j
) / j
;
1521 width
= ALIGN_NPOT(width
, i
) / i
;
1524 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1525 * below won't apply since we can't do the depth's Y tiling or the
1526 * stencil's W tiling in the blitter.
1528 if (src_mt
->stencil_mt
) {
1529 intel_miptree_copy_slice_sw(brw
,
1530 src_mt
, src_level
, src_layer
,
1531 dst_mt
, dst_level
, dst_layer
,
1536 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1537 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1539 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1542 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1543 _mesa_get_format_name(src_mt
->format
),
1544 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1545 _mesa_get_format_name(dst_mt
->format
),
1546 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1549 if (!intel_miptree_blit(brw
,
1550 src_mt
, src_level
, src_layer
, 0, 0, false,
1551 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1552 width
, height
, GL_COPY
)) {
1553 perf_debug("miptree validate blit for %s failed\n",
1554 _mesa_get_format_name(format
));
1556 intel_miptree_copy_slice_sw(brw
,
1557 src_mt
, src_level
, src_layer
,
1558 dst_mt
, dst_level
, dst_layer
,
1564 * Copies the image's current data to the given miptree, and associates that
1565 * miptree with the image.
1567 * If \c invalidate is true, then the actual image data does not need to be
1568 * copied, but the image still needs to be associated to the new miptree (this
1569 * is set to true if we're about to clear the image).
1572 intel_miptree_copy_teximage(struct brw_context
*brw
,
1573 struct intel_texture_image
*intelImage
,
1574 struct intel_mipmap_tree
*dst_mt
,
1577 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1578 struct intel_texture_object
*intel_obj
=
1579 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1580 int level
= intelImage
->base
.Base
.Level
;
1581 const unsigned face
= intelImage
->base
.Base
.Face
;
1582 unsigned start_layer
, end_layer
;
1584 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1586 assert(intelImage
->base
.Base
.Height
);
1588 end_layer
= intelImage
->base
.Base
.Height
- 1;
1589 } else if (face
> 0) {
1593 assert(intelImage
->base
.Base
.Depth
);
1595 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1599 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1600 intel_miptree_copy_slice(brw
,
1606 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1607 intel_obj
->needs_validate
= true;
1611 intel_miptree_init_mcs(struct brw_context
*brw
,
1612 struct intel_mipmap_tree
*mt
,
1615 assert(mt
->mcs_buf
!= NULL
);
1617 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1619 * When MCS buffer is enabled and bound to MSRT, it is required that it
1620 * is cleared prior to any rendering.
1622 * Since we don't use the MCS buffer for any purpose other than rendering,
1623 * it makes sense to just clear it immediately upon allocation.
1625 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1627 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1628 if (unlikely(map
== NULL
)) {
1629 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1630 brw_bo_unreference(mt
->mcs_buf
->bo
);
1635 memset(data
, init_value
, mt
->mcs_buf
->size
);
1636 brw_bo_unmap(mt
->mcs_buf
->bo
);
1639 static struct intel_miptree_aux_buffer
*
1640 intel_alloc_aux_buffer(struct brw_context
*brw
,
1642 const struct isl_surf
*aux_surf
,
1643 uint32_t alloc_flags
,
1644 struct intel_mipmap_tree
*mt
)
1646 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1650 buf
->size
= aux_surf
->size
;
1651 buf
->pitch
= aux_surf
->row_pitch
;
1652 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1654 /* ISL has stricter set of alignment rules then the drm allocator.
1655 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1656 * trying to recalculate based on different format block sizes.
1658 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1659 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1665 buf
->surf
= *aux_surf
;
1671 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1672 struct intel_mipmap_tree
*mt
,
1675 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1676 assert(mt
->mcs_buf
== NULL
);
1677 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1679 /* Multisampled miptrees are only supported for single level. */
1680 assert(mt
->first_level
== 0);
1681 enum isl_aux_state
**aux_state
=
1682 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1686 struct isl_surf temp_mcs_surf
;
1688 MAYBE_UNUSED
bool ok
=
1689 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1692 /* Buffer needs to be initialised requiring the buffer to be immediately
1693 * mapped to cpu space for writing. Therefore do not use the gpu access
1694 * flag which can cause an unnecessary delay if the backing pages happened
1695 * to be just used by the GPU.
1697 const uint32_t alloc_flags
= 0;
1698 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1699 &temp_mcs_surf
, alloc_flags
, mt
);
1705 mt
->aux_state
= aux_state
;
1707 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1713 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1714 struct intel_mipmap_tree
*mt
)
1716 assert(mt
->mcs_buf
== NULL
);
1717 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1718 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1720 struct isl_surf temp_ccs_surf
;
1722 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1725 assert(temp_ccs_surf
.size
&&
1726 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1728 enum isl_aux_state
**aux_state
=
1729 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1733 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1734 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1736 * "If Software wants to enable Color Compression without Fast clear,
1737 * Software needs to initialize MCS with zeros."
1739 * A CCS value of 0 indicates that the corresponding block is in the
1740 * pass-through state which is what we want.
1742 * For CCS_D, on the other hand, we don't care as we're about to perform a
1743 * fast-clear operation. In that case, being hot in caches more useful.
1745 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1746 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1747 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1748 &temp_ccs_surf
, alloc_flags
, mt
);
1754 mt
->aux_state
= aux_state
;
1760 * Helper for intel_miptree_alloc_hiz() that sets
1761 * \c mt->level[level].has_hiz. Return true if and only if
1762 * \c has_hiz was set.
1765 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1766 struct intel_mipmap_tree
*mt
,
1769 assert(mt
->hiz_buf
);
1770 assert(mt
->surf
.size
> 0);
1772 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1773 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1774 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1776 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1777 * and the height is 4 aligned. This allows our HiZ support
1778 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1779 * we can grow the width & height to allow the HiZ op to
1780 * force the proper size alignments.
1782 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1783 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1788 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1789 mt
->level
[level
].has_hiz
= true;
1794 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1795 struct intel_mipmap_tree
*mt
)
1797 assert(mt
->hiz_buf
== NULL
);
1798 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1800 enum isl_aux_state
**aux_state
=
1801 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1805 struct isl_surf temp_hiz_surf
;
1807 MAYBE_UNUSED
bool ok
=
1808 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1811 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1812 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1813 &temp_hiz_surf
, alloc_flags
, mt
);
1820 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1821 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1823 mt
->aux_state
= aux_state
;
1830 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1832 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1833 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1834 * compress clear color so we wait until an actual fast-clear to allocate it.
1837 intel_miptree_alloc_aux(struct brw_context
*brw
,
1838 struct intel_mipmap_tree
*mt
)
1840 switch (mt
->aux_usage
) {
1841 case ISL_AUX_USAGE_NONE
:
1844 case ISL_AUX_USAGE_HIZ
:
1845 assert(!_mesa_is_format_color_format(mt
->format
));
1846 if (!intel_miptree_alloc_hiz(brw
, mt
))
1850 case ISL_AUX_USAGE_MCS
:
1851 assert(_mesa_is_format_color_format(mt
->format
));
1852 assert(mt
->surf
.samples
> 1);
1853 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1857 case ISL_AUX_USAGE_CCS_D
:
1858 /* Since CCS_D can only compress clear color so we wait until an actual
1859 * fast-clear to allocate it.
1863 case ISL_AUX_USAGE_CCS_E
:
1864 assert(_mesa_is_format_color_format(mt
->format
));
1865 assert(mt
->surf
.samples
== 1);
1866 if (!intel_miptree_alloc_ccs(brw
, mt
))
1871 unreachable("Invalid aux usage");
1876 * Can the miptree sample using the hiz buffer?
1879 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1880 struct intel_mipmap_tree
*mt
)
1882 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1883 * so keep things conservative for now and never enable it unless we're SKL+.
1893 /* It seems the hardware won't fallback to the depth buffer if some of the
1894 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1895 * of the texture to be HiZ enabled.
1897 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1898 if (!intel_miptree_level_has_hiz(mt
, level
))
1902 /* If compressed multisampling is enabled, then we use it for the auxiliary
1905 * From the BDW PRM (Volume 2d: Command Reference: Structures
1906 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1908 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1909 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1911 * There is no such blurb for 1D textures, but there is sufficient evidence
1912 * that this is broken on SKL+.
1914 return (mt
->surf
.samples
== 1 &&
1915 mt
->target
!= GL_TEXTURE_3D
&&
1916 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1920 * Does the miptree slice have hiz enabled?
1923 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1925 intel_miptree_check_level_layer(mt
, level
, 0);
1926 return mt
->level
[level
].has_hiz
;
1929 static inline uint32_t
1930 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1931 uint32_t start_level
, uint32_t num_levels
)
1933 assert(start_level
>= mt
->first_level
);
1934 assert(start_level
<= mt
->last_level
);
1936 if (num_levels
== INTEL_REMAINING_LAYERS
)
1937 num_levels
= mt
->last_level
- start_level
+ 1;
1938 /* Check for overflow */
1939 assert(start_level
+ num_levels
>= start_level
);
1940 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1945 static inline uint32_t
1946 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1947 uint32_t start_layer
, uint32_t num_layers
)
1949 assert(level
<= mt
->last_level
);
1951 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1952 assert(start_layer
< total_num_layers
);
1953 if (num_layers
== INTEL_REMAINING_LAYERS
)
1954 num_layers
= total_num_layers
- start_layer
;
1955 /* Check for overflow */
1956 assert(start_layer
+ num_layers
>= start_layer
);
1957 assert(start_layer
+ num_layers
<= total_num_layers
);
1963 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1964 unsigned start_level
, unsigned num_levels
,
1965 unsigned start_layer
, unsigned num_layers
)
1967 assert(_mesa_is_format_color_format(mt
->format
));
1972 /* Clamp the level range to fit the miptree */
1973 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1975 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1976 const uint32_t level
= start_level
+ l
;
1977 const uint32_t level_layers
=
1978 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1979 for (unsigned a
= 0; a
< level_layers
; a
++) {
1980 enum isl_aux_state aux_state
=
1981 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1982 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1983 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1992 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1993 const struct intel_mipmap_tree
*mt
,
1994 unsigned level
, unsigned layer
)
2000 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2001 assert(brw
->gen
>= 8 ||
2002 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2004 /* Compression of arrayed msaa surfaces is supported. */
2005 if (mt
->surf
.samples
> 1)
2008 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2009 assert(brw
->gen
>= 8 ||
2011 mt
->surf
.logical_level0_px
.depth
== 1 &&
2012 mt
->surf
.logical_level0_px
.array_len
== 1));
2018 static enum blorp_fast_clear_op
2019 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2020 enum isl_aux_usage aux_usage
,
2021 bool fast_clear_supported
)
2023 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2025 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2027 assert(ccs_supported
== fast_clear_supported
);
2029 switch (aux_state
) {
2030 case ISL_AUX_STATE_CLEAR
:
2031 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2033 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2035 return BLORP_FAST_CLEAR_OP_NONE
;
2037 case ISL_AUX_STATE_PASS_THROUGH
:
2038 return BLORP_FAST_CLEAR_OP_NONE
;
2040 case ISL_AUX_STATE_RESOLVED
:
2041 case ISL_AUX_STATE_AUX_INVALID
:
2042 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2043 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2047 unreachable("Invalid aux state for CCS_D");
2050 static enum blorp_fast_clear_op
2051 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2052 enum isl_aux_usage aux_usage
,
2053 bool fast_clear_supported
)
2055 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2056 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2057 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2058 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2060 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2061 assert(fast_clear_supported
);
2063 switch (aux_state
) {
2064 case ISL_AUX_STATE_CLEAR
:
2065 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2066 if (fast_clear_supported
)
2067 return BLORP_FAST_CLEAR_OP_NONE
;
2068 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2069 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2071 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2073 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2074 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2075 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2076 else if (!fast_clear_supported
)
2077 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2079 return BLORP_FAST_CLEAR_OP_NONE
;
2081 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2082 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2083 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2085 return BLORP_FAST_CLEAR_OP_NONE
;
2087 case ISL_AUX_STATE_PASS_THROUGH
:
2088 return BLORP_FAST_CLEAR_OP_NONE
;
2090 case ISL_AUX_STATE_RESOLVED
:
2091 case ISL_AUX_STATE_AUX_INVALID
:
2095 unreachable("Invalid aux state for CCS_E");
2099 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2100 struct intel_mipmap_tree
*mt
,
2101 uint32_t level
, uint32_t layer
,
2102 enum isl_aux_usage aux_usage
,
2103 bool fast_clear_supported
)
2105 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2107 enum blorp_fast_clear_op resolve_op
;
2108 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2109 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2110 fast_clear_supported
);
2112 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2113 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2114 fast_clear_supported
);
2117 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2118 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2119 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2121 switch (resolve_op
) {
2122 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2123 /* The CCS full resolve operation destroys the CCS and sets it to the
2124 * pass-through state. (You can also think of this as being both a
2125 * resolve and an ambiguate in one operation.)
2127 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2128 ISL_AUX_STATE_PASS_THROUGH
);
2131 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2132 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2133 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2137 unreachable("Invalid resolve op");
2143 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2144 struct intel_mipmap_tree
*mt
,
2145 uint32_t level
, uint32_t layer
,
2146 enum isl_aux_usage aux_usage
)
2148 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2149 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2150 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2152 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2154 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2155 switch (aux_state
) {
2156 case ISL_AUX_STATE_CLEAR
:
2157 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2158 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2159 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2161 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2162 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2163 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2164 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2165 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2166 ISL_AUX_STATE_PARTIAL_CLEAR
);
2170 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2171 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2172 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2173 break; /* Nothing to do */
2175 case ISL_AUX_STATE_PASS_THROUGH
:
2176 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2177 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2178 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2184 case ISL_AUX_STATE_RESOLVED
:
2185 case ISL_AUX_STATE_AUX_INVALID
:
2186 unreachable("Invalid aux state for CCS_E");
2189 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2190 /* CCS_D is a bit simpler */
2191 switch (aux_state
) {
2192 case ISL_AUX_STATE_CLEAR
:
2193 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2194 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2195 ISL_AUX_STATE_PARTIAL_CLEAR
);
2198 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2199 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2200 break; /* Nothing to do */
2202 case ISL_AUX_STATE_PASS_THROUGH
:
2206 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2207 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2208 case ISL_AUX_STATE_RESOLVED
:
2209 case ISL_AUX_STATE_AUX_INVALID
:
2210 unreachable("Invalid aux state for CCS_D");
2216 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2217 struct intel_mipmap_tree
*mt
,
2219 enum isl_aux_usage aux_usage
,
2220 bool fast_clear_supported
)
2222 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2224 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2225 case ISL_AUX_STATE_CLEAR
:
2226 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2227 if (!fast_clear_supported
) {
2228 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2229 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2230 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2234 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2235 break; /* Nothing to do */
2237 case ISL_AUX_STATE_RESOLVED
:
2238 case ISL_AUX_STATE_PASS_THROUGH
:
2239 case ISL_AUX_STATE_AUX_INVALID
:
2240 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2241 unreachable("Invalid aux state for MCS");
2246 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2247 struct intel_mipmap_tree
*mt
,
2249 enum isl_aux_usage aux_usage
)
2251 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2253 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2254 case ISL_AUX_STATE_CLEAR
:
2255 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2256 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2259 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2260 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2261 break; /* Nothing to do */
2263 case ISL_AUX_STATE_RESOLVED
:
2264 case ISL_AUX_STATE_PASS_THROUGH
:
2265 case ISL_AUX_STATE_AUX_INVALID
:
2266 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2267 unreachable("Invalid aux state for MCS");
2272 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2273 struct intel_mipmap_tree
*mt
,
2274 uint32_t level
, uint32_t layer
,
2275 enum isl_aux_usage aux_usage
,
2276 bool fast_clear_supported
)
2278 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2280 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2281 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2282 case ISL_AUX_STATE_CLEAR
:
2283 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2284 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2285 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2288 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2289 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2290 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2293 case ISL_AUX_STATE_PASS_THROUGH
:
2294 case ISL_AUX_STATE_RESOLVED
:
2297 case ISL_AUX_STATE_AUX_INVALID
:
2298 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2299 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2302 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2303 unreachable("Invalid HiZ state");
2306 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2307 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2310 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2311 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2312 ISL_AUX_STATE_RESOLVED
);
2315 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2316 /* The HiZ resolve operation is actually an ambiguate */
2317 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2318 ISL_AUX_STATE_PASS_THROUGH
);
2322 unreachable("Invalid HiZ op");
2328 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2329 struct intel_mipmap_tree
*mt
,
2330 uint32_t level
, uint32_t layer
,
2331 enum isl_aux_usage aux_usage
)
2333 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2335 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2336 case ISL_AUX_STATE_CLEAR
:
2337 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2338 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2339 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2342 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2343 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2344 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2345 break; /* Nothing to do */
2347 case ISL_AUX_STATE_RESOLVED
:
2348 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2349 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2350 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2352 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2353 ISL_AUX_STATE_AUX_INVALID
);
2357 case ISL_AUX_STATE_PASS_THROUGH
:
2358 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2359 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2360 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2364 case ISL_AUX_STATE_AUX_INVALID
:
2365 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2368 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2369 unreachable("Invalid HiZ state");
2374 intel_miptree_prepare_access(struct brw_context
*brw
,
2375 struct intel_mipmap_tree
*mt
,
2376 uint32_t start_level
, uint32_t num_levels
,
2377 uint32_t start_layer
, uint32_t num_layers
,
2378 enum isl_aux_usage aux_usage
,
2379 bool fast_clear_supported
)
2381 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2383 switch (mt
->aux_usage
) {
2384 case ISL_AUX_USAGE_NONE
:
2388 case ISL_AUX_USAGE_MCS
:
2389 assert(mt
->mcs_buf
);
2390 assert(start_level
== 0 && num_levels
== 1);
2391 const uint32_t level_layers
=
2392 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2393 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2394 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2395 aux_usage
, fast_clear_supported
);
2399 case ISL_AUX_USAGE_CCS_D
:
2400 case ISL_AUX_USAGE_CCS_E
:
2404 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2405 const uint32_t level
= start_level
+ l
;
2406 const uint32_t level_layers
=
2407 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2408 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2409 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2411 aux_usage
, fast_clear_supported
);
2416 case ISL_AUX_USAGE_HIZ
:
2417 assert(mt
->hiz_buf
);
2418 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2419 const uint32_t level
= start_level
+ l
;
2420 if (!intel_miptree_level_has_hiz(mt
, level
))
2423 const uint32_t level_layers
=
2424 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2425 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2426 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2427 aux_usage
, fast_clear_supported
);
2433 unreachable("Invalid aux usage");
2438 intel_miptree_finish_write(struct brw_context
*brw
,
2439 struct intel_mipmap_tree
*mt
, uint32_t level
,
2440 uint32_t start_layer
, uint32_t num_layers
,
2441 enum isl_aux_usage aux_usage
)
2443 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2445 switch (mt
->aux_usage
) {
2446 case ISL_AUX_USAGE_NONE
:
2450 case ISL_AUX_USAGE_MCS
:
2451 assert(mt
->mcs_buf
);
2452 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2453 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2458 case ISL_AUX_USAGE_CCS_D
:
2459 case ISL_AUX_USAGE_CCS_E
:
2463 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2464 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2469 case ISL_AUX_USAGE_HIZ
:
2470 if (!intel_miptree_level_has_hiz(mt
, level
))
2473 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2474 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2480 unreachable("Invavlid aux usage");
2485 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2486 uint32_t level
, uint32_t layer
)
2488 intel_miptree_check_level_layer(mt
, level
, layer
);
2490 if (_mesa_is_format_color_format(mt
->format
)) {
2491 assert(mt
->mcs_buf
!= NULL
);
2492 assert(mt
->surf
.samples
== 1 ||
2493 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2494 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2495 unreachable("Cannot get aux state for stencil");
2497 assert(intel_miptree_level_has_hiz(mt
, level
));
2500 return mt
->aux_state
[level
][layer
];
2504 intel_miptree_set_aux_state(struct brw_context
*brw
,
2505 struct intel_mipmap_tree
*mt
, uint32_t level
,
2506 uint32_t start_layer
, uint32_t num_layers
,
2507 enum isl_aux_state aux_state
)
2509 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2511 if (_mesa_is_format_color_format(mt
->format
)) {
2512 assert(mt
->mcs_buf
!= NULL
);
2513 assert(mt
->surf
.samples
== 1 ||
2514 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2515 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2516 unreachable("Cannot get aux state for stencil");
2518 assert(intel_miptree_level_has_hiz(mt
, level
));
2521 for (unsigned a
= 0; a
< num_layers
; a
++)
2522 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2525 /* On Gen9 color buffers may be compressed by the hardware (lossless
2526 * compression). There are, however, format restrictions and care needs to be
2527 * taken that the sampler engine is capable for re-interpreting a buffer with
2528 * format different the buffer was originally written with.
2530 * For example, SRGB formats are not compressible and the sampler engine isn't
2531 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2532 * color buffer needs to be resolved so that the sampling surface can be
2533 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2537 can_texture_with_ccs(struct brw_context
*brw
,
2538 struct intel_mipmap_tree
*mt
,
2539 enum isl_format view_format
)
2541 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2544 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2545 mt
->surf
.format
, view_format
)) {
2546 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2547 isl_format_get_layout(view_format
)->name
,
2548 _mesa_get_format_name(mt
->format
));
2556 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
,
2558 enum isl_format view_format
)
2560 switch (mt
->aux_usage
) {
2561 case ISL_AUX_USAGE_HIZ
:
2562 if (intel_miptree_sample_with_hiz(brw
, mt
))
2563 return ISL_AUX_USAGE_HIZ
;
2566 case ISL_AUX_USAGE_MCS
:
2567 return ISL_AUX_USAGE_MCS
;
2569 case ISL_AUX_USAGE_CCS_D
:
2570 case ISL_AUX_USAGE_CCS_E
:
2571 if (mt
->mcs_buf
&& can_texture_with_ccs(brw
, mt
, view_format
))
2572 return ISL_AUX_USAGE_CCS_E
;
2579 return ISL_AUX_USAGE_NONE
;
2583 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2585 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2586 * values so sRGB curve application was a no-op for all fast-clearable
2589 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2590 * values, the hardware interprets the floats, not as what would be
2591 * returned from the sampler (or written by the shader), but as being
2592 * between format conversion and sRGB curve application. This means that
2593 * we can switch between sRGB and UNORM without having to whack the clear
2596 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2600 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2601 struct intel_mipmap_tree
*mt
,
2602 enum isl_format view_format
,
2603 uint32_t start_level
, uint32_t num_levels
,
2604 uint32_t start_layer
, uint32_t num_layers
,
2605 bool *aux_supported_out
)
2607 enum isl_aux_usage aux_usage
=
2608 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2609 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2611 /* Clear color is specified as ints or floats and the conversion is done by
2612 * the sampler. If we have a texture view, we would have to perform the
2613 * clear color conversion manually. Just disable clear color.
2615 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2616 clear_supported
= false;
2618 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2619 start_layer
, num_layers
,
2620 aux_usage
, clear_supported
);
2621 if (aux_supported_out
)
2622 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2626 intel_miptree_prepare_texture(struct brw_context
*brw
,
2627 struct intel_mipmap_tree
*mt
,
2628 enum isl_format view_format
,
2629 bool *aux_supported_out
)
2631 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2632 0, INTEL_REMAINING_LEVELS
,
2633 0, INTEL_REMAINING_LAYERS
,
2638 intel_miptree_prepare_image(struct brw_context
*brw
,
2639 struct intel_mipmap_tree
*mt
)
2641 /* The data port doesn't understand any compression */
2642 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2643 0, INTEL_REMAINING_LAYERS
,
2644 ISL_AUX_USAGE_NONE
, false);
2648 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2649 struct intel_mipmap_tree
*mt
, uint32_t level
,
2650 uint32_t start_layer
, uint32_t num_layers
)
2652 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2653 start_layer
, num_layers
, NULL
);
2657 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2658 struct intel_mipmap_tree
*mt
,
2659 bool srgb_enabled
, bool blend_enabled
)
2661 switch (mt
->aux_usage
) {
2662 case ISL_AUX_USAGE_MCS
:
2663 assert(mt
->mcs_buf
);
2664 return ISL_AUX_USAGE_MCS
;
2666 case ISL_AUX_USAGE_CCS_D
:
2667 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2669 case ISL_AUX_USAGE_CCS_E
: {
2670 mesa_format mesa_format
=
2671 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2672 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2674 /* If the format supports CCS_E, then we can just use it */
2675 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2676 return ISL_AUX_USAGE_CCS_E
;
2678 /* Otherwise, we have to fall back to CCS_D */
2680 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2681 * formats. However, there are issues with blending where it doesn't
2682 * properly apply the sRGB curve to the clear color when blending.
2684 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2685 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2686 return ISL_AUX_USAGE_NONE
;
2688 return ISL_AUX_USAGE_CCS_D
;
2692 return ISL_AUX_USAGE_NONE
;
2697 intel_miptree_prepare_render(struct brw_context
*brw
,
2698 struct intel_mipmap_tree
*mt
, uint32_t level
,
2699 uint32_t start_layer
, uint32_t layer_count
,
2700 bool srgb_enabled
, bool blend_enabled
)
2702 enum isl_aux_usage aux_usage
=
2703 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2704 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2705 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2709 intel_miptree_finish_render(struct brw_context
*brw
,
2710 struct intel_mipmap_tree
*mt
, uint32_t level
,
2711 uint32_t start_layer
, uint32_t layer_count
,
2712 bool srgb_enabled
, bool blend_enabled
)
2714 assert(_mesa_is_format_color_format(mt
->format
));
2716 enum isl_aux_usage aux_usage
=
2717 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2718 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2723 intel_miptree_prepare_depth(struct brw_context
*brw
,
2724 struct intel_mipmap_tree
*mt
, uint32_t level
,
2725 uint32_t start_layer
, uint32_t layer_count
)
2727 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2728 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2732 intel_miptree_finish_depth(struct brw_context
*brw
,
2733 struct intel_mipmap_tree
*mt
, uint32_t level
,
2734 uint32_t start_layer
, uint32_t layer_count
,
2737 if (depth_written
) {
2738 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2739 mt
->hiz_buf
!= NULL
);
2744 * Make it possible to share the BO backing the given miptree with another
2745 * process or another miptree.
2747 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2748 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2749 * ensure that no MCS buffer gets allocated in the future.
2751 * HiZ is similarly unsafe with shared buffers.
2754 intel_miptree_make_shareable(struct brw_context
*brw
,
2755 struct intel_mipmap_tree
*mt
)
2757 /* MCS buffers are also used for multisample buffers, but we can't resolve
2758 * away a multisample MCS buffer because it's an integral part of how the
2759 * pixel data is stored. Fortunately this code path should never be
2760 * reached for multisample buffers.
2762 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2763 mt
->surf
.samples
== 1);
2765 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2766 0, INTEL_REMAINING_LAYERS
,
2767 ISL_AUX_USAGE_NONE
, false);
2770 brw_bo_unreference(mt
->mcs_buf
->bo
);
2774 /* Any pending MCS/CCS operations are no longer needed. Trying to
2775 * execute any will likely crash due to the missing aux buffer. So let's
2776 * delete all pending ops.
2778 free(mt
->aux_state
);
2779 mt
->aux_state
= NULL
;
2783 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2786 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2787 mt
->level
[l
].has_hiz
= false;
2790 /* Any pending HiZ operations are no longer needed. Trying to execute
2791 * any will likely crash due to the missing aux buffer. So let's delete
2794 free(mt
->aux_state
);
2795 mt
->aux_state
= NULL
;
2798 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2799 mt
->supports_fast_clear
= false;
2804 * \brief Get pointer offset into stencil buffer.
2806 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2807 * must decode the tile's layout in software.
2810 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2812 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2814 * Even though the returned offset is always positive, the return type is
2816 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2817 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2820 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2822 uint32_t tile_size
= 4096;
2823 uint32_t tile_width
= 64;
2824 uint32_t tile_height
= 64;
2825 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2827 uint32_t tile_x
= x
/ tile_width
;
2828 uint32_t tile_y
= y
/ tile_height
;
2830 /* The byte's address relative to the tile's base addres. */
2831 uint32_t byte_x
= x
% tile_width
;
2832 uint32_t byte_y
= y
% tile_height
;
2834 uintptr_t u
= tile_y
* row_size
2835 + tile_x
* tile_size
2836 + 512 * (byte_x
/ 8)
2838 + 32 * ((byte_y
/ 4) % 2)
2839 + 16 * ((byte_x
/ 4) % 2)
2840 + 8 * ((byte_y
/ 2) % 2)
2841 + 4 * ((byte_x
/ 2) % 2)
2846 /* adjust for bit6 swizzling */
2847 if (((byte_x
/ 8) % 2) == 1) {
2848 if (((byte_y
/ 8) % 2) == 0) {
2860 intel_miptree_updownsample(struct brw_context
*brw
,
2861 struct intel_mipmap_tree
*src
,
2862 struct intel_mipmap_tree
*dst
)
2864 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2865 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2866 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2867 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2869 brw_blorp_blit_miptrees(brw
,
2870 src
, 0 /* level */, 0 /* layer */,
2871 src
->format
, SWIZZLE_XYZW
,
2872 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2875 GL_NEAREST
, false, false /*mirror x, y*/,
2878 if (src
->stencil_mt
) {
2879 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2880 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2881 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2882 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2884 brw_blorp_blit_miptrees(brw
,
2885 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2886 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2887 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2888 dst
->stencil_mt
->format
,
2891 GL_NEAREST
, false, false /*mirror x, y*/,
2892 false, false /* decode/encode srgb */);
2897 intel_update_r8stencil(struct brw_context
*brw
,
2898 struct intel_mipmap_tree
*mt
)
2900 assert(brw
->gen
>= 7);
2901 struct intel_mipmap_tree
*src
=
2902 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2903 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2906 assert(src
->surf
.size
> 0);
2908 if (!mt
->r8stencil_mt
) {
2909 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2910 mt
->r8stencil_mt
= make_surface(
2913 MESA_FORMAT_R_UINT8
,
2914 src
->first_level
, src
->last_level
,
2915 src
->surf
.logical_level0_px
.width
,
2916 src
->surf
.logical_level0_px
.height
,
2917 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2918 src
->surf
.logical_level0_px
.depth
:
2919 src
->surf
.logical_level0_px
.array_len
,
2922 ISL_SURF_USAGE_TEXTURE_BIT
,
2923 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2924 assert(mt
->r8stencil_mt
);
2927 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2929 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2930 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2931 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2932 src
->surf
.phys_level0_sa
.array_len
;
2934 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2935 brw_blorp_copy_miptrees(brw
,
2939 minify(src
->surf
.logical_level0_px
.width
,
2941 minify(src
->surf
.logical_level0_px
.height
,
2946 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2947 src
->r8stencil_needs_update
= false;
2951 intel_miptree_map_raw(struct brw_context
*brw
,
2952 struct intel_mipmap_tree
*mt
,
2955 struct brw_bo
*bo
= mt
->bo
;
2957 if (brw_batch_references(&brw
->batch
, bo
))
2958 intel_batchbuffer_flush(brw
);
2960 return brw_bo_map(brw
, bo
, mode
);
2964 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2966 brw_bo_unmap(mt
->bo
);
2970 intel_miptree_map_gtt(struct brw_context
*brw
,
2971 struct intel_mipmap_tree
*mt
,
2972 struct intel_miptree_map
*map
,
2973 unsigned int level
, unsigned int slice
)
2975 unsigned int bw
, bh
;
2977 unsigned int image_x
, image_y
;
2978 intptr_t x
= map
->x
;
2979 intptr_t y
= map
->y
;
2981 /* For compressed formats, the stride is the number of bytes per
2982 * row of blocks. intel_miptree_get_image_offset() already does
2985 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2986 assert(y
% bh
== 0);
2987 assert(x
% bw
== 0);
2991 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2998 /* Note that in the case of cube maps, the caller must have passed the
2999 * slice number referencing the face.
3001 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3005 map
->stride
= mt
->surf
.row_pitch
;
3006 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3009 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3010 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3011 map
->x
, map
->y
, map
->w
, map
->h
,
3012 mt
, _mesa_get_format_name(mt
->format
),
3013 x
, y
, map
->ptr
, map
->stride
);
3017 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3019 intel_miptree_unmap_raw(mt
);
3023 intel_miptree_map_blit(struct brw_context
*brw
,
3024 struct intel_mipmap_tree
*mt
,
3025 struct intel_miptree_map
*map
,
3026 unsigned int level
, unsigned int slice
)
3028 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3029 /* first_level */ 0,
3033 MIPTREE_CREATE_LINEAR
);
3035 if (!map
->linear_mt
) {
3036 fprintf(stderr
, "Failed to allocate blit temporary\n");
3039 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3041 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3042 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3043 * invalidate is set, since we'll be writing the whole rectangle from our
3044 * temporary buffer back out.
3046 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3047 if (!intel_miptree_copy(brw
,
3048 mt
, level
, slice
, map
->x
, map
->y
,
3049 map
->linear_mt
, 0, 0, 0, 0,
3051 fprintf(stderr
, "Failed to blit\n");
3056 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3058 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3059 map
->x
, map
->y
, map
->w
, map
->h
,
3060 mt
, _mesa_get_format_name(mt
->format
),
3061 level
, slice
, map
->ptr
, map
->stride
);
3066 intel_miptree_release(&map
->linear_mt
);
3072 intel_miptree_unmap_blit(struct brw_context
*brw
,
3073 struct intel_mipmap_tree
*mt
,
3074 struct intel_miptree_map
*map
,
3078 struct gl_context
*ctx
= &brw
->ctx
;
3080 intel_miptree_unmap_raw(map
->linear_mt
);
3082 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3083 bool ok
= intel_miptree_copy(brw
,
3084 map
->linear_mt
, 0, 0, 0, 0,
3085 mt
, level
, slice
, map
->x
, map
->y
,
3087 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3090 intel_miptree_release(&map
->linear_mt
);
3094 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3096 #if defined(USE_SSE41)
3098 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3099 struct intel_mipmap_tree
*mt
,
3100 struct intel_miptree_map
*map
,
3101 unsigned int level
, unsigned int slice
)
3103 assert(map
->mode
& GL_MAP_READ_BIT
);
3104 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3106 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3107 map
->x
, map
->y
, map
->w
, map
->h
,
3108 mt
, _mesa_get_format_name(mt
->format
),
3109 level
, slice
, map
->ptr
, map
->stride
);
3111 /* Map the original image */
3114 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3118 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3124 src
+= image_y
* mt
->surf
.row_pitch
;
3125 src
+= image_x
* mt
->cpp
;
3127 /* Due to the pixel offsets for the particular image being mapped, our
3128 * src pointer may not be 16-byte aligned. However, if the pitch is
3129 * divisible by 16, then the amount by which it's misaligned will remain
3130 * consistent from row to row.
3132 assert((mt
->surf
.row_pitch
% 16) == 0);
3133 const int misalignment
= ((uintptr_t) src
) & 15;
3135 /* Create an untiled temporary buffer for the mapping. */
3136 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3138 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3140 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3141 /* Offset the destination so it has the same misalignment as src. */
3142 map
->ptr
= map
->buffer
+ misalignment
;
3144 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3146 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3147 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3148 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3150 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3153 intel_miptree_unmap_raw(mt
);
3157 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3158 struct intel_mipmap_tree
*mt
,
3159 struct intel_miptree_map
*map
,
3163 _mesa_align_free(map
->buffer
);
3170 intel_miptree_map_s8(struct brw_context
*brw
,
3171 struct intel_mipmap_tree
*mt
,
3172 struct intel_miptree_map
*map
,
3173 unsigned int level
, unsigned int slice
)
3175 map
->stride
= map
->w
;
3176 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3180 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3181 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3182 * invalidate is set, since we'll be writing the whole rectangle from our
3183 * temporary buffer back out.
3185 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3186 uint8_t *untiled_s8_map
= map
->ptr
;
3187 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3188 unsigned int image_x
, image_y
;
3190 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3192 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3193 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3194 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3195 x
+ image_x
+ map
->x
,
3196 y
+ image_y
+ map
->y
,
3197 brw
->has_swizzling
);
3198 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3202 intel_miptree_unmap_raw(mt
);
3204 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3205 map
->x
, map
->y
, map
->w
, map
->h
,
3206 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3208 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3209 map
->x
, map
->y
, map
->w
, map
->h
,
3210 mt
, map
->ptr
, map
->stride
);
3215 intel_miptree_unmap_s8(struct brw_context
*brw
,
3216 struct intel_mipmap_tree
*mt
,
3217 struct intel_miptree_map
*map
,
3221 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3222 unsigned int image_x
, image_y
;
3223 uint8_t *untiled_s8_map
= map
->ptr
;
3224 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3226 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3228 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3229 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3230 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3231 image_x
+ x
+ map
->x
,
3232 image_y
+ y
+ map
->y
,
3233 brw
->has_swizzling
);
3234 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3238 intel_miptree_unmap_raw(mt
);
3245 intel_miptree_map_etc(struct brw_context
*brw
,
3246 struct intel_mipmap_tree
*mt
,
3247 struct intel_miptree_map
*map
,
3251 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3252 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3253 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3256 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3257 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3259 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3260 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3261 map
->w
, map
->h
, 1));
3262 map
->ptr
= map
->buffer
;
3266 intel_miptree_unmap_etc(struct brw_context
*brw
,
3267 struct intel_mipmap_tree
*mt
,
3268 struct intel_miptree_map
*map
,
3274 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3279 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3280 + image_y
* mt
->surf
.row_pitch
3281 + image_x
* mt
->cpp
;
3283 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3284 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3285 map
->ptr
, map
->stride
,
3288 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3289 map
->ptr
, map
->stride
,
3290 map
->w
, map
->h
, mt
->etc_format
);
3292 intel_miptree_unmap_raw(mt
);
3297 * Mapping function for packed depth/stencil miptrees backed by real separate
3298 * miptrees for depth and stencil.
3300 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3301 * separate from the depth buffer. Yet at the GL API level, we have to expose
3302 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3303 * be able to map that memory for texture storage and glReadPixels-type
3304 * operations. We give Mesa core that access by mallocing a temporary and
3305 * copying the data between the actual backing store and the temporary.
3308 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3309 struct intel_mipmap_tree
*mt
,
3310 struct intel_miptree_map
*map
,
3311 unsigned int level
, unsigned int slice
)
3313 struct intel_mipmap_tree
*z_mt
= mt
;
3314 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3315 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3316 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3318 map
->stride
= map
->w
* packed_bpp
;
3319 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3323 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3324 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3325 * invalidate is set, since we'll be writing the whole rectangle from our
3326 * temporary buffer back out.
3328 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3329 uint32_t *packed_map
= map
->ptr
;
3330 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3331 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3332 unsigned int s_image_x
, s_image_y
;
3333 unsigned int z_image_x
, z_image_y
;
3335 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3336 &s_image_x
, &s_image_y
);
3337 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3338 &z_image_x
, &z_image_y
);
3340 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3341 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3342 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3343 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3346 brw
->has_swizzling
);
3347 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3348 (z_mt
->surf
.row_pitch
/ 4) +
3349 (map_x
+ z_image_x
));
3350 uint8_t s
= s_map
[s_offset
];
3351 uint32_t z
= z_map
[z_offset
];
3353 if (map_z32f_x24s8
) {
3354 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3355 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3357 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3362 intel_miptree_unmap_raw(s_mt
);
3363 intel_miptree_unmap_raw(z_mt
);
3365 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3367 map
->x
, map
->y
, map
->w
, map
->h
,
3368 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3369 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3370 map
->ptr
, map
->stride
);
3372 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3373 map
->x
, map
->y
, map
->w
, map
->h
,
3374 mt
, map
->ptr
, map
->stride
);
3379 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3380 struct intel_mipmap_tree
*mt
,
3381 struct intel_miptree_map
*map
,
3385 struct intel_mipmap_tree
*z_mt
= mt
;
3386 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3387 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3389 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3390 uint32_t *packed_map
= map
->ptr
;
3391 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3392 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3393 unsigned int s_image_x
, s_image_y
;
3394 unsigned int z_image_x
, z_image_y
;
3396 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3397 &s_image_x
, &s_image_y
);
3398 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3399 &z_image_x
, &z_image_y
);
3401 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3402 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3403 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3404 x
+ s_image_x
+ map
->x
,
3405 y
+ s_image_y
+ map
->y
,
3406 brw
->has_swizzling
);
3407 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3408 (z_mt
->surf
.row_pitch
/ 4) +
3409 (x
+ z_image_x
+ map
->x
));
3411 if (map_z32f_x24s8
) {
3412 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3413 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3415 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3416 s_map
[s_offset
] = packed
>> 24;
3417 z_map
[z_offset
] = packed
;
3422 intel_miptree_unmap_raw(s_mt
);
3423 intel_miptree_unmap_raw(z_mt
);
3425 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3427 map
->x
, map
->y
, map
->w
, map
->h
,
3428 z_mt
, _mesa_get_format_name(z_mt
->format
),
3429 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3430 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3431 map
->ptr
, map
->stride
);
3438 * Create and attach a map to the miptree at (level, slice). Return the
3441 static struct intel_miptree_map
*
3442 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3451 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3456 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3457 mt
->level
[level
].slice
[slice
].map
= map
;
3469 * Release the map at (level, slice).
3472 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3476 struct intel_miptree_map
**map
;
3478 map
= &mt
->level
[level
].slice
[slice
].map
;
3484 can_blit_slice(struct intel_mipmap_tree
*mt
,
3485 unsigned int level
, unsigned int slice
)
3487 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3488 if (mt
->surf
.row_pitch
>= 32768)
3495 use_intel_mipree_map_blit(struct brw_context
*brw
,
3496 struct intel_mipmap_tree
*mt
,
3502 /* It's probably not worth swapping to the blit ring because of
3503 * all the overhead involved.
3505 !(mode
& GL_MAP_WRITE_BIT
) &&
3507 (mt
->surf
.tiling
== ISL_TILING_X
||
3508 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3509 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3510 /* Fast copy blit on skl+ supports all tiling formats. */
3512 can_blit_slice(mt
, level
, slice
))
3515 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3516 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3517 assert(can_blit_slice(mt
, level
, slice
));
3525 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3526 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3527 * arithmetic overflow.
3529 * If you call this function and use \a out_stride, then you're doing pointer
3530 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3531 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3532 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3533 * which usually have type uint32_t or GLuint.
3536 intel_miptree_map(struct brw_context
*brw
,
3537 struct intel_mipmap_tree
*mt
,
3546 ptrdiff_t *out_stride
)
3548 struct intel_miptree_map
*map
;
3550 assert(mt
->surf
.samples
== 1);
3552 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3559 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3560 map
->mode
& GL_MAP_WRITE_BIT
);
3562 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3563 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3564 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3565 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3566 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3567 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3568 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3569 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3570 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3571 #if defined(USE_SSE41)
3572 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3573 !mt
->compressed
&& cpu_has_sse4_1
&&
3574 (mt
->surf
.row_pitch
% 16 == 0)) {
3575 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3578 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3581 *out_ptr
= map
->ptr
;
3582 *out_stride
= map
->stride
;
3584 if (map
->ptr
== NULL
)
3585 intel_miptree_release_map(mt
, level
, slice
);
3589 intel_miptree_unmap(struct brw_context
*brw
,
3590 struct intel_mipmap_tree
*mt
,
3594 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3596 assert(mt
->surf
.samples
== 1);
3601 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3602 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3604 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3605 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3606 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3607 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3608 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3609 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3610 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3611 } else if (map
->linear_mt
) {
3612 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3613 #if defined(USE_SSE41)
3614 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3615 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3618 intel_miptree_unmap_gtt(mt
);
3621 intel_miptree_release_map(mt
, level
, slice
);
3625 get_isl_surf_dim(GLenum target
)
3629 case GL_TEXTURE_1D_ARRAY
:
3630 return ISL_SURF_DIM_1D
;
3633 case GL_TEXTURE_2D_ARRAY
:
3634 case GL_TEXTURE_RECTANGLE
:
3635 case GL_TEXTURE_CUBE_MAP
:
3636 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3637 case GL_TEXTURE_2D_MULTISAMPLE
:
3638 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3639 case GL_TEXTURE_EXTERNAL_OES
:
3640 return ISL_SURF_DIM_2D
;
3643 return ISL_SURF_DIM_3D
;
3646 unreachable("Invalid texture target");
3650 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3651 enum isl_tiling tiling
, GLenum target
)
3655 case GL_TEXTURE_1D_ARRAY
:
3656 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3657 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3660 case GL_TEXTURE_2D_ARRAY
:
3661 case GL_TEXTURE_RECTANGLE
:
3662 case GL_TEXTURE_2D_MULTISAMPLE
:
3663 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3664 case GL_TEXTURE_EXTERNAL_OES
:
3665 return ISL_DIM_LAYOUT_GEN4_2D
;
3667 case GL_TEXTURE_CUBE_MAP
:
3668 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3669 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3670 ISL_DIM_LAYOUT_GEN4_2D
);
3673 return (devinfo
->gen
>= 9 ?
3674 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3677 unreachable("Invalid texture target");
3681 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3682 const struct intel_mipmap_tree
*mt
)
3685 return ISL_AUX_USAGE_HIZ
;
3688 return ISL_AUX_USAGE_NONE
;
3690 return mt
->aux_usage
;