2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return brw_losslessly_compressible_format(brw
, brw_format
);
270 /* On Gen9 support for color buffer compression was extended to single
271 * sampled surfaces. This is a helper considering both auxiliary buffer
272 * type and number of samples telling if the given miptree represents
273 * the new single sampled case - also called lossless compression.
276 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
277 const struct intel_mipmap_tree
*mt
)
279 /* Only available from Gen9 onwards. */
283 /* Compression always requires auxiliary buffer. */
287 /* Single sample compression is represented re-using msaa compression
288 * layout type: "Compressed Multisampled Surfaces".
290 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
293 /* And finally distinguish between msaa and single sample case. */
294 return mt
->num_samples
<= 1;
298 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
299 const struct intel_mipmap_tree
*mt
)
301 /* For now compression is only enabled for integer formats even though
302 * there exist supported floating point formats also. This is a heuristic
303 * decision based on current public benchmarks. In none of the cases these
304 * formats provided any improvement but a few cases were seen to regress.
305 * Hence these are left to to be enabled in the future when they are known
308 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
311 /* Fast clear mechanism and lossless compression go hand in hand. */
312 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
315 /* Fast clear can be also used to clear srgb surfaces by using equivalent
316 * linear format. This trick, however, can't be extended to be used with
317 * lossless compression and therefore a check is needed to see if the format
320 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
324 * Determine depth format corresponding to a depth+stencil format,
325 * for separate stencil.
328 intel_depth_format_for_depthstencil_format(mesa_format format
) {
330 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
331 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
332 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
333 return MESA_FORMAT_Z_FLOAT32
;
341 * @param for_bo Indicates that the caller is
342 * intel_miptree_create_for_bo(). If true, then do not create
345 static struct intel_mipmap_tree
*
346 intel_miptree_create_layout(struct brw_context
*brw
,
355 uint32_t layout_flags
)
357 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
361 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
362 _mesa_enum_to_string(target
),
363 _mesa_get_format_name(format
),
364 first_level
, last_level
, depth0
, mt
);
366 if (target
== GL_TEXTURE_1D_ARRAY
) {
367 /* For a 1D Array texture the OpenGL API will treat the height0
368 * parameter as the number of array slices. For Intel hardware, we treat
369 * the 1D array as a 2D Array with a height of 1.
371 * So, when we first come through this path to create a 1D Array
372 * texture, height0 stores the number of slices, and depth0 is 1. In
373 * this case, we want to swap height0 and depth0.
375 * Since some miptrees will be created based on the base miptree, we may
376 * come through this path and see height0 as 1 and depth0 being the
377 * number of slices. In this case we don't need to do the swap.
379 assert(height0
== 1 || depth0
== 1);
388 mt
->first_level
= first_level
;
389 mt
->last_level
= last_level
;
390 mt
->logical_width0
= width0
;
391 mt
->logical_height0
= height0
;
392 mt
->logical_depth0
= depth0
;
393 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
394 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
395 exec_list_make_empty(&mt
->hiz_map
);
396 mt
->cpp
= _mesa_get_format_bytes(format
);
397 mt
->num_samples
= num_samples
;
398 mt
->compressed
= _mesa_is_format_compressed(format
);
399 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
402 if (num_samples
> 1) {
403 /* Adjust width/height/depth for MSAA */
404 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
405 mt
->disable_aux_buffers
);
406 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
407 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
408 * "If the surface is multisampled and it is a depth or stencil
409 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
410 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
413 * +----------------------------------------------------------------+
414 * | Num Multisamples | W_l = | H_l = |
415 * +----------------------------------------------------------------+
416 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
417 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
418 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
419 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
420 * +----------------------------------------------------------------+
423 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
424 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
425 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
427 * Another more complicated explanation for these adjustments comes
428 * from the Sandybridge PRM, volume 4, part 1, page 31:
430 * "Any of the other messages (sample*, LOD, load4) used with a
431 * (4x) multisampled surface will in-effect sample a surface with
432 * double the height and width as that indicated in the surface
433 * state. Each pixel position on the original-sized surface is
434 * replaced with a 2x2 of samples with the following arrangement:
439 * Thus, when sampling from a multisampled texture, it behaves as
440 * though the layout in memory for (x,y,sample) is:
442 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
443 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
445 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
446 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
448 * However, the actual layout of multisampled data in memory is:
450 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
451 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
453 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
454 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
456 * This pattern repeats for each 2x2 pixel block.
458 * As a result, when calculating the size of our 4-sample buffer for
459 * an odd width or height, we have to align before scaling up because
460 * sample 3 is in that bottom right 2x2 block.
462 switch (num_samples
) {
464 assert(brw
->gen
>= 8);
465 width0
= ALIGN(width0
, 2) * 2;
466 height0
= ALIGN(height0
, 2);
469 width0
= ALIGN(width0
, 2) * 2;
470 height0
= ALIGN(height0
, 2) * 2;
473 width0
= ALIGN(width0
, 2) * 4;
474 height0
= ALIGN(height0
, 2) * 2;
477 width0
= ALIGN(width0
, 2) * 4;
478 height0
= ALIGN(height0
, 2) * 4;
481 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
484 unreachable("not reached");
487 /* Non-interleaved */
488 depth0
*= num_samples
;
492 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
493 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
494 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
495 * used on Gen8 to make it pick a qpitch value which doesn't include space
496 * for the mipmaps. On Gen9 this is not necessary because it will
497 * automatically pick a packed qpitch value whenever mt->first_level ==
499 * TODO: can we use it elsewhere?
500 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
503 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
505 switch (mt
->msaa_layout
) {
506 case INTEL_MSAA_LAYOUT_NONE
:
507 case INTEL_MSAA_LAYOUT_IMS
:
508 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
510 case INTEL_MSAA_LAYOUT_UMS
:
511 case INTEL_MSAA_LAYOUT_CMS
:
512 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
517 if (target
== GL_TEXTURE_CUBE_MAP
) {
522 mt
->physical_width0
= width0
;
523 mt
->physical_height0
= height0
;
524 mt
->physical_depth0
= depth0
;
526 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
527 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
528 (brw
->must_use_separate_stencil
||
529 (brw
->has_separate_stencil
&&
530 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
531 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
533 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
534 MIPTREE_LAYOUT_TILING_ANY
;
537 mt
->stencil_mt
= intel_miptree_create(brw
,
548 if (!mt
->stencil_mt
) {
549 intel_miptree_release(&mt
);
553 /* Fix up the Z miptree format for how we're splitting out separate
554 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
556 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
559 if (format
== mt
->format
) {
560 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
561 _mesa_get_format_name(mt
->format
));
565 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
566 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
569 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
570 * multisampled or have an AUX buffer attached to it.
572 * GEN | MSRT | AUX_CCS_* or AUX_MCS
573 * -------------------------------------------
574 * 9 | HALIGN_16 | HALIGN_16
575 * 8 | HALIGN_ANY | HALIGN_16
579 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
580 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
581 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
582 } else if (brw
->gen
>= 9 && num_samples
> 1) {
583 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
585 const bool is_lossless_compressed_aux
=
586 brw
->gen
>= 9 && num_samples
== 1 &&
587 mt
->format
== MESA_FORMAT_R_UINT32
;
589 /* For now, nothing else has this requirement */
590 assert(is_lossless_compressed_aux
||
591 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
594 brw_miptree_layout(brw
, mt
, layout_flags
);
596 if (mt
->disable_aux_buffers
)
597 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
604 * Choose an appropriate uncompressed format for a requested
605 * compressed format, if unsupported.
608 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
610 /* No need to lower ETC formats on these platforms,
611 * they are supported natively.
613 if (brw
->gen
>= 8 || brw
->is_baytrail
)
617 case MESA_FORMAT_ETC1_RGB8
:
618 return MESA_FORMAT_R8G8B8X8_UNORM
;
619 case MESA_FORMAT_ETC2_RGB8
:
620 return MESA_FORMAT_R8G8B8X8_UNORM
;
621 case MESA_FORMAT_ETC2_SRGB8
:
622 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
623 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
624 return MESA_FORMAT_B8G8R8A8_SRGB
;
625 case MESA_FORMAT_ETC2_RGBA8_EAC
:
626 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
627 return MESA_FORMAT_R8G8B8A8_UNORM
;
628 case MESA_FORMAT_ETC2_R11_EAC
:
629 return MESA_FORMAT_R_UNORM16
;
630 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
631 return MESA_FORMAT_R_SNORM16
;
632 case MESA_FORMAT_ETC2_RG11_EAC
:
633 return MESA_FORMAT_R16G16_UNORM
;
634 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
635 return MESA_FORMAT_R16G16_SNORM
;
637 /* Non ETC1 / ETC2 format */
642 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
644 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
645 unsigned long *pitch
)
647 uint32_t tile_width
, tile_height
;
648 unsigned long stride
, size
, aligned_y
;
650 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
651 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
652 &tile_width
, &tile_height
);
654 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
655 stride
= mt
->total_width
* mt
->cpp
;
656 stride
= ALIGN(stride
, tile_width
);
657 size
= stride
* aligned_y
;
659 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
660 assert(size
% 4096 == 0);
663 assert(size
% (64 * 1024) == 0);
664 *alignment
= 64 * 1024;
670 static struct intel_mipmap_tree
*
671 miptree_create(struct brw_context
*brw
,
680 uint32_t layout_flags
)
682 struct intel_mipmap_tree
*mt
;
683 mesa_format tex_format
= format
;
684 mesa_format etc_format
= MESA_FORMAT_NONE
;
685 uint32_t alloc_flags
= 0;
687 format
= intel_lower_compressed_format(brw
, format
);
689 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
691 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
692 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
693 mt
= intel_miptree_create_layout(brw
, target
, format
,
694 first_level
, last_level
, width0
,
695 height0
, depth0
, num_samples
,
698 * pitch == 0 || height == 0 indicates the null texture
700 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
701 intel_miptree_release(&mt
);
705 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
706 mt
->tiling
= I915_TILING_Y
;
708 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
709 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
712 mt
->etc_format
= etc_format
;
714 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
715 unsigned alignment
= 0;
717 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
719 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
722 if (format
== MESA_FORMAT_S_UINT8
) {
723 /* Align to size of W tile, 64x64. */
724 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
725 ALIGN(mt
->total_width
, 64),
726 ALIGN(mt
->total_height
, 64),
727 mt
->cpp
, &mt
->tiling
, &pitch
,
730 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
731 mt
->total_width
, mt
->total_height
,
732 mt
->cpp
, &mt
->tiling
, &pitch
,
742 struct intel_mipmap_tree
*
743 intel_miptree_create(struct brw_context
*brw
,
752 uint32_t layout_flags
)
754 struct intel_mipmap_tree
*mt
= miptree_create(
756 first_level
, last_level
,
757 width0
, height0
, depth0
, num_samples
,
760 /* If the BO is too large to fit in the aperture, we need to use the
761 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
762 * handle Y-tiling, so we need to fall back to X.
764 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
765 mt
->tiling
== I915_TILING_Y
) {
766 unsigned long pitch
= mt
->pitch
;
767 const uint32_t alloc_flags
=
768 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
769 BO_ALLOC_FOR_RENDER
: 0;
770 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
771 mt
->total_width
, mt
->total_height
);
773 mt
->tiling
= I915_TILING_X
;
774 drm_intel_bo_unreference(mt
->bo
);
775 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
776 mt
->total_width
, mt
->total_height
, mt
->cpp
,
777 &mt
->tiling
, &pitch
, alloc_flags
);
784 intel_miptree_release(&mt
);
789 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
790 assert(mt
->num_samples
> 1);
791 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
792 intel_miptree_release(&mt
);
797 /* If this miptree is capable of supporting fast color clears, set
798 * fast_clear_state appropriately to ensure that fast clears will occur.
799 * Allocation of the MCS miptree will be deferred until the first fast
800 * clear actually occurs.
802 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
803 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
804 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
805 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
811 struct intel_mipmap_tree
*
812 intel_miptree_create_for_bo(struct brw_context
*brw
,
820 uint32_t layout_flags
)
822 struct intel_mipmap_tree
*mt
;
823 uint32_t tiling
, swizzle
;
826 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
828 /* Nothing will be able to use this miptree with the BO if the offset isn't
831 if (tiling
!= I915_TILING_NONE
)
832 assert(offset
% 4096 == 0);
834 /* miptrees can't handle negative pitch. If you need flipping of images,
835 * that's outside of the scope of the mt.
839 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
841 /* The BO already has a tiling format and we shouldn't confuse the lower
842 * layers by making it try to find a tiling format again.
844 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
845 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
847 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
848 mt
= intel_miptree_create_layout(brw
, target
, format
,
850 width
, height
, depth
, 0,
855 drm_intel_bo_reference(bo
);
865 * For a singlesample renderbuffer, this simply wraps the given BO with a
868 * For a multisample renderbuffer, this wraps the window system's
869 * (singlesample) BO with a singlesample miptree attached to the
870 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
871 * that will contain the actual rendering (which is lazily resolved to
872 * irb->singlesample_mt).
875 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
876 struct intel_renderbuffer
*irb
,
878 uint32_t width
, uint32_t height
,
881 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
882 struct intel_mipmap_tree
*multisample_mt
= NULL
;
883 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
884 mesa_format format
= rb
->Format
;
885 int num_samples
= rb
->NumSamples
;
887 /* Only the front and back buffers, which are color buffers, are allocated
888 * through the image loader.
890 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
891 _mesa_get_format_base_format(format
) == GL_RGBA
);
893 singlesample_mt
= intel_miptree_create_for_bo(intel
,
902 if (!singlesample_mt
)
905 /* If this miptree is capable of supporting fast color clears, set
906 * mcs_state appropriately to ensure that fast clears will occur.
907 * Allocation of the MCS miptree will be deferred until the first fast
908 * clear actually occurs.
910 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
911 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
912 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
915 if (num_samples
== 0) {
916 intel_miptree_release(&irb
->mt
);
917 irb
->mt
= singlesample_mt
;
919 assert(!irb
->singlesample_mt
);
921 intel_miptree_release(&irb
->singlesample_mt
);
922 irb
->singlesample_mt
= singlesample_mt
;
925 irb
->mt
->logical_width0
!= width
||
926 irb
->mt
->logical_height0
!= height
) {
927 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
935 irb
->need_downsample
= false;
936 intel_miptree_release(&irb
->mt
);
937 irb
->mt
= multisample_mt
;
943 intel_miptree_release(&irb
->singlesample_mt
);
944 intel_miptree_release(&irb
->mt
);
948 struct intel_mipmap_tree
*
949 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
953 uint32_t num_samples
)
955 struct intel_mipmap_tree
*mt
;
958 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
959 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
960 MIPTREE_LAYOUT_TILING_ANY
;
963 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
964 width
, height
, depth
, num_samples
,
969 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
970 ok
= intel_miptree_alloc_hiz(brw
, mt
);
978 intel_miptree_release(&mt
);
983 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
984 struct intel_mipmap_tree
*src
)
989 intel_miptree_release(dst
);
993 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1001 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1006 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1007 if (--(*mt
)->refcount
<= 0) {
1010 DBG("%s deleting %p\n", __func__
, *mt
);
1012 drm_intel_bo_unreference((*mt
)->bo
);
1013 intel_miptree_release(&(*mt
)->stencil_mt
);
1014 if ((*mt
)->hiz_buf
) {
1015 if ((*mt
)->hiz_buf
->mt
)
1016 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1018 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1019 free((*mt
)->hiz_buf
);
1021 intel_miptree_release(&(*mt
)->mcs_mt
);
1022 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1024 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1025 free((*mt
)->level
[i
].slice
);
1035 intel_get_image_dims(struct gl_texture_image
*image
,
1036 int *width
, int *height
, int *depth
)
1038 switch (image
->TexObject
->Target
) {
1039 case GL_TEXTURE_1D_ARRAY
:
1040 /* For a 1D Array texture the OpenGL API will treat the image height as
1041 * the number of array slices. For Intel hardware, we treat the 1D array
1042 * as a 2D Array with a height of 1. So, here we want to swap image
1045 *width
= image
->Width
;
1047 *depth
= image
->Height
;
1050 *width
= image
->Width
;
1051 *height
= image
->Height
;
1052 *depth
= image
->Depth
;
1058 * Can the image be pulled into a unified mipmap tree? This mirrors
1059 * the completeness test in a lot of ways.
1061 * Not sure whether I want to pass gl_texture_image here.
1064 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1065 struct gl_texture_image
*image
)
1067 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1068 GLuint level
= intelImage
->base
.Base
.Level
;
1069 int width
, height
, depth
;
1071 /* glTexImage* choose the texture object based on the target passed in, and
1072 * objects can't change targets over their lifetimes, so this should be
1075 assert(image
->TexObject
->Target
== mt
->target
);
1077 mesa_format mt_format
= mt
->format
;
1078 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1079 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1080 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1081 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1082 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1083 mt_format
= mt
->etc_format
;
1085 if (image
->TexFormat
!= mt_format
)
1088 intel_get_image_dims(image
, &width
, &height
, &depth
);
1090 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1093 int level_depth
= mt
->level
[level
].depth
;
1094 if (mt
->num_samples
> 1) {
1095 switch (mt
->msaa_layout
) {
1096 case INTEL_MSAA_LAYOUT_NONE
:
1097 case INTEL_MSAA_LAYOUT_IMS
:
1099 case INTEL_MSAA_LAYOUT_UMS
:
1100 case INTEL_MSAA_LAYOUT_CMS
:
1101 level_depth
/= mt
->num_samples
;
1106 /* Test image dimensions against the base level image adjusted for
1107 * minification. This will also catch images not present in the
1108 * tree, changed targets, etc.
1110 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1111 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1112 depth
!= level_depth
) {
1116 if (image
->NumSamples
!= mt
->num_samples
)
1124 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1126 GLuint x
, GLuint y
, GLuint d
)
1128 mt
->level
[level
].depth
= d
;
1129 mt
->level
[level
].level_x
= x
;
1130 mt
->level
[level
].level_y
= y
;
1132 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1135 assert(mt
->level
[level
].slice
== NULL
);
1137 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1138 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1139 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1144 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1145 GLuint level
, GLuint img
,
1148 if (img
== 0 && level
== 0)
1149 assert(x
== 0 && y
== 0);
1151 assert(img
< mt
->level
[level
].depth
);
1153 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1154 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1156 DBG("%s level %d img %d pos %d,%d\n",
1157 __func__
, level
, img
,
1158 mt
->level
[level
].slice
[img
].x_offset
,
1159 mt
->level
[level
].slice
[img
].y_offset
);
1163 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1164 GLuint level
, GLuint slice
,
1165 GLuint
*x
, GLuint
*y
)
1167 assert(slice
< mt
->level
[level
].depth
);
1169 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1170 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1175 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1176 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1177 * and tile_h is set to 1.
1180 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1181 uint32_t *tile_w
, uint32_t *tile_h
)
1183 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1193 case I915_TILING_NONE
:
1198 unreachable("not reached");
1201 uint32_t aspect_ratio
= 1;
1202 assert(_mesa_is_pow_two(cpp
));
1217 unreachable("not reached");
1220 if (cpp
== 2 || cpp
== 8)
1223 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1226 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1232 * This function computes masks that may be used to select the bits of the X
1233 * and Y coordinates that indicate the offset within a tile. If the BO is
1234 * untiled, the masks are set to 0.
1237 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1238 bool map_stencil_as_y_tiled
,
1239 uint32_t *mask_x
, uint32_t *mask_y
)
1241 uint32_t tile_w_bytes
, tile_h
;
1242 if (map_stencil_as_y_tiled
)
1243 tiling
= I915_TILING_Y
;
1245 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1247 *mask_x
= tile_w_bytes
/ cpp
- 1;
1248 *mask_y
= tile_h
- 1;
1252 * Compute the offset (in bytes) from the start of the BO to the given x
1253 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1254 * multiples of the tile size.
1257 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1258 uint32_t x
, uint32_t y
,
1259 bool map_stencil_as_y_tiled
)
1262 uint32_t pitch
= mt
->pitch
;
1263 uint32_t tiling
= mt
->tiling
;
1265 if (map_stencil_as_y_tiled
) {
1266 tiling
= I915_TILING_Y
;
1268 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1269 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1270 * the resulting surface is twice the pitch of the original miptree,
1271 * since each row in the Y-tiled view corresponds to two rows in the
1272 * actual W-tiled surface. So we need to correct the pitch before
1273 * computing the offsets.
1280 unreachable("not reached");
1281 case I915_TILING_NONE
:
1282 return y
* pitch
+ x
* cpp
;
1284 assert((x
% (512 / cpp
)) == 0);
1285 assert((y
% 8) == 0);
1286 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1288 assert((x
% (128 / cpp
)) == 0);
1289 assert((y
% 32) == 0);
1290 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1295 * Rendering with tiled buffers requires that the base address of the buffer
1296 * be aligned to a page boundary. For renderbuffers, and sometimes with
1297 * textures, we may want the surface to point at a texture image level that
1298 * isn't at a page boundary.
1300 * This function returns an appropriately-aligned base offset
1301 * according to the tiling restrictions, plus any required x/y offset
1305 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1306 GLuint level
, GLuint slice
,
1311 uint32_t mask_x
, mask_y
;
1313 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1314 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1316 *tile_x
= x
& mask_x
;
1317 *tile_y
= y
& mask_y
;
1319 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1323 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1324 struct intel_mipmap_tree
*dst_mt
,
1325 struct intel_mipmap_tree
*src_mt
,
1332 ptrdiff_t src_stride
, dst_stride
;
1333 int cpp
= dst_mt
->cpp
;
1335 intel_miptree_map(brw
, src_mt
,
1339 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1342 intel_miptree_map(brw
, dst_mt
,
1346 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1350 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1351 _mesa_get_format_name(src_mt
->format
),
1352 src_mt
, src
, src_stride
,
1353 _mesa_get_format_name(dst_mt
->format
),
1354 dst_mt
, dst
, dst_stride
,
1357 int row_size
= cpp
* width
;
1358 if (src_stride
== row_size
&&
1359 dst_stride
== row_size
) {
1360 memcpy(dst
, src
, row_size
* height
);
1362 for (int i
= 0; i
< height
; i
++) {
1363 memcpy(dst
, src
, row_size
);
1369 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1370 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1372 /* Don't forget to copy the stencil data over, too. We could have skipped
1373 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1374 * shuffling the two data sources in/out of temporary storage instead of
1375 * the direct mapping we get this way.
1377 if (dst_mt
->stencil_mt
) {
1378 assert(src_mt
->stencil_mt
);
1379 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1380 level
, slice
, width
, height
);
1385 intel_miptree_copy_slice(struct brw_context
*brw
,
1386 struct intel_mipmap_tree
*dst_mt
,
1387 struct intel_mipmap_tree
*src_mt
,
1393 mesa_format format
= src_mt
->format
;
1394 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1395 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1403 assert(depth
< src_mt
->level
[level
].depth
);
1404 assert(src_mt
->format
== dst_mt
->format
);
1406 if (dst_mt
->compressed
) {
1408 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1409 height
= ALIGN_NPOT(height
, j
) / j
;
1410 width
= ALIGN_NPOT(width
, i
) / i
;
1413 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1414 * below won't apply since we can't do the depth's Y tiling or the
1415 * stencil's W tiling in the blitter.
1417 if (src_mt
->stencil_mt
) {
1418 intel_miptree_copy_slice_sw(brw
,
1425 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1426 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1427 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1429 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1430 _mesa_get_format_name(src_mt
->format
),
1431 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1432 _mesa_get_format_name(dst_mt
->format
),
1433 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1436 if (!intel_miptree_blit(brw
,
1437 src_mt
, level
, slice
, 0, 0, false,
1438 dst_mt
, level
, slice
, 0, 0, false,
1439 width
, height
, GL_COPY
)) {
1440 perf_debug("miptree validate blit for %s failed\n",
1441 _mesa_get_format_name(format
));
1443 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1449 * Copies the image's current data to the given miptree, and associates that
1450 * miptree with the image.
1452 * If \c invalidate is true, then the actual image data does not need to be
1453 * copied, but the image still needs to be associated to the new miptree (this
1454 * is set to true if we're about to clear the image).
1457 intel_miptree_copy_teximage(struct brw_context
*brw
,
1458 struct intel_texture_image
*intelImage
,
1459 struct intel_mipmap_tree
*dst_mt
,
1462 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1463 struct intel_texture_object
*intel_obj
=
1464 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1465 int level
= intelImage
->base
.Base
.Level
;
1466 int face
= intelImage
->base
.Base
.Face
;
1469 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1470 depth
= intelImage
->base
.Base
.Height
;
1472 depth
= intelImage
->base
.Base
.Depth
;
1475 for (int slice
= 0; slice
< depth
; slice
++) {
1476 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1480 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1481 intel_obj
->needs_validate
= true;
1485 intel_miptree_init_mcs(struct brw_context
*brw
,
1486 struct intel_mipmap_tree
*mt
,
1489 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1491 * When MCS buffer is enabled and bound to MSRT, it is required that it
1492 * is cleared prior to any rendering.
1494 * Since we don't use the MCS buffer for any purpose other than rendering,
1495 * it makes sense to just clear it immediately upon allocation.
1497 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1499 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1500 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1501 intel_miptree_unmap_raw(mt
->mcs_mt
);
1502 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1506 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1507 struct intel_mipmap_tree
*mt
,
1510 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1511 assert(mt
->mcs_mt
== NULL
);
1512 assert(!mt
->disable_aux_buffers
);
1514 /* Choose the correct format for the MCS buffer. All that really matters
1515 * is that we allocate the right buffer size, since we'll always be
1516 * accessing this miptree using MCS-specific hardware mechanisms, which
1517 * infer the correct format based on num_samples.
1520 switch (num_samples
) {
1523 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1526 format
= MESA_FORMAT_R_UNORM8
;
1529 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1530 * for each sample, plus 8 padding bits).
1532 format
= MESA_FORMAT_R_UINT32
;
1535 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1538 format
= MESA_FORMAT_RG_UINT32
;
1541 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1544 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1546 * "The MCS surface must be stored as Tile Y."
1548 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1549 MIPTREE_LAYOUT_TILING_Y
;
1550 mt
->mcs_mt
= miptree_create(brw
,
1556 mt
->logical_height0
,
1558 0 /* num_samples */,
1561 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1568 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1569 struct intel_mipmap_tree
*mt
)
1571 assert(mt
->mcs_mt
== NULL
);
1572 assert(!mt
->disable_aux_buffers
);
1574 /* The format of the MCS buffer is opaque to the driver; all that matters
1575 * is that we get its size and pitch right. We'll pretend that the format
1576 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1577 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1578 * the block width and then a further factor of 4. Since an MCS tile
1579 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1580 * we'll need to scale the height down by the block height and then a
1581 * further factor of 8.
1583 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1584 unsigned block_width_px
;
1585 unsigned block_height
;
1586 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1587 unsigned width_divisor
= block_width_px
* 4;
1588 unsigned height_divisor
= block_height
* 8;
1590 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1592 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1593 * in the main surface. In Skylake, it's two bits. The extra bit
1594 * doubles the MCS height, not width, because in Skylake the MCS is always
1598 height_divisor
/= 2;
1600 unsigned mcs_width
=
1601 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1602 unsigned mcs_height
=
1603 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1604 assert(mt
->logical_depth0
== 1);
1605 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1606 MIPTREE_LAYOUT_TILING_Y
;
1607 if (brw
->gen
>= 8) {
1608 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1610 mt
->mcs_mt
= miptree_create(brw
,
1618 0 /* num_samples */,
1626 * Helper for intel_miptree_alloc_hiz() that sets
1627 * \c mt->level[level].has_hiz. Return true if and only if
1628 * \c has_hiz was set.
1631 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1632 struct intel_mipmap_tree
*mt
,
1635 assert(mt
->hiz_buf
);
1637 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1638 uint32_t width
= minify(mt
->physical_width0
, level
);
1639 uint32_t height
= minify(mt
->physical_height0
, level
);
1641 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1642 * and the height is 4 aligned. This allows our HiZ support
1643 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1644 * we can grow the width & height to allow the HiZ op to
1645 * force the proper size alignments.
1647 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1648 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1653 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1654 mt
->level
[level
].has_hiz
= true;
1660 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1661 * buffer dimensions and allocates a bo for the hiz buffer.
1663 static struct intel_miptree_aux_buffer
*
1664 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1665 struct intel_mipmap_tree
*mt
)
1667 unsigned z_width
= mt
->logical_width0
;
1668 unsigned z_height
= mt
->logical_height0
;
1669 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1670 unsigned hz_width
, hz_height
;
1671 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1676 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1677 * adjustments required for Z_Height and Z_Width based on multisampling.
1679 switch (mt
->num_samples
) {
1693 unreachable("unsupported sample count");
1696 const unsigned vertical_align
= 8; /* 'j' in the docs */
1697 const unsigned H0
= z_height
;
1698 const unsigned h0
= ALIGN(H0
, vertical_align
);
1699 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1700 const unsigned Z0
= z_depth
;
1702 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1703 hz_width
= ALIGN(z_width
, 16);
1705 if (mt
->target
== GL_TEXTURE_3D
) {
1709 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1710 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1711 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1712 hz_height
+= h_i
* Z_i
;
1713 H_i
= minify(H_i
, 1);
1714 Z_i
= minify(Z_i
, 1);
1717 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1719 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1721 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1722 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1723 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1724 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1725 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1727 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1728 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1732 unsigned long pitch
;
1733 uint32_t tiling
= I915_TILING_Y
;
1734 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1735 hz_width
, hz_height
, 1,
1737 BO_ALLOC_FOR_RENDER
);
1741 } else if (tiling
!= I915_TILING_Y
) {
1742 drm_intel_bo_unreference(buf
->bo
);
1754 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1755 * buffer dimensions and allocates a bo for the hiz buffer.
1757 static struct intel_miptree_aux_buffer
*
1758 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1759 struct intel_mipmap_tree
*mt
)
1761 unsigned z_width
= mt
->logical_width0
;
1762 unsigned z_height
= mt
->logical_height0
;
1763 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1764 unsigned hz_width
, hz_height
;
1765 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1770 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1771 * adjustments required for Z_Height and Z_Width based on multisampling.
1774 switch (mt
->num_samples
) {
1788 unreachable("unsupported sample count");
1792 const unsigned vertical_align
= 8; /* 'j' in the docs */
1793 const unsigned H0
= z_height
;
1794 const unsigned h0
= ALIGN(H0
, vertical_align
);
1795 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1796 const unsigned Z0
= z_depth
;
1798 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1799 hz_width
= ALIGN(z_width
, 16);
1803 unsigned sum_h_i
= 0;
1804 unsigned hz_height_3d_sum
= 0;
1805 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1806 unsigned i
= level
- mt
->first_level
;
1807 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1808 /* sum(i=2 to m; h_i) */
1812 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1813 hz_height_3d_sum
+= h_i
* Z_i
;
1814 H_i
= minify(H_i
, 1);
1815 Z_i
= minify(Z_i
, 1);
1817 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1818 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1820 if (mt
->target
== GL_TEXTURE_3D
) {
1821 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1822 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1824 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1825 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1826 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1827 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1828 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1830 * We can can just take our hz_height calculation from above, and
1831 * multiply by 6 for the cube map and cube map array types.
1837 unsigned long pitch
;
1838 uint32_t tiling
= I915_TILING_Y
;
1839 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1840 hz_width
, hz_height
, 1,
1842 BO_ALLOC_FOR_RENDER
);
1846 } else if (tiling
!= I915_TILING_Y
) {
1847 drm_intel_bo_unreference(buf
->bo
);
1858 static struct intel_miptree_aux_buffer
*
1859 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1860 struct intel_mipmap_tree
*mt
)
1862 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1863 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1866 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1871 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1872 buf
->mt
= intel_miptree_create(brw
,
1878 mt
->logical_height0
,
1887 buf
->bo
= buf
->mt
->bo
;
1888 buf
->pitch
= buf
->mt
->pitch
;
1889 buf
->qpitch
= buf
->mt
->qpitch
;
1895 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1896 struct intel_mipmap_tree
*mt
)
1901 if (mt
->hiz_buf
!= NULL
)
1904 if (mt
->disable_aux_buffers
)
1907 switch (mt
->format
) {
1908 case MESA_FORMAT_Z_FLOAT32
:
1909 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1910 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1911 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1912 case MESA_FORMAT_Z_UNORM16
:
1920 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1921 struct intel_mipmap_tree
*mt
)
1923 assert(mt
->hiz_buf
== NULL
);
1924 assert(!mt
->disable_aux_buffers
);
1926 if (brw
->gen
== 7) {
1927 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1928 } else if (brw
->gen
>= 8) {
1929 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1931 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1937 /* Mark that all slices need a HiZ resolve. */
1938 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1939 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1942 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1943 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1944 exec_node_init(&m
->link
);
1947 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1949 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1957 * Does the miptree slice have hiz enabled?
1960 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1962 intel_miptree_check_level_layer(mt
, level
, 0);
1963 return mt
->level
[level
].has_hiz
;
1967 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1971 if (!intel_miptree_level_has_hiz(mt
, level
))
1974 intel_resolve_map_set(&mt
->hiz_map
,
1975 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1980 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1984 if (!intel_miptree_level_has_hiz(mt
, level
))
1987 intel_resolve_map_set(&mt
->hiz_map
,
1988 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1992 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1996 uint32_t end_layer
= mt
->level
[level
].depth
;
1998 for (layer
= 0; layer
< end_layer
; layer
++) {
1999 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2004 intel_miptree_slice_resolve(struct brw_context
*brw
,
2005 struct intel_mipmap_tree
*mt
,
2008 enum gen6_hiz_op need
)
2010 intel_miptree_check_level_layer(mt
, level
, layer
);
2012 struct intel_resolve_map
*item
=
2013 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2015 if (!item
|| item
->need
!= need
)
2018 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2019 intel_resolve_map_remove(item
);
2024 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2025 struct intel_mipmap_tree
*mt
,
2029 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2030 GEN6_HIZ_OP_HIZ_RESOLVE
);
2034 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2035 struct intel_mipmap_tree
*mt
,
2039 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2040 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2044 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2045 struct intel_mipmap_tree
*mt
,
2046 enum gen6_hiz_op need
)
2048 bool did_resolve
= false;
2050 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2051 if (map
->need
!= need
)
2054 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2055 intel_resolve_map_remove(map
);
2063 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2064 struct intel_mipmap_tree
*mt
)
2066 return intel_miptree_all_slices_resolve(brw
, mt
,
2067 GEN6_HIZ_OP_HIZ_RESOLVE
);
2071 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2072 struct intel_mipmap_tree
*mt
)
2074 return intel_miptree_all_slices_resolve(brw
, mt
,
2075 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2080 intel_miptree_resolve_color(struct brw_context
*brw
,
2081 struct intel_mipmap_tree
*mt
,
2084 /* From gen9 onwards there is new compression scheme for single sampled
2085 * surfaces called "lossless compressed". These don't need to be always
2088 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2089 intel_miptree_is_lossless_compressed(brw
, mt
))
2092 switch (mt
->fast_clear_state
) {
2093 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2094 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2095 /* No resolve needed */
2097 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2098 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2099 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2100 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2101 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2102 brw_blorp_resolve_color(brw
, mt
);
2110 * Make it possible to share the BO backing the given miptree with another
2111 * process or another miptree.
2113 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2114 * then discard the MCS buffer, if present. We also set the fast_clear_state
2115 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2116 * allocated in the future.
2119 intel_miptree_make_shareable(struct brw_context
*brw
,
2120 struct intel_mipmap_tree
*mt
)
2122 /* MCS buffers are also used for multisample buffers, but we can't resolve
2123 * away a multisample MCS buffer because it's an integral part of how the
2124 * pixel data is stored. Fortunately this code path should never be
2125 * reached for multisample buffers.
2127 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2130 intel_miptree_resolve_color(brw
, mt
, 0);
2131 intel_miptree_release(&mt
->mcs_mt
);
2132 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2138 * \brief Get pointer offset into stencil buffer.
2140 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2141 * must decode the tile's layout in software.
2144 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2146 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2148 * Even though the returned offset is always positive, the return type is
2150 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2151 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2154 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2156 uint32_t tile_size
= 4096;
2157 uint32_t tile_width
= 64;
2158 uint32_t tile_height
= 64;
2159 uint32_t row_size
= 64 * stride
;
2161 uint32_t tile_x
= x
/ tile_width
;
2162 uint32_t tile_y
= y
/ tile_height
;
2164 /* The byte's address relative to the tile's base addres. */
2165 uint32_t byte_x
= x
% tile_width
;
2166 uint32_t byte_y
= y
% tile_height
;
2168 uintptr_t u
= tile_y
* row_size
2169 + tile_x
* tile_size
2170 + 512 * (byte_x
/ 8)
2172 + 32 * ((byte_y
/ 4) % 2)
2173 + 16 * ((byte_x
/ 4) % 2)
2174 + 8 * ((byte_y
/ 2) % 2)
2175 + 4 * ((byte_x
/ 2) % 2)
2180 /* adjust for bit6 swizzling */
2181 if (((byte_x
/ 8) % 2) == 1) {
2182 if (((byte_y
/ 8) % 2) == 0) {
2194 intel_miptree_updownsample(struct brw_context
*brw
,
2195 struct intel_mipmap_tree
*src
,
2196 struct intel_mipmap_tree
*dst
)
2198 /* There is support for only up to eight samples. */
2199 const bool use_blorp
= src
->num_samples
<= 8 && dst
->num_samples
<= 8;
2202 brw_blorp_blit_miptrees(brw
,
2203 src
, 0 /* level */, 0 /* layer */,
2204 src
->format
, SWIZZLE_XYZW
,
2205 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2207 src
->logical_width0
, src
->logical_height0
,
2209 dst
->logical_width0
, dst
->logical_height0
,
2210 GL_NEAREST
, false, false /*mirror x, y*/,
2212 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2213 brw_meta_stencil_updownsample(brw
, src
, dst
);
2215 brw_meta_updownsample(brw
, src
, dst
);
2218 if (src
->stencil_mt
) {
2220 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2224 brw_blorp_blit_miptrees(brw
,
2225 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2226 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2227 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2228 dst
->stencil_mt
->format
,
2230 src
->logical_width0
, src
->logical_height0
,
2232 dst
->logical_width0
, dst
->logical_height0
,
2233 GL_NEAREST
, false, false /*mirror x, y*/,
2234 false, false /* decode/encode srgb */);
2239 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2241 /* CPU accesses to color buffers don't understand fast color clears, so
2242 * resolve any pending fast color clears before we map.
2244 intel_miptree_resolve_color(brw
, mt
, 0);
2246 drm_intel_bo
*bo
= mt
->bo
;
2248 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2249 intel_batchbuffer_flush(brw
);
2251 if (mt
->tiling
!= I915_TILING_NONE
)
2252 brw_bo_map_gtt(brw
, bo
, "miptree");
2254 brw_bo_map(brw
, bo
, true, "miptree");
2260 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2262 drm_intel_bo_unmap(mt
->bo
);
2266 intel_miptree_map_gtt(struct brw_context
*brw
,
2267 struct intel_mipmap_tree
*mt
,
2268 struct intel_miptree_map
*map
,
2269 unsigned int level
, unsigned int slice
)
2271 unsigned int bw
, bh
;
2273 unsigned int image_x
, image_y
;
2274 intptr_t x
= map
->x
;
2275 intptr_t y
= map
->y
;
2277 /* For compressed formats, the stride is the number of bytes per
2278 * row of blocks. intel_miptree_get_image_offset() already does
2281 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2282 assert(y
% bh
== 0);
2283 assert(x
% bw
== 0);
2287 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2292 /* Note that in the case of cube maps, the caller must have passed the
2293 * slice number referencing the face.
2295 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2299 map
->stride
= mt
->pitch
;
2300 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2303 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2304 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2305 map
->x
, map
->y
, map
->w
, map
->h
,
2306 mt
, _mesa_get_format_name(mt
->format
),
2307 x
, y
, map
->ptr
, map
->stride
);
2311 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2313 intel_miptree_unmap_raw(mt
);
2317 intel_miptree_map_blit(struct brw_context
*brw
,
2318 struct intel_mipmap_tree
*mt
,
2319 struct intel_miptree_map
*map
,
2320 unsigned int level
, unsigned int slice
)
2322 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2323 /* first_level */ 0,
2327 MIPTREE_LAYOUT_TILING_NONE
);
2329 if (!map
->linear_mt
) {
2330 fprintf(stderr
, "Failed to allocate blit temporary\n");
2333 map
->stride
= map
->linear_mt
->pitch
;
2335 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2336 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2337 * invalidate is set, since we'll be writing the whole rectangle from our
2338 * temporary buffer back out.
2340 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2341 if (!intel_miptree_blit(brw
,
2343 map
->x
, map
->y
, false,
2344 map
->linear_mt
, 0, 0,
2346 map
->w
, map
->h
, GL_COPY
)) {
2347 fprintf(stderr
, "Failed to blit\n");
2352 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2354 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2355 map
->x
, map
->y
, map
->w
, map
->h
,
2356 mt
, _mesa_get_format_name(mt
->format
),
2357 level
, slice
, map
->ptr
, map
->stride
);
2362 intel_miptree_release(&map
->linear_mt
);
2368 intel_miptree_unmap_blit(struct brw_context
*brw
,
2369 struct intel_mipmap_tree
*mt
,
2370 struct intel_miptree_map
*map
,
2374 struct gl_context
*ctx
= &brw
->ctx
;
2376 intel_miptree_unmap_raw(map
->linear_mt
);
2378 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2379 bool ok
= intel_miptree_blit(brw
,
2380 map
->linear_mt
, 0, 0,
2383 map
->x
, map
->y
, false,
2384 map
->w
, map
->h
, GL_COPY
);
2385 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2388 intel_miptree_release(&map
->linear_mt
);
2392 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2394 #if defined(USE_SSE41)
2396 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2397 struct intel_mipmap_tree
*mt
,
2398 struct intel_miptree_map
*map
,
2399 unsigned int level
, unsigned int slice
)
2401 assert(map
->mode
& GL_MAP_READ_BIT
);
2402 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2404 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2405 map
->x
, map
->y
, map
->w
, map
->h
,
2406 mt
, _mesa_get_format_name(mt
->format
),
2407 level
, slice
, map
->ptr
, map
->stride
);
2409 /* Map the original image */
2412 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2416 void *src
= intel_miptree_map_raw(brw
, mt
);
2419 src
+= image_y
* mt
->pitch
;
2420 src
+= image_x
* mt
->cpp
;
2422 /* Due to the pixel offsets for the particular image being mapped, our
2423 * src pointer may not be 16-byte aligned. However, if the pitch is
2424 * divisible by 16, then the amount by which it's misaligned will remain
2425 * consistent from row to row.
2427 assert((mt
->pitch
% 16) == 0);
2428 const int misalignment
= ((uintptr_t) src
) & 15;
2430 /* Create an untiled temporary buffer for the mapping. */
2431 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2433 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2435 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2436 /* Offset the destination so it has the same misalignment as src. */
2437 map
->ptr
= map
->buffer
+ misalignment
;
2439 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2441 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2442 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2443 void *src_ptr
= src
+ y
* mt
->pitch
;
2445 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2448 intel_miptree_unmap_raw(mt
);
2452 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2453 struct intel_mipmap_tree
*mt
,
2454 struct intel_miptree_map
*map
,
2458 _mesa_align_free(map
->buffer
);
2465 intel_miptree_map_s8(struct brw_context
*brw
,
2466 struct intel_mipmap_tree
*mt
,
2467 struct intel_miptree_map
*map
,
2468 unsigned int level
, unsigned int slice
)
2470 map
->stride
= map
->w
;
2471 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2475 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2476 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2477 * invalidate is set, since we'll be writing the whole rectangle from our
2478 * temporary buffer back out.
2480 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2481 uint8_t *untiled_s8_map
= map
->ptr
;
2482 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2483 unsigned int image_x
, image_y
;
2485 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2487 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2488 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2489 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2490 x
+ image_x
+ map
->x
,
2491 y
+ image_y
+ map
->y
,
2492 brw
->has_swizzling
);
2493 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2497 intel_miptree_unmap_raw(mt
);
2499 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2500 map
->x
, map
->y
, map
->w
, map
->h
,
2501 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2503 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2504 map
->x
, map
->y
, map
->w
, map
->h
,
2505 mt
, map
->ptr
, map
->stride
);
2510 intel_miptree_unmap_s8(struct brw_context
*brw
,
2511 struct intel_mipmap_tree
*mt
,
2512 struct intel_miptree_map
*map
,
2516 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2517 unsigned int image_x
, image_y
;
2518 uint8_t *untiled_s8_map
= map
->ptr
;
2519 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2521 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2523 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2524 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2525 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2526 image_x
+ x
+ map
->x
,
2527 image_y
+ y
+ map
->y
,
2528 brw
->has_swizzling
);
2529 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2533 intel_miptree_unmap_raw(mt
);
2540 intel_miptree_map_etc(struct brw_context
*brw
,
2541 struct intel_mipmap_tree
*mt
,
2542 struct intel_miptree_map
*map
,
2546 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2547 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2548 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2551 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2552 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2554 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2555 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2556 map
->w
, map
->h
, 1));
2557 map
->ptr
= map
->buffer
;
2561 intel_miptree_unmap_etc(struct brw_context
*brw
,
2562 struct intel_mipmap_tree
*mt
,
2563 struct intel_miptree_map
*map
,
2569 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2574 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2575 + image_y
* mt
->pitch
2576 + image_x
* mt
->cpp
;
2578 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2579 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2580 map
->ptr
, map
->stride
,
2583 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2584 map
->ptr
, map
->stride
,
2585 map
->w
, map
->h
, mt
->etc_format
);
2587 intel_miptree_unmap_raw(mt
);
2592 * Mapping function for packed depth/stencil miptrees backed by real separate
2593 * miptrees for depth and stencil.
2595 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2596 * separate from the depth buffer. Yet at the GL API level, we have to expose
2597 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2598 * be able to map that memory for texture storage and glReadPixels-type
2599 * operations. We give Mesa core that access by mallocing a temporary and
2600 * copying the data between the actual backing store and the temporary.
2603 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2604 struct intel_mipmap_tree
*mt
,
2605 struct intel_miptree_map
*map
,
2606 unsigned int level
, unsigned int slice
)
2608 struct intel_mipmap_tree
*z_mt
= mt
;
2609 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2610 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2611 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2613 map
->stride
= map
->w
* packed_bpp
;
2614 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2618 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2619 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2620 * invalidate is set, since we'll be writing the whole rectangle from our
2621 * temporary buffer back out.
2623 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2624 uint32_t *packed_map
= map
->ptr
;
2625 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2626 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2627 unsigned int s_image_x
, s_image_y
;
2628 unsigned int z_image_x
, z_image_y
;
2630 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2631 &s_image_x
, &s_image_y
);
2632 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2633 &z_image_x
, &z_image_y
);
2635 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2636 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2637 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2638 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2641 brw
->has_swizzling
);
2642 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2644 (map_x
+ z_image_x
));
2645 uint8_t s
= s_map
[s_offset
];
2646 uint32_t z
= z_map
[z_offset
];
2648 if (map_z32f_x24s8
) {
2649 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2650 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2652 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2657 intel_miptree_unmap_raw(s_mt
);
2658 intel_miptree_unmap_raw(z_mt
);
2660 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2662 map
->x
, map
->y
, map
->w
, map
->h
,
2663 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2664 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2665 map
->ptr
, map
->stride
);
2667 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2668 map
->x
, map
->y
, map
->w
, map
->h
,
2669 mt
, map
->ptr
, map
->stride
);
2674 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2675 struct intel_mipmap_tree
*mt
,
2676 struct intel_miptree_map
*map
,
2680 struct intel_mipmap_tree
*z_mt
= mt
;
2681 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2682 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2684 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2685 uint32_t *packed_map
= map
->ptr
;
2686 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2687 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2688 unsigned int s_image_x
, s_image_y
;
2689 unsigned int z_image_x
, z_image_y
;
2691 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2692 &s_image_x
, &s_image_y
);
2693 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2694 &z_image_x
, &z_image_y
);
2696 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2697 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2698 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2699 x
+ s_image_x
+ map
->x
,
2700 y
+ s_image_y
+ map
->y
,
2701 brw
->has_swizzling
);
2702 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2704 (x
+ z_image_x
+ map
->x
));
2706 if (map_z32f_x24s8
) {
2707 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2708 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2710 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2711 s_map
[s_offset
] = packed
>> 24;
2712 z_map
[z_offset
] = packed
;
2717 intel_miptree_unmap_raw(s_mt
);
2718 intel_miptree_unmap_raw(z_mt
);
2720 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2722 map
->x
, map
->y
, map
->w
, map
->h
,
2723 z_mt
, _mesa_get_format_name(z_mt
->format
),
2724 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2725 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2726 map
->ptr
, map
->stride
);
2733 * Create and attach a map to the miptree at (level, slice). Return the
2736 static struct intel_miptree_map
*
2737 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2746 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2751 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2752 mt
->level
[level
].slice
[slice
].map
= map
;
2764 * Release the map at (level, slice).
2767 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2771 struct intel_miptree_map
**map
;
2773 map
= &mt
->level
[level
].slice
[slice
].map
;
2779 can_blit_slice(struct intel_mipmap_tree
*mt
,
2780 unsigned int level
, unsigned int slice
)
2784 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2785 if (image_x
>= 32768 || image_y
>= 32768)
2788 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2789 if (mt
->pitch
>= 32768)
2796 use_intel_mipree_map_blit(struct brw_context
*brw
,
2797 struct intel_mipmap_tree
*mt
,
2803 /* It's probably not worth swapping to the blit ring because of
2804 * all the overhead involved. But, we must use blitter for the
2805 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2807 (!(mode
& GL_MAP_WRITE_BIT
) ||
2808 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2810 (mt
->tiling
== I915_TILING_X
||
2811 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2812 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2813 /* Fast copy blit on skl+ supports all tiling formats. */
2815 can_blit_slice(mt
, level
, slice
))
2818 if (mt
->tiling
!= I915_TILING_NONE
&&
2819 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2820 assert(can_blit_slice(mt
, level
, slice
));
2828 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2829 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2830 * arithmetic overflow.
2832 * If you call this function and use \a out_stride, then you're doing pointer
2833 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2834 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2835 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2836 * which usually have type uint32_t or GLuint.
2839 intel_miptree_map(struct brw_context
*brw
,
2840 struct intel_mipmap_tree
*mt
,
2849 ptrdiff_t *out_stride
)
2851 struct intel_miptree_map
*map
;
2853 assert(mt
->num_samples
<= 1);
2855 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2862 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2863 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2864 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2867 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2868 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2869 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2870 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2871 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2872 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2873 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2874 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2875 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2876 #if defined(USE_SSE41)
2877 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2878 !mt
->compressed
&& cpu_has_sse4_1
&&
2879 (mt
->pitch
% 16 == 0)) {
2880 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2883 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2884 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2885 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2888 *out_ptr
= map
->ptr
;
2889 *out_stride
= map
->stride
;
2891 if (map
->ptr
== NULL
)
2892 intel_miptree_release_map(mt
, level
, slice
);
2896 intel_miptree_unmap(struct brw_context
*brw
,
2897 struct intel_mipmap_tree
*mt
,
2901 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2903 assert(mt
->num_samples
<= 1);
2908 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2909 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2911 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2912 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2913 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2914 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2915 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2916 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2917 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2918 } else if (map
->linear_mt
) {
2919 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2920 #if defined(USE_SSE41)
2921 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2922 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2925 intel_miptree_unmap_gtt(mt
);
2928 intel_miptree_release_map(mt
, level
, slice
);