2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
289 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
290 unsigned depth0
, struct intel_mipmap_level
*table
)
292 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
294 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
296 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
297 if (!table
[level
].slice
)
304 for (unsigned level
= first_level
; level
<= last_level
; level
++)
305 free(table
[level
].slice
);
311 * @param for_bo Indicates that the caller is
312 * intel_miptree_create_for_bo(). If true, then do not create
315 static struct intel_mipmap_tree
*
316 intel_miptree_create_layout(struct brw_context
*brw
,
325 uint32_t layout_flags
)
327 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
331 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
332 _mesa_enum_to_string(target
),
333 _mesa_get_format_name(format
),
334 first_level
, last_level
, depth0
, mt
);
336 if (target
== GL_TEXTURE_1D_ARRAY
)
337 assert(height0
== 1);
341 mt
->first_level
= first_level
;
342 mt
->last_level
= last_level
;
343 mt
->logical_width0
= width0
;
344 mt
->logical_height0
= height0
;
345 mt
->logical_depth0
= depth0
;
346 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
347 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
348 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
349 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
350 mt
->aux_state
= NULL
;
351 mt
->cpp
= _mesa_get_format_bytes(format
);
352 mt
->num_samples
= num_samples
;
353 mt
->compressed
= _mesa_is_format_compressed(format
);
354 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
357 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
358 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
360 int depth_multiply
= 1;
361 if (num_samples
> 1) {
362 /* Adjust width/height/depth for MSAA */
363 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
364 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
365 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
366 * "If the surface is multisampled and it is a depth or stencil
367 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
368 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
371 * +----------------------------------------------------------------+
372 * | Num Multisamples | W_l = | H_l = |
373 * +----------------------------------------------------------------+
374 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
375 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
376 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
377 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
378 * +----------------------------------------------------------------+
381 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
382 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
383 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
385 * Another more complicated explanation for these adjustments comes
386 * from the Sandybridge PRM, volume 4, part 1, page 31:
388 * "Any of the other messages (sample*, LOD, load4) used with a
389 * (4x) multisampled surface will in-effect sample a surface with
390 * double the height and width as that indicated in the surface
391 * state. Each pixel position on the original-sized surface is
392 * replaced with a 2x2 of samples with the following arrangement:
397 * Thus, when sampling from a multisampled texture, it behaves as
398 * though the layout in memory for (x,y,sample) is:
400 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
401 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
403 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
404 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
406 * However, the actual layout of multisampled data in memory is:
408 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
409 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
411 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
412 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
414 * This pattern repeats for each 2x2 pixel block.
416 * As a result, when calculating the size of our 4-sample buffer for
417 * an odd width or height, we have to align before scaling up because
418 * sample 3 is in that bottom right 2x2 block.
420 switch (num_samples
) {
422 assert(brw
->gen
>= 8);
423 width0
= ALIGN(width0
, 2) * 2;
424 height0
= ALIGN(height0
, 2);
427 width0
= ALIGN(width0
, 2) * 2;
428 height0
= ALIGN(height0
, 2) * 2;
431 width0
= ALIGN(width0
, 2) * 4;
432 height0
= ALIGN(height0
, 2) * 2;
435 width0
= ALIGN(width0
, 2) * 4;
436 height0
= ALIGN(height0
, 2) * 4;
439 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
442 unreachable("not reached");
445 /* Non-interleaved */
446 depth_multiply
= num_samples
;
447 depth0
*= depth_multiply
;
451 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
457 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
458 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
459 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
460 * used on Gen8 to make it pick a qpitch value which doesn't include space
461 * for the mipmaps. On Gen9 this is not necessary because it will
462 * automatically pick a packed qpitch value whenever mt->first_level ==
464 * TODO: can we use it elsewhere?
465 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
468 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
470 switch (mt
->msaa_layout
) {
471 case INTEL_MSAA_LAYOUT_NONE
:
472 case INTEL_MSAA_LAYOUT_IMS
:
473 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
475 case INTEL_MSAA_LAYOUT_UMS
:
476 case INTEL_MSAA_LAYOUT_CMS
:
477 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
482 if (target
== GL_TEXTURE_CUBE_MAP
)
483 assert(depth0
== 6 * depth_multiply
);
485 mt
->physical_width0
= width0
;
486 mt
->physical_height0
= height0
;
487 mt
->physical_depth0
= depth0
;
489 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
490 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
491 (brw
->must_use_separate_stencil
||
492 (brw
->has_separate_stencil
&&
493 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
494 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
496 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
499 mt
->stencil_mt
= intel_miptree_create(brw
,
510 if (!mt
->stencil_mt
) {
511 intel_miptree_release(&mt
);
514 mt
->stencil_mt
->r8stencil_needs_update
= true;
516 /* Fix up the Z miptree format for how we're splitting out separate
517 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
519 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
522 if (format
== mt
->format
) {
523 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
524 _mesa_get_format_name(mt
->format
));
528 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
529 mt
->array_layout
= GEN6_HIZ_STENCIL
;
532 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
533 * multisampled or have an AUX buffer attached to it.
535 * GEN | MSRT | AUX_CCS_* or AUX_MCS
536 * -------------------------------------------
537 * 9 | HALIGN_16 | HALIGN_16
538 * 8 | HALIGN_ANY | HALIGN_16
542 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
543 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
544 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
545 } else if (brw
->gen
>= 9 && num_samples
> 1) {
546 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
548 const UNUSED
bool is_lossless_compressed_aux
=
549 brw
->gen
>= 9 && num_samples
== 1 &&
550 mt
->format
== MESA_FORMAT_R_UINT32
;
552 /* For now, nothing else has this requirement */
553 assert(is_lossless_compressed_aux
||
554 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
557 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
558 intel_miptree_release(&mt
);
562 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
563 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
570 * Choose an appropriate uncompressed format for a requested
571 * compressed format, if unsupported.
574 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
576 /* No need to lower ETC formats on these platforms,
577 * they are supported natively.
579 if (brw
->gen
>= 8 || brw
->is_baytrail
)
583 case MESA_FORMAT_ETC1_RGB8
:
584 return MESA_FORMAT_R8G8B8X8_UNORM
;
585 case MESA_FORMAT_ETC2_RGB8
:
586 return MESA_FORMAT_R8G8B8X8_UNORM
;
587 case MESA_FORMAT_ETC2_SRGB8
:
588 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
589 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
590 return MESA_FORMAT_B8G8R8A8_SRGB
;
591 case MESA_FORMAT_ETC2_RGBA8_EAC
:
592 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
593 return MESA_FORMAT_R8G8B8A8_UNORM
;
594 case MESA_FORMAT_ETC2_R11_EAC
:
595 return MESA_FORMAT_R_UNORM16
;
596 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
597 return MESA_FORMAT_R_SNORM16
;
598 case MESA_FORMAT_ETC2_RG11_EAC
:
599 return MESA_FORMAT_R16G16_UNORM
;
600 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
601 return MESA_FORMAT_R16G16_SNORM
;
603 /* Non ETC1 / ETC2 format */
608 static enum isl_aux_state
**
609 create_aux_state_map(struct intel_mipmap_tree
*mt
,
610 enum isl_aux_state initial
)
612 const uint32_t levels
= mt
->last_level
+ 1;
614 uint32_t total_slices
= 0;
615 for (uint32_t level
= 0; level
< levels
; level
++)
616 total_slices
+= mt
->level
[level
].depth
;
618 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
620 /* We're going to allocate a single chunk of data for both the per-level
621 * reference array and the arrays of aux_state. This makes cleanup
622 * significantly easier.
624 const size_t total_size
= per_level_array_size
+
625 total_slices
* sizeof(enum isl_aux_state
);
626 void *data
= malloc(total_size
);
630 enum isl_aux_state
**per_level_arr
= data
;
631 enum isl_aux_state
*s
= data
+ per_level_array_size
;
632 for (uint32_t level
= 0; level
< levels
; level
++) {
633 per_level_arr
[level
] = s
;
634 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
637 assert((void *)s
== data
+ total_size
);
639 return per_level_arr
;
643 free_aux_state_map(enum isl_aux_state
**state
)
648 static struct intel_mipmap_tree
*
649 miptree_create(struct brw_context
*brw
,
658 uint32_t layout_flags
)
660 struct intel_mipmap_tree
*mt
;
661 mesa_format tex_format
= format
;
662 mesa_format etc_format
= MESA_FORMAT_NONE
;
663 uint32_t alloc_flags
= 0;
665 format
= intel_lower_compressed_format(brw
, format
);
667 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
669 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
670 mt
= intel_miptree_create_layout(brw
, target
, format
,
671 first_level
, last_level
, width0
,
672 height0
, depth0
, num_samples
,
677 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
678 mt
->tiling
= I915_TILING_Y
;
680 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
681 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
683 mt
->etc_format
= etc_format
;
685 if (format
== MESA_FORMAT_S_UINT8
) {
686 /* Align to size of W tile, 64x64. */
687 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
688 ALIGN(mt
->total_width
, 64),
689 ALIGN(mt
->total_height
, 64),
690 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
693 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
694 mt
->total_width
, mt
->total_height
,
695 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
699 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
700 mt
->bo
->cache_coherent
= false;
705 struct intel_mipmap_tree
*
706 intel_miptree_create(struct brw_context
*brw
,
715 uint32_t layout_flags
)
717 struct intel_mipmap_tree
*mt
= miptree_create(
719 first_level
, last_level
,
720 width0
, height0
, depth0
, num_samples
,
723 /* If the BO is too large to fit in the aperture, we need to use the
724 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
725 * handle Y-tiling, so we need to fall back to X.
727 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
728 mt
->tiling
== I915_TILING_Y
) {
729 const uint32_t alloc_flags
=
730 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
731 BO_ALLOC_FOR_RENDER
: 0;
732 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
733 mt
->total_width
, mt
->total_height
);
735 mt
->tiling
= I915_TILING_X
;
736 brw_bo_unreference(mt
->bo
);
737 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
738 mt
->total_width
, mt
->total_height
, mt
->cpp
,
739 mt
->tiling
, &mt
->pitch
, alloc_flags
);
745 intel_miptree_release(&mt
);
750 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
751 assert(mt
->num_samples
> 1);
752 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
753 intel_miptree_release(&mt
);
758 /* If this miptree is capable of supporting fast color clears, set
759 * fast_clear_state appropriately to ensure that fast clears will occur.
760 * Allocation of the MCS miptree will be deferred until the first fast
761 * clear actually occurs or when compressed single sampled buffer is
762 * written by the GPU for the first time.
764 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
765 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
766 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
767 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
769 /* On Gen9+ clients are not currently capable of consuming compressed
770 * single-sampled buffers. Disabling compression allows us to skip
773 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
774 const bool is_lossless_compressed
=
775 unlikely(!lossless_compression_disabled
) &&
776 brw
->gen
>= 9 && !mt
->is_scanout
&&
777 intel_miptree_supports_lossless_compressed(brw
, mt
);
779 if (is_lossless_compressed
) {
780 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
787 struct intel_mipmap_tree
*
788 intel_miptree_create_for_bo(struct brw_context
*brw
,
796 uint32_t layout_flags
)
798 struct intel_mipmap_tree
*mt
;
799 uint32_t tiling
, swizzle
;
802 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
804 /* Nothing will be able to use this miptree with the BO if the offset isn't
807 if (tiling
!= I915_TILING_NONE
)
808 assert(offset
% 4096 == 0);
810 /* miptrees can't handle negative pitch. If you need flipping of images,
811 * that's outside of the scope of the mt.
815 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
817 /* The BO already has a tiling format and we shouldn't confuse the lower
818 * layers by making it try to find a tiling format again.
820 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
821 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
823 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
824 mt
= intel_miptree_create_layout(brw
, target
, format
,
826 width
, height
, depth
, 0,
831 brw_bo_reference(bo
);
841 * For a singlesample renderbuffer, this simply wraps the given BO with a
844 * For a multisample renderbuffer, this wraps the window system's
845 * (singlesample) BO with a singlesample miptree attached to the
846 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
847 * that will contain the actual rendering (which is lazily resolved to
848 * irb->singlesample_mt).
851 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
852 struct intel_renderbuffer
*irb
,
854 uint32_t width
, uint32_t height
,
857 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
858 struct intel_mipmap_tree
*multisample_mt
= NULL
;
859 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
860 mesa_format format
= rb
->Format
;
861 int num_samples
= rb
->NumSamples
;
863 /* Only the front and back buffers, which are color buffers, are allocated
864 * through the image loader.
866 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
867 _mesa_get_format_base_format(format
) == GL_RGBA
);
869 singlesample_mt
= intel_miptree_create_for_bo(intel
,
877 MIPTREE_LAYOUT_FOR_SCANOUT
);
878 if (!singlesample_mt
)
881 /* If this miptree is capable of supporting fast color clears, set
882 * mcs_state appropriately to ensure that fast clears will occur.
883 * Allocation of the MCS miptree will be deferred until the first fast
884 * clear actually occurs.
886 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
887 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
888 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
891 if (num_samples
== 0) {
892 intel_miptree_release(&irb
->mt
);
893 irb
->mt
= singlesample_mt
;
895 assert(!irb
->singlesample_mt
);
897 intel_miptree_release(&irb
->singlesample_mt
);
898 irb
->singlesample_mt
= singlesample_mt
;
901 irb
->mt
->logical_width0
!= width
||
902 irb
->mt
->logical_height0
!= height
) {
903 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
911 irb
->need_downsample
= false;
912 intel_miptree_release(&irb
->mt
);
913 irb
->mt
= multisample_mt
;
919 intel_miptree_release(&irb
->singlesample_mt
);
920 intel_miptree_release(&irb
->mt
);
924 struct intel_mipmap_tree
*
925 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
929 uint32_t num_samples
)
931 struct intel_mipmap_tree
*mt
;
934 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
935 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
936 MIPTREE_LAYOUT_TILING_ANY
|
937 MIPTREE_LAYOUT_FOR_SCANOUT
;
939 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
940 width
, height
, depth
, num_samples
,
945 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
946 ok
= intel_miptree_alloc_hiz(brw
, mt
);
954 intel_miptree_release(&mt
);
959 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
960 struct intel_mipmap_tree
*src
)
965 intel_miptree_release(dst
);
969 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
976 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
982 intel_miptree_release(&hiz_buf
->mt
);
984 brw_bo_unreference(hiz_buf
->aux_base
.bo
);
990 intel_miptree_release(struct intel_mipmap_tree
**mt
)
995 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
996 if (--(*mt
)->refcount
<= 0) {
999 DBG("%s deleting %p\n", __func__
, *mt
);
1001 brw_bo_unreference((*mt
)->bo
);
1002 intel_miptree_release(&(*mt
)->stencil_mt
);
1003 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1004 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
1005 if ((*mt
)->mcs_buf
) {
1006 brw_bo_unreference((*mt
)->mcs_buf
->bo
);
1007 free((*mt
)->mcs_buf
);
1009 free_aux_state_map((*mt
)->aux_state
);
1011 intel_miptree_release(&(*mt
)->plane
[0]);
1012 intel_miptree_release(&(*mt
)->plane
[1]);
1014 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1015 free((*mt
)->level
[i
].slice
);
1025 intel_get_image_dims(struct gl_texture_image
*image
,
1026 int *width
, int *height
, int *depth
)
1028 switch (image
->TexObject
->Target
) {
1029 case GL_TEXTURE_1D_ARRAY
:
1030 /* For a 1D Array texture the OpenGL API will treat the image height as
1031 * the number of array slices. For Intel hardware, we treat the 1D array
1032 * as a 2D Array with a height of 1. So, here we want to swap image
1035 assert(image
->Depth
== 1);
1036 *width
= image
->Width
;
1038 *depth
= image
->Height
;
1040 case GL_TEXTURE_CUBE_MAP
:
1041 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1042 * though we really have 6 slices.
1044 assert(image
->Depth
== 1);
1045 *width
= image
->Width
;
1046 *height
= image
->Height
;
1050 *width
= image
->Width
;
1051 *height
= image
->Height
;
1052 *depth
= image
->Depth
;
1058 * Can the image be pulled into a unified mipmap tree? This mirrors
1059 * the completeness test in a lot of ways.
1061 * Not sure whether I want to pass gl_texture_image here.
1064 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1065 struct gl_texture_image
*image
)
1067 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1068 GLuint level
= intelImage
->base
.Base
.Level
;
1069 int width
, height
, depth
;
1071 /* glTexImage* choose the texture object based on the target passed in, and
1072 * objects can't change targets over their lifetimes, so this should be
1075 assert(image
->TexObject
->Target
== mt
->target
);
1077 mesa_format mt_format
= mt
->format
;
1078 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1079 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1080 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1081 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1082 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1083 mt_format
= mt
->etc_format
;
1085 if (image
->TexFormat
!= mt_format
)
1088 intel_get_image_dims(image
, &width
, &height
, &depth
);
1090 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1093 int level_depth
= mt
->level
[level
].depth
;
1094 if (mt
->num_samples
> 1) {
1095 switch (mt
->msaa_layout
) {
1096 case INTEL_MSAA_LAYOUT_NONE
:
1097 case INTEL_MSAA_LAYOUT_IMS
:
1099 case INTEL_MSAA_LAYOUT_UMS
:
1100 case INTEL_MSAA_LAYOUT_CMS
:
1101 level_depth
/= mt
->num_samples
;
1106 /* Test image dimensions against the base level image adjusted for
1107 * minification. This will also catch images not present in the
1108 * tree, changed targets, etc.
1110 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1111 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1112 depth
!= level_depth
) {
1116 if (image
->NumSamples
!= mt
->num_samples
)
1124 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1126 GLuint x
, GLuint y
, GLuint d
)
1128 mt
->level
[level
].depth
= d
;
1129 mt
->level
[level
].level_x
= x
;
1130 mt
->level
[level
].level_y
= y
;
1132 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1135 assert(mt
->level
[level
].slice
);
1137 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1138 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1143 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1144 GLuint level
, GLuint img
,
1147 if (img
== 0 && level
== 0)
1148 assert(x
== 0 && y
== 0);
1150 assert(img
< mt
->level
[level
].depth
);
1152 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1153 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1155 DBG("%s level %d img %d pos %d,%d\n",
1156 __func__
, level
, img
,
1157 mt
->level
[level
].slice
[img
].x_offset
,
1158 mt
->level
[level
].slice
[img
].y_offset
);
1162 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1163 GLuint level
, GLuint slice
,
1164 GLuint
*x
, GLuint
*y
)
1166 assert(slice
< mt
->level
[level
].depth
);
1168 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1169 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1174 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1175 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1176 * and tile_h is set to 1.
1179 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1180 uint32_t *tile_w
, uint32_t *tile_h
)
1191 case I915_TILING_NONE
:
1196 unreachable("not reached");
1202 * This function computes masks that may be used to select the bits of the X
1203 * and Y coordinates that indicate the offset within a tile. If the BO is
1204 * untiled, the masks are set to 0.
1207 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1208 uint32_t *mask_x
, uint32_t *mask_y
)
1210 uint32_t tile_w_bytes
, tile_h
;
1212 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1214 *mask_x
= tile_w_bytes
/ cpp
- 1;
1215 *mask_y
= tile_h
- 1;
1219 * Compute the offset (in bytes) from the start of the BO to the given x
1220 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1221 * multiples of the tile size.
1224 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1225 uint32_t x
, uint32_t y
)
1228 uint32_t pitch
= mt
->pitch
;
1229 uint32_t tiling
= mt
->tiling
;
1233 unreachable("not reached");
1234 case I915_TILING_NONE
:
1235 return y
* pitch
+ x
* cpp
;
1237 assert((x
% (512 / cpp
)) == 0);
1238 assert((y
% 8) == 0);
1239 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1241 assert((x
% (128 / cpp
)) == 0);
1242 assert((y
% 32) == 0);
1243 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1248 * Rendering with tiled buffers requires that the base address of the buffer
1249 * be aligned to a page boundary. For renderbuffers, and sometimes with
1250 * textures, we may want the surface to point at a texture image level that
1251 * isn't at a page boundary.
1253 * This function returns an appropriately-aligned base offset
1254 * according to the tiling restrictions, plus any required x/y offset
1258 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1259 GLuint level
, GLuint slice
,
1264 uint32_t mask_x
, mask_y
;
1266 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1267 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1269 *tile_x
= x
& mask_x
;
1270 *tile_y
= y
& mask_y
;
1272 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1276 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1277 struct intel_mipmap_tree
*src_mt
,
1278 unsigned src_level
, unsigned src_layer
,
1279 struct intel_mipmap_tree
*dst_mt
,
1280 unsigned dst_level
, unsigned dst_layer
,
1281 unsigned width
, unsigned height
)
1284 ptrdiff_t src_stride
, dst_stride
;
1285 int cpp
= dst_mt
->cpp
;
1287 intel_miptree_map(brw
, src_mt
,
1288 src_level
, src_layer
,
1291 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1294 intel_miptree_map(brw
, dst_mt
,
1295 dst_level
, dst_layer
,
1298 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1302 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1303 _mesa_get_format_name(src_mt
->format
),
1304 src_mt
, src
, src_stride
,
1305 _mesa_get_format_name(dst_mt
->format
),
1306 dst_mt
, dst
, dst_stride
,
1309 int row_size
= cpp
* width
;
1310 if (src_stride
== row_size
&&
1311 dst_stride
== row_size
) {
1312 memcpy(dst
, src
, row_size
* height
);
1314 for (int i
= 0; i
< height
; i
++) {
1315 memcpy(dst
, src
, row_size
);
1321 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1322 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1324 /* Don't forget to copy the stencil data over, too. We could have skipped
1325 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1326 * shuffling the two data sources in/out of temporary storage instead of
1327 * the direct mapping we get this way.
1329 if (dst_mt
->stencil_mt
) {
1330 assert(src_mt
->stencil_mt
);
1331 intel_miptree_copy_slice_sw(brw
,
1332 src_mt
->stencil_mt
, src_level
, src_layer
,
1333 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1339 intel_miptree_copy_slice(struct brw_context
*brw
,
1340 struct intel_mipmap_tree
*src_mt
,
1341 unsigned src_level
, unsigned src_layer
,
1342 struct intel_mipmap_tree
*dst_mt
,
1343 unsigned dst_level
, unsigned dst_layer
)
1346 uint32_t width
= minify(src_mt
->physical_width0
,
1347 src_level
- src_mt
->first_level
);
1348 uint32_t height
= minify(src_mt
->physical_height0
,
1349 src_level
- src_mt
->first_level
);
1350 mesa_format format
= src_mt
->format
;
1352 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1353 assert(src_mt
->format
== dst_mt
->format
);
1355 if (dst_mt
->compressed
) {
1357 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1358 height
= ALIGN_NPOT(height
, j
) / j
;
1359 width
= ALIGN_NPOT(width
, i
) / i
;
1362 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1363 * below won't apply since we can't do the depth's Y tiling or the
1364 * stencil's W tiling in the blitter.
1366 if (src_mt
->stencil_mt
) {
1367 intel_miptree_copy_slice_sw(brw
,
1368 src_mt
, src_level
, src_layer
,
1369 dst_mt
, dst_level
, dst_layer
,
1374 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1375 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1377 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1380 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1381 _mesa_get_format_name(src_mt
->format
),
1382 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1383 _mesa_get_format_name(dst_mt
->format
),
1384 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1387 if (!intel_miptree_blit(brw
,
1388 src_mt
, src_level
, src_layer
, 0, 0, false,
1389 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1390 width
, height
, GL_COPY
)) {
1391 perf_debug("miptree validate blit for %s failed\n",
1392 _mesa_get_format_name(format
));
1394 intel_miptree_copy_slice_sw(brw
,
1395 src_mt
, src_level
, src_layer
,
1396 dst_mt
, dst_level
, dst_layer
,
1402 * Copies the image's current data to the given miptree, and associates that
1403 * miptree with the image.
1405 * If \c invalidate is true, then the actual image data does not need to be
1406 * copied, but the image still needs to be associated to the new miptree (this
1407 * is set to true if we're about to clear the image).
1410 intel_miptree_copy_teximage(struct brw_context
*brw
,
1411 struct intel_texture_image
*intelImage
,
1412 struct intel_mipmap_tree
*dst_mt
,
1415 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1416 struct intel_texture_object
*intel_obj
=
1417 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1418 int level
= intelImage
->base
.Base
.Level
;
1419 const unsigned face
= intelImage
->base
.Base
.Face
;
1420 unsigned start_layer
, end_layer
;
1422 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1424 assert(intelImage
->base
.Base
.Height
);
1426 end_layer
= intelImage
->base
.Base
.Height
- 1;
1427 } else if (face
> 0) {
1431 assert(intelImage
->base
.Base
.Depth
);
1433 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1437 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1438 intel_miptree_copy_slice(brw
,
1444 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1445 intel_obj
->needs_validate
= true;
1449 intel_miptree_init_mcs(struct brw_context
*brw
,
1450 struct intel_mipmap_tree
*mt
,
1453 assert(mt
->mcs_buf
!= NULL
);
1455 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1457 * When MCS buffer is enabled and bound to MSRT, it is required that it
1458 * is cleared prior to any rendering.
1460 * Since we don't use the MCS buffer for any purpose other than rendering,
1461 * it makes sense to just clear it immediately upon allocation.
1463 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1465 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1466 if (unlikely(map
== NULL
)) {
1467 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1468 brw_bo_unreference(mt
->mcs_buf
->bo
);
1473 memset(data
, init_value
, mt
->mcs_buf
->size
);
1474 brw_bo_unmap(mt
->mcs_buf
->bo
);
1477 static struct intel_miptree_aux_buffer
*
1478 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1479 struct intel_mipmap_tree
*mt
,
1482 unsigned mcs_height
,
1483 uint32_t layout_flags
)
1485 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1486 struct intel_mipmap_tree
*temp_mt
;
1491 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1493 * "The MCS surface must be stored as Tile Y."
1495 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1496 temp_mt
= miptree_create(brw
,
1504 0 /* num_samples */,
1511 buf
->bo
= temp_mt
->bo
;
1512 buf
->offset
= temp_mt
->offset
;
1513 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1514 buf
->pitch
= temp_mt
->pitch
;
1515 buf
->qpitch
= temp_mt
->qpitch
;
1517 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1518 * structure should go away. We use miptree create simply as a means to make
1519 * sure all the constraints for the buffer are satisfied.
1521 brw_bo_reference(temp_mt
->bo
);
1522 intel_miptree_release(&temp_mt
);
1528 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1529 struct intel_mipmap_tree
*mt
,
1532 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1533 assert(mt
->mcs_buf
== NULL
);
1534 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1536 /* Choose the correct format for the MCS buffer. All that really matters
1537 * is that we allocate the right buffer size, since we'll always be
1538 * accessing this miptree using MCS-specific hardware mechanisms, which
1539 * infer the correct format based on num_samples.
1542 switch (num_samples
) {
1545 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1548 format
= MESA_FORMAT_R_UNORM8
;
1551 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1552 * for each sample, plus 8 padding bits).
1554 format
= MESA_FORMAT_R_UINT32
;
1557 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1560 format
= MESA_FORMAT_RG_UINT32
;
1563 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1566 /* Multisampled miptrees are only supported for single level. */
1567 assert(mt
->first_level
== 0);
1568 enum isl_aux_state
**aux_state
=
1569 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1574 intel_mcs_miptree_buf_create(brw
, mt
,
1577 mt
->logical_height0
,
1578 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1584 mt
->aux_state
= aux_state
;
1586 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1592 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1593 struct intel_mipmap_tree
*mt
,
1594 bool is_lossless_compressed
)
1596 assert(mt
->mcs_buf
== NULL
);
1597 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1599 struct isl_surf temp_main_surf
;
1600 struct isl_surf temp_ccs_surf
;
1602 /* Create first an ISL presentation for the main color surface and let ISL
1603 * calculate equivalent CCS surface against it.
1605 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1606 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1609 assert(temp_ccs_surf
.size
&&
1610 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1612 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1616 enum isl_aux_state
**aux_state
=
1617 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1623 buf
->size
= temp_ccs_surf
.size
;
1624 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1625 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1627 /* In case of compression mcs buffer needs to be initialised requiring the
1628 * buffer to be immediately mapped to cpu space for writing. Therefore do
1629 * not use the gpu access flag which can cause an unnecessary delay if the
1630 * backing pages happened to be just used by the GPU.
1632 const uint32_t alloc_flags
=
1633 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1635 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree", buf
->size
,
1636 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1644 mt
->aux_state
= aux_state
;
1646 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1647 * used for lossless compression which requires similar initialisation
1648 * as multi-sample compression.
1650 if (is_lossless_compressed
) {
1651 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1652 * resolve. Initialize it accordingly in case the first renderer is
1653 * cpu (or other none compression aware party).
1655 * This is also explicitly stated in the spec (MCS Buffer for Render
1657 * "If Software wants to enable Color Compression without Fast clear,
1658 * Software needs to initialize MCS with zeros."
1660 intel_miptree_init_mcs(brw
, mt
, 0);
1661 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1668 * Helper for intel_miptree_alloc_hiz() that sets
1669 * \c mt->level[level].has_hiz. Return true if and only if
1670 * \c has_hiz was set.
1673 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1674 struct intel_mipmap_tree
*mt
,
1677 assert(mt
->hiz_buf
);
1679 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1680 uint32_t width
= minify(mt
->physical_width0
, level
);
1681 uint32_t height
= minify(mt
->physical_height0
, level
);
1683 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1684 * and the height is 4 aligned. This allows our HiZ support
1685 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1686 * we can grow the width & height to allow the HiZ op to
1687 * force the proper size alignments.
1689 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1690 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1695 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1696 mt
->level
[level
].has_hiz
= true;
1702 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1703 * buffer dimensions and allocates a bo for the hiz buffer.
1705 static struct intel_miptree_hiz_buffer
*
1706 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1707 struct intel_mipmap_tree
*mt
)
1709 unsigned z_width
= mt
->logical_width0
;
1710 unsigned z_height
= mt
->logical_height0
;
1711 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1712 unsigned hz_width
, hz_height
;
1713 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1718 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1719 * adjustments required for Z_Height and Z_Width based on multisampling.
1721 switch (mt
->num_samples
) {
1735 unreachable("unsupported sample count");
1738 const unsigned vertical_align
= 8; /* 'j' in the docs */
1739 const unsigned H0
= z_height
;
1740 const unsigned h0
= ALIGN(H0
, vertical_align
);
1741 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1742 const unsigned Z0
= z_depth
;
1744 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1745 hz_width
= ALIGN(z_width
, 16);
1747 if (mt
->target
== GL_TEXTURE_3D
) {
1751 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1752 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1753 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1754 hz_height
+= h_i
* Z_i
;
1755 H_i
= minify(H_i
, 1);
1756 Z_i
= minify(Z_i
, 1);
1759 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1761 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1763 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1764 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1765 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1768 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
1769 hz_width
, hz_height
, 1,
1770 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1771 BO_ALLOC_FOR_RENDER
);
1772 if (!buf
->aux_base
.bo
) {
1777 buf
->aux_base
.size
= hz_width
* hz_height
;
1784 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1785 * buffer dimensions and allocates a bo for the hiz buffer.
1787 static struct intel_miptree_hiz_buffer
*
1788 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1789 struct intel_mipmap_tree
*mt
)
1791 unsigned z_width
= mt
->logical_width0
;
1792 unsigned z_height
= mt
->logical_height0
;
1793 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1794 unsigned hz_width
, hz_height
;
1795 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1800 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1801 * adjustments required for Z_Height and Z_Width based on multisampling.
1804 switch (mt
->num_samples
) {
1818 unreachable("unsupported sample count");
1822 const unsigned vertical_align
= 8; /* 'j' in the docs */
1823 const unsigned H0
= z_height
;
1824 const unsigned h0
= ALIGN(H0
, vertical_align
);
1825 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1826 const unsigned Z0
= z_depth
;
1828 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1829 hz_width
= ALIGN(z_width
, 16);
1833 unsigned sum_h_i
= 0;
1834 unsigned hz_height_3d_sum
= 0;
1835 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1836 unsigned i
= level
- mt
->first_level
;
1837 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1838 /* sum(i=2 to m; h_i) */
1842 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1843 hz_height_3d_sum
+= h_i
* Z_i
;
1844 H_i
= minify(H_i
, 1);
1845 Z_i
= minify(Z_i
, 1);
1847 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1848 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1850 if (mt
->target
== GL_TEXTURE_3D
) {
1851 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1852 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1854 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1855 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1858 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
1859 hz_width
, hz_height
, 1,
1860 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1861 BO_ALLOC_FOR_RENDER
);
1862 if (!buf
->aux_base
.bo
) {
1867 buf
->aux_base
.size
= hz_width
* hz_height
;
1873 static struct intel_miptree_hiz_buffer
*
1874 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1875 struct intel_mipmap_tree
*mt
)
1877 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1878 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1881 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
1886 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1887 buf
->mt
= intel_miptree_create(brw
,
1893 mt
->logical_height0
,
1902 buf
->aux_base
.bo
= buf
->mt
->bo
;
1903 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1904 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1905 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
* 2;
1911 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1912 struct intel_mipmap_tree
*mt
)
1917 if (mt
->hiz_buf
!= NULL
)
1920 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1923 switch (mt
->format
) {
1924 case MESA_FORMAT_Z_FLOAT32
:
1925 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1926 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1927 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1928 case MESA_FORMAT_Z_UNORM16
:
1936 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1937 struct intel_mipmap_tree
*mt
)
1939 assert(mt
->hiz_buf
== NULL
);
1940 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1942 enum isl_aux_state
**aux_state
=
1943 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1947 if (brw
->gen
== 7) {
1948 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1949 } else if (brw
->gen
>= 8) {
1950 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1952 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1960 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1961 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1963 mt
->aux_state
= aux_state
;
1969 * Can the miptree sample using the hiz buffer?
1972 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1973 struct intel_mipmap_tree
*mt
)
1975 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1976 * so keep things conservative for now and never enable it unless we're SKL+.
1986 /* It seems the hardware won't fallback to the depth buffer if some of the
1987 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1988 * of the texture to be HiZ enabled.
1990 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1991 if (!intel_miptree_level_has_hiz(mt
, level
))
1995 /* If compressed multisampling is enabled, then we use it for the auxiliary
1998 * From the BDW PRM (Volume 2d: Command Reference: Structures
1999 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2001 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2002 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2004 * There is no such blurb for 1D textures, but there is sufficient evidence
2005 * that this is broken on SKL+.
2007 return (mt
->num_samples
<= 1 &&
2008 mt
->target
!= GL_TEXTURE_3D
&&
2009 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2013 * Does the miptree slice have hiz enabled?
2016 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2018 intel_miptree_check_level_layer(mt
, level
, 0);
2019 return mt
->level
[level
].has_hiz
;
2023 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2024 unsigned start_level
, unsigned num_levels
,
2025 unsigned start_layer
, unsigned num_layers
)
2027 assert(_mesa_is_format_color_format(mt
->format
));
2032 /* Clamp the level range to fit the miptree */
2033 assert(start_level
+ num_levels
>= start_level
);
2034 const uint32_t last_level
=
2035 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2036 start_level
= MAX2(mt
->first_level
, start_level
);
2037 num_levels
= last_level
- start_level
+ 1;
2039 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2040 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2041 for (unsigned a
= 0; a
< level_layers
; a
++) {
2042 enum isl_aux_state aux_state
=
2043 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2044 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2045 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2054 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2055 const struct intel_mipmap_tree
*mt
,
2056 unsigned level
, unsigned layer
)
2059 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2062 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2063 assert(brw
->gen
>= 8 ||
2064 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2066 /* Compression of arrayed msaa surfaces is supported. */
2067 if (mt
->num_samples
> 1)
2070 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2071 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2077 static enum blorp_fast_clear_op
2078 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2079 bool ccs_supported
, bool fast_clear_supported
)
2081 assert(ccs_supported
== fast_clear_supported
);
2083 switch (aux_state
) {
2084 case ISL_AUX_STATE_CLEAR
:
2085 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2087 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2089 return BLORP_FAST_CLEAR_OP_NONE
;
2091 case ISL_AUX_STATE_PASS_THROUGH
:
2092 return BLORP_FAST_CLEAR_OP_NONE
;
2094 case ISL_AUX_STATE_RESOLVED
:
2095 case ISL_AUX_STATE_AUX_INVALID
:
2096 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2100 unreachable("Invalid aux state for CCS_D");
2103 static enum blorp_fast_clear_op
2104 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2105 bool ccs_supported
, bool fast_clear_supported
)
2107 switch (aux_state
) {
2108 case ISL_AUX_STATE_CLEAR
:
2109 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2111 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2112 else if (!fast_clear_supported
)
2113 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2115 return BLORP_FAST_CLEAR_OP_NONE
;
2117 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2119 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2121 return BLORP_FAST_CLEAR_OP_NONE
;
2123 case ISL_AUX_STATE_PASS_THROUGH
:
2124 return BLORP_FAST_CLEAR_OP_NONE
;
2126 case ISL_AUX_STATE_RESOLVED
:
2127 case ISL_AUX_STATE_AUX_INVALID
:
2131 unreachable("Invalid aux state for CCS_E");
2135 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2136 struct intel_mipmap_tree
*mt
,
2137 uint32_t level
, uint32_t layer
,
2139 bool fast_clear_supported
)
2141 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2143 enum blorp_fast_clear_op resolve_op
;
2144 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2145 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2146 fast_clear_supported
);
2148 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2149 fast_clear_supported
);
2152 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2153 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2154 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2156 switch (resolve_op
) {
2157 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2158 /* The CCS full resolve operation destroys the CCS and sets it to the
2159 * pass-through state. (You can also think of this as being both a
2160 * resolve and an ambiguate in one operation.)
2162 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2163 ISL_AUX_STATE_PASS_THROUGH
);
2166 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2167 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2168 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2172 unreachable("Invalid resolve op");
2178 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2179 struct intel_mipmap_tree
*mt
,
2180 uint32_t level
, uint32_t layer
,
2181 bool written_with_ccs
)
2183 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2185 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2186 switch (aux_state
) {
2187 case ISL_AUX_STATE_CLEAR
:
2188 assert(written_with_ccs
);
2189 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2190 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2193 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2194 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2195 assert(written_with_ccs
);
2196 break; /* Nothing to do */
2198 case ISL_AUX_STATE_PASS_THROUGH
:
2199 if (written_with_ccs
) {
2200 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2201 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2207 case ISL_AUX_STATE_RESOLVED
:
2208 case ISL_AUX_STATE_AUX_INVALID
:
2209 unreachable("Invalid aux state for CCS_E");
2212 /* CCS_D is a bit simpler */
2213 switch (aux_state
) {
2214 case ISL_AUX_STATE_CLEAR
:
2215 assert(written_with_ccs
);
2216 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2217 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2220 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2221 assert(written_with_ccs
);
2222 break; /* Nothing to do */
2224 case ISL_AUX_STATE_PASS_THROUGH
:
2228 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2229 case ISL_AUX_STATE_RESOLVED
:
2230 case ISL_AUX_STATE_AUX_INVALID
:
2231 unreachable("Invalid aux state for CCS_D");
2237 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2238 struct intel_mipmap_tree
*mt
,
2239 uint32_t level
, uint32_t layer
,
2240 bool written_with_aux
)
2242 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2243 case ISL_AUX_STATE_CLEAR
:
2244 assert(written_with_aux
);
2245 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2246 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2249 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2250 assert(written_with_aux
);
2251 break; /* Nothing to do */
2253 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2254 case ISL_AUX_STATE_RESOLVED
:
2255 case ISL_AUX_STATE_PASS_THROUGH
:
2256 case ISL_AUX_STATE_AUX_INVALID
:
2257 unreachable("Invalid aux state for MCS");
2262 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2263 struct intel_mipmap_tree
*mt
,
2264 uint32_t level
, uint32_t layer
,
2265 bool hiz_supported
, bool fast_clear_supported
)
2267 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2268 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2269 case ISL_AUX_STATE_CLEAR
:
2270 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2271 if (!hiz_supported
|| !fast_clear_supported
)
2272 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2275 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2277 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2280 case ISL_AUX_STATE_PASS_THROUGH
:
2281 case ISL_AUX_STATE_RESOLVED
:
2284 case ISL_AUX_STATE_AUX_INVALID
:
2286 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2290 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2291 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2294 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2295 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2296 ISL_AUX_STATE_RESOLVED
);
2299 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2300 /* The HiZ resolve operation is actually an ambiguate */
2301 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2302 ISL_AUX_STATE_PASS_THROUGH
);
2306 unreachable("Invalid HiZ op");
2312 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2313 struct intel_mipmap_tree
*mt
,
2314 uint32_t level
, uint32_t layer
,
2315 bool written_with_hiz
)
2317 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2318 case ISL_AUX_STATE_CLEAR
:
2319 assert(written_with_hiz
);
2320 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2321 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2324 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2325 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2326 assert(written_with_hiz
);
2327 break; /* Nothing to do */
2329 case ISL_AUX_STATE_RESOLVED
:
2330 if (written_with_hiz
) {
2331 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2332 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2334 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2335 ISL_AUX_STATE_AUX_INVALID
);
2339 case ISL_AUX_STATE_PASS_THROUGH
:
2340 if (written_with_hiz
) {
2341 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2342 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2346 case ISL_AUX_STATE_AUX_INVALID
:
2347 assert(!written_with_hiz
);
2352 static inline uint32_t
2353 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2354 uint32_t start_level
, uint32_t num_levels
)
2356 assert(start_level
>= mt
->first_level
);
2357 assert(start_level
<= mt
->last_level
);
2359 if (num_levels
== INTEL_REMAINING_LAYERS
)
2360 num_levels
= mt
->last_level
- start_level
+ 1;
2361 /* Check for overflow */
2362 assert(start_level
+ num_levels
>= start_level
);
2363 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2368 static inline uint32_t
2369 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2370 uint32_t start_layer
, uint32_t num_layers
)
2372 assert(level
<= mt
->last_level
);
2373 uint32_t total_num_layers
= mt
->level
[level
].depth
;
2375 assert(start_layer
< total_num_layers
);
2376 if (num_layers
== INTEL_REMAINING_LAYERS
)
2377 num_layers
= total_num_layers
- start_layer
;
2378 /* Check for overflow */
2379 assert(start_layer
+ num_layers
>= start_layer
);
2380 assert(start_layer
+ num_layers
<= total_num_layers
);
2386 intel_miptree_prepare_access(struct brw_context
*brw
,
2387 struct intel_mipmap_tree
*mt
,
2388 uint32_t start_level
, uint32_t num_levels
,
2389 uint32_t start_layer
, uint32_t num_layers
,
2390 bool aux_supported
, bool fast_clear_supported
)
2392 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2394 if (_mesa_is_format_color_format(mt
->format
)) {
2398 if (mt
->num_samples
> 1) {
2399 /* Nothing to do for MSAA */
2400 assert(aux_supported
&& fast_clear_supported
);
2402 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2403 const uint32_t level
= start_level
+ l
;
2404 const uint32_t level_layers
=
2405 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2406 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2407 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2408 start_layer
+ a
, aux_supported
,
2409 fast_clear_supported
);
2413 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2414 /* Nothing to do for stencil */
2419 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2420 const uint32_t level
= start_level
+ l
;
2421 if (!intel_miptree_level_has_hiz(mt
, level
))
2424 const uint32_t level_layers
=
2425 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2426 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2427 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2429 fast_clear_supported
);
2436 intel_miptree_finish_write(struct brw_context
*brw
,
2437 struct intel_mipmap_tree
*mt
, uint32_t level
,
2438 uint32_t start_layer
, uint32_t num_layers
,
2439 bool written_with_aux
)
2441 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2443 if (_mesa_is_format_color_format(mt
->format
)) {
2447 if (mt
->num_samples
> 1) {
2448 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2449 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2453 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2454 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2458 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2459 /* Nothing to do for stencil */
2461 if (!intel_miptree_level_has_hiz(mt
, level
))
2464 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2465 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2472 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2473 uint32_t level
, uint32_t layer
)
2475 intel_miptree_check_level_layer(mt
, level
, layer
);
2477 if (_mesa_is_format_color_format(mt
->format
)) {
2478 assert(mt
->mcs_buf
!= NULL
);
2479 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2480 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2481 unreachable("Cannot get aux state for stencil");
2483 assert(intel_miptree_level_has_hiz(mt
, level
));
2486 return mt
->aux_state
[level
][layer
];
2490 intel_miptree_set_aux_state(struct brw_context
*brw
,
2491 struct intel_mipmap_tree
*mt
, uint32_t level
,
2492 uint32_t start_layer
, uint32_t num_layers
,
2493 enum isl_aux_state aux_state
)
2495 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2497 if (_mesa_is_format_color_format(mt
->format
)) {
2498 assert(mt
->mcs_buf
!= NULL
);
2499 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2500 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2501 unreachable("Cannot get aux state for stencil");
2503 assert(intel_miptree_level_has_hiz(mt
, level
));
2506 for (unsigned a
= 0; a
< num_layers
; a
++)
2507 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2510 /* On Gen9 color buffers may be compressed by the hardware (lossless
2511 * compression). There are, however, format restrictions and care needs to be
2512 * taken that the sampler engine is capable for re-interpreting a buffer with
2513 * format different the buffer was originally written with.
2515 * For example, SRGB formats are not compressible and the sampler engine isn't
2516 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2517 * color buffer needs to be resolved so that the sampling surface can be
2518 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2522 can_texture_with_ccs(struct brw_context
*brw
,
2523 struct intel_mipmap_tree
*mt
,
2524 mesa_format view_format
)
2526 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2529 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2530 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2532 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2533 isl_mt_format
, isl_view_format
)) {
2534 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2535 _mesa_get_format_name(view_format
),
2536 _mesa_get_format_name(mt
->format
));
2544 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2545 struct intel_mipmap_tree
*mt
,
2546 mesa_format view_format
,
2547 uint32_t start_level
, uint32_t num_levels
,
2548 uint32_t start_layer
, uint32_t num_layers
,
2549 bool *aux_supported_out
)
2551 bool aux_supported
, clear_supported
;
2552 if (_mesa_is_format_color_format(mt
->format
)) {
2553 if (mt
->num_samples
> 1) {
2554 aux_supported
= clear_supported
= true;
2556 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2558 /* Clear color is specified as ints or floats and the conversion is
2559 * done by the sampler. If we have a texture view, we would have to
2560 * perform the clear color conversion manually. Just disable clear
2563 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2565 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2566 aux_supported
= clear_supported
= false;
2568 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2571 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2572 start_layer
, num_layers
,
2573 aux_supported
, clear_supported
);
2574 if (aux_supported_out
)
2575 *aux_supported_out
= aux_supported
;
2579 intel_miptree_prepare_texture(struct brw_context
*brw
,
2580 struct intel_mipmap_tree
*mt
,
2581 mesa_format view_format
,
2582 bool *aux_supported_out
)
2584 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2585 0, INTEL_REMAINING_LEVELS
,
2586 0, INTEL_REMAINING_LAYERS
,
2591 intel_miptree_prepare_image(struct brw_context
*brw
,
2592 struct intel_mipmap_tree
*mt
)
2594 /* The data port doesn't understand any compression */
2595 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2596 0, INTEL_REMAINING_LAYERS
, false, false);
2600 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2601 struct intel_mipmap_tree
*mt
, uint32_t level
,
2602 uint32_t start_layer
, uint32_t num_layers
)
2604 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2605 start_layer
, num_layers
, NULL
);
2609 intel_miptree_prepare_render(struct brw_context
*brw
,
2610 struct intel_mipmap_tree
*mt
, uint32_t level
,
2611 uint32_t start_layer
, uint32_t layer_count
,
2614 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2615 * the single-sampled color renderbuffers because the CCS buffer isn't
2616 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2617 * enabled because otherwise the surface state will be programmed with
2618 * the linear equivalent format anyway.
2620 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2621 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2623 /* Lossless compression is not supported for SRGB formats, it
2624 * should be impossible to get here with such surfaces.
2626 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2627 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2631 /* For layered rendering non-compressed fast cleared buffers need to be
2632 * resolved. Surface state can carry only one fast color clear value
2633 * while each layer may have its own fast clear color value. For
2634 * compressed buffers color value is available in the color buffer.
2636 if (layer_count
> 1 &&
2637 !(mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) &&
2638 !intel_miptree_is_lossless_compressed(brw
, mt
)) {
2639 assert(brw
->gen
>= 8);
2641 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2647 intel_miptree_finish_render(struct brw_context
*brw
,
2648 struct intel_mipmap_tree
*mt
, uint32_t level
,
2649 uint32_t start_layer
, uint32_t layer_count
)
2651 assert(_mesa_is_format_color_format(mt
->format
));
2652 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2653 mt
->mcs_buf
!= NULL
);
2657 intel_miptree_prepare_depth(struct brw_context
*brw
,
2658 struct intel_mipmap_tree
*mt
, uint32_t level
,
2659 uint32_t start_layer
, uint32_t layer_count
)
2661 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2662 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2666 intel_miptree_finish_depth(struct brw_context
*brw
,
2667 struct intel_mipmap_tree
*mt
, uint32_t level
,
2668 uint32_t start_layer
, uint32_t layer_count
,
2671 if (depth_written
) {
2672 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2673 mt
->hiz_buf
!= NULL
);
2678 * Make it possible to share the BO backing the given miptree with another
2679 * process or another miptree.
2681 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2682 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2683 * ensure that no MCS buffer gets allocated in the future.
2685 * HiZ is similarly unsafe with shared buffers.
2688 intel_miptree_make_shareable(struct brw_context
*brw
,
2689 struct intel_mipmap_tree
*mt
)
2691 /* MCS buffers are also used for multisample buffers, but we can't resolve
2692 * away a multisample MCS buffer because it's an integral part of how the
2693 * pixel data is stored. Fortunately this code path should never be
2694 * reached for multisample buffers.
2696 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2698 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2699 0, INTEL_REMAINING_LAYERS
, false, false);
2702 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2703 brw_bo_unreference(mt
->mcs_buf
->bo
);
2707 /* Any pending MCS/CCS operations are no longer needed. Trying to
2708 * execute any will likely crash due to the missing aux buffer. So let's
2709 * delete all pending ops.
2711 free(mt
->aux_state
);
2712 mt
->aux_state
= NULL
;
2716 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2717 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2720 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2721 mt
->level
[l
].has_hiz
= false;
2724 /* Any pending HiZ operations are no longer needed. Trying to execute
2725 * any will likely crash due to the missing aux buffer. So let's delete
2728 free(mt
->aux_state
);
2729 mt
->aux_state
= NULL
;
2735 * \brief Get pointer offset into stencil buffer.
2737 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2738 * must decode the tile's layout in software.
2741 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2743 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2745 * Even though the returned offset is always positive, the return type is
2747 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2748 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2751 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2753 uint32_t tile_size
= 4096;
2754 uint32_t tile_width
= 64;
2755 uint32_t tile_height
= 64;
2756 uint32_t row_size
= 64 * stride
;
2758 uint32_t tile_x
= x
/ tile_width
;
2759 uint32_t tile_y
= y
/ tile_height
;
2761 /* The byte's address relative to the tile's base addres. */
2762 uint32_t byte_x
= x
% tile_width
;
2763 uint32_t byte_y
= y
% tile_height
;
2765 uintptr_t u
= tile_y
* row_size
2766 + tile_x
* tile_size
2767 + 512 * (byte_x
/ 8)
2769 + 32 * ((byte_y
/ 4) % 2)
2770 + 16 * ((byte_x
/ 4) % 2)
2771 + 8 * ((byte_y
/ 2) % 2)
2772 + 4 * ((byte_x
/ 2) % 2)
2777 /* adjust for bit6 swizzling */
2778 if (((byte_x
/ 8) % 2) == 1) {
2779 if (((byte_y
/ 8) % 2) == 0) {
2791 intel_miptree_updownsample(struct brw_context
*brw
,
2792 struct intel_mipmap_tree
*src
,
2793 struct intel_mipmap_tree
*dst
)
2795 brw_blorp_blit_miptrees(brw
,
2796 src
, 0 /* level */, 0 /* layer */,
2797 src
->format
, SWIZZLE_XYZW
,
2798 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2800 src
->logical_width0
, src
->logical_height0
,
2802 dst
->logical_width0
, dst
->logical_height0
,
2803 GL_NEAREST
, false, false /*mirror x, y*/,
2806 if (src
->stencil_mt
) {
2807 brw_blorp_blit_miptrees(brw
,
2808 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2809 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2810 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2811 dst
->stencil_mt
->format
,
2813 src
->logical_width0
, src
->logical_height0
,
2815 dst
->logical_width0
, dst
->logical_height0
,
2816 GL_NEAREST
, false, false /*mirror x, y*/,
2817 false, false /* decode/encode srgb */);
2822 intel_update_r8stencil(struct brw_context
*brw
,
2823 struct intel_mipmap_tree
*mt
)
2825 assert(brw
->gen
>= 7);
2826 struct intel_mipmap_tree
*src
=
2827 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2828 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2831 if (!mt
->r8stencil_mt
) {
2832 const uint32_t r8stencil_flags
=
2833 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2834 MIPTREE_LAYOUT_DISABLE_AUX
;
2835 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2836 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2838 MESA_FORMAT_R_UINT8
,
2841 src
->logical_width0
,
2842 src
->logical_height0
,
2843 src
->logical_depth0
,
2846 assert(mt
->r8stencil_mt
);
2849 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2851 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2852 const unsigned depth
= src
->level
[level
].depth
;
2854 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2855 brw_blorp_copy_miptrees(brw
,
2859 minify(src
->logical_width0
, level
),
2860 minify(src
->logical_height0
, level
));
2864 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2865 src
->r8stencil_needs_update
= false;
2869 intel_miptree_map_raw(struct brw_context
*brw
,
2870 struct intel_mipmap_tree
*mt
,
2873 struct brw_bo
*bo
= mt
->bo
;
2875 if (brw_batch_references(&brw
->batch
, bo
))
2876 intel_batchbuffer_flush(brw
);
2878 return brw_bo_map(brw
, bo
, mode
);
2882 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2884 brw_bo_unmap(mt
->bo
);
2888 intel_miptree_map_gtt(struct brw_context
*brw
,
2889 struct intel_mipmap_tree
*mt
,
2890 struct intel_miptree_map
*map
,
2891 unsigned int level
, unsigned int slice
)
2893 unsigned int bw
, bh
;
2895 unsigned int image_x
, image_y
;
2896 intptr_t x
= map
->x
;
2897 intptr_t y
= map
->y
;
2899 /* For compressed formats, the stride is the number of bytes per
2900 * row of blocks. intel_miptree_get_image_offset() already does
2903 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2904 assert(y
% bh
== 0);
2905 assert(x
% bw
== 0);
2909 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2914 /* Note that in the case of cube maps, the caller must have passed the
2915 * slice number referencing the face.
2917 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2921 map
->stride
= mt
->pitch
;
2922 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2925 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2926 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2927 map
->x
, map
->y
, map
->w
, map
->h
,
2928 mt
, _mesa_get_format_name(mt
->format
),
2929 x
, y
, map
->ptr
, map
->stride
);
2933 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2935 intel_miptree_unmap_raw(mt
);
2939 intel_miptree_map_blit(struct brw_context
*brw
,
2940 struct intel_mipmap_tree
*mt
,
2941 struct intel_miptree_map
*map
,
2942 unsigned int level
, unsigned int slice
)
2944 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2945 /* first_level */ 0,
2949 MIPTREE_LAYOUT_TILING_NONE
);
2951 if (!map
->linear_mt
) {
2952 fprintf(stderr
, "Failed to allocate blit temporary\n");
2955 map
->stride
= map
->linear_mt
->pitch
;
2957 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2958 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2959 * invalidate is set, since we'll be writing the whole rectangle from our
2960 * temporary buffer back out.
2962 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2963 if (!intel_miptree_copy(brw
,
2964 mt
, level
, slice
, map
->x
, map
->y
,
2965 map
->linear_mt
, 0, 0, 0, 0,
2967 fprintf(stderr
, "Failed to blit\n");
2972 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2974 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2975 map
->x
, map
->y
, map
->w
, map
->h
,
2976 mt
, _mesa_get_format_name(mt
->format
),
2977 level
, slice
, map
->ptr
, map
->stride
);
2982 intel_miptree_release(&map
->linear_mt
);
2988 intel_miptree_unmap_blit(struct brw_context
*brw
,
2989 struct intel_mipmap_tree
*mt
,
2990 struct intel_miptree_map
*map
,
2994 struct gl_context
*ctx
= &brw
->ctx
;
2996 intel_miptree_unmap_raw(map
->linear_mt
);
2998 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2999 bool ok
= intel_miptree_copy(brw
,
3000 map
->linear_mt
, 0, 0, 0, 0,
3001 mt
, level
, slice
, map
->x
, map
->y
,
3003 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3006 intel_miptree_release(&map
->linear_mt
);
3010 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3012 #if defined(USE_SSE41)
3014 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3015 struct intel_mipmap_tree
*mt
,
3016 struct intel_miptree_map
*map
,
3017 unsigned int level
, unsigned int slice
)
3019 assert(map
->mode
& GL_MAP_READ_BIT
);
3020 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3022 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3023 map
->x
, map
->y
, map
->w
, map
->h
,
3024 mt
, _mesa_get_format_name(mt
->format
),
3025 level
, slice
, map
->ptr
, map
->stride
);
3027 /* Map the original image */
3030 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3034 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3040 src
+= image_y
* mt
->pitch
;
3041 src
+= image_x
* mt
->cpp
;
3043 /* Due to the pixel offsets for the particular image being mapped, our
3044 * src pointer may not be 16-byte aligned. However, if the pitch is
3045 * divisible by 16, then the amount by which it's misaligned will remain
3046 * consistent from row to row.
3048 assert((mt
->pitch
% 16) == 0);
3049 const int misalignment
= ((uintptr_t) src
) & 15;
3051 /* Create an untiled temporary buffer for the mapping. */
3052 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3054 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3056 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3057 /* Offset the destination so it has the same misalignment as src. */
3058 map
->ptr
= map
->buffer
+ misalignment
;
3060 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3062 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3063 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3064 void *src_ptr
= src
+ y
* mt
->pitch
;
3066 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3069 intel_miptree_unmap_raw(mt
);
3073 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3074 struct intel_mipmap_tree
*mt
,
3075 struct intel_miptree_map
*map
,
3079 _mesa_align_free(map
->buffer
);
3086 intel_miptree_map_s8(struct brw_context
*brw
,
3087 struct intel_mipmap_tree
*mt
,
3088 struct intel_miptree_map
*map
,
3089 unsigned int level
, unsigned int slice
)
3091 map
->stride
= map
->w
;
3092 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3096 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3097 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3098 * invalidate is set, since we'll be writing the whole rectangle from our
3099 * temporary buffer back out.
3101 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3102 uint8_t *untiled_s8_map
= map
->ptr
;
3103 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3104 unsigned int image_x
, image_y
;
3106 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3108 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3109 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3110 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3111 x
+ image_x
+ map
->x
,
3112 y
+ image_y
+ map
->y
,
3113 brw
->has_swizzling
);
3114 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3118 intel_miptree_unmap_raw(mt
);
3120 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3121 map
->x
, map
->y
, map
->w
, map
->h
,
3122 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3124 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3125 map
->x
, map
->y
, map
->w
, map
->h
,
3126 mt
, map
->ptr
, map
->stride
);
3131 intel_miptree_unmap_s8(struct brw_context
*brw
,
3132 struct intel_mipmap_tree
*mt
,
3133 struct intel_miptree_map
*map
,
3137 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3138 unsigned int image_x
, image_y
;
3139 uint8_t *untiled_s8_map
= map
->ptr
;
3140 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3142 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3144 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3145 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3146 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3147 image_x
+ x
+ map
->x
,
3148 image_y
+ y
+ map
->y
,
3149 brw
->has_swizzling
);
3150 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3154 intel_miptree_unmap_raw(mt
);
3161 intel_miptree_map_etc(struct brw_context
*brw
,
3162 struct intel_mipmap_tree
*mt
,
3163 struct intel_miptree_map
*map
,
3167 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3168 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3169 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3172 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3173 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3175 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3176 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3177 map
->w
, map
->h
, 1));
3178 map
->ptr
= map
->buffer
;
3182 intel_miptree_unmap_etc(struct brw_context
*brw
,
3183 struct intel_mipmap_tree
*mt
,
3184 struct intel_miptree_map
*map
,
3190 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3195 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3196 + image_y
* mt
->pitch
3197 + image_x
* mt
->cpp
;
3199 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3200 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3201 map
->ptr
, map
->stride
,
3204 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3205 map
->ptr
, map
->stride
,
3206 map
->w
, map
->h
, mt
->etc_format
);
3208 intel_miptree_unmap_raw(mt
);
3213 * Mapping function for packed depth/stencil miptrees backed by real separate
3214 * miptrees for depth and stencil.
3216 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3217 * separate from the depth buffer. Yet at the GL API level, we have to expose
3218 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3219 * be able to map that memory for texture storage and glReadPixels-type
3220 * operations. We give Mesa core that access by mallocing a temporary and
3221 * copying the data between the actual backing store and the temporary.
3224 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3225 struct intel_mipmap_tree
*mt
,
3226 struct intel_miptree_map
*map
,
3227 unsigned int level
, unsigned int slice
)
3229 struct intel_mipmap_tree
*z_mt
= mt
;
3230 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3231 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3232 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3234 map
->stride
= map
->w
* packed_bpp
;
3235 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3239 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3240 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3241 * invalidate is set, since we'll be writing the whole rectangle from our
3242 * temporary buffer back out.
3244 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3245 uint32_t *packed_map
= map
->ptr
;
3246 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3247 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3248 unsigned int s_image_x
, s_image_y
;
3249 unsigned int z_image_x
, z_image_y
;
3251 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3252 &s_image_x
, &s_image_y
);
3253 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3254 &z_image_x
, &z_image_y
);
3256 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3257 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3258 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3259 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3262 brw
->has_swizzling
);
3263 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3265 (map_x
+ z_image_x
));
3266 uint8_t s
= s_map
[s_offset
];
3267 uint32_t z
= z_map
[z_offset
];
3269 if (map_z32f_x24s8
) {
3270 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3271 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3273 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3278 intel_miptree_unmap_raw(s_mt
);
3279 intel_miptree_unmap_raw(z_mt
);
3281 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3283 map
->x
, map
->y
, map
->w
, map
->h
,
3284 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3285 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3286 map
->ptr
, map
->stride
);
3288 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3289 map
->x
, map
->y
, map
->w
, map
->h
,
3290 mt
, map
->ptr
, map
->stride
);
3295 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3296 struct intel_mipmap_tree
*mt
,
3297 struct intel_miptree_map
*map
,
3301 struct intel_mipmap_tree
*z_mt
= mt
;
3302 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3303 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3305 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3306 uint32_t *packed_map
= map
->ptr
;
3307 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3308 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3309 unsigned int s_image_x
, s_image_y
;
3310 unsigned int z_image_x
, z_image_y
;
3312 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3313 &s_image_x
, &s_image_y
);
3314 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3315 &z_image_x
, &z_image_y
);
3317 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3318 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3319 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3320 x
+ s_image_x
+ map
->x
,
3321 y
+ s_image_y
+ map
->y
,
3322 brw
->has_swizzling
);
3323 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3325 (x
+ z_image_x
+ map
->x
));
3327 if (map_z32f_x24s8
) {
3328 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3329 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3331 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3332 s_map
[s_offset
] = packed
>> 24;
3333 z_map
[z_offset
] = packed
;
3338 intel_miptree_unmap_raw(s_mt
);
3339 intel_miptree_unmap_raw(z_mt
);
3341 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3343 map
->x
, map
->y
, map
->w
, map
->h
,
3344 z_mt
, _mesa_get_format_name(z_mt
->format
),
3345 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3346 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3347 map
->ptr
, map
->stride
);
3354 * Create and attach a map to the miptree at (level, slice). Return the
3357 static struct intel_miptree_map
*
3358 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3367 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3372 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3373 mt
->level
[level
].slice
[slice
].map
= map
;
3385 * Release the map at (level, slice).
3388 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3392 struct intel_miptree_map
**map
;
3394 map
= &mt
->level
[level
].slice
[slice
].map
;
3400 can_blit_slice(struct intel_mipmap_tree
*mt
,
3401 unsigned int level
, unsigned int slice
)
3403 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3404 if (mt
->pitch
>= 32768)
3411 use_intel_mipree_map_blit(struct brw_context
*brw
,
3412 struct intel_mipmap_tree
*mt
,
3418 /* It's probably not worth swapping to the blit ring because of
3419 * all the overhead involved.
3421 !(mode
& GL_MAP_WRITE_BIT
) &&
3423 (mt
->tiling
== I915_TILING_X
||
3424 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3425 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3426 /* Fast copy blit on skl+ supports all tiling formats. */
3428 can_blit_slice(mt
, level
, slice
))
3431 if (mt
->tiling
!= I915_TILING_NONE
&&
3432 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3433 assert(can_blit_slice(mt
, level
, slice
));
3441 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3442 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3443 * arithmetic overflow.
3445 * If you call this function and use \a out_stride, then you're doing pointer
3446 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3447 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3448 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3449 * which usually have type uint32_t or GLuint.
3452 intel_miptree_map(struct brw_context
*brw
,
3453 struct intel_mipmap_tree
*mt
,
3462 ptrdiff_t *out_stride
)
3464 struct intel_miptree_map
*map
;
3466 assert(mt
->num_samples
<= 1);
3468 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3475 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3476 map
->mode
& GL_MAP_WRITE_BIT
);
3478 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3479 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3480 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3481 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3482 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3483 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3484 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3485 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3486 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3487 #if defined(USE_SSE41)
3488 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3489 !mt
->compressed
&& cpu_has_sse4_1
&&
3490 (mt
->pitch
% 16 == 0)) {
3491 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3494 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3497 *out_ptr
= map
->ptr
;
3498 *out_stride
= map
->stride
;
3500 if (map
->ptr
== NULL
)
3501 intel_miptree_release_map(mt
, level
, slice
);
3505 intel_miptree_unmap(struct brw_context
*brw
,
3506 struct intel_mipmap_tree
*mt
,
3510 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3512 assert(mt
->num_samples
<= 1);
3517 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3518 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3520 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3521 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3522 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3523 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3524 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3525 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3526 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3527 } else if (map
->linear_mt
) {
3528 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3529 #if defined(USE_SSE41)
3530 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3531 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3534 intel_miptree_unmap_gtt(mt
);
3537 intel_miptree_release_map(mt
, level
, slice
);
3541 get_isl_surf_dim(GLenum target
)
3545 case GL_TEXTURE_1D_ARRAY
:
3546 return ISL_SURF_DIM_1D
;
3549 case GL_TEXTURE_2D_ARRAY
:
3550 case GL_TEXTURE_RECTANGLE
:
3551 case GL_TEXTURE_CUBE_MAP
:
3552 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3553 case GL_TEXTURE_2D_MULTISAMPLE
:
3554 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3555 case GL_TEXTURE_EXTERNAL_OES
:
3556 return ISL_SURF_DIM_2D
;
3559 return ISL_SURF_DIM_3D
;
3562 unreachable("Invalid texture target");
3566 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3567 GLenum target
, enum miptree_array_layout array_layout
)
3569 if (array_layout
== GEN6_HIZ_STENCIL
)
3570 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3574 case GL_TEXTURE_1D_ARRAY
:
3575 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3576 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3579 case GL_TEXTURE_2D_ARRAY
:
3580 case GL_TEXTURE_RECTANGLE
:
3581 case GL_TEXTURE_2D_MULTISAMPLE
:
3582 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3583 case GL_TEXTURE_EXTERNAL_OES
:
3584 return ISL_DIM_LAYOUT_GEN4_2D
;
3586 case GL_TEXTURE_CUBE_MAP
:
3587 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3588 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3589 ISL_DIM_LAYOUT_GEN4_2D
);
3592 return (devinfo
->gen
>= 9 ?
3593 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3596 unreachable("Invalid texture target");
3600 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3602 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3603 return ISL_TILING_W
;
3605 switch (mt
->tiling
) {
3606 case I915_TILING_NONE
:
3607 return ISL_TILING_LINEAR
;
3609 return ISL_TILING_X
;
3611 return ISL_TILING_Y0
;
3613 unreachable("Invalid tiling mode");
3619 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3620 const struct intel_mipmap_tree
*mt
,
3621 struct isl_surf
*surf
)
3623 surf
->dim
= get_isl_surf_dim(mt
->target
);
3624 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3625 mt
->tiling
, mt
->target
,
3628 if (mt
->num_samples
> 1) {
3629 switch (mt
->msaa_layout
) {
3630 case INTEL_MSAA_LAYOUT_IMS
:
3631 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3633 case INTEL_MSAA_LAYOUT_UMS
:
3634 case INTEL_MSAA_LAYOUT_CMS
:
3635 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3638 unreachable("Invalid MSAA layout");
3641 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3644 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3646 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3647 /* The ISL definition of row_pitch matches the surface state pitch field
3648 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3649 * the factor of 2 for W-tiling in row_pitch.
3651 surf
->row_pitch
= 2 * mt
->pitch
;
3653 surf
->row_pitch
= mt
->pitch
;
3656 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3658 if (brw
->gen
>= 9) {
3659 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3660 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3661 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3663 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3664 * alignment in terms of surface elements like we want.
3666 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3669 /* On earlier gens it's stored in pixels. */
3671 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3672 surf
->image_alignment_el
=
3673 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3676 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3677 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3678 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3679 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3680 surf
->logical_level0_px
.array_len
= 1;
3682 surf
->logical_level0_px
.depth
= 1;
3683 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3686 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3687 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3688 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3689 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3690 surf
->phys_level0_sa
.array_len
= 1;
3692 surf
->phys_level0_sa
.depth
= 1;
3693 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3696 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3697 surf
->samples
= MAX2(mt
->num_samples
, 1);
3699 surf
->size
= 0; /* TODO */
3700 surf
->alignment
= 0; /* TODO */
3702 switch (surf
->dim_layout
) {
3703 case ISL_DIM_LAYOUT_GEN4_2D
:
3704 case ISL_DIM_LAYOUT_GEN4_3D
:
3705 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3706 if (brw
->gen
>= 9) {
3707 surf
->array_pitch_el_rows
= mt
->qpitch
;
3710 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3711 assert(mt
->qpitch
% bh
== 0);
3712 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3715 case ISL_DIM_LAYOUT_GEN9_1D
:
3716 surf
->array_pitch_el_rows
= 1;
3720 switch (mt
->array_layout
) {
3721 case ALL_LOD_IN_EACH_SLICE
:
3722 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3724 case ALL_SLICES_AT_EACH_LOD
:
3725 case GEN6_HIZ_STENCIL
:
3726 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3729 unreachable("Invalid array layout");
3732 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3733 switch (base_format
) {
3734 case GL_DEPTH_COMPONENT
:
3735 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3737 case GL_STENCIL_INDEX
:
3738 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3740 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3742 case GL_DEPTH_STENCIL
:
3743 /* In this case we only texture from the depth part */
3744 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3745 ISL_SURF_USAGE_TEXTURE_BIT
;
3748 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3749 if (brw
->format_supported_as_render_target
[mt
->format
])
3750 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3754 if (_mesa_is_cube_map_texture(mt
->target
))
3755 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3758 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3759 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3760 * PASS IT INTO isl_surf_fill_state.
3763 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3764 const struct intel_mipmap_tree
*mt
,
3765 struct isl_surf
*surf
,
3766 enum isl_aux_usage
*usage
)
3768 uint32_t aux_pitch
, aux_qpitch
;
3770 aux_pitch
= mt
->mcs_buf
->pitch
;
3771 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3773 if (mt
->num_samples
> 1) {
3774 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3775 *usage
= ISL_AUX_USAGE_MCS
;
3776 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3777 assert(brw
->gen
>= 9);
3778 *usage
= ISL_AUX_USAGE_CCS_E
;
3779 } else if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0) {
3780 *usage
= ISL_AUX_USAGE_CCS_D
;
3782 unreachable("Invalid MCS miptree");
3784 } else if (mt
->hiz_buf
) {
3785 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3786 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3788 *usage
= ISL_AUX_USAGE_HIZ
;
3790 *usage
= ISL_AUX_USAGE_NONE
;
3794 /* Start with a copy of the original surface. */
3795 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3797 /* Figure out the format and tiling of the auxiliary surface */
3799 case ISL_AUX_USAGE_NONE
:
3800 unreachable("Invalid auxiliary usage");
3802 case ISL_AUX_USAGE_HIZ
:
3803 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3806 case ISL_AUX_USAGE_MCS
:
3809 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3810 * HALIGN 16 must be used."
3813 assert(mt
->halign
== 16);
3815 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3818 case ISL_AUX_USAGE_CCS_D
:
3819 case ISL_AUX_USAGE_CCS_E
:
3821 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3823 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3825 * From the hardware spec for GEN9:
3827 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3828 * HALIGN 16 must be used."
3830 assert(mt
->num_samples
<= 1);
3832 assert(mt
->halign
== 16);
3834 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3838 /* We want the pitch of the actual aux buffer. */
3839 surf
->row_pitch
= aux_pitch
;
3841 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3842 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3843 * in elements of the primary color surface so we have to divide by the
3844 * compression block height.
3846 surf
->array_pitch_el_rows
=
3847 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;